| blob | 858bbd609ae9d4e84c270503db7ca552cbaf7b42 |
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * logicore_dp_dpcd.h
4 *
5 * DPCD interface definition for XILINX LogiCore DisplayPort v6.1
6 * based on Xilinx dp_v3_1 driver sources
7 *
8 * (C) Copyright 2016
9 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
10 */
12 #ifndef __GDSYS_LOGICORE_DP_DPCD_H__
13 #define __GDSYS_LOGICORE_DP_DPCD_H__
15 /* receiver capability field */
16 #define DPCD_REV 0x00000
17 #define DPCD_MAX_LINK_RATE 0x00001
18 #define DPCD_MAX_LANE_COUNT 0x00002
19 #define DPCD_MAX_DOWNSPREAD 0x00003
20 #define DPCD_NORP_PWR_V_CAP 0x00004
21 #define DPCD_DOWNSP_PRESENT 0x00005
22 #define DPCD_ML_CH_CODING_CAP 0x00006
23 #define DPCD_DOWNSP_COUNT_MSA_OUI 0x00007
24 #define DPCD_RX_PORT0_CAP_0 0x00008
25 #define DPCD_RX_PORT0_CAP_1 0x00009
26 #define DPCD_RX_PORT1_CAP_0 0x0000A
27 #define DPCD_RX_PORT1_CAP_1 0x0000B
28 #define DPCD_I2C_SPEED_CTL_CAP 0x0000C
29 #define DPCD_EDP_CFG_CAP 0x0000D
30 #define DPCD_TRAIN_AUX_RD_INTERVAL 0x0000E
31 #define DPCD_ADAPTER_CAP 0x0000F
32 #define DPCD_FAUX_CAP 0x00020
33 #define DPCD_MSTM_CAP 0x00021
34 #define DPCD_NUM_AUDIO_EPS 0x00022
35 #define DPCD_AV_GRANULARITY 0x00023
36 #define DPCD_AUD_DEC_LAT_7_0 0x00024
37 #define DPCD_AUD_DEC_LAT_15_8 0x00025
38 #define DPCD_AUD_PP_LAT_7_0 0x00026
39 #define DPCD_AUD_PP_LAT_15_8 0x00027
40 #define DPCD_VID_INTER_LAT 0x00028
41 #define DPCD_VID_PROG_LAT 0x00029
42 #define DPCD_REP_LAT 0x0002A
43 #define DPCD_AUD_DEL_INS_7_0 0x0002B
44 #define DPCD_AUD_DEL_INS_15_8 0x0002C
45 #define DPCD_AUD_DEL_INS_23_16 0x0002D
46 #define DPCD_GUID 0x00030
47 #define DPCD_RX_GTC_VALUE_7_0 0x00054
48 #define DPCD_RX_GTC_VALUE_15_8 0x00055
49 #define DPCD_RX_GTC_VALUE_23_16 0x00056
50 #define DPCD_RX_GTC_VALUE_31_24 0x00057
51 #define DPCD_RX_GTC_MSTR_REQ 0x00058
52 #define DPCD_RX_GTC_FREQ_LOCK_DONE 0x00059
53 #define DPCD_DOWNSP_0_CAP 0x00080
54 #define DPCD_DOWNSP_1_CAP 0x00081
55 #define DPCD_DOWNSP_2_CAP 0x00082
56 #define DPCD_DOWNSP_3_CAP 0x00083
57 #define DPCD_DOWNSP_0_DET_CAP 0x00080
58 #define DPCD_DOWNSP_1_DET_CAP 0x00084
59 #define DPCD_DOWNSP_2_DET_CAP 0x00088
60 #define DPCD_DOWNSP_3_DET_CAP 0x0008C
62 /* link configuration field */
63 #define DPCD_LINK_BW_SET 0x00100
64 #define DPCD_LANE_COUNT_SET 0x00101
65 #define DPCD_TP_SET 0x00102
66 #define DPCD_TRAINING_LANE0_SET 0x00103
67 #define DPCD_TRAINING_LANE1_SET 0x00104
68 #define DPCD_TRAINING_LANE2_SET 0x00105
69 #define DPCD_TRAINING_LANE3_SET 0x00106
70 #define DPCD_DOWNSPREAD_CTRL 0x00107
71 #define DPCD_ML_CH_CODING_SET 0x00108
72 #define DPCD_I2C_SPEED_CTL_SET 0x00109
73 #define DPCD_EDP_CFG_SET 0x0010A
74 #define DPCD_LINK_QUAL_LANE0_SET 0x0010B
75 #define DPCD_LINK_QUAL_LANE1_SET 0x0010C
76 #define DPCD_LINK_QUAL_LANE2_SET 0x0010D
77 #define DPCD_LINK_QUAL_LANE3_SET 0x0010E
78 #define DPCD_TRAINING_LANE0_1_SET2 0x0010F
79 #define DPCD_TRAINING_LANE2_3_SET2 0x00110
80 #define DPCD_MSTM_CTRL 0x00111
81 #define DPCD_AUDIO_DELAY_7_0 0x00112
82 #define DPCD_AUDIO_DELAY_15_8 0x00113
83 #define DPCD_AUDIO_DELAY_23_6 0x00114
84 #define DPCD_UPSTREAM_DEVICE_DP_PWR_NEED 0x00118
85 #define DPCD_FAUX_MODE_CTRL 0x00120
86 #define DPCD_FAUX_FORWARD_CH_DRIVE_SET 0x00121
87 #define DPCD_BACK_CH_STATUS 0x00122
88 #define DPCD_FAUX_BACK_CH_SYMBOL_ERROR_COUNT 0x00123
89 #define DPCD_FAUX_BACK_CH_TRAINING_PATTERN_TIME 0x00125
90 #define DPCD_TX_GTC_VALUE_7_0 0x00154
91 #define DPCD_TX_GTC_VALUE_15_8 0x00155
92 #define DPCD_TX_GTC_VALUE_23_16 0x00156
93 #define DPCD_TX_GTC_VALUE_31_24 0x00157
94 #define DPCD_RX_GTC_VALUE_PHASE_SKEW_EN 0x00158
95 #define DPCD_TX_GTC_FREQ_LOCK_DONE 0x00159
96 #define DPCD_ADAPTER_CTRL 0x001A0
97 #define DPCD_BRANCH_DEVICE_CTRL 0x001A1
98 #define DPCD_PAYLOAD_ALLOCATE_SET 0x001C0
99 #define DPCD_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x001C1
100 #define DPCD_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x001C2
102 /* link/sink status field */
103 #define DPCD_SINK_COUNT 0x00200
104 #define DPCD_DEVICE_SERVICE_IRQ 0x00201
105 #define DPCD_STATUS_LANE_0_1 0x00202
106 #define DPCD_STATUS_LANE_2_3 0x00203
107 #define DPCD_LANE_ALIGN_STATUS_UPDATED 0x00204
108 #define DPCD_SINK_STATUS 0x00205
109 #define DPCD_ADJ_REQ_LANE_0_1 0x00206
110 #define DPCD_ADJ_REQ_LANE_2_3 0x00207
111 #define DPCD_TRAINING_SCORE_LANE_0 0x00208
112 #define DPCD_TRAINING_SCORE_LANE_1 0x00209
113 #define DPCD_TRAINING_SCORE_LANE_2 0x0020A
114 #define DPCD_TRAINING_SCORE_LANE_3 0x0020B
115 #define DPCD_ADJ_REQ_PC2 0x0020C
116 #define DPCD_FAUX_FORWARD_CH_SYMBOL_ERROR_COUNT 0x0020D
117 #define DPCD_SYMBOL_ERROR_COUNT_LANE_0 0x00210
118 #define DPCD_SYMBOL_ERROR_COUNT_LANE_1 0x00212
119 #define DPCD_SYMBOL_ERROR_COUNT_LANE_2 0x00214
120 #define DPCD_SYMBOL_ERROR_COUNT_LANE_3 0x00216
122 /* automated testing sub-field */
123 #define DPCD_FAUX_FORWARD_CH_STATUS 0x00280
124 #define DPCD_FAUX_BACK_CH_DRIVE_SET 0x00281
125 #define DPCD_FAUX_BACK_CH_SYM_ERR_COUNT_CTRL 0x00282
126 #define DPCD_PAYLOAD_TABLE_UPDATE_STATUS 0x002C0
127 #define DPCD_VC_PAYLOAD_ID_SLOT(slotnum) \
128 (DPCD_PAYLOAD_TABLE_UPDATE_STATUS + slotnum)
130 /* sink control field */
131 #define DPCD_SET_POWER_DP_PWR_VOLTAGE 0x00600
133 /* sideband message buffers */
134 #define DPCD_DOWN_REQ 0x01000
135 #define DPCD_UP_REP 0x01200
136 #define DPCD_DOWN_REP 0x01400
137 #define DPCD_UP_REQ 0x01600
139 /* event status indicator field */
140 #define DPCD_SINK_COUNT_ESI 0x02002
141 #define DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x02003
142 #define DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x02004
143 #define DPCD_SINK_LINK_SERVICE_IRQ_VECTOR_ESI0 0x02005
144 #define DPCD_SINK_LANE0_1_STATUS 0x0200C
145 #define DPCD_SINK_LANE2_3_STATUS 0x0200D
146 #define DPCD_SINK_ALIGN_STATUS_UPDATED_ESI 0x0200E
147 #define DPCD_SINK_STATUS_ESI 0x0200F
149 /*
150 * field addresses and sizes.
151 */
152 #define DPCD_RECEIVER_CAP_FIELD_START DPCD_REV
153 #define DPCD_RECEIVER_CAP_FIELD_SIZE 0x100
154 #define DPCD_LINK_CFG_FIELD_START DPCD_LINK_BW_SET
155 #define DPCD_LINK_CFG_FIELD_SIZE 0x100
156 #define DPCD_LINK_SINK_STATUS_FIELD_START DPCD_SINK_COUNT
157 #define DPCD_LINK_SINK_STATUS_FIELD_SIZE 0x17
158 /* 0x00000: DPCD_REV */
159 #define DPCD_REV_MNR_MASK 0x0F
160 #define DPCD_REV_MJR_MASK 0xF0
161 #define DPCD_REV_MJR_SHIFT 4
162 /* 0x00001: MAX_LINK_RATE */
163 #define DPCD_MAX_LINK_RATE_162GBPS 0x06
164 #define DPCD_MAX_LINK_RATE_270GBPS 0x0A
165 #define DPCD_MAX_LINK_RATE_540GBPS 0x14
166 /* 0x00002: MAX_LANE_COUNT */
167 #define DPCD_MAX_LANE_COUNT_MASK 0x1F
168 #define DPCD_MAX_LANE_COUNT_1 0x01
169 #define DPCD_MAX_LANE_COUNT_2 0x02
170 #define DPCD_MAX_LANE_COUNT_4 0x04
171 #define DPCD_TPS3_SUPPORT_MASK 0x40
172 #define DPCD_ENHANCED_FRAME_SUPPORT_MASK 0x80
173 /* 0x00003: MAX_DOWNSPREAD */
174 #define DPCD_MAX_DOWNSPREAD_MASK 0x01
175 #define DPCD_NO_AUX_HANDSHAKE_LINK_TRAIN_MASK 0x40
176 /* 0x00005: DOWNSP_PRESENT */
177 #define DPCD_DOWNSP_PRESENT_MASK 0x01
178 #define DPCD_DOWNSP_TYPE_MASK 0x06
179 #define DPCD_DOWNSP_TYPE_SHIFT 1
180 #define DPCD_DOWNSP_TYPE_DP 0x0
181 #define DPCD_DOWNSP_TYPE_AVGA_ADVII 0x1
182 #define DPCD_DOWNSP_TYPE_DVI_HDMI_DPPP 0x2
183 #define DPCD_DOWNSP_TYPE_OTHERS 0x3
184 #define DPCD_DOWNSP_FORMAT_CONV_MASK 0x08
185 #define DPCD_DOWNSP_DCAP_INFO_AVAIL_MASK 0x10
186 /* 0x00006, 0x00108: ML_CH_CODING_SUPPORT, ML_CH_CODING_SET */
187 #define DPCD_ML_CH_CODING_MASK 0x01
188 /* 0x00007: DOWNSP_COUNT_MSA_OUI */
189 #define DPCD_DOWNSP_COUNT_MASK 0x0F
190 #define DPCD_MSA_TIMING_PAR_IGNORED_MASK 0x40
191 #define DPCD_OUI_SUPPORT_MASK 0x80
192 /* 0x00008, 0x0000A: RX_PORT[0-1]_CAP_0 */
193 #define DPCD_RX_PORTX_CAP_0_LOCAL_EDID_PRESENT_MASK 0x02
194 #define DPCD_RX_PORTX_CAP_0_ASSOC_TO_PRECEDING_PORT_MASK 0x04
195 /* 0x0000C, 0x00109: I2C_SPEED_CTL_CAP, I2C_SPEED_CTL_SET */
196 #define DPCD_I2C_SPEED_CTL_NONE 0x00
197 #define DPCD_I2C_SPEED_CTL_1KBIPS 0x01
198 #define DPCD_I2C_SPEED_CTL_5KBIPS 0x02
199 #define DPCD_I2C_SPEED_CTL_10KBIPS 0x04
200 #define DPCD_I2C_SPEED_CTL_100KBIPS 0x08
201 #define DPCD_I2C_SPEED_CTL_400KBIPS 0x10
202 #define DPCD_I2C_SPEED_CTL_1MBIPS 0x20
203 /* 0x0000E: TRAIN_AUX_RD_INTERVAL */
204 #define DPCD_TRAIN_AUX_RD_INT_100_400US 0x00
205 #define DPCD_TRAIN_AUX_RD_INT_4MS 0x01
206 #define DPCD_TRAIN_AUX_RD_INT_8MS 0x02
207 #define DPCD_TRAIN_AUX_RD_INT_12MS 0x03
208 #define DPCD_TRAIN_AUX_RD_INT_16MS 0x04
209 /* 0x00020: DPCD_FAUX_CAP */
210 #define DPCD_FAUX_CAP_MASK 0x01
211 /* 0x00021: MSTM_CAP */
212 #define DPCD_MST_CAP_MASK 0x01
213 /* 0x00080, 0x00081|4, 0x00082|8, 0x00083|C: DOWNSP_X_(DET_)CAP */
214 #define DPCD_DOWNSP_X_CAP_TYPE_MASK 0x07
215 #define DPCD_DOWNSP_X_CAP_TYPE_DP 0x0
216 #define DPCD_DOWNSP_X_CAP_TYPE_AVGA 0x1
217 #define DPCD_DOWNSP_X_CAP_TYPE_DVI 0x2
218 #define DPCD_DOWNSP_X_CAP_TYPE_HDMI 0x3
219 #define DPCD_DOWNSP_X_CAP_TYPE_OTHERS 0x4
220 #define DPCD_DOWNSP_X_CAP_TYPE_DPPP 0x5
221 #define DPCD_DOWNSP_X_CAP_HPD_MASK 0x80
222 #define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_MASK 0xF0
223 #define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_SHIFT 4
224 #define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_60 0x1
225 #define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_50 0x2
226 #define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_60 0x3
227 #define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_50 0x4
228 #define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_60 0x5
229 #define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_50 0x7
230 /* 0x00082, 0x00086, 0x0008A, 0x0008E: DOWNSP_X_(DET_)CAP2 */
231 #define DPCD_DOWNSP_X_DCAP_MAX_BPC_MASK 0x03
232 #define DPCD_DOWNSP_X_DCAP_MAX_BPC_8 0x0
233 #define DPCD_DOWNSP_X_DCAP_MAX_BPC_10 0x1
234 #define DPCD_DOWNSP_X_DCAP_MAX_BPC_12 0x2
235 #define DPCD_DOWNSP_X_DCAP_MAX_BPC_16 0x3
236 /* 0x00082, 0x00086, 0x0008A, 0x0008E: DOWNSP_X_(DET_)CAP2 */
237 #define DPCD_DOWNSP_X_DCAP_HDMI_DPPP_FS2FP_MASK 0x01
238 #define DPCD_DOWNSP_X_DCAP_DVI_DL_MASK 0x02
239 #define DPCD_DOWNSP_X_DCAP_DVI_HCD_MASK 0x04
241 /* link configuration field masks, shifts, and register values */
242 /* 0x00100: DPCD_LINK_BW_SET */
243 #define DPCD_LINK_BW_SET_162GBPS 0x06
244 #define DPCD_LINK_BW_SET_270GBPS 0x0A
245 #define DPCD_LINK_BW_SET_540GBPS 0x14
246 /* 0x00101: LANE_COUNT_SET */
247 #define DPCD_LANE_COUNT_SET_MASK 0x1F
248 #define DPCD_LANE_COUNT_SET_1 0x01
249 #define DPCD_LANE_COUNT_SET_2 0x02
250 #define DPCD_LANE_COUNT_SET_4 0x04
251 #define DPCD_ENHANCED_FRAME_EN_MASK 0x80
252 /* 0x00102: TP_SET */
253 #define DPCD_TP_SEL_MASK 0x03
254 #define DPCD_TP_SEL_OFF 0x0
255 #define DPCD_TP_SEL_TP1 0x1
256 #define DPCD_TP_SEL_TP2 0x2
257 #define DPCD_TP_SEL_TP3 0x3
258 #define DPCD_TP_SET_LQP_MASK 0x06
259 #define DPCD_TP_SET_LQP_SHIFT 2
260 #define DPCD_TP_SET_LQP_OFF 0x0
261 #define DPCD_TP_SET_LQP_D102_TEST 0x1
262 #define DPCD_TP_SET_LQP_SER_MES 0x2
263 #define DPCD_TP_SET_LQP_PRBS7 0x3
264 #define DPCD_TP_SET_REC_CLK_OUT_EN_MASK 0x10
265 #define DPCD_TP_SET_SCRAMB_DIS_MASK 0x20
266 #define DPCD_TP_SET_SE_COUNT_SEL_MASK 0xC0
267 #define DPCD_TP_SET_SE_COUNT_SEL_SHIFT 6
268 #define DPCD_TP_SET_SE_COUNT_SEL_DE_ISE 0x0
269 #define DPCD_TP_SET_SE_COUNT_SEL_DE 0x1
270 #define DPCD_TP_SET_SE_COUNT_SEL_ISE 0x2
271 /* 0x00103-0x00106: TRAINING_LANE[0-3]_SET */
272 #define DPCD_TRAINING_LANEX_SET_VS_MASK 0x03
273 #define DPCD_TRAINING_LANEX_SET_MAX_VS_MASK 0x04
274 #define DPCD_TRAINING_LANEX_SET_PE_MASK 0x18
275 #define DPCD_TRAINING_LANEX_SET_PE_SHIFT 3
276 #define DPCD_TRAINING_LANEX_SET_MAX_PE_MASK 0x20
277 /* 0x00107: DOWNSPREAD_CTRL */
278 #define DPCD_SPREAD_AMP_MASK 0x10
279 #define DPCD_MSA_TIMING_PAR_IGNORED_EN_MASK 0x80
280 /* 0x00108: ML_CH_CODING_SET - Same as 0x00006: ML_CH_CODING_SUPPORT */
281 /* 0x00109: I2C_SPEED_CTL_SET - Same as 0x0000C: I2C_SPEED_CTL_CAP */
282 /* 0x0010F-0x00110: TRAINING_LANE[0_1-2_3]_SET2 */
283 #define DPCD_TRAINING_LANE_0_2_SET_PC2_MASK 0x03
284 #define DPCD_TRAINING_LANE_0_2_SET_MAX_PC2_MASK 0x04
285 #define DPCD_TRAINING_LANE_1_3_SET_PC2_MASK 0x30
286 #define DPCD_TRAINING_LANE_1_3_SET_PC2_SHIFT 4
287 #define DPCD_TRAINING_LANE_1_3_SET_MAX_PC2_MASK 0x40
288 /* 0x00111: MSTM_CTRL */
289 #define DPCD_MST_EN_MASK 0x01
290 #define DPCD_UP_REQ_EN_MASK 0x02
291 #define DPCD_UP_IS_SRC_MASK 0x03
293 /* link/sink status field masks, shifts, and register values */
294 /* 0x00200: SINK_COUNT */
295 #define DPCD_SINK_COUNT_LOW_MASK 0x3F
296 #define DPCD_SINK_CP_READY_MASK 0x40
297 #define DPCD_SINK_COUNT_HIGH_MASK 0x80
298 #define DPCD_SINK_COUNT_HIGH_LOW_SHIFT 1
299 /* 0x00202: STATUS_LANE_0_1 */
300 #define DPCD_STATUS_LANE_0_CR_DONE_MASK 0x01
301 #define DPCD_STATUS_LANE_0_CE_DONE_MASK 0x02
302 #define DPCD_STATUS_LANE_0_SL_DONE_MASK 0x04
303 #define DPCD_STATUS_LANE_1_CR_DONE_MASK 0x10
304 #define DPCD_STATUS_LANE_1_CE_DONE_MASK 0x20
305 #define DPCD_STATUS_LANE_1_SL_DONE_MASK 0x40
306 /* 0x00202: STATUS_LANE_2_3 */
307 #define DPCD_STATUS_LANE_2_CR_DONE_MASK 0x01
308 #define DPCD_STATUS_LANE_2_CE_DONE_MASK 0x02
309 #define DPCD_STATUS_LANE_2_SL_DONE_MASK 0x04
310 #define DPCD_STATUS_LANE_3_CR_DONE_MASK 0x10
311 #define DPCD_STATUS_LANE_3_CE_DONE_MASK 0x20
312 #define DPCD_STATUS_LANE_3_SL_DONE_MASK 0x40
313 /* 0x00204: LANE_ALIGN_STATUS_UPDATED */
314 #define DPCD_LANE_ALIGN_STATUS_UPDATED_IA_DONE_MASK \
315 0x01
316 #define DPCD_LANE_ALIGN_STATUS_UPDATED_DOWNSP_STATUS_CHANGED_MASK \
317 0x40
318 #define DPCD_LANE_ALIGN_STATUS_UPDATED_LINK_STATUS_UPDATED_MASK \
319 0x80
320 /* 0x00205: SINK_STATUS */
321 #define DPCD_SINK_STATUS_RX_PORT0_SYNC_STATUS_MASK 0x01
322 #define DPCD_SINK_STATUS_RX_PORT1_SYNC_STATUS_MASK 0x02
324 /* 0x00206, 0x00207: ADJ_REQ_LANE_[0,2]_[1,3] */
325 #define DPCD_ADJ_REQ_LANE_0_2_VS_MASK 0x03
326 #define DPCD_ADJ_REQ_LANE_0_2_PE_MASK 0x0C
327 #define DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT 2
328 #define DPCD_ADJ_REQ_LANE_1_3_VS_MASK 0x30
329 #define DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT 4
330 #define DPCD_ADJ_REQ_LANE_1_3_PE_MASK 0xC0
331 #define DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT 6
332 /* 0x0020C: ADJ_REQ_PC2 */
333 #define DPCD_ADJ_REQ_PC2_LANE_0_MASK 0x03
334 #define DPCD_ADJ_REQ_PC2_LANE_1_MASK 0x0C
335 #define DPCD_ADJ_REQ_PC2_LANE_1_SHIFT 2
336 #define DPCD_ADJ_REQ_PC2_LANE_2_MASK 0x30
337 #define DPCD_ADJ_REQ_PC2_LANE_2_SHIFT 4
338 #define DPCD_ADJ_REQ_PC2_LANE_3_MASK 0xC0
339 #define DPCD_ADJ_REQ_PC2_LANE_3_SHIFT 6