drivers/video/seps525.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * FB driver for the WiseChip Semiconductor Inc. (UG-6028GDEBF02) display
   4  * using the SEPS525 (Syncoam) LCD Controller
   5  *
   6  * Copyright (C) 2020 Xilinx Inc.
   7  */
   8
   9 #include <command.h>
  10 #include <cpu_func.h>
  11 #include <dm.h>
  12 #include <errno.h>
  13 #include <spi.h>
  14 #include <video.h>
  15 #include <asm/gpio.h>
  16 #include <dm/device_compat.h>
  17 #include <linux/delay.h>
  18
  19 #define WIDTH           160
  20 #define HEIGHT          128
  21
  22 #define SEPS525_INDEX                   0x00
  23 #define SEPS525_STATUS_RD               0x01
  24 #define SEPS525_OSC_CTL                 0x02
  25 #define SEPS525_IREF                    0x80
  26 #define SEPS525_CLOCK_DIV               0x03
  27 #define SEPS525_REDUCE_CURRENT          0x04
  28 #define SEPS525_SOFT_RST                0x05
  29 #define SEPS525_DISP_ONOFF              0x06
  30 #define SEPS525_PRECHARGE_TIME_R        0x08
  31 #define SEPS525_PRECHARGE_TIME_G        0x09
  32 #define SEPS525_PRECHARGE_TIME_B        0x0A
  33 #define SEPS525_PRECHARGE_CURRENT_R     0x0B
  34 #define SEPS525_PRECHARGE_CURRENT_G     0x0C
  35 #define SEPS525_PRECHARGE_CURRENT_B     0x0D
  36 #define SEPS525_DRIVING_CURRENT_R       0x10
  37 #define SEPS525_DRIVING_CURRENT_G       0x11
  38 #define SEPS525_DRIVING_CURRENT_B       0x12
  39 #define SEPS525_DISPLAYMODE_SET         0x13
  40 #define SEPS525_RGBIF                   0x14
  41 #define SEPS525_RGB_POL                 0x15
  42 #define SEPS525_MEMORY_WRITEMODE        0x16
  43 #define SEPS525_MX1_ADDR                0x17
  44 #define SEPS525_MX2_ADDR                0x18
  45 #define SEPS525_MY1_ADDR                0x19
  46 #define SEPS525_MY2_ADDR                0x1A
  47 #define SEPS525_MEMORY_ACCESS_POINTER_X 0x20
  48 #define SEPS525_MEMORY_ACCESS_POINTER_Y 0x21
  49 #define SEPS525_DDRAM_DATA_ACCESS_PORT  0x22
  50 #define SEPS525_GRAY_SCALE_TABLE_INDEX  0x50
  51 #define SEPS525_GRAY_SCALE_TABLE_DATA   0x51
  52 #define SEPS525_DUTY                    0x28
  53 #define SEPS525_DSL                     0x29
  54 #define SEPS525_D1_DDRAM_FAC            0x2E
  55 #define SEPS525_D1_DDRAM_FAR            0x2F
  56 #define SEPS525_D2_DDRAM_SAC            0x31
  57 #define SEPS525_D2_DDRAM_SAR            0x32
  58 #define SEPS525_SCR1_FX1                0x33
  59 #define SEPS525_SCR1_FX2                0x34
  60 #define SEPS525_SCR1_FY1                0x35
  61 #define SEPS525_SCR1_FY2                0x36
  62 #define SEPS525_SCR2_SX1                0x37
  63 #define SEPS525_SCR2_SX2                0x38
  64 #define SEPS525_SCR2_SY1                0x39
  65 #define SEPS525_SCR2_SY2                0x3A
  66 #define SEPS525_SCREEN_SAVER_CONTEROL   0x3B
  67 #define SEPS525_SS_SLEEP_TIMER          0x3C
  68 #define SEPS525_SCREEN_SAVER_MODE       0x3D
  69 #define SEPS525_SS_SCR1_FU              0x3E
  70 #define SEPS525_SS_SCR1_MXY             0x3F
  71 #define SEPS525_SS_SCR2_FU              0x40
  72 #define SEPS525_SS_SCR2_MXY             0x41
  73 #define SEPS525_MOVING_DIRECTION        0x42
  74 #define SEPS525_SS_SCR2_SX1             0x47
  75 #define SEPS525_SS_SCR2_SX2             0x48
  76 #define SEPS525_SS_SCR2_SY1             0x49
  77 #define SEPS525_SS_SCR2_SY2             0x4A
  78
  79 /* SEPS525_DISPLAYMODE_SET */
  80 #define MODE_SWAP_BGR   BIT(7)
  81 #define MODE_SM         BIT(6)
  82 #define MODE_RD         BIT(5)
  83 #define MODE_CD         BIT(4)
  84
  85 /**
  86  * struct seps525_priv - Private structure
  87  * @reset_gpio: Reset gpio pin
  88  * @dc_gpio: Data/command control gpio pin
  89  * @dev: Device uclass for video_ops
  90  */
  91 struct seps525_priv {
  92         struct gpio_desc reset_gpio;
  93         struct gpio_desc dc_gpio;
  94         struct udevice *dev;
  95 };
  96
  97 static int seps525_spi_write_cmd(struct udevice *dev, u32 reg)
  98 {
  99         struct seps525_priv *priv = dev_get_priv(dev);
 100         u8 buf8 = reg;
 101         int ret;
 102
 103         ret = dm_gpio_set_value(&priv->dc_gpio, 0);
 104         if (ret) {
 105                 dev_dbg(dev, "Failed to handle dc\n");
 106                 return ret;
 107         }
 108
 109         ret = dm_spi_xfer(dev, 8, &buf8, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
 110         if (ret)
 111                 dev_dbg(dev, "Failed to write command\n");
 112
 113         return ret;
 114 }
 115
 116 static int seps525_spi_write_data(struct udevice *dev, u32 val)
 117 {
 118         struct seps525_priv *priv = dev_get_priv(dev);
 119         u8 buf8 = val;
 120         int ret;
 121
 122         ret = dm_gpio_set_value(&priv->dc_gpio, 1);
 123         if (ret) {
 124                 dev_dbg(dev, "Failed to handle dc\n");
 125                 return ret;
 126         }
 127
 128         ret = dm_spi_xfer(dev, 8, &buf8, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
 129         if (ret)
 130                 dev_dbg(dev, "Failed to write data\n");
 131
 132         return ret;
 133 }
 134
 135 static void seps525_spi_write(struct udevice *dev, u32 reg, u32 val)
 136 {
 137         (void)seps525_spi_write_cmd(dev, reg);
 138         (void)seps525_spi_write_data(dev, val);
 139 }
 140
 141 static int seps525_display_init(struct udevice *dev)
 142 {
 143         /* Disable Oscillator Power Down */
 144         seps525_spi_write(dev, SEPS525_REDUCE_CURRENT, 0x03);
 145         mdelay(5);
 146
 147         /* Set Normal Driving Current */
 148         seps525_spi_write(dev, SEPS525_REDUCE_CURRENT, 0x00);
 149         mdelay(5);
 150
 151         seps525_spi_write(dev, SEPS525_SCREEN_SAVER_CONTEROL, 0x00);
 152         /* Set EXPORT1 Pin at Internal Clock */
 153         seps525_spi_write(dev, SEPS525_OSC_CTL, 0x01);
 154         /* Set Clock as 120 Frames/Sec */
 155         seps525_spi_write(dev, SEPS525_CLOCK_DIV, 0x90);
 156         /* Set Reference Voltage Controlled by External Resister */
 157         seps525_spi_write(dev, SEPS525_IREF, 0x01);
 158
 159         /* precharge time R G B */
 160         seps525_spi_write(dev, SEPS525_PRECHARGE_TIME_R, 0x04);
 161         seps525_spi_write(dev, SEPS525_PRECHARGE_TIME_G, 0x05);
 162         seps525_spi_write(dev, SEPS525_PRECHARGE_TIME_B, 0x05);
 163
 164         /* precharge current R G B (uA) */
 165         seps525_spi_write(dev, SEPS525_PRECHARGE_CURRENT_R, 0x9D);
 166         seps525_spi_write(dev, SEPS525_PRECHARGE_CURRENT_G, 0x8C);
 167         seps525_spi_write(dev, SEPS525_PRECHARGE_CURRENT_B, 0x57);
 168
 169         /* driving current R G B (uA) */
 170         seps525_spi_write(dev, SEPS525_DRIVING_CURRENT_R, 0x56);
 171         seps525_spi_write(dev, SEPS525_DRIVING_CURRENT_G, 0x4D);
 172         seps525_spi_write(dev, SEPS525_DRIVING_CURRENT_B, 0x46);
 173         /* Set Color Sequence */
 174         seps525_spi_write(dev, SEPS525_DISPLAYMODE_SET, 0x00);
 175         /* Set MCU Interface Mode */
 176         seps525_spi_write(dev, SEPS525_RGBIF, 0x01);
 177         /* Set Memory Write Mode */
 178         seps525_spi_write(dev, SEPS525_MEMORY_WRITEMODE, 0x66);
 179         /* 1/128 Duty (0x0F~0x7F) */
 180         seps525_spi_write(dev, SEPS525_DUTY, 0x7F);
 181         /* Set Mapping RAM Display Start Line (0x00~0x7F) */
 182         seps525_spi_write(dev, SEPS525_DSL, 0x00);
 183         /* Display On (0x00/0x01) */
 184         seps525_spi_write(dev, SEPS525_DISP_ONOFF, 0x01);
 185         /* Set All Internal Register Value as Normal Mode */
 186         seps525_spi_write(dev, SEPS525_SOFT_RST, 0x00);
 187         /* Set RGB Interface Polarity as Active Low */
 188         seps525_spi_write(dev, SEPS525_RGB_POL, 0x00);
 189
 190         /* Enable access for data */
 191         (void)seps525_spi_write_cmd(dev, SEPS525_DDRAM_DATA_ACCESS_PORT);
 192
 193         return 0;
 194 }
 195
 196 static int seps525_spi_startup(struct udevice *dev)
 197 {
 198         struct seps525_priv *priv = dev_get_priv(dev);
 199         int ret;
 200
 201         ret = dm_gpio_set_value(&priv->reset_gpio, 1);
 202         if (ret)
 203                 return ret;
 204
 205         ret = dm_gpio_set_value(&priv->reset_gpio, 0);
 206         if (ret)
 207                 return ret;
 208
 209         ret = dm_spi_claim_bus(dev);
 210         if (ret) {
 211                 dev_err(dev, "Failed to claim SPI bus: %d\n", ret);
 212                 return ret;
 213         }
 214
 215         ret = seps525_display_init(dev);
 216         if (ret)
 217                 return ret;
 218
 219         dm_spi_release_bus(dev);
 220
 221         return 0;
 222 }
 223
 224 static int seps525_sync(struct udevice *vid)
 225 {
 226         struct video_priv *uc_priv = dev_get_uclass_priv(vid);
 227         struct seps525_priv *priv = dev_get_priv(vid);
 228         struct udevice *dev = priv->dev;
 229         int i, ret;
 230         u8 data1, data2;
 231         u8 *start = uc_priv->fb;
 232
 233         ret = dm_spi_claim_bus(dev);
 234         if (ret) {
 235                 dev_err(dev, "Failed to claim SPI bus: %d\n", ret);
 236                 return ret;
 237         }
 238
 239         /* start position X,Y */
 240         seps525_spi_write(dev, SEPS525_MEMORY_ACCESS_POINTER_X, 0);
 241         seps525_spi_write(dev, SEPS525_MEMORY_ACCESS_POINTER_Y, 0);
 242
 243         /* Enable access for data */
 244         (void)seps525_spi_write_cmd(dev, SEPS525_DDRAM_DATA_ACCESS_PORT);
 245
 246         for (i = 0; i < (uc_priv->xsize * uc_priv->ysize); i++) {
 247                 data2 = *start++;
 248                 data1 = *start++;
 249                 (void)seps525_spi_write_data(dev, data1);
 250                 (void)seps525_spi_write_data(dev, data2);
 251         }
 252
 253         dm_spi_release_bus(dev);
 254
 255         return 0;
 256 }
 257
 258 static int seps525_probe(struct udevice *dev)
 259 {
 260         struct video_priv *uc_priv = dev_get_uclass_priv(dev);
 261         struct seps525_priv *priv = dev_get_priv(dev);
 262         u32 buswidth;
 263         int ret;
 264
 265         buswidth = dev_read_u32_default(dev, "buswidth", 0);
 266         if (buswidth != 8) {
 267                 dev_err(dev, "Only 8bit buswidth is supported now");
 268                 return -EINVAL;
 269         }
 270
 271         ret = gpio_request_by_name(dev, "reset-gpios", 0,
 272                                    &priv->reset_gpio, GPIOD_IS_OUT);
 273         if (ret) {
 274                 dev_err(dev, "missing reset GPIO\n");
 275                 return ret;
 276         }
 277
 278         ret = gpio_request_by_name(dev, "dc-gpios", 0,
 279                                    &priv->dc_gpio, GPIOD_IS_OUT);
 280         if (ret) {
 281                 dev_err(dev, "missing dc GPIO\n");
 282                 return ret;
 283         }
 284
 285         uc_priv->bpix = VIDEO_BPP16;
 286         uc_priv->xsize = WIDTH;
 287         uc_priv->ysize = HEIGHT;
 288         uc_priv->rot = 0;
 289
 290         priv->dev = dev;
 291
 292         ret = seps525_spi_startup(dev);
 293         if (ret)
 294                 return ret;
 295
 296         return 0;
 297 }
 298
 299 static int seps525_bind(struct udevice *dev)
 300 {
 301         struct video_uc_plat *plat = dev_get_uclass_plat(dev);
 302
 303         plat->size = WIDTH * HEIGHT * 16;
 304
 305         return 0;
 306 }
 307
 308 static const struct video_ops seps525_ops = {
 309         .video_sync = seps525_sync,
 310 };
 311
 312 static const struct udevice_id seps525_ids[] = {
 313         { .compatible = "syncoam,seps525" },
 314         { }
 315 };
 316
 317 U_BOOT_DRIVER(seps525_video) = {
 318         .name = "seps525_video",
 319         .id = UCLASS_VIDEO,
 320         .of_match = seps525_ids,
 321         .ops = &seps525_ops,
 322         .plat_auto = sizeof(struct video_uc_plat),
 323         .bind = seps525_bind,
 324         .probe = seps525_probe,
 325         .priv_auto = sizeof(struct seps525_priv),
 326 };