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arm: vf610: fix double iomux configuration for vf610twr board
[u-boot/qq2440-u-boot.git] / drivers / mmc / fsl_esdhc.c
blob7b146a360444b1a3f524aaf43c0be0eac76eb0aa
1 /*
2 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
3 * Andy Fleming
4 *
5 * Based vaguely on the pxa mmc code:
6 * (C) Copyright 2003
7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
8 *
9 * SPDX-License-Identifier: GPL-2.0+
10 */
11
12 #include <config.h>
13 #include <common.h>
14 #include <command.h>
15 #include <hwconfig.h>
16 #include <mmc.h>
17 #include <part.h>
18 #include <malloc.h>
19 #include <mmc.h>
20 #include <fsl_esdhc.h>
21 #include <fdt_support.h>
22 #include <asm/io.h>
23
24 DECLARE_GLOBAL_DATA_PTR;
25
26 struct fsl_esdhc {
27 uint dsaddr; /* SDMA system address register */
28 uint blkattr; /* Block attributes register */
29 uint cmdarg; /* Command argument register */
30 uint xfertyp; /* Transfer type register */
31 uint cmdrsp0; /* Command response 0 register */
32 uint cmdrsp1; /* Command response 1 register */
33 uint cmdrsp2; /* Command response 2 register */
34 uint cmdrsp3; /* Command response 3 register */
35 uint datport; /* Buffer data port register */
36 uint prsstat; /* Present state register */
37 uint proctl; /* Protocol control register */
38 uint sysctl; /* System Control Register */
39 uint irqstat; /* Interrupt status register */
40 uint irqstaten; /* Interrupt status enable register */
41 uint irqsigen; /* Interrupt signal enable register */
42 uint autoc12err; /* Auto CMD error status register */
43 uint hostcapblt; /* Host controller capabilities register */
44 uint wml; /* Watermark level register */
45 uint mixctrl; /* For USDHC */
46 char reserved1[4]; /* reserved */
47 uint fevt; /* Force event register */
48 uint admaes; /* ADMA error status register */
49 uint adsaddr; /* ADMA system address register */
50 char reserved2[160]; /* reserved */
51 uint hostver; /* Host controller version register */
52 char reserved3[4]; /* reserved */
53 uint dmaerraddr; /* DMA error address register */
54 char reserved4[4]; /* reserved */
55 uint dmaerrattr; /* DMA error attribute register */
56 char reserved5[4]; /* reserved */
57 uint hostcapblt2; /* Host controller capabilities register 2 */
58 char reserved6[8]; /* reserved */
59 uint tcr; /* Tuning control register */
60 char reserved7[28]; /* reserved */
61 uint sddirctl; /* SD direction control register */
62 char reserved8[712]; /* reserved */
63 uint scr; /* eSDHC control register */
64 };
65
66 /* Return the XFERTYP flags for a given command and data packet */
67 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
68 {
69 uint xfertyp = 0;
70
71 if (data) {
72 xfertyp |= XFERTYP_DPSEL;
73 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
74 xfertyp |= XFERTYP_DMAEN;
75 #endif
76 if (data->blocks > 1) {
77 xfertyp |= XFERTYP_MSBSEL;
78 xfertyp |= XFERTYP_BCEN;
79 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
80 xfertyp |= XFERTYP_AC12EN;
81 #endif
82 }
83
84 if (data->flags & MMC_DATA_READ)
85 xfertyp |= XFERTYP_DTDSEL;
86 }
87
88 if (cmd->resp_type & MMC_RSP_CRC)
89 xfertyp |= XFERTYP_CCCEN;
90 if (cmd->resp_type & MMC_RSP_OPCODE)
91 xfertyp |= XFERTYP_CICEN;
92 if (cmd->resp_type & MMC_RSP_136)
93 xfertyp |= XFERTYP_RSPTYP_136;
94 else if (cmd->resp_type & MMC_RSP_BUSY)
95 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
96 else if (cmd->resp_type & MMC_RSP_PRESENT)
97 xfertyp |= XFERTYP_RSPTYP_48;
98
99 #if defined(CONFIG_MX53) || defined(CONFIG_T4240QDS)
100 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
101 xfertyp |= XFERTYP_CMDTYP_ABORT;
102 #endif
103 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
104 }
105
106 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
107 /*
108 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
109 */
110 static void
111 esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
112 {
113 struct fsl_esdhc_cfg *cfg = mmc->priv;
114 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
115 uint blocks;
116 char *buffer;
117 uint databuf;
118 uint size;
119 uint irqstat;
120 uint timeout;
121
122 if (data->flags & MMC_DATA_READ) {
123 blocks = data->blocks;
124 buffer = data->dest;
125 while (blocks) {
126 timeout = PIO_TIMEOUT;
127 size = data->blocksize;
128 irqstat = esdhc_read32(&regs->irqstat);
129 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)
130 && --timeout);
131 if (timeout <= 0) {
132 printf("\nData Read Failed in PIO Mode.");
133 return;
134 }
135 while (size && (!(irqstat & IRQSTAT_TC))) {
136 udelay(100); /* Wait before last byte transfer complete */
137 irqstat = esdhc_read32(&regs->irqstat);
138 databuf = in_le32(&regs->datport);
139 *((uint *)buffer) = databuf;
140 buffer += 4;
141 size -= 4;
142 }
143 blocks--;
144 }
145 } else {
146 blocks = data->blocks;
147 buffer = (char *)data->src;
148 while (blocks) {
149 timeout = PIO_TIMEOUT;
150 size = data->blocksize;
151 irqstat = esdhc_read32(&regs->irqstat);
152 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)
153 && --timeout);
154 if (timeout <= 0) {
155 printf("\nData Write Failed in PIO Mode.");
156 return;
157 }
158 while (size && (!(irqstat & IRQSTAT_TC))) {
159 udelay(100); /* Wait before last byte transfer complete */
160 databuf = *((uint *)buffer);
161 buffer += 4;
162 size -= 4;
163 irqstat = esdhc_read32(&regs->irqstat);
164 out_le32(&regs->datport, databuf);
165 }
166 blocks--;
167 }
168 }
169 }
170 #endif
171
172 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
173 {
174 int timeout;
175 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
176 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
177 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
178 uint wml_value;
179
180 wml_value = data->blocksize/4;
181
182 if (data->flags & MMC_DATA_READ) {
183 if (wml_value > WML_RD_WML_MAX)
184 wml_value = WML_RD_WML_MAX_VAL;
185
186 esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
187 esdhc_write32(&regs->dsaddr, (u32)data->dest);
188 } else {
189 flush_dcache_range((ulong)data->src,
190 (ulong)data->src+data->blocks
191 *data->blocksize);
192
193 if (wml_value > WML_WR_WML_MAX)
194 wml_value = WML_WR_WML_MAX_VAL;
195 if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
196 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
197 return TIMEOUT;
198 }
199
200 esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
201 wml_value << 16);
202 esdhc_write32(&regs->dsaddr, (u32)data->src);
203 }
204 #else /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
205 if (!(data->flags & MMC_DATA_READ)) {
206 if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
207 printf("\nThe SD card is locked. "
208 "Can not write to a locked card.\n\n");
209 return TIMEOUT;
210 }
211 esdhc_write32(&regs->dsaddr, (u32)data->src);
212 } else
213 esdhc_write32(&regs->dsaddr, (u32)data->dest);
214 #endif /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
215
216 esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
217
218 /* Calculate the timeout period for data transactions */
219 /*
220 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
221 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
222 * So, Number of SD Clock cycles for 0.25sec should be minimum
223 * (SD Clock/sec * 0.25 sec) SD Clock cycles
224 * = (mmc->tran_speed * 1/4) SD Clock cycles
225 * As 1) >= 2)
226 * => (2^(timeout+13)) >= mmc->tran_speed * 1/4
227 * Taking log2 both the sides
228 * => timeout + 13 >= log2(mmc->tran_speed/4)
229 * Rounding up to next power of 2
230 * => timeout + 13 = log2(mmc->tran_speed/4) + 1
231 * => timeout + 13 = fls(mmc->tran_speed/4)
232 */
233 timeout = fls(mmc->tran_speed/4);
234 timeout -= 13;
235
236 if (timeout > 14)
237 timeout = 14;
238
239 if (timeout < 0)
240 timeout = 0;
241
242 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
243 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
244 timeout++;
245 #endif
246
247 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
248
249 return 0;
250 }
251
252 static void check_and_invalidate_dcache_range
253 (struct mmc_cmd *cmd,
254 struct mmc_data *data) {
255 unsigned start = (unsigned)data->dest ;
256 unsigned size = roundup(ARCH_DMA_MINALIGN,
257 data->blocks*data->blocksize);
258 unsigned end = start+size ;
259 invalidate_dcache_range(start, end);
260 }
261 /*
262 * Sends a command out on the bus. Takes the mmc pointer,
263 * a command pointer, and an optional data pointer.
264 */
265 static int
266 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
267 {
268 uint xfertyp;
269 uint irqstat;
270 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
271 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
272
273 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
274 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
275 return 0;
276 #endif
277
278 esdhc_write32(&regs->irqstat, -1);
279
280 sync();
281
282 /* Wait for the bus to be idle */
283 while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
284 (esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
285 ;
286
287 while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
288 ;
289
290 /* Wait at least 8 SD clock cycles before the next command */
291 /*
292 * Note: This is way more than 8 cycles, but 1ms seems to
293 * resolve timing issues with some cards
294 */
295 udelay(1000);
296
297 /* Set up for a data transfer if we have one */
298 if (data) {
299 int err;
300
301 err = esdhc_setup_data(mmc, data);
302 if(err)
303 return err;
304 }
305
306 /* Figure out the transfer arguments */
307 xfertyp = esdhc_xfertyp(cmd, data);
308
309 /* Mask all irqs */
310 esdhc_write32(&regs->irqsigen, 0);
311
312 /* Send the command */
313 esdhc_write32(&regs->cmdarg, cmd->cmdarg);
314 #if defined(CONFIG_FSL_USDHC)
315 esdhc_write32(&regs->mixctrl,
316 (esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F));
317 esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
318 #else
319 esdhc_write32(&regs->xfertyp, xfertyp);
320 #endif
321
322 /* Wait for the command to complete */
323 while (!(esdhc_read32(&regs->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
324 ;
325
326 irqstat = esdhc_read32(&regs->irqstat);
327
328 /* Reset CMD and DATA portions on error */
329 if (irqstat & (CMD_ERR | IRQSTAT_CTOE)) {
330 esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
331 SYSCTL_RSTC);
332 while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
333 ;
334
335 if (data) {
336 esdhc_write32(&regs->sysctl,
337 esdhc_read32(&regs->sysctl) |
338 SYSCTL_RSTD);
339 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
340 ;
341 }
342 }
343
344 if (irqstat & CMD_ERR)
345 return COMM_ERR;
346
347 if (irqstat & IRQSTAT_CTOE)
348 return TIMEOUT;
349
350 /* Workaround for ESDHC errata ENGcm03648 */
351 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
352 int timeout = 2500;
353
354 /* Poll on DATA0 line for cmd with busy signal for 250 ms */
355 while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
356 PRSSTAT_DAT0)) {
357 udelay(100);
358 timeout--;
359 }
360
361 if (timeout <= 0) {
362 printf("Timeout waiting for DAT0 to go high!\n");
363 return TIMEOUT;
364 }
365 }
366
367 /* Copy the response to the response buffer */
368 if (cmd->resp_type & MMC_RSP_136) {
369 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
370
371 cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
372 cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
373 cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
374 cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
375 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
376 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
377 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
378 cmd->response[3] = (cmdrsp0 << 8);
379 } else
380 cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
381
382 /* Wait until all of the blocks are transferred */
383 if (data) {
384 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
385 esdhc_pio_read_write(mmc, data);
386 #else
387 do {
388 irqstat = esdhc_read32(&regs->irqstat);
389
390 if (irqstat & IRQSTAT_DTOE)
391 return TIMEOUT;
392
393 if (irqstat & DATA_ERR)
394 return COMM_ERR;
395 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
396 #endif
397 if (data->flags & MMC_DATA_READ)
398 check_and_invalidate_dcache_range(cmd, data);
399 }
400
401 esdhc_write32(&regs->irqstat, -1);
402
403 return 0;
404 }
405
406 static void set_sysctl(struct mmc *mmc, uint clock)
407 {
408 int div, pre_div;
409 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
410 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
411 int sdhc_clk = cfg->sdhc_clk;
412 uint clk;
413
414 if (clock < mmc->f_min)
415 clock = mmc->f_min;
416
417 if (sdhc_clk / 16 > clock) {
418 for (pre_div = 2; pre_div < 256; pre_div *= 2)
419 if ((sdhc_clk / pre_div) <= (clock * 16))
420 break;
421 } else
422 pre_div = 2;
423
424 for (div = 1; div <= 16; div++)
425 if ((sdhc_clk / (div * pre_div)) <= clock)
426 break;
427
428 pre_div >>= 1;
429 div -= 1;
430
431 clk = (pre_div << 8) | (div << 4);
432
433 esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
434
435 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
436
437 udelay(10000);
438
439 clk = SYSCTL_PEREN | SYSCTL_CKEN;
440
441 esdhc_setbits32(&regs->sysctl, clk);
442 }
443
444 static void esdhc_set_ios(struct mmc *mmc)
445 {
446 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
447 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
448
449 /* Set the clock speed */
450 set_sysctl(mmc, mmc->clock);
451
452 /* Set the bus width */
453 esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
454
455 if (mmc->bus_width == 4)
456 esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
457 else if (mmc->bus_width == 8)
458 esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
459
460 }
461
462 static int esdhc_init(struct mmc *mmc)
463 {
464 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
465 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
466 int timeout = 1000;
467
468 /* Reset the entire host controller */
469 esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
470
471 /* Wait until the controller is available */
472 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
473 udelay(1000);
474
475 #ifndef ARCH_MXC
476 /* Enable cache snooping */
477 esdhc_write32(&regs->scr, 0x00000040);
478 #endif
479
480 esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
481
482 /* Set the initial clock speed */
483 mmc_set_clock(mmc, 400000);
484
485 /* Disable the BRR and BWR bits in IRQSTAT */
486 esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
487
488 /* Put the PROCTL reg back to the default */
489 esdhc_write32(&regs->proctl, PROCTL_INIT);
490
491 /* Set timout to the maximum value */
492 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
493
494 return 0;
495 }
496
497 static int esdhc_getcd(struct mmc *mmc)
498 {
499 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
500 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
501 int timeout = 1000;
502
503 #ifdef CONFIG_ESDHC_DETECT_QUIRK
504 if (CONFIG_ESDHC_DETECT_QUIRK)
505 return 1;
506 #endif
507 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
508 udelay(1000);
509
510 return timeout > 0;
511 }
512
513 static void esdhc_reset(struct fsl_esdhc *regs)
514 {
515 unsigned long timeout = 100; /* wait max 100 ms */
516
517 /* reset the controller */
518 esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
519
520 /* hardware clears the bit when it is done */
521 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
522 udelay(1000);
523 if (!timeout)
524 printf("MMC/SD: Reset never completed.\n");
525 }
526
527 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
528 {
529 struct fsl_esdhc *regs;
530 struct mmc *mmc;
531 u32 caps, voltage_caps;
532
533 if (!cfg)
534 return -1;
535
536 mmc = malloc(sizeof(struct mmc));
537 if (!mmc)
538 return -ENOMEM;
539
540 memset(mmc, 0, sizeof(struct mmc));
541 sprintf(mmc->name, "FSL_SDHC");
542 regs = (struct fsl_esdhc *)cfg->esdhc_base;
543
544 /* First reset the eSDHC controller */
545 esdhc_reset(regs);
546
547 esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
548 | SYSCTL_IPGEN | SYSCTL_CKEN);
549
550 mmc->priv = cfg;
551 mmc->send_cmd = esdhc_send_cmd;
552 mmc->set_ios = esdhc_set_ios;
553 mmc->init = esdhc_init;
554 mmc->getcd = esdhc_getcd;
555 mmc->getwp = NULL;
556
557 voltage_caps = 0;
558 caps = regs->hostcapblt;
559
560 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
561 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
562 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
563 #endif
564
565 /* T4240 host controller capabilities register should have VS33 bit */
566 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
567 caps = caps | ESDHC_HOSTCAPBLT_VS33;
568 #endif
569
570 if (caps & ESDHC_HOSTCAPBLT_VS18)
571 voltage_caps |= MMC_VDD_165_195;
572 if (caps & ESDHC_HOSTCAPBLT_VS30)
573 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
574 if (caps & ESDHC_HOSTCAPBLT_VS33)
575 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
576
577 #ifdef CONFIG_SYS_SD_VOLTAGE
578 mmc->voltages = CONFIG_SYS_SD_VOLTAGE;
579 #else
580 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
581 #endif
582 if ((mmc->voltages & voltage_caps) == 0) {
583 printf("voltage not supported by controller\n");
584 return -1;
585 }
586
587 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC;
588
589 if (cfg->max_bus_width > 0) {
590 if (cfg->max_bus_width < 8)
591 mmc->host_caps &= ~MMC_MODE_8BIT;
592 if (cfg->max_bus_width < 4)
593 mmc->host_caps &= ~MMC_MODE_4BIT;
594 }
595
596 if (caps & ESDHC_HOSTCAPBLT_HSS)
597 mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
598
599 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
600 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
601 mmc->host_caps &= ~MMC_MODE_8BIT;
602 #endif
603
604 mmc->f_min = 400000;
605 mmc->f_max = MIN(gd->arch.sdhc_clk, 52000000);
606
607 mmc->b_max = 0;
608 mmc_register(mmc);
609
610 return 0;
611 }
612
613 int fsl_esdhc_mmc_init(bd_t *bis)
614 {
615 struct fsl_esdhc_cfg *cfg;
616
617 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
618 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
619 cfg->sdhc_clk = gd->arch.sdhc_clk;
620 return fsl_esdhc_initialize(bis, cfg);
621 }
622
623 #ifdef CONFIG_OF_LIBFDT
624 void fdt_fixup_esdhc(void *blob, bd_t *bd)
625 {
626 const char *compat = "fsl,esdhc";
627
628 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
629 if (!hwconfig("esdhc")) {
630 do_fixup_by_compat(blob, compat, "status", "disabled",
631 8 + 1, 1);
632 return;
633 }
634 #endif
635
636 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
637 gd->arch.sdhc_clk, 1);
638
639 do_fixup_by_compat(blob, compat, "status", "okay",
640 4 + 1, 1);
641 }
642 #endif
u-boot for qq2440