arm: vf610: fix double iomux configuration for vf610twr board
[u-boot/qq2440-u-boot.git] / drivers / mmc / s5p_sdhci.c
blobccae4ccae15638410eb73c9766ee07467164f0a4
1 /*
2 * (C) Copyright 2012 SAMSUNG Electronics
3 * Jaehoon Chung <jh80.chung@samsung.com>
5 * SPDX-License-Identifier: GPL-2.0+
6 */
8 #include <common.h>
9 #include <malloc.h>
10 #include <sdhci.h>
11 #include <fdtdec.h>
12 #include <libfdt.h>
13 #include <asm/gpio.h>
14 #include <asm/arch/mmc.h>
15 #include <asm/arch/clk.h>
16 #include <errno.h>
17 #ifdef CONFIG_OF_CONTROL
18 #include <asm/arch/pinmux.h>
19 #endif
21 static char *S5P_NAME = "SAMSUNG SDHCI";
22 static void s5p_sdhci_set_control_reg(struct sdhci_host *host)
24 unsigned long val, ctrl;
26 * SELCLKPADDS[17:16]
27 * 00 = 2mA
28 * 01 = 4mA
29 * 10 = 7mA
30 * 11 = 9mA
32 sdhci_writel(host, SDHCI_CTRL4_DRIVE_MASK(0x3), SDHCI_CONTROL4);
34 val = sdhci_readl(host, SDHCI_CONTROL2);
35 val &= SDHCI_CTRL2_SELBASECLK_SHIFT;
37 val |= SDHCI_CTRL2_ENSTAASYNCCLR |
38 SDHCI_CTRL2_ENCMDCNFMSK |
39 SDHCI_CTRL2_ENFBCLKRX |
40 SDHCI_CTRL2_ENCLKOUTHOLD;
42 sdhci_writel(host, val, SDHCI_CONTROL2);
45 * FCSEL3[31] FCSEL2[23] FCSEL1[15] FCSEL0[7]
46 * FCSel[1:0] : Rx Feedback Clock Delay Control
47 * Inverter delay means10ns delay if SDCLK 50MHz setting
48 * 01 = Delay1 (basic delay)
49 * 11 = Delay2 (basic delay + 2ns)
50 * 00 = Delay3 (inverter delay)
51 * 10 = Delay4 (inverter delay + 2ns)
53 val = SDHCI_CTRL3_FCSEL0 | SDHCI_CTRL3_FCSEL1;
54 sdhci_writel(host, val, SDHCI_CONTROL3);
57 * SELBASECLK[5:4]
58 * 00/01 = HCLK
59 * 10 = EPLL
60 * 11 = XTI or XEXTCLK
62 ctrl = sdhci_readl(host, SDHCI_CONTROL2);
63 ctrl &= ~SDHCI_CTRL2_SELBASECLK_MASK(0x3);
64 ctrl |= SDHCI_CTRL2_SELBASECLK_MASK(0x2);
65 sdhci_writel(host, ctrl, SDHCI_CONTROL2);
68 int s5p_sdhci_init(u32 regbase, int index, int bus_width)
70 struct sdhci_host *host = NULL;
71 host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
72 if (!host) {
73 printf("sdhci__host malloc fail!\n");
74 return 1;
77 host->name = S5P_NAME;
78 host->ioaddr = (void *)regbase;
80 host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE |
81 SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR |
82 SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_USE_WIDE8;
83 host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
84 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
86 host->set_control_reg = &s5p_sdhci_set_control_reg;
87 host->set_clock = set_mmc_clk;
88 host->index = index;
90 host->host_caps = MMC_MODE_HC;
91 if (bus_width == 8)
92 host->host_caps |= MMC_MODE_8BIT;
94 return add_sdhci(host, 52000000, 400000);
97 #ifdef CONFIG_OF_CONTROL
98 struct sdhci_host sdhci_host[SDHCI_MAX_HOSTS];
100 static int do_sdhci_init(struct sdhci_host *host)
102 int dev_id, flag;
103 int err = 0;
105 flag = host->bus_width == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
106 dev_id = host->index + PERIPH_ID_SDMMC0;
108 if (fdt_gpio_isvalid(&host->pwr_gpio)) {
109 gpio_direction_output(host->pwr_gpio.gpio, 1);
110 err = exynos_pinmux_config(dev_id, flag);
111 if (err) {
112 debug("MMC not configured\n");
113 return err;
117 if (fdt_gpio_isvalid(&host->cd_gpio)) {
118 gpio_direction_output(host->cd_gpio.gpio, 0xf);
119 if (gpio_get_value(host->cd_gpio.gpio))
120 return -ENODEV;
122 err = exynos_pinmux_config(dev_id, flag);
123 if (err) {
124 printf("external SD not configured\n");
125 return err;
129 host->name = S5P_NAME;
131 host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE |
132 SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR |
133 SDHCI_QUIRK_WAIT_SEND_CMD;
134 host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
135 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
137 host->set_control_reg = &s5p_sdhci_set_control_reg;
138 host->set_clock = set_mmc_clk;
140 host->host_caps = MMC_MODE_HC;
142 return add_sdhci(host, 52000000, 400000);
145 static int sdhci_get_config(const void *blob, int node, struct sdhci_host *host)
147 int bus_width, dev_id;
148 unsigned int base;
150 /* Get device id */
151 dev_id = pinmux_decode_periph_id(blob, node);
152 if (dev_id < PERIPH_ID_SDMMC0 && dev_id > PERIPH_ID_SDMMC3) {
153 debug("MMC: Can't get device id\n");
154 return -1;
156 host->index = dev_id - PERIPH_ID_SDMMC0;
158 /* Get bus width */
159 bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
160 if (bus_width <= 0) {
161 debug("MMC: Can't get bus-width\n");
162 return -1;
164 host->bus_width = bus_width;
166 /* Get the base address from the device node */
167 base = fdtdec_get_addr(blob, node, "reg");
168 if (!base) {
169 debug("MMC: Can't get base address\n");
170 return -1;
172 host->ioaddr = (void *)base;
174 fdtdec_decode_gpio(blob, node, "pwr-gpios", &host->pwr_gpio);
175 fdtdec_decode_gpio(blob, node, "cd-gpios", &host->cd_gpio);
177 return 0;
180 static int process_nodes(const void *blob, int node_list[], int count)
182 struct sdhci_host *host;
183 int i, node;
185 debug("%s: count = %d\n", __func__, count);
187 /* build sdhci_host[] for each controller */
188 for (i = 0; i < count; i++) {
189 node = node_list[i];
190 if (node <= 0)
191 continue;
193 host = &sdhci_host[i];
195 if (sdhci_get_config(blob, node, host)) {
196 printf("%s: failed to decode dev %d\n", __func__, i);
197 return -1;
199 do_sdhci_init(host);
201 return 0;
204 int exynos_mmc_init(const void *blob)
206 int count;
207 int node_list[SDHCI_MAX_HOSTS];
209 count = fdtdec_find_aliases_for_id(blob, "mmc",
210 COMPAT_SAMSUNG_EXYNOS_MMC, node_list,
211 SDHCI_MAX_HOSTS);
213 process_nodes(blob, node_list, count);
215 return 1;
217 #endif