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[u-boot/qq2440-u-boot.git] / drivers / usb / host / xhci.c
blobd1c2e5c4551ada7521f077c16e6a8525a2aef5e3
1 /*
2 * USB HOST XHCI Controller stack
3 *
4 * Based on xHCI host controller driver in linux-kernel
5 * by Sarah Sharp.
6 *
7 * Copyright (C) 2008 Intel Corp.
8 * Author: Sarah Sharp
9 *
10 * Copyright (C) 2013 Samsung Electronics Co.Ltd
11 * Authors: Vivek Gautam <gautam.vivek@samsung.com>
12 * Vikas Sajjan <vikas.sajjan@samsung.com>
13 *
14 * SPDX-License-Identifier: GPL-2.0+
15 */
16
17 /**
18 * This file gives the xhci stack for usb3.0 looking into
19 * xhci specification Rev1.0 (5/21/10).
20 * The quirk devices support hasn't been given yet.
21 */
22
23 #include <common.h>
24 #include <asm/byteorder.h>
25 #include <usb.h>
26 #include <malloc.h>
27 #include <watchdog.h>
28 #include <asm/cache.h>
29 #include <asm/unaligned.h>
30 #include <asm-generic/errno.h>
31 #include "xhci.h"
32
33 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
34 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
35 #endif
36
37 static struct descriptor {
38 struct usb_hub_descriptor hub;
39 struct usb_device_descriptor device;
40 struct usb_config_descriptor config;
41 struct usb_interface_descriptor interface;
42 struct usb_endpoint_descriptor endpoint;
43 struct usb_ss_ep_comp_descriptor ep_companion;
44 } __attribute__ ((packed)) descriptor = {
45 {
46 0xc, /* bDescLength */
47 0x2a, /* bDescriptorType: hub descriptor */
48 2, /* bNrPorts -- runtime modified */
49 cpu_to_le16(0x8), /* wHubCharacteristics */
50 10, /* bPwrOn2PwrGood */
51 0, /* bHubCntrCurrent */
52 {}, /* Device removable */
53 {} /* at most 7 ports! XXX */
54 },
55 {
56 0x12, /* bLength */
57 1, /* bDescriptorType: UDESC_DEVICE */
58 cpu_to_le16(0x0300), /* bcdUSB: v3.0 */
59 9, /* bDeviceClass: UDCLASS_HUB */
60 0, /* bDeviceSubClass: UDSUBCLASS_HUB */
61 3, /* bDeviceProtocol: UDPROTO_SSHUBSTT */
62 9, /* bMaxPacketSize: 512 bytes 2^9 */
63 0x0000, /* idVendor */
64 0x0000, /* idProduct */
65 cpu_to_le16(0x0100), /* bcdDevice */
66 1, /* iManufacturer */
67 2, /* iProduct */
68 0, /* iSerialNumber */
69 1 /* bNumConfigurations: 1 */
70 },
71 {
72 0x9,
73 2, /* bDescriptorType: UDESC_CONFIG */
74 cpu_to_le16(0x1f), /* includes SS endpoint descriptor */
75 1, /* bNumInterface */
76 1, /* bConfigurationValue */
77 0, /* iConfiguration */
78 0x40, /* bmAttributes: UC_SELF_POWER */
79 0 /* bMaxPower */
80 },
81 {
82 0x9, /* bLength */
83 4, /* bDescriptorType: UDESC_INTERFACE */
84 0, /* bInterfaceNumber */
85 0, /* bAlternateSetting */
86 1, /* bNumEndpoints */
87 9, /* bInterfaceClass: UICLASS_HUB */
88 0, /* bInterfaceSubClass: UISUBCLASS_HUB */
89 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
90 0 /* iInterface */
91 },
92 {
93 0x7, /* bLength */
94 5, /* bDescriptorType: UDESC_ENDPOINT */
95 0x81, /* bEndpointAddress: IN endpoint 1 */
96 3, /* bmAttributes: UE_INTERRUPT */
97 8, /* wMaxPacketSize */
98 255 /* bInterval */
99 },
100 {
101 0x06, /* ss_bLength */
102 0x30, /* ss_bDescriptorType: SS EP Companion */
103 0x00, /* ss_bMaxBurst: allows 1 TX between ACKs */
104 /* ss_bmAttributes: 1 packet per service interval */
105 0x00,
106 /* ss_wBytesPerInterval: 15 bits for max 15 ports */
107 cpu_to_le16(0x02),
108 },
109 };
110
111 static struct xhci_ctrl xhcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
112
113 /**
114 * Waits for as per specified amount of time
115 * for the "result" to match with "done"
116 *
117 * @param ptr pointer to the register to be read
118 * @param mask mask for the value read
119 * @param done value to be campared with result
120 * @param usec time to wait till
121 * @return 0 if handshake is success else < 0 on failure
122 */
123 static int handshake(uint32_t volatile *ptr, uint32_t mask,
124 uint32_t done, int usec)
125 {
126 uint32_t result;
127
128 do {
129 result = xhci_readl(ptr);
130 if (result == ~(uint32_t)0)
131 return -ENODEV;
132 result &= mask;
133 if (result == done)
134 return 0;
135 usec--;
136 udelay(1);
137 } while (usec > 0);
138
139 return -ETIMEDOUT;
140 }
141
142 /**
143 * Set the run bit and wait for the host to be running.
144 *
145 * @param hcor pointer to host controller operation registers
146 * @return status of the Handshake
147 */
148 static int xhci_start(struct xhci_hcor *hcor)
149 {
150 u32 temp;
151 int ret;
152
153 puts("Starting the controller\n");
154 temp = xhci_readl(&hcor->or_usbcmd);
155 temp |= (CMD_RUN);
156 xhci_writel(&hcor->or_usbcmd, temp);
157
158 /*
159 * Wait for the HCHalted Status bit to be 0 to indicate the host is
160 * running.
161 */
162 ret = handshake(&hcor->or_usbsts, STS_HALT, 0, XHCI_MAX_HALT_USEC);
163 if (ret)
164 debug("Host took too long to start, "
165 "waited %u microseconds.\n",
166 XHCI_MAX_HALT_USEC);
167 return ret;
168 }
169
170 /**
171 * Resets the XHCI Controller
172 *
173 * @param hcor pointer to host controller operation registers
174 * @return -EBUSY if XHCI Controller is not halted else status of handshake
175 */
176 int xhci_reset(struct xhci_hcor *hcor)
177 {
178 u32 cmd;
179 u32 state;
180 int ret;
181
182 /* Halting the Host first */
183 debug("// Halt the HC\n");
184 state = xhci_readl(&hcor->or_usbsts) & STS_HALT;
185 if (!state) {
186 cmd = xhci_readl(&hcor->or_usbcmd);
187 cmd &= ~CMD_RUN;
188 xhci_writel(&hcor->or_usbcmd, cmd);
189 }
190
191 ret = handshake(&hcor->or_usbsts,
192 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
193 if (ret) {
194 printf("Host not halted after %u microseconds.\n",
195 XHCI_MAX_HALT_USEC);
196 return -EBUSY;
197 }
198
199 debug("// Reset the HC\n");
200 cmd = xhci_readl(&hcor->or_usbcmd);
201 cmd |= CMD_RESET;
202 xhci_writel(&hcor->or_usbcmd, cmd);
203
204 ret = handshake(&hcor->or_usbcmd, CMD_RESET, 0, XHCI_MAX_RESET_USEC);
205 if (ret)
206 return ret;
207
208 /*
209 * xHCI cannot write to any doorbells or operational registers other
210 * than status until the "Controller Not Ready" flag is cleared.
211 */
212 return handshake(&hcor->or_usbsts, STS_CNR, 0, XHCI_MAX_RESET_USEC);
213 }
214
215 /**
216 * Used for passing endpoint bitmasks between the core and HCDs.
217 * Find the index for an endpoint given its descriptor.
218 * Use the return value to right shift 1 for the bitmask.
219 *
220 * Index = (epnum * 2) + direction - 1,
221 * where direction = 0 for OUT, 1 for IN.
222 * For control endpoints, the IN index is used (OUT index is unused), so
223 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
224 *
225 * @param desc USB enpdoint Descriptor
226 * @return index of the Endpoint
227 */
228 static unsigned int xhci_get_ep_index(struct usb_endpoint_descriptor *desc)
229 {
230 unsigned int index;
231
232 if (usb_endpoint_xfer_control(desc))
233 index = (unsigned int)(usb_endpoint_num(desc) * 2);
234 else
235 index = (unsigned int)((usb_endpoint_num(desc) * 2) -
236 (usb_endpoint_dir_in(desc) ? 0 : 1));
237
238 return index;
239 }
240
241 /**
242 * Issue a configure endpoint command or evaluate context command
243 * and wait for it to finish.
244 *
245 * @param udev pointer to the Device Data Structure
246 * @param ctx_change flag to indicate the Context has changed or NOT
247 * @return 0 on success, -1 on failure
248 */
249 static int xhci_configure_endpoints(struct usb_device *udev, bool ctx_change)
250 {
251 struct xhci_container_ctx *in_ctx;
252 struct xhci_virt_device *virt_dev;
253 struct xhci_ctrl *ctrl = udev->controller;
254 union xhci_trb *event;
255
256 virt_dev = ctrl->devs[udev->slot_id];
257 in_ctx = virt_dev->in_ctx;
258
259 xhci_flush_cache((uint32_t)in_ctx->bytes, in_ctx->size);
260 xhci_queue_command(ctrl, in_ctx->bytes, udev->slot_id, 0,
261 ctx_change ? TRB_EVAL_CONTEXT : TRB_CONFIG_EP);
262 event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
263 BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
264 != udev->slot_id);
265
266 switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) {
267 case COMP_SUCCESS:
268 debug("Successful %s command\n",
269 ctx_change ? "Evaluate Context" : "Configure Endpoint");
270 break;
271 default:
272 printf("ERROR: %s command returned completion code %d.\n",
273 ctx_change ? "Evaluate Context" : "Configure Endpoint",
274 GET_COMP_CODE(le32_to_cpu(event->event_cmd.status)));
275 return -EINVAL;
276 }
277
278 xhci_acknowledge_event(ctrl);
279
280 return 0;
281 }
282
283 /**
284 * Configure the endpoint, programming the device contexts.
285 *
286 * @param udev pointer to the USB device structure
287 * @return returns the status of the xhci_configure_endpoints
288 */
289 static int xhci_set_configuration(struct usb_device *udev)
290 {
291 struct xhci_container_ctx *in_ctx;
292 struct xhci_container_ctx *out_ctx;
293 struct xhci_input_control_ctx *ctrl_ctx;
294 struct xhci_slot_ctx *slot_ctx;
295 struct xhci_ep_ctx *ep_ctx[MAX_EP_CTX_NUM];
296 int cur_ep;
297 int max_ep_flag = 0;
298 int ep_index;
299 unsigned int dir;
300 unsigned int ep_type;
301 struct xhci_ctrl *ctrl = udev->controller;
302 int num_of_ep;
303 int ep_flag = 0;
304 u64 trb_64 = 0;
305 int slot_id = udev->slot_id;
306 struct xhci_virt_device *virt_dev = ctrl->devs[slot_id];
307 struct usb_interface *ifdesc;
308
309 out_ctx = virt_dev->out_ctx;
310 in_ctx = virt_dev->in_ctx;
311
312 num_of_ep = udev->config.if_desc[0].no_of_ep;
313 ifdesc = &udev->config.if_desc[0];
314
315 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
316 /* Zero the input context control */
317 ctrl_ctx->add_flags = 0;
318 ctrl_ctx->drop_flags = 0;
319
320 /* EP_FLAG gives values 1 & 4 for EP1OUT and EP2IN */
321 for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) {
322 ep_flag = xhci_get_ep_index(&ifdesc->ep_desc[cur_ep]);
323 ctrl_ctx->add_flags |= cpu_to_le32(1 << (ep_flag + 1));
324 if (max_ep_flag < ep_flag)
325 max_ep_flag = ep_flag;
326 }
327
328 xhci_inval_cache((uint32_t)out_ctx->bytes, out_ctx->size);
329
330 /* slot context */
331 xhci_slot_copy(ctrl, in_ctx, out_ctx);
332 slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx);
333 slot_ctx->dev_info &= ~(LAST_CTX_MASK);
334 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(max_ep_flag + 1) | 0);
335
336 xhci_endpoint_copy(ctrl, in_ctx, out_ctx, 0);
337
338 /* filling up ep contexts */
339 for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) {
340 struct usb_endpoint_descriptor *endpt_desc = NULL;
341
342 endpt_desc = &ifdesc->ep_desc[cur_ep];
343 trb_64 = 0;
344
345 ep_index = xhci_get_ep_index(endpt_desc);
346 ep_ctx[ep_index] = xhci_get_ep_ctx(ctrl, in_ctx, ep_index);
347
348 /* Allocate the ep rings */
349 virt_dev->eps[ep_index].ring = xhci_ring_alloc(1, true);
350 if (!virt_dev->eps[ep_index].ring)
351 return -ENOMEM;
352
353 /*NOTE: ep_desc[0] actually represents EP1 and so on */
354 dir = (((endpt_desc->bEndpointAddress) & (0x80)) >> 7);
355 ep_type = (((endpt_desc->bmAttributes) & (0x3)) | (dir << 2));
356 ep_ctx[ep_index]->ep_info2 =
357 cpu_to_le32(ep_type << EP_TYPE_SHIFT);
358 ep_ctx[ep_index]->ep_info2 |=
359 cpu_to_le32(MAX_PACKET
360 (get_unaligned(&endpt_desc->wMaxPacketSize)));
361
362 ep_ctx[ep_index]->ep_info2 |=
363 cpu_to_le32(((0 & MAX_BURST_MASK) << MAX_BURST_SHIFT) |
364 ((3 & ERROR_COUNT_MASK) << ERROR_COUNT_SHIFT));
365
366 trb_64 = (uintptr_t)
367 virt_dev->eps[ep_index].ring->enqueue;
368 ep_ctx[ep_index]->deq = cpu_to_le64(trb_64 |
369 virt_dev->eps[ep_index].ring->cycle_state);
370 }
371
372 return xhci_configure_endpoints(udev, false);
373 }
374
375 /**
376 * Issue an Address Device command (which will issue a SetAddress request to
377 * the device).
378 *
379 * @param udev pointer to the Device Data Structure
380 * @return 0 if successful else error code on failure
381 */
382 static int xhci_address_device(struct usb_device *udev)
383 {
384 int ret = 0;
385 struct xhci_ctrl *ctrl = udev->controller;
386 struct xhci_slot_ctx *slot_ctx;
387 struct xhci_input_control_ctx *ctrl_ctx;
388 struct xhci_virt_device *virt_dev;
389 int slot_id = udev->slot_id;
390 union xhci_trb *event;
391
392 virt_dev = ctrl->devs[slot_id];
393
394 /*
395 * This is the first Set Address since device plug-in
396 * so setting up the slot context.
397 */
398 debug("Setting up addressable devices\n");
399 xhci_setup_addressable_virt_dev(udev);
400
401 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
402 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
403 ctrl_ctx->drop_flags = 0;
404
405 xhci_queue_command(ctrl, (void *)ctrl_ctx, slot_id, 0, TRB_ADDR_DEV);
406 event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
407 BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags)) != slot_id);
408
409 switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) {
410 case COMP_CTX_STATE:
411 case COMP_EBADSLT:
412 printf("Setup ERROR: address device command for slot %d.\n",
413 slot_id);
414 ret = -EINVAL;
415 break;
416 case COMP_TX_ERR:
417 puts("Device not responding to set address.\n");
418 ret = -EPROTO;
419 break;
420 case COMP_DEV_ERR:
421 puts("ERROR: Incompatible device"
422 "for address device command.\n");
423 ret = -ENODEV;
424 break;
425 case COMP_SUCCESS:
426 debug("Successful Address Device command\n");
427 udev->status = 0;
428 break;
429 default:
430 printf("ERROR: unexpected command completion code 0x%x.\n",
431 GET_COMP_CODE(le32_to_cpu(event->event_cmd.status)));
432 ret = -EINVAL;
433 break;
434 }
435
436 xhci_acknowledge_event(ctrl);
437
438 if (ret < 0)
439 /*
440 * TODO: Unsuccessful Address Device command shall leave the
441 * slot in default state. So, issue Disable Slot command now.
442 */
443 return ret;
444
445 xhci_inval_cache((uint32_t)virt_dev->out_ctx->bytes,
446 virt_dev->out_ctx->size);
447 slot_ctx = xhci_get_slot_ctx(ctrl, virt_dev->out_ctx);
448
449 debug("xHC internal address is: %d\n",
450 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
451
452 return 0;
453 }
454
455 /**
456 * Issue Enable slot command to the controller to allocate
457 * device slot and assign the slot id. It fails if the xHC
458 * ran out of device slots, the Enable Slot command timed out,
459 * or allocating memory failed.
460 *
461 * @param udev pointer to the Device Data Structure
462 * @return Returns 0 on succes else return error code on failure
463 */
464 int usb_alloc_device(struct usb_device *udev)
465 {
466 union xhci_trb *event;
467 struct xhci_ctrl *ctrl = udev->controller;
468 int ret;
469
470 /*
471 * Root hub will be first device to be initailized.
472 * If this device is root-hub, don't do any xHC related
473 * stuff.
474 */
475 if (ctrl->rootdev == 0) {
476 udev->speed = USB_SPEED_SUPER;
477 return 0;
478 }
479
480 xhci_queue_command(ctrl, NULL, 0, 0, TRB_ENABLE_SLOT);
481 event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
482 BUG_ON(GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))
483 != COMP_SUCCESS);
484
485 udev->slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags));
486
487 xhci_acknowledge_event(ctrl);
488
489 ret = xhci_alloc_virt_device(udev);
490 if (ret < 0) {
491 /*
492 * TODO: Unsuccessful Address Device command shall leave
493 * the slot in default. So, issue Disable Slot command now.
494 */
495 puts("Could not allocate xHCI USB device data structures\n");
496 return ret;
497 }
498
499 return 0;
500 }
501
502 /*
503 * Full speed devices may have a max packet size greater than 8 bytes, but the
504 * USB core doesn't know that until it reads the first 8 bytes of the
505 * descriptor. If the usb_device's max packet size changes after that point,
506 * we need to issue an evaluate context command and wait on it.
507 *
508 * @param udev pointer to the Device Data Structure
509 * @return returns the status of the xhci_configure_endpoints
510 */
511 int xhci_check_maxpacket(struct usb_device *udev)
512 {
513 struct xhci_ctrl *ctrl = udev->controller;
514 unsigned int slot_id = udev->slot_id;
515 int ep_index = 0; /* control endpoint */
516 struct xhci_container_ctx *in_ctx;
517 struct xhci_container_ctx *out_ctx;
518 struct xhci_input_control_ctx *ctrl_ctx;
519 struct xhci_ep_ctx *ep_ctx;
520 int max_packet_size;
521 int hw_max_packet_size;
522 int ret = 0;
523 struct usb_interface *ifdesc;
524
525 ifdesc = &udev->config.if_desc[0];
526
527 out_ctx = ctrl->devs[slot_id]->out_ctx;
528 xhci_inval_cache((uint32_t)out_ctx->bytes, out_ctx->size);
529
530 ep_ctx = xhci_get_ep_ctx(ctrl, out_ctx, ep_index);
531 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
532 max_packet_size = usb_endpoint_maxp(&ifdesc->ep_desc[0]);
533 if (hw_max_packet_size != max_packet_size) {
534 debug("Max Packet Size for ep 0 changed.\n");
535 debug("Max packet size in usb_device = %d\n", max_packet_size);
536 debug("Max packet size in xHCI HW = %d\n", hw_max_packet_size);
537 debug("Issuing evaluate context command.\n");
538
539 /* Set up the modified control endpoint 0 */
540 xhci_endpoint_copy(ctrl, ctrl->devs[slot_id]->in_ctx,
541 ctrl->devs[slot_id]->out_ctx, ep_index);
542 in_ctx = ctrl->devs[slot_id]->in_ctx;
543 ep_ctx = xhci_get_ep_ctx(ctrl, in_ctx, ep_index);
544 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
545 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
546
547 /*
548 * Set up the input context flags for the command
549 * FIXME: This won't work if a non-default control endpoint
550 * changes max packet sizes.
551 */
552 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
553 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
554 ctrl_ctx->drop_flags = 0;
555
556 ret = xhci_configure_endpoints(udev, true);
557 }
558 return ret;
559 }
560
561 /**
562 * Clears the Change bits of the Port Status Register
563 *
564 * @param wValue request value
565 * @param wIndex request index
566 * @param addr address of posrt status register
567 * @param port_status state of port status register
568 * @return none
569 */
570 static void xhci_clear_port_change_bit(u16 wValue,
571 u16 wIndex, volatile uint32_t *addr, u32 port_status)
572 {
573 char *port_change_bit;
574 u32 status;
575
576 switch (wValue) {
577 case USB_PORT_FEAT_C_RESET:
578 status = PORT_RC;
579 port_change_bit = "reset";
580 break;
581 case USB_PORT_FEAT_C_CONNECTION:
582 status = PORT_CSC;
583 port_change_bit = "connect";
584 break;
585 case USB_PORT_FEAT_C_OVER_CURRENT:
586 status = PORT_OCC;
587 port_change_bit = "over-current";
588 break;
589 case USB_PORT_FEAT_C_ENABLE:
590 status = PORT_PEC;
591 port_change_bit = "enable/disable";
592 break;
593 case USB_PORT_FEAT_C_SUSPEND:
594 status = PORT_PLC;
595 port_change_bit = "suspend/resume";
596 break;
597 default:
598 /* Should never happen */
599 return;
600 }
601
602 /* Change bits are all write 1 to clear */
603 xhci_writel(addr, port_status | status);
604
605 port_status = xhci_readl(addr);
606 debug("clear port %s change, actual port %d status = 0x%x\n",
607 port_change_bit, wIndex, port_status);
608 }
609
610 /**
611 * Save Read Only (RO) bits and save read/write bits where
612 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
613 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
614 *
615 * @param state state of the Port Status and Control Regsiter
616 * @return a value that would result in the port being in the
617 * same state, if the value was written to the port
618 * status control register.
619 */
620 static u32 xhci_port_state_to_neutral(u32 state)
621 {
622 /* Save read-only status and port state */
623 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
624 }
625
626 /**
627 * Submits the Requests to the XHCI Host Controller
628 *
629 * @param udev pointer to the USB device structure
630 * @param pipe contains the DIR_IN or OUT , devnum
631 * @param buffer buffer to be read/written based on the request
632 * @return returns 0 if successful else -1 on failure
633 */
634 static int xhci_submit_root(struct usb_device *udev, unsigned long pipe,
635 void *buffer, struct devrequest *req)
636 {
637 uint8_t tmpbuf[4];
638 u16 typeReq;
639 void *srcptr = NULL;
640 int len, srclen;
641 uint32_t reg;
642 volatile uint32_t *status_reg;
643 struct xhci_ctrl *ctrl = udev->controller;
644 struct xhci_hcor *hcor = ctrl->hcor;
645
646 if (((req->requesttype & USB_RT_PORT) &&
647 le16_to_cpu(req->index)) > CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS) {
648 printf("The request port(%d) is not configured\n",
649 le16_to_cpu(req->index) - 1);
650 return -EINVAL;
651 }
652
653 status_reg = (volatile uint32_t *)
654 (&hcor->portregs[le16_to_cpu(req->index) - 1].or_portsc);
655 srclen = 0;
656
657 typeReq = req->request | req->requesttype << 8;
658
659 switch (typeReq) {
660 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
661 switch (le16_to_cpu(req->value) >> 8) {
662 case USB_DT_DEVICE:
663 debug("USB_DT_DEVICE request\n");
664 srcptr = &descriptor.device;
665 srclen = 0x12;
666 break;
667 case USB_DT_CONFIG:
668 debug("USB_DT_CONFIG config\n");
669 srcptr = &descriptor.config;
670 srclen = 0x19;
671 break;
672 case USB_DT_STRING:
673 debug("USB_DT_STRING config\n");
674 switch (le16_to_cpu(req->value) & 0xff) {
675 case 0: /* Language */
676 srcptr = "\4\3\11\4";
677 srclen = 4;
678 break;
679 case 1: /* Vendor String */
680 srcptr = "\16\3u\0-\0b\0o\0o\0t\0";
681 srclen = 14;
682 break;
683 case 2: /* Product Name */
684 srcptr = "\52\3X\0H\0C\0I\0 "
685 "\0H\0o\0s\0t\0 "
686 "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
687 srclen = 42;
688 break;
689 default:
690 printf("unknown value DT_STRING %x\n",
691 le16_to_cpu(req->value));
692 goto unknown;
693 }
694 break;
695 default:
696 printf("unknown value %x\n", le16_to_cpu(req->value));
697 goto unknown;
698 }
699 break;
700 case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
701 switch (le16_to_cpu(req->value) >> 8) {
702 case USB_DT_HUB:
703 debug("USB_DT_HUB config\n");
704 srcptr = &descriptor.hub;
705 srclen = 0x8;
706 break;
707 default:
708 printf("unknown value %x\n", le16_to_cpu(req->value));
709 goto unknown;
710 }
711 break;
712 case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
713 debug("USB_REQ_SET_ADDRESS\n");
714 ctrl->rootdev = le16_to_cpu(req->value);
715 break;
716 case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
717 /* Do nothing */
718 break;
719 case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
720 tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */
721 tmpbuf[1] = 0;
722 srcptr = tmpbuf;
723 srclen = 2;
724 break;
725 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
726 memset(tmpbuf, 0, 4);
727 reg = xhci_readl(status_reg);
728 if (reg & PORT_CONNECT) {
729 tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
730 switch (reg & DEV_SPEED_MASK) {
731 case XDEV_FS:
732 debug("SPEED = FULLSPEED\n");
733 break;
734 case XDEV_LS:
735 debug("SPEED = LOWSPEED\n");
736 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
737 break;
738 case XDEV_HS:
739 debug("SPEED = HIGHSPEED\n");
740 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
741 break;
742 case XDEV_SS:
743 debug("SPEED = SUPERSPEED\n");
744 tmpbuf[1] |= USB_PORT_STAT_SUPER_SPEED >> 8;
745 break;
746 }
747 }
748 if (reg & PORT_PE)
749 tmpbuf[0] |= USB_PORT_STAT_ENABLE;
750 if ((reg & PORT_PLS_MASK) == XDEV_U3)
751 tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
752 if (reg & PORT_OC)
753 tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
754 if (reg & PORT_RESET)
755 tmpbuf[0] |= USB_PORT_STAT_RESET;
756 if (reg & PORT_POWER)
757 /*
758 * XXX: This Port power bit (for USB 3.0 hub)
759 * we are faking in USB 2.0 hub port status;
760 * since there's a change in bit positions in
761 * two:
762 * USB 2.0 port status PP is at position[8]
763 * USB 3.0 port status PP is at position[9]
764 * So, we are still keeping it at position [8]
765 */
766 tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
767 if (reg & PORT_CSC)
768 tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
769 if (reg & PORT_PEC)
770 tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
771 if (reg & PORT_OCC)
772 tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
773 if (reg & PORT_RC)
774 tmpbuf[2] |= USB_PORT_STAT_C_RESET;
775
776 srcptr = tmpbuf;
777 srclen = 4;
778 break;
779 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
780 reg = xhci_readl(status_reg);
781 reg = xhci_port_state_to_neutral(reg);
782 switch (le16_to_cpu(req->value)) {
783 case USB_PORT_FEAT_ENABLE:
784 reg |= PORT_PE;
785 xhci_writel(status_reg, reg);
786 break;
787 case USB_PORT_FEAT_POWER:
788 reg |= PORT_POWER;
789 xhci_writel(status_reg, reg);
790 break;
791 case USB_PORT_FEAT_RESET:
792 reg |= PORT_RESET;
793 xhci_writel(status_reg, reg);
794 break;
795 default:
796 printf("unknown feature %x\n", le16_to_cpu(req->value));
797 goto unknown;
798 }
799 break;
800 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
801 reg = xhci_readl(status_reg);
802 reg = xhci_port_state_to_neutral(reg);
803 switch (le16_to_cpu(req->value)) {
804 case USB_PORT_FEAT_ENABLE:
805 reg &= ~PORT_PE;
806 break;
807 case USB_PORT_FEAT_POWER:
808 reg &= ~PORT_POWER;
809 break;
810 case USB_PORT_FEAT_C_RESET:
811 case USB_PORT_FEAT_C_CONNECTION:
812 case USB_PORT_FEAT_C_OVER_CURRENT:
813 case USB_PORT_FEAT_C_ENABLE:
814 xhci_clear_port_change_bit((le16_to_cpu(req->value)),
815 le16_to_cpu(req->index),
816 status_reg, reg);
817 break;
818 default:
819 printf("unknown feature %x\n", le16_to_cpu(req->value));
820 goto unknown;
821 }
822 xhci_writel(status_reg, reg);
823 break;
824 default:
825 puts("Unknown request\n");
826 goto unknown;
827 }
828
829 debug("scrlen = %d\n req->length = %d\n",
830 srclen, le16_to_cpu(req->length));
831
832 len = min(srclen, le16_to_cpu(req->length));
833
834 if (srcptr != NULL && len > 0)
835 memcpy(buffer, srcptr, len);
836 else
837 debug("Len is 0\n");
838
839 udev->act_len = len;
840 udev->status = 0;
841
842 return 0;
843
844 unknown:
845 udev->act_len = 0;
846 udev->status = USB_ST_STALLED;
847
848 return -ENODEV;
849 }
850
851 /**
852 * Submits the INT request to XHCI Host cotroller
853 *
854 * @param udev pointer to the USB device
855 * @param pipe contains the DIR_IN or OUT , devnum
856 * @param buffer buffer to be read/written based on the request
857 * @param length length of the buffer
858 * @param interval interval of the interrupt
859 * @return 0
860 */
861 int
862 submit_int_msg(struct usb_device *udev, unsigned long pipe, void *buffer,
863 int length, int interval)
864 {
865 /*
866 * TODO: Not addressing any interrupt type transfer requests
867 * Add support for it later.
868 */
869 return -EINVAL;
870 }
871
872 /**
873 * submit the BULK type of request to the USB Device
874 *
875 * @param udev pointer to the USB device
876 * @param pipe contains the DIR_IN or OUT , devnum
877 * @param buffer buffer to be read/written based on the request
878 * @param length length of the buffer
879 * @return returns 0 if successful else -1 on failure
880 */
881 int
882 submit_bulk_msg(struct usb_device *udev, unsigned long pipe, void *buffer,
883 int length)
884 {
885 if (usb_pipetype(pipe) != PIPE_BULK) {
886 printf("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
887 return -EINVAL;
888 }
889
890 return xhci_bulk_tx(udev, pipe, length, buffer);
891 }
892
893 /**
894 * submit the control type of request to the Root hub/Device based on the devnum
895 *
896 * @param udev pointer to the USB device
897 * @param pipe contains the DIR_IN or OUT , devnum
898 * @param buffer buffer to be read/written based on the request
899 * @param length length of the buffer
900 * @param setup Request type
901 * @return returns 0 if successful else -1 on failure
902 */
903 int
904 submit_control_msg(struct usb_device *udev, unsigned long pipe, void *buffer,
905 int length, struct devrequest *setup)
906 {
907 struct xhci_ctrl *ctrl = udev->controller;
908 int ret = 0;
909
910 if (usb_pipetype(pipe) != PIPE_CONTROL) {
911 printf("non-control pipe (type=%lu)", usb_pipetype(pipe));
912 return -EINVAL;
913 }
914
915 if (usb_pipedevice(pipe) == ctrl->rootdev)
916 return xhci_submit_root(udev, pipe, buffer, setup);
917
918 if (setup->request == USB_REQ_SET_ADDRESS)
919 return xhci_address_device(udev);
920
921 if (setup->request == USB_REQ_SET_CONFIGURATION) {
922 ret = xhci_set_configuration(udev);
923 if (ret) {
924 puts("Failed to configure xHCI endpoint\n");
925 return ret;
926 }
927 }
928
929 return xhci_ctrl_tx(udev, pipe, setup, length, buffer);
930 }
931
932 /**
933 * Intialises the XHCI host controller
934 * and allocates the necessary data structures
935 *
936 * @param index index to the host controller data structure
937 * @return pointer to the intialised controller
938 */
939 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
940 {
941 uint32_t val;
942 uint32_t val2;
943 uint32_t reg;
944 struct xhci_hccr *hccr;
945 struct xhci_hcor *hcor;
946 struct xhci_ctrl *ctrl;
947
948 if (xhci_hcd_init(index, &hccr, (struct xhci_hcor **)&hcor) != 0)
949 return -ENODEV;
950
951 if (xhci_reset(hcor) != 0)
952 return -ENODEV;
953
954 ctrl = &xhcic[index];
955
956 ctrl->hccr = hccr;
957 ctrl->hcor = hcor;
958
959 /*
960 * Program the Number of Device Slots Enabled field in the CONFIG
961 * register with the max value of slots the HC can handle.
962 */
963 val = (xhci_readl(&hccr->cr_hcsparams1) & HCS_SLOTS_MASK);
964 val2 = xhci_readl(&hcor->or_config);
965 val |= (val2 & ~HCS_SLOTS_MASK);
966 xhci_writel(&hcor->or_config, val);
967
968 /* initializing xhci data structures */
969 if (xhci_mem_init(ctrl, hccr, hcor) < 0)
970 return -ENOMEM;
971
972 reg = xhci_readl(&hccr->cr_hcsparams1);
973 descriptor.hub.bNbrPorts = ((reg & HCS_MAX_PORTS_MASK) >>
974 HCS_MAX_PORTS_SHIFT);
975 printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
976
977 /* Port Indicators */
978 reg = xhci_readl(&hccr->cr_hccparams);
979 if (HCS_INDICATOR(reg))
980 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
981 | 0x80, &descriptor.hub.wHubCharacteristics);
982
983 /* Port Power Control */
984 if (HCC_PPC(reg))
985 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
986 | 0x01, &descriptor.hub.wHubCharacteristics);
987
988 if (xhci_start(hcor)) {
989 xhci_reset(hcor);
990 return -ENODEV;
991 }
992
993 /* Zero'ing IRQ control register and IRQ pending register */
994 xhci_writel(&ctrl->ir_set->irq_control, 0x0);
995 xhci_writel(&ctrl->ir_set->irq_pending, 0x0);
996
997 reg = HC_VERSION(xhci_readl(&hccr->cr_capbase));
998 printf("USB XHCI %x.%02x\n", reg >> 8, reg & 0xff);
999
1000 *controller = &xhcic[index];
1001
1002 return 0;
1003 }
1004
1005 /**
1006 * Stops the XHCI host controller
1007 * and cleans up all the related data structures
1008 *
1009 * @param index index to the host controller data structure
1010 * @return none
1011 */
1012 int usb_lowlevel_stop(int index)
1013 {
1014 struct xhci_ctrl *ctrl = (xhcic + index);
1015 u32 temp;
1016
1017 xhci_reset(ctrl->hcor);
1018
1019 debug("// Disabling event ring interrupts\n");
1020 temp = xhci_readl(&ctrl->hcor->or_usbsts);
1021 xhci_writel(&ctrl->hcor->or_usbsts, temp & ~STS_EINT);
1022 temp = xhci_readl(&ctrl->ir_set->irq_pending);
1023 xhci_writel(&ctrl->ir_set->irq_pending, ER_IRQ_DISABLE(temp));
1024
1025 xhci_hcd_stop(index);
1026
1027 xhci_cleanup(ctrl);
1028
1029 return 0;
1030 }
u-boot for qq2440