include/sys/auxv_386.h

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 /*
  22  * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved.
  23  * Copyright (c) 2015, Joyent, Inc.
  24  */
  25
  26 #ifndef _SYS_AUXV_386_H
  27 #define _SYS_AUXV_386_H
  28
  29 #ifdef __cplusplus
  30 extern "C" {
  31 #endif
  32
  33 /*
  34  * Flags used in AT_SUN_HWCAP elements to describe various userland
  35  * instruction set extensions available on different processors.
  36  * The basic assumption is that of the i386 ABI; that is, i386 plus i387
  37  * floating point.
  38  *
  39  * Note that if a given bit is set; the implication is that the kernel
  40  * provides all the underlying architectural support for the correct
  41  * functioning of the extended instruction(s).
  42  */
  43 #define AV_386_FPU              0x00001 /* x87-style floating point */
  44 #define AV_386_TSC              0x00002 /* rdtsc insn */
  45 #define AV_386_CX8              0x00004 /* cmpxchg8b insn */
  46 #define AV_386_SEP              0x00008 /* sysenter and sysexit */
  47 #define AV_386_AMD_SYSC         0x00010 /* AMD's syscall and sysret */
  48 #define AV_386_CMOV             0x00020 /* conditional move insns */
  49 #define AV_386_MMX              0x00040 /* MMX insns */
  50 #define AV_386_AMD_MMX          0x00080 /* AMD's MMX insns */
  51 #define AV_386_AMD_3DNow        0x00100 /* AMD's 3Dnow! insns */
  52 #define AV_386_AMD_3DNowx       0x00200 /* AMD's 3Dnow! extended insns */
  53 #define AV_386_FXSR             0x00400 /* fxsave and fxrstor */
  54 #define AV_386_SSE              0x00800 /* SSE insns and regs */
  55 #define AV_386_SSE2             0x01000 /* SSE2 insns and regs */
  56                                         /* 0x02000 withdrawn - do not assign */
  57 #define AV_386_SSE3             0x04000 /* SSE3 insns and regs */
  58                                         /* 0x08000 withdrawn - do not assign */
  59 #define AV_386_CX16             0x10000 /* cmpxchg16b insn */
  60 #define AV_386_AHF              0x20000 /* lahf/sahf insns */
  61 #define AV_386_TSCP             0x40000 /* rdtscp instruction */
  62 #define AV_386_AMD_SSE4A        0x80000 /* AMD's SSE4A insns */
  63 #define AV_386_POPCNT           0x100000 /* POPCNT insn */
  64 #define AV_386_AMD_LZCNT        0x200000 /* AMD's LZCNT insn */
  65 #define AV_386_SSSE3            0x400000 /* Intel SSSE3 insns */
  66 #define AV_386_SSE4_1           0x800000 /* Intel SSE4.1 insns */
  67 #define AV_386_SSE4_2           0x1000000 /* Intel SSE4.2 insns */
  68 #define AV_386_MOVBE            0x2000000 /* Intel MOVBE insns */
  69 #define AV_386_AES              0x4000000 /* Intel AES insns */
  70 #define AV_386_PCLMULQDQ        0x8000000 /* Intel PCLMULQDQ insn */
  71 #define AV_386_XSAVE            0x10000000 /* Intel XSAVE/XRSTOR insns */
  72 #define AV_386_AVX              0x20000000 /* Intel AVX insns */
  73 #define AV_386_VMX              0x40000000 /* Intel VMX support */
  74 #define AV_386_AMD_SVM          0x80000000 /* AMD SVM support */
  75
  76 #define FMT_AV_386                                                      \
  77         "\020"                                                          \
  78         "\040svm\037vmx\036avx\035xsave"                                \
  79         "\034pclmulqdq\033aes"                                          \
  80         "\032movbe\031sse4.2"                                           \
  81         "\030sse4.1\027ssse3\026amd_lzcnt\025popcnt"                    \
  82         "\024amd_sse4a\023tscp\022ahf\021cx16"                          \
  83         "\017sse3\015sse2\014sse\013fxsr\012amd3dx\011amd3d"            \
  84         "\010amdmmx\07mmx\06cmov\05amdsysc\04sep\03cx8\02tsc\01fpu"
  85
  86 #define AV_386_2_F16C           0x00001 /* F16C half percision extensions */
  87 #define AV_386_2_RDRAND         0x00002 /* RDRAND insn */
  88 #define AV_386_2_BMI1           0x00004 /* BMI1 insns */
  89 #define AV_386_2_BMI2           0x00008 /* BMI2 insns */
  90 #define AV_386_2_FMA            0x00010 /* FMA insns */
  91 #define AV_386_2_AVX2           0x00020 /* AVX2 insns */
  92 #define AV_386_2_ADX            0x00040 /* ADX insns */
  93 #define AV_386_2_RDSEED         0x00080 /* RDSEED insn */
  94
  95 #define FMT_AV_386_2                                                    \
  96         "\020"                                                          \
  97         "\10rdseed\07adx\06avx2\05fma\04bmi2\03bmi1\02rdrand\01f16c"
  98
  99 #ifdef __cplusplus
 100 }
 101 #endif
 102
 103 #endif  /* !_SYS_AUXV_386_H */