include/sys/nxge/nxge.h

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 /*
  22  * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved.
  23  */
  24
  25 #ifndef _SYS_NXGE_NXGE_H
  26 #define _SYS_NXGE_NXGE_H
  27
  28 #ifdef  __cplusplus
  29 extern "C" {
  30 #endif
  31
  32 #include <nxge_mac.h>
  33 #include <nxge_ipp.h>
  34 #include <nxge_fflp.h>
  35
  36 /*
  37  * NXGE diagnostics IOCTLS.
  38  */
  39 #define NXGE_IOC                ((((('N' << 8) + 'X') << 8) + 'G') << 8)
  40
  41 #define NXGE_GET64              (NXGE_IOC|1)
  42 #define NXGE_PUT64              (NXGE_IOC|2)
  43 #define NXGE_GET_TX_RING_SZ     (NXGE_IOC|3)
  44 #define NXGE_GET_TX_DESC        (NXGE_IOC|4)
  45 #define NXGE_GLOBAL_RESET       (NXGE_IOC|5)
  46 #define NXGE_TX_SIDE_RESET      (NXGE_IOC|6)
  47 #define NXGE_RX_SIDE_RESET      (NXGE_IOC|7)
  48 #define NXGE_RESET_MAC          (NXGE_IOC|8)
  49
  50 #define NXGE_GET_MII            (NXGE_IOC|11)
  51 #define NXGE_PUT_MII            (NXGE_IOC|12)
  52 #define NXGE_RTRACE             (NXGE_IOC|13)
  53 #define NXGE_RTRACE_TEST        (NXGE_IOC|20)
  54 #define NXGE_TX_REGS_DUMP       (NXGE_IOC|21)
  55 #define NXGE_RX_REGS_DUMP       (NXGE_IOC|22)
  56 #define NXGE_INT_REGS_DUMP      (NXGE_IOC|23)
  57 #define NXGE_VIR_REGS_DUMP      (NXGE_IOC|24)
  58 #define NXGE_VIR_INT_REGS_DUMP  (NXGE_IOC|25)
  59 #define NXGE_RDUMP              (NXGE_IOC|26)
  60 #define NXGE_RDC_GRPS_DUMP      (NXGE_IOC|27)
  61 #define NXGE_PIO_TEST           (NXGE_IOC|28)
  62
  63 #define NXGE_GET_TCAM           (NXGE_IOC|29)
  64 #define NXGE_PUT_TCAM           (NXGE_IOC|30)
  65 #define NXGE_INJECT_ERR         (NXGE_IOC|40)
  66
  67 #define NXGE_RX_CLASS           (NXGE_IOC|41)
  68 #define NXGE_RX_HASH            (NXGE_IOC|42)
  69
  70 #define NXGE_OK                 0
  71 #define NXGE_ERROR              0x40000000
  72 #define NXGE_DDI_FAILED         0x20000000
  73 #define NXGE_GET_PORT_NUM(n)    n
  74
  75 /*
  76  * Definitions for module_info.
  77  */
  78 #define NXGE_IDNUM              (0)                     /* module ID number */
  79 #define NXGE_DRIVER_NAME        "nxge"                  /* module name */
  80
  81 #define NXGE_MINPSZ             (0)                     /* min packet size */
  82 #define NXGE_MAXPSZ             (ETHERMTU)              /* max packet size */
  83 #define NXGE_HIWAT              (2048 * NXGE_MAXPSZ)    /* hi-water mark */
  84 #define NXGE_LOWAT              (1)                     /* lo-water mark */
  85 #define NXGE_HIWAT_MAX          (192000 * NXGE_MAXPSZ)
  86 #define NXGE_HIWAT_MIN          (2 * NXGE_MAXPSZ)
  87 #define NXGE_LOWAT_MAX          (192000 * NXGE_MAXPSZ)
  88 #define NXGE_LOWAT_MIN          (1)
  89
  90 #ifndef D_HOTPLUG
  91 #define D_HOTPLUG               0x00
  92 #endif
  93
  94 #define INIT_BUCKET_SIZE        16      /* Initial Hash Bucket Size */
  95
  96 #define NXGE_CHECK_TIMER        (5000)
  97
  98 /* KT/NIU OBP creates a compatible property for KT */
  99 #define KT_NIU_COMPATIBLE       "SUNW,niusl-kt"
 100
 101 typedef enum {
 102         param_instance,
 103         param_main_instance,
 104         param_function_number,
 105         param_partition_id,
 106         param_read_write_mode,
 107         param_fw_version,
 108         param_port_mode,
 109         param_niu_cfg_type,
 110         param_tx_quick_cfg,
 111         param_rx_quick_cfg,
 112         param_master_cfg_enable,
 113         param_master_cfg_value,
 114
 115         param_autoneg,
 116         param_anar_10gfdx,
 117         param_anar_10ghdx,
 118         param_anar_1000fdx,
 119         param_anar_1000hdx,
 120         param_anar_100T4,
 121         param_anar_100fdx,
 122         param_anar_100hdx,
 123         param_anar_10fdx,
 124         param_anar_10hdx,
 125
 126         param_anar_asmpause,
 127         param_anar_pause,
 128         param_use_int_xcvr,
 129         param_enable_ipg0,
 130         param_ipg0,
 131         param_ipg1,
 132         param_ipg2,
 133         param_txdma_weight,
 134         param_txdma_channels_begin,
 135
 136         param_txdma_channels,
 137         param_txdma_info,
 138         param_rxdma_channels_begin,
 139         param_rxdma_channels,
 140         param_rxdma_drr_weight,
 141         param_rxdma_full_header,
 142         param_rxdma_info,
 143         param_rxdma_rbr_size,
 144         param_rxdma_rcr_size,
 145         param_default_port_rdc,
 146         param_rxdma_intr_time,
 147         param_rxdma_intr_pkts,
 148
 149         param_rdc_grps_start,
 150         param_rx_rdc_grps,
 151         param_default_grp0_rdc,
 152         param_default_grp1_rdc,
 153         param_default_grp2_rdc,
 154         param_default_grp3_rdc,
 155         param_default_grp4_rdc,
 156         param_default_grp5_rdc,
 157         param_default_grp6_rdc,
 158         param_default_grp7_rdc,
 159
 160         param_info_rdc_groups,
 161         param_start_ldg,
 162         param_max_ldg,
 163         param_mac_2rdc_grp,
 164         param_vlan_2rdc_grp,
 165         param_fcram_part_cfg,
 166         param_fcram_access_ratio,
 167         param_tcam_access_ratio,
 168         param_tcam_enable,
 169         param_hash_lookup_enable,
 170         param_llc_snap_enable,
 171
 172         param_h1_init_value,
 173         param_h2_init_value,
 174         param_class_cfg_ether_usr1,
 175         param_class_cfg_ether_usr2,
 176         param_class_cfg_ip_usr4,
 177         param_class_cfg_ip_usr5,
 178         param_class_cfg_ip_usr6,
 179         param_class_cfg_ip_usr7,
 180         param_class_opt_ip_usr4,
 181         param_class_opt_ip_usr5,
 182         param_class_opt_ip_usr6,
 183         param_class_opt_ip_usr7,
 184         param_class_opt_ipv4_tcp,
 185         param_class_opt_ipv4_udp,
 186         param_class_opt_ipv4_ah,
 187         param_class_opt_ipv4_sctp,
 188         param_class_opt_ipv6_tcp,
 189         param_class_opt_ipv6_udp,
 190         param_class_opt_ipv6_ah,
 191         param_class_opt_ipv6_sctp,
 192         param_nxge_debug_flag,
 193         param_npi_debug_flag,
 194         param_dump_rdc,
 195         param_dump_tdc,
 196         param_dump_mac_regs,
 197         param_dump_ipp_regs,
 198         param_dump_fflp_regs,
 199         param_dump_vlan_table,
 200         param_dump_rdc_table,
 201         param_dump_ptrs,
 202         param_end
 203 } nxge_param_index_t;
 204
 205 typedef enum {
 206         SOLARIS_DOMAIN,
 207         SOLARIS_SERVICE_DOMAIN,
 208         SOLARIS_GUEST_DOMAIN,
 209         LINUX_SERVICE_DOMAIN,
 210         LINUX_GUEST_DOMAIN
 211 } nxge_environs_t;
 212
 213 /*
 214  * Named Dispatch Parameter Management Structure
 215  */
 216 typedef int (*nxge_ndgetf_t)(p_nxge_t, queue_t *, MBLKP, caddr_t, cred_t *);
 217 typedef int (*nxge_ndsetf_t)(p_nxge_t, queue_t *,
 218             MBLKP, char *, caddr_t, cred_t *);
 219
 220 #define NXGE_PARAM_READ                 0x00000001ULL
 221 #define NXGE_PARAM_WRITE                0x00000002ULL
 222 #define NXGE_PARAM_SHARED               0x00000004ULL
 223 #define NXGE_PARAM_PRIV                 0x00000008ULL
 224 #define NXGE_PARAM_RW                   NXGE_PARAM_READ | NXGE_PARAM_WRITE
 225 #define NXGE_PARAM_RWS                  NXGE_PARAM_RW | NXGE_PARAM_SHARED
 226 #define NXGE_PARAM_RWP                  NXGE_PARAM_RW | NXGE_PARAM_PRIV
 227
 228 #define NXGE_PARAM_RXDMA                0x00000010ULL
 229 #define NXGE_PARAM_TXDMA                0x00000020ULL
 230 #define NXGE_PARAM_CLASS_GEN    0x00000040ULL
 231 #define NXGE_PARAM_MAC                  0x00000080ULL
 232 #define NXGE_PARAM_CLASS_BIN    NXGE_PARAM_CLASS_GEN | NXGE_PARAM_BASE_BIN
 233 #define NXGE_PARAM_CLASS_HEX    NXGE_PARAM_CLASS_GEN | NXGE_PARAM_BASE_HEX
 234 #define NXGE_PARAM_CLASS                NXGE_PARAM_CLASS_HEX
 235
 236 #define NXGE_PARAM_CMPLX                0x00010000ULL
 237 #define NXGE_PARAM_NDD_WR_OK            0x00020000ULL
 238 #define NXGE_PARAM_INIT_ONLY            0x00040000ULL
 239 #define NXGE_PARAM_INIT_CONFIG          0x00080000ULL
 240
 241 #define NXGE_PARAM_READ_PROP            0x00100000ULL
 242 #define NXGE_PARAM_PROP_ARR32           0x00200000ULL
 243 #define NXGE_PARAM_PROP_ARR64           0x00400000ULL
 244 #define NXGE_PARAM_PROP_STR             0x00800000ULL
 245
 246 #define NXGE_PARAM_BASE_DEC             0x00000000ULL
 247 #define NXGE_PARAM_BASE_BIN             0x10000000ULL
 248 #define NXGE_PARAM_BASE_HEX             0x20000000ULL
 249 #define NXGE_PARAM_BASE_STR             0x40000000ULL
 250 #define NXGE_PARAM_DONT_SHOW            0x80000000ULL
 251
 252 #define NXGE_PARAM_ARRAY_CNT_MASK       0x0000ffff00000000ULL
 253 #define NXGE_PARAM_ARRAY_CNT_SHIFT      32ULL
 254 #define NXGE_PARAM_ARRAY_ALLOC_MASK     0xffff000000000000ULL
 255 #define NXGE_PARAM_ARRAY_ALLOC_SHIFT    48ULL
 256
 257 typedef struct _nxge_param_t {
 258         int (*getf)();
 259         int (*setf)();   /* null for read only */
 260         uint64_t type;  /* R/W/ Common/Port/ .... */
 261         uint64_t minimum;
 262         uint64_t maximum;
 263         uint64_t value; /* for array params, pointer to value array */
 264         uint64_t old_value; /* for array params, pointer to old_value array */
 265         char   *fcode_name;
 266         char   *name;
 267 } nxge_param_t, *p_nxge_param_t;
 268
 269
 270 /*
 271  * Do not change the order of the elements of this enum as that will
 272  * break the driver code.
 273  */
 274 typedef enum {
 275         nxge_lb_normal,
 276         nxge_lb_ext10g,
 277         nxge_lb_ext1000,
 278         nxge_lb_ext100,
 279         nxge_lb_ext10,
 280         nxge_lb_phy10g,
 281         nxge_lb_phy1000,
 282         nxge_lb_phy,
 283         nxge_lb_serdes10g,
 284         nxge_lb_serdes1000,
 285         nxge_lb_serdes,
 286         nxge_lb_mac10g,
 287         nxge_lb_mac1000,
 288         nxge_lb_mac
 289 } nxge_lb_t;
 290
 291 enum nxge_mac_state {
 292         NXGE_MAC_STOPPED = 0,
 293         NXGE_MAC_STARTED,
 294         NXGE_MAC_STOPPING
 295 };
 296
 297 /*
 298  * Private DLPI full dlsap address format.
 299  */
 300 typedef struct _nxge_dladdr_t {
 301         ether_addr_st dl_phys;
 302         uint16_t dl_sap;
 303 } nxge_dladdr_t, *p_nxge_dladdr_t;
 304
 305 typedef struct _mc_addr_t {
 306         ether_addr_st multcast_addr;
 307         uint_t mc_addr_cnt;
 308 } mc_addr_t, *p_mc_addr_t;
 309
 310 typedef struct _mc_bucket_t {
 311         p_mc_addr_t addr_list;
 312         uint_t list_size;
 313 } mc_bucket_t, *p_mc_bucket_t;
 314
 315 typedef struct _mc_table_t {
 316         p_mc_bucket_t bucket_list;
 317         uint_t buckets_used;
 318 } mc_table_t, *p_mc_table_t;
 319
 320 typedef struct _filter_t {
 321         uint32_t all_phys_cnt;
 322         uint32_t all_multicast_cnt;
 323         uint32_t all_sap_cnt;
 324 } filter_t, *p_filter_t;
 325
 326
 327 typedef struct _nxge_port_stats_t {
 328         /*
 329          *  Overall structure size
 330          */
 331         size_t                  stats_size;
 332
 333         /*
 334          * Link Input/Output stats
 335          */
 336         uint64_t                ipackets;
 337         uint64_t                ierrors;
 338         uint64_t                opackets;
 339         uint64_t                oerrors;
 340         uint64_t                collisions;
 341
 342         /*
 343          * MIB II variables
 344          */
 345         uint64_t                rbytes;    /* # bytes received */
 346         uint64_t                obytes;    /* # bytes transmitted */
 347         uint32_t                multircv;  /* # multicast packets received */
 348         uint32_t                multixmt;  /* # multicast packets for xmit */
 349         uint32_t                brdcstrcv; /* # broadcast packets received */
 350         uint32_t                brdcstxmt; /* # broadcast packets for xmit */
 351         uint32_t                norcvbuf;  /* # rcv packets discarded */
 352         uint32_t                noxmtbuf;  /* # xmit packets discarded */
 353
 354         /*
 355          * Lets the user know the MTU currently in use by
 356          * the physical MAC port.
 357          */
 358         nxge_lb_t               lb_mode;
 359         uint32_t                qos_mode;
 360         uint32_t                trunk_mode;
 361         uint32_t                poll_mode;
 362
 363         /*
 364          * Tx Statistics.
 365          */
 366         uint32_t                tx_inits;
 367         uint32_t                tx_starts;
 368         uint32_t                tx_nocanput;
 369         uint32_t                tx_msgdup_fail;
 370         uint32_t                tx_allocb_fail;
 371         uint32_t                tx_no_desc;
 372         uint32_t                tx_dma_bind_fail;
 373         uint32_t                tx_uflo;
 374         uint32_t                tx_hdr_pkts;
 375         uint32_t                tx_ddi_pkts;
 376         uint32_t                tx_dvma_pkts;
 377
 378         uint32_t                tx_max_pend;
 379
 380         /*
 381          * Rx Statistics.
 382          */
 383         uint32_t                rx_inits;
 384         uint32_t                rx_hdr_pkts;
 385         uint32_t                rx_mtu_pkts;
 386         uint32_t                rx_split_pkts;
 387         uint32_t                rx_no_buf;
 388         uint32_t                rx_no_comp_wb;
 389         uint32_t                rx_ov_flow;
 390         uint32_t                rx_len_mm;
 391         uint32_t                rx_tag_err;
 392         uint32_t                rx_nocanput;
 393         uint32_t                rx_msgdup_fail;
 394         uint32_t                rx_allocb_fail;
 395
 396         /*
 397          * Receive buffer management statistics.
 398          */
 399         uint32_t                rx_new_pages;
 400         uint32_t                rx_new_hdr_pgs;
 401         uint32_t                rx_new_mtu_pgs;
 402         uint32_t                rx_new_nxt_pgs;
 403         uint32_t                rx_reused_pgs;
 404         uint32_t                rx_hdr_drops;
 405         uint32_t                rx_mtu_drops;
 406         uint32_t                rx_nxt_drops;
 407
 408         /*
 409          * Receive flow statistics
 410          */
 411         uint32_t                rx_rel_flow;
 412         uint32_t                rx_rel_bit;
 413
 414         uint32_t                rx_pkts_dropped;
 415
 416         /*
 417          * PCI-E Bus Statistics.
 418          */
 419         uint32_t                pci_bus_speed;
 420         uint32_t                pci_err;
 421         uint32_t                pci_rta_err;
 422         uint32_t                pci_rma_err;
 423         uint32_t                pci_parity_err;
 424         uint32_t                pci_bad_ack_err;
 425         uint32_t                pci_drto_err;
 426         uint32_t                pci_dmawz_err;
 427         uint32_t                pci_dmarz_err;
 428
 429         uint32_t                rx_taskq_waits;
 430
 431         uint32_t                tx_jumbo_pkts;
 432
 433         /*
 434          * Some statistics added to support bringup, these
 435          * should be removed.
 436          */
 437         uint32_t                user_defined;
 438 } nxge_port_stats_t, *p_nxge_port_stats_t;
 439
 440
 441 typedef struct _nxge_stats_t {
 442         /*
 443          *  Overall structure size
 444          */
 445         size_t                  stats_size;
 446
 447         kstat_t                 *ksp;
 448         kstat_t                 *rdc_ksp[NXGE_MAX_RDCS];
 449         kstat_t                 *tdc_ksp[NXGE_MAX_TDCS];
 450         kstat_t                 *rdc_sys_ksp;
 451         kstat_t                 *fflp_ksp[1];
 452         kstat_t                 *ipp_ksp;
 453         kstat_t                 *txc_ksp;
 454         kstat_t                 *mac_ksp;
 455         kstat_t                 *zcp_ksp;
 456         kstat_t                 *port_ksp;
 457         kstat_t                 *mmac_ksp;
 458
 459         nxge_mac_stats_t        mac_stats;      /* Common MAC Statistics */
 460         nxge_xmac_stats_t       xmac_stats;     /* XMAC Statistics */
 461         nxge_bmac_stats_t       bmac_stats;     /* BMAC Statistics */
 462
 463         nxge_rx_ring_stats_t    rx_stats;       /* per port RX stats */
 464         nxge_ipp_stats_t        ipp_stats;      /* per port IPP stats */
 465         nxge_zcp_stats_t        zcp_stats;      /* per port IPP stats */
 466         nxge_rx_ring_stats_t    rdc_stats[NXGE_MAX_RDCS]; /* per rdc stats */
 467         nxge_rdc_sys_stats_t    rdc_sys_stats;  /* per port RDC stats */
 468
 469         nxge_tx_ring_stats_t    tx_stats;       /* per port TX stats */
 470         nxge_txc_stats_t        txc_stats;      /* per port TX stats */
 471         nxge_tx_ring_stats_t    tdc_stats[NXGE_MAX_TDCS]; /* per tdc stats */
 472         nxge_fflp_stats_t       fflp_stats;     /* fflp stats */
 473         nxge_port_stats_t       port_stats;     /* fflp stats */
 474         nxge_mmac_stats_t       mmac_stats;     /* Multi mac. stats */
 475
 476 } nxge_stats_t, *p_nxge_stats_t;
 477
 478
 479
 480 typedef struct _nxge_intr_t {
 481         boolean_t               intr_registered; /* interrupts are registered */
 482         boolean_t               intr_enabled;   /* interrupts are enabled */
 483         boolean_t               niu_msi_enable; /* debug or configurable? */
 484         int                     intr_types;     /* interrupt types supported */
 485         int                     intr_type;      /* interrupt type to add */
 486         int                     max_int_cnt;    /* max MSIX/INT HW supports */
 487         int                     start_inum;     /* start inum (in sequence?) */
 488         int                     msi_intx_cnt;   /* # msi/intx ints returned */
 489         int                     intr_added;     /* # ints actually needed */
 490         int                     intr_cap;       /* interrupt capabilities */
 491         size_t                  intr_size;      /* size of array to allocate */
 492         ddi_intr_handle_t       *htable;        /* For array of interrupts */
 493         /* Add interrupt number for each interrupt vector */
 494         int                     pri;
 495 } nxge_intr_t, *p_nxge_intr_t;
 496
 497 typedef struct _nxge_ldgv_t {
 498         uint8_t                 ndma_ldvs;
 499         uint8_t                 nldvs;
 500         uint8_t                 maxldgs;
 501         uint8_t                 maxldvs;
 502         uint8_t                 ldg_intrs;
 503         uint32_t                tmres;
 504         p_nxge_ldg_t            ldgp;
 505         p_nxge_ldv_t            ldvp;
 506         p_nxge_ldv_t            ldvp_syserr;
 507         boolean_t               ldvp_syserr_alloced;
 508 } nxge_ldgv_t, *p_nxge_ldgv_t;
 509
 510 typedef enum {
 511         NXGE_TRANSMIT_GROUP,    /* Legacy transmit group */
 512         NXGE_RECEIVE_GROUP,     /* Legacy receive group */
 513         NXGE_VR_GROUP,          /* Virtualization Region group */
 514         EXT_TRANSMIT_GROUP,     /* External (Crossbow) transmit group */
 515         EXT_RECEIVE_GROUP       /* External (Crossbow) receive group */
 516 } nxge_grp_type_t;
 517
 518 #define NXGE_ILLEGAL_CHANNEL    (NXGE_MAX_TDCS + 1)
 519
 520 typedef uint8_t nxge_channel_t;
 521
 522 typedef struct nxge_grp {
 523         nxge_t                  *nxge;
 524         nxge_grp_type_t         type; /* Tx or Rx */
 525
 526         int                     sequence; /* When it was created. */
 527         int                     index; /* nxge_grp_set_t.group[index] */
 528
 529         struct nx_dc            *dc; /* Linked list of DMA channels. */
 530         size_t                  count; /* A count of <dc> above. */
 531
 532         boolean_t               active; /* Is it being used? */
 533
 534         dc_map_t                map; /* A bitmap of the channels in <dc>. */
 535         nxge_channel_t          legend[NXGE_MAX_TDCS];
 536
 537 } nxge_grp_t;
 538
 539 typedef struct {
 540         lg_map_t                map;
 541         size_t                  count;
 542 } lg_data_t;
 543
 544 typedef struct {
 545         dc_map_t                map;
 546         size_t                  count;
 547 } dc_data_t;
 548
 549 #define NXGE_DC_SET(map, channel)       map |= (1 << channel)
 550 #define NXGE_DC_RESET(map, channel)     map &= (~(1 << channel))
 551
 552 /* For now, we only support up to 8 RDC/TDC groups */
 553 #define NXGE_LOGICAL_GROUP_MAX  NXGE_MAX_RDC_GROUPS
 554
 555 typedef struct {
 556         int                     sequence; /* To order groups in time. */
 557
 558         /* These are this instance's logical groups. */
 559         nxge_grp_t              *group[NXGE_LOGICAL_GROUP_MAX];
 560         lg_data_t               lg;
 561
 562         dc_data_t               shared; /* These DCs are being shared. */
 563         dc_data_t               owned; /* These DCs belong to me. */
 564         dc_data_t               dead; /* These DCs are in an error state. */
 565
 566 } nxge_grp_set_t;
 567
 568 /*
 569  * Transmit Ring Group
 570  * TX groups will be used exclusively for the purpose of Hybrid I/O.  From
 571  * the point of view of the nxge driver, the groups will be software
 572  * constructs which will be used to establish the relationship between TX
 573  * rings and shares.
 574  *
 575  * Receive Ring Group
 576  * One of the advanced virtualization features is the ability to bundle
 577  * multiple Receive Rings in a single group.  One or more MAC addresses may
 578  * be assigned to a group.  Incoming packets destined to the group's MAC
 579  * address(es) are delivered to any ring member, according to a programmable
 580  * or predefined RTS policy.  Member rings can be polled individually.
 581  * RX ring groups can come with a predefined set of member rings, or they
 582  * are programmable by adding and removing rings to/from them.
 583  */
 584 typedef struct _nxge_ring_group_t {
 585         mac_group_handle_t      ghandle;
 586         p_nxge_t                nxgep;
 587         boolean_t               started;
 588         boolean_t               port_default_grp;
 589         mac_ring_type_t         type;
 590         int                     gindex;
 591         int                     sindex;
 592         int                     rdctbl;
 593         int                     n_mac_addrs;
 594 } nxge_ring_group_t;
 595
 596 /*
 597  * Ring Handle
 598  */
 599 typedef struct _nxge_ring_handle_t {
 600         p_nxge_t                nxgep;
 601         int                     index;          /* port-wise */
 602         mac_ring_handle_t       ring_handle;
 603         uint64_t                ring_gen_num;   /* For RX Ring Start */
 604         uint32_t                channel;
 605 } nxge_ring_handle_t, *p_nxge_ring_handle_t;
 606
 607 /*
 608  * Share Handle
 609  */
 610 typedef struct _nxge_share_handle_t {
 611         p_nxge_t                nxgep;          /* Driver Handle */
 612         int                     index;
 613         void                    *vrp;
 614         uint64_t                tmap;
 615         uint64_t                rmap;
 616         int                     rxgroup;
 617         boolean_t               active;
 618 } nxge_share_handle_t;
 619
 620 /*
 621  * Neptune Device instance state information.
 622  *
 623  * Each instance is dynamically allocated on first attach.
 624  */
 625 struct _nxge_t {
 626         dev_info_t              *dip;           /* device instance */
 627         dev_info_t              *p_dip;         /* Parent's device instance */
 628         int                     instance;       /* instance number */
 629         int                     function_num;   /* device function number */
 630         int                     nports;         /* # of ports on this device */
 631         int                     board_ver;      /* Board Version */
 632         int                     use_partition;  /* partition is enabled */
 633         uint32_t                drv_state;      /* driver state bit flags */
 634         uint64_t                nxge_debug_level; /* driver state bit flags */
 635         kmutex_t                genlock[1];
 636         enum nxge_mac_state     nxge_mac_state;
 637
 638         p_dev_regs_t            dev_regs;
 639         npi_handle_t            npi_handle;
 640         npi_handle_t            npi_pci_handle;
 641         npi_handle_t            npi_reg_handle;
 642         npi_handle_t            npi_msi_handle;
 643         npi_handle_t            npi_vreg_handle;
 644         npi_handle_t            npi_v2reg_handle;
 645
 646         nxge_xcvr_table_t       xcvr;
 647         boolean_t               hot_swappable_phy;
 648         boolean_t               phy_absent;
 649         uint32_t                xcvr_addr;
 650         uint16_t                chip_id;
 651         nxge_nlp_conn_t         nlp_conn;
 652         nxge_phy_prop_t         phy_prop;
 653         nxge_serdes_prop_t      srds_prop;
 654
 655         nxge_mac_t              mac;
 656         nxge_ipp_t              ipp;
 657         nxge_txc_t              txc;
 658         nxge_classify_t         classifier;
 659
 660         mac_handle_t            mach;   /* mac module handle */
 661         p_nxge_stats_t          statsp;
 662         uint32_t                param_count;
 663         p_nxge_param_t          param_arr;
 664
 665         uint32_t                param_en_pause:1,
 666                                 param_en_asym_pause:1,
 667                                 param_en_1000fdx:1,
 668                                 param_en_100fdx:1,
 669                                 param_en_10fdx:1,
 670                                 param_pad_to_32:27;
 671
 672         nxge_hw_list_t          *nxge_hw_p;     /* pointer to per Neptune */
 673         niu_type_t              niu_type;
 674         platform_type_t         platform_type;
 675         boolean_t               os_addr_mode32; /* set to 1 for 32 bit mode */
 676
 677         uint8_t                 def_rdc;
 678
 679         nxge_intr_t             nxge_intr_type;
 680         nxge_dma_pt_cfg_t       pt_config;
 681         nxge_class_pt_cfg_t     class_config;
 682
 683         /* Logical device and group data structures. */
 684         p_nxge_ldgv_t           ldgvp;
 685
 686         npi_vpd_info_t          vpd_info;
 687
 688         ether_addr_st           factaddr;       /* factory mac address      */
 689         ether_addr_st           ouraddr;        /* individual address       */
 690         boolean_t               primary;        /* primary addr set?.       */
 691         kmutex_t                ouraddr_lock;   /* lock to protect to uradd */
 692
 693         ddi_iblock_cookie_t     interrupt_cookie;
 694
 695         /*
 696          * Blocks of memory may be pre-allocated by the
 697          * partition manager or the driver. They may include
 698          * blocks for configuration and buffers. The idea is
 699          * to preallocate big blocks of contiguous areas in
 700          * system memory (i.e. with IOMMU). These blocks then
 701          * will be broken up to a fixed number of blocks with
 702          * each block having the same block size (4K, 8K, 16K or
 703          * 32K) in the case of buffer blocks. For systems that
 704          * do not support DVMA, more than one big block will be
 705          * allocated.
 706          */
 707         uint32_t                rx_default_block_size;
 708         nxge_rx_block_size_t    rx_bksize_code;
 709
 710         p_nxge_dma_pool_t       rx_buf_pool_p;
 711         p_nxge_dma_pool_t       rx_cntl_pool_p;
 712
 713         p_nxge_dma_pool_t       tx_buf_pool_p;
 714         p_nxge_dma_pool_t       tx_cntl_pool_p;
 715
 716         /* Receive buffer block ring and completion ring. */
 717         p_rx_rbr_rings_t        rx_rbr_rings;
 718         p_rx_rcr_rings_t        rx_rcr_rings;
 719         p_rx_mbox_areas_t       rx_mbox_areas_p;
 720
 721         uint32_t                rdc_mask;
 722
 723         /* Transmit descriptors rings */
 724         p_tx_rings_t            tx_rings;
 725         p_tx_mbox_areas_t       tx_mbox_areas_p;
 726
 727         ddi_dma_handle_t        dmasparehandle;
 728
 729         ulong_t                 sys_page_sz;
 730         ulong_t                 sys_page_mask;
 731         int                     suspended;
 732
 733         mii_bmsr_t              bmsr;           /* xcvr status at last poll. */
 734         mii_bmsr_t              soft_bmsr;      /* xcvr status kept by SW. */
 735
 736         kmutex_t                mif_lock;       /* Lock to protect the list. */
 737
 738         void                    (*mii_read)();
 739         void                    (*mii_write)();
 740         void                    (*mii_poll)();
 741         filter_t                filter;         /* Current instance filter */
 742         p_hash_filter_t         hash_filter;    /* Multicast hash filter. */
 743         krwlock_t               filter_lock;    /* Lock to protect filters. */
 744
 745         ulong_t                 sys_burst_sz;
 746
 747         uint8_t                 cache_line;
 748
 749         timeout_id_t            nxge_link_poll_timerid;
 750         timeout_id_t            nxge_timerid;
 751
 752         uint_t                  need_periodic_reclaim;
 753         timeout_id_t            reclaim_timer;
 754
 755         uint8_t                 msg_min;
 756         uint8_t                 crc_size;
 757
 758         boolean_t               hard_props_read;
 759
 760         uint32_t                nxge_ncpus;
 761         uint16_t                intr_timeout;
 762         uint16_t                intr_threshold;
 763
 764         int                     fm_capabilities; /* FMA capabilities */
 765
 766         uint32_t                nxge_port_rbr_size;
 767         uint32_t                nxge_port_rbr_spare_size;
 768         uint32_t                nxge_port_rcr_size;
 769         uint32_t                nxge_port_rx_cntl_alloc_size;
 770         uint32_t                nxge_port_tx_ring_size;
 771         nxge_mmac_t             nxge_mmac_info;
 772 #if     defined(sun4v)
 773         boolean_t               niu_hsvc_available;
 774         hsvc_info_t             niu_hsvc;
 775         uint64_t                niu_min_ver;
 776 #endif
 777         boolean_t               link_notify;
 778         int                     link_check_count;
 779
 780         kmutex_t                poll_lock;
 781         kcondvar_t              poll_cv;
 782         link_mon_enable_t       poll_state;
 783 #define NXGE_MAGIC              0x3ab434e3
 784         uint32_t                nxge_magic;
 785
 786         int                     soft_lso_enable;
 787         /* The following fields are LDOMs-specific additions. */
 788         nxge_environs_t         environs;
 789         ether_addr_t            hio_mac_addr;
 790         uint32_t                niu_cfg_hdl;
 791         kmutex_t                group_lock;
 792
 793         struct nxge_hio_vr      *hio_vr;
 794
 795         nxge_grp_set_t          rx_set;
 796         nxge_grp_set_t          tx_set;
 797         boolean_t               tdc_is_shared[NXGE_MAX_TDCS];
 798
 799         /* Ring Handles */
 800         nxge_ring_handle_t      tx_ring_handles[NXGE_MAX_TDCS];
 801         nxge_ring_handle_t      rx_ring_handles[NXGE_MAX_RDCS];
 802
 803         nxge_ring_group_t       tx_hio_groups[NXGE_MAX_TDC_GROUPS];
 804         nxge_ring_group_t       rx_hio_groups[NXGE_MAX_RDC_GROUPS];
 805
 806         nxge_share_handle_t     shares[NXGE_MAX_VRS];
 807
 808         /*
 809          * KT-NIU:
 810          *      KT family will have up to 4 NIUs per system.
 811          *      Differences between N2/NIU and KT/NIU:
 812          *              SerDes, Hypervisor interfaces,
 813          *              additional NIU classification features.
 814          */
 815         niu_hw_type_t           niu_hw_type;
 816 };
 817
 818 /*
 819  * Driver state flags.
 820  */
 821 #define STATE_REGS_MAPPED       0x000000001     /* device registers mapped */
 822 #define STATE_KSTATS_SETUP      0x000000002     /* kstats allocated     */
 823 #define STATE_NODE_CREATED      0x000000004     /* device node created  */
 824 #define STATE_HW_CONFIG_CREATED 0x000000008     /* hardware properties  */
 825 #define STATE_HW_INITIALIZED    0x000000010     /* hardware initialized */
 826 #define STATE_MDIO_LOCK_INIT    0x000000020     /* mdio lock initialized */
 827 #define STATE_MII_LOCK_INIT     0x000000040     /* mii lock initialized */
 828
 829 #define STOP_POLL_THRESH        9
 830 #define START_POLL_THRESH       2
 831
 832 typedef struct _nxge_port_kstat_t {
 833         /*
 834          * Transciever state informations.
 835          */
 836         kstat_named_t   xcvr_inits;
 837         kstat_named_t   xcvr_inuse;
 838         kstat_named_t   xcvr_addr;
 839         kstat_named_t   xcvr_id;
 840         kstat_named_t   cap_autoneg;
 841         kstat_named_t   cap_10gfdx;
 842         kstat_named_t   cap_10ghdx;
 843         kstat_named_t   cap_1000fdx;
 844         kstat_named_t   cap_1000hdx;
 845         kstat_named_t   cap_100T4;
 846         kstat_named_t   cap_100fdx;
 847         kstat_named_t   cap_100hdx;
 848         kstat_named_t   cap_10fdx;
 849         kstat_named_t   cap_10hdx;
 850         kstat_named_t   cap_asmpause;
 851         kstat_named_t   cap_pause;
 852
 853         /*
 854          * Link partner capabilities.
 855          */
 856         kstat_named_t   lp_cap_autoneg;
 857         kstat_named_t   lp_cap_10gfdx;
 858         kstat_named_t   lp_cap_10ghdx;
 859         kstat_named_t   lp_cap_1000fdx;
 860         kstat_named_t   lp_cap_1000hdx;
 861         kstat_named_t   lp_cap_100T4;
 862         kstat_named_t   lp_cap_100fdx;
 863         kstat_named_t   lp_cap_100hdx;
 864         kstat_named_t   lp_cap_10fdx;
 865         kstat_named_t   lp_cap_10hdx;
 866         kstat_named_t   lp_cap_asmpause;
 867         kstat_named_t   lp_cap_pause;
 868
 869         /*
 870          * Shared link setup.
 871          */
 872         kstat_named_t   link_T4;
 873         kstat_named_t   link_speed;
 874         kstat_named_t   link_duplex;
 875         kstat_named_t   link_asmpause;
 876         kstat_named_t   link_pause;
 877         kstat_named_t   link_up;
 878
 879         /*
 880          * Lets the user know the MTU currently in use by
 881          * the physical MAC port.
 882          */
 883         kstat_named_t   mac_mtu;
 884         kstat_named_t   lb_mode;
 885         kstat_named_t   qos_mode;
 886         kstat_named_t   trunk_mode;
 887
 888         /*
 889          * Misc MAC statistics.
 890          */
 891         kstat_named_t   ifspeed;
 892         kstat_named_t   promisc;
 893         kstat_named_t   rev_id;
 894
 895         /*
 896          * Some statistics added to support bringup, these
 897          * should be removed.
 898          */
 899         kstat_named_t   user_defined;
 900 } nxge_port_kstat_t, *p_nxge_port_kstat_t;
 901
 902 typedef struct _nxge_rdc_kstat {
 903         /*
 904          * Receive DMA channel statistics.
 905          */
 906         kstat_named_t   ipackets;
 907         kstat_named_t   rbytes;
 908         kstat_named_t   errors;
 909         kstat_named_t   dcf_err;
 910         kstat_named_t   rcr_ack_err;
 911
 912         kstat_named_t   dc_fifoflow_err;
 913         kstat_named_t   rcr_sha_par_err;
 914         kstat_named_t   rbr_pre_par_err;
 915         kstat_named_t   wred_drop;
 916         kstat_named_t   rbr_pre_emty;
 917
 918         kstat_named_t   rcr_shadow_full;
 919         kstat_named_t   rbr_tmout;
 920         kstat_named_t   rsp_cnt_err;
 921         kstat_named_t   byte_en_bus;
 922         kstat_named_t   rsp_dat_err;
 923
 924         kstat_named_t   pkt_too_long_err;
 925         kstat_named_t   compl_l2_err;
 926         kstat_named_t   compl_l4_cksum_err;
 927         kstat_named_t   compl_zcp_soft_err;
 928         kstat_named_t   compl_fflp_soft_err;
 929         kstat_named_t   config_err;
 930
 931         kstat_named_t   rcrincon;
 932         kstat_named_t   rcrfull;
 933         kstat_named_t   rbr_empty;
 934         kstat_named_t   rbrfull;
 935         kstat_named_t   rbrlogpage;
 936
 937         kstat_named_t   cfiglogpage;
 938         kstat_named_t   port_drop_pkt;
 939         kstat_named_t   rcr_to;
 940         kstat_named_t   rcr_thresh;
 941         kstat_named_t   rcr_mex;
 942         kstat_named_t   id_mismatch;
 943         kstat_named_t   zcp_eop_err;
 944         kstat_named_t   ipp_eop_err;
 945 } nxge_rdc_kstat_t, *p_nxge_rdc_kstat_t;
 946
 947 typedef struct _nxge_rdc_sys_kstat {
 948         /*
 949          * Receive DMA system statistics.
 950          */
 951         kstat_named_t   pre_par;
 952         kstat_named_t   sha_par;
 953         kstat_named_t   id_mismatch;
 954         kstat_named_t   ipp_eop_err;
 955         kstat_named_t   zcp_eop_err;
 956 } nxge_rdc_sys_kstat_t, *p_nxge_rdc_sys_kstat_t;
 957
 958 typedef struct _nxge_tdc_kstat {
 959         /*
 960          * Transmit DMA channel statistics.
 961          */
 962         kstat_named_t   opackets;
 963         kstat_named_t   obytes;
 964         kstat_named_t   oerrors;
 965         kstat_named_t   tx_inits;
 966         kstat_named_t   tx_no_buf;
 967
 968         kstat_named_t   mbox_err;
 969         kstat_named_t   pkt_size_err;
 970         kstat_named_t   tx_ring_oflow;
 971         kstat_named_t   pref_buf_ecc_err;
 972         kstat_named_t   nack_pref;
 973         kstat_named_t   nack_pkt_rd;
 974         kstat_named_t   conf_part_err;
 975         kstat_named_t   pkt_prt_err;
 976         kstat_named_t   reset_fail;
 977 /* used to in the common (per port) counter */
 978
 979         kstat_named_t   tx_starts;
 980         kstat_named_t   tx_nocanput;
 981         kstat_named_t   tx_msgdup_fail;
 982         kstat_named_t   tx_allocb_fail;
 983         kstat_named_t   tx_no_desc;
 984         kstat_named_t   tx_dma_bind_fail;
 985         kstat_named_t   tx_uflo;
 986         kstat_named_t   tx_hdr_pkts;
 987         kstat_named_t   tx_ddi_pkts;
 988         kstat_named_t   tx_dvma_pkts;
 989         kstat_named_t   tx_max_pend;
 990 } nxge_tdc_kstat_t, *p_nxge_tdc_kstat_t;
 991
 992 typedef struct _nxge_txc_kstat {
 993         /*
 994          * Transmit port TXC block statistics.
 995          */
 996         kstat_named_t   pkt_stuffed;
 997         kstat_named_t   pkt_xmit;
 998         kstat_named_t   ro_correct_err;
 999         kstat_named_t   ro_uncorrect_err;
1000         kstat_named_t   sf_correct_err;
1001         kstat_named_t   sf_uncorrect_err;
1002         kstat_named_t   address_failed;
1003         kstat_named_t   dma_failed;
1004         kstat_named_t   length_failed;
1005         kstat_named_t   pkt_assy_dead;
1006         kstat_named_t   reorder_err;
1007 } nxge_txc_kstat_t, *p_nxge_txc_kstat_t;
1008
1009 typedef struct _nxge_ipp_kstat {
1010         /*
1011          * Receive port IPP block statistics.
1012          */
1013         kstat_named_t   eop_miss;
1014         kstat_named_t   sop_miss;
1015         kstat_named_t   dfifo_ue;
1016         kstat_named_t   ecc_err_cnt;
1017         kstat_named_t   pfifo_perr;
1018         kstat_named_t   pfifo_over;
1019         kstat_named_t   pfifo_und;
1020         kstat_named_t   bad_cs_cnt;
1021         kstat_named_t   pkt_dis_cnt;
1022 } nxge_ipp_kstat_t, *p_nxge_ipp_kstat_t;
1023
1024 typedef struct _nxge_zcp_kstat {
1025         /*
1026          * ZCP statistics.
1027          */
1028         kstat_named_t   errors;
1029         kstat_named_t   inits;
1030         kstat_named_t   rrfifo_underrun;
1031         kstat_named_t   rrfifo_overrun;
1032         kstat_named_t   rspfifo_uncorr_err;
1033         kstat_named_t   buffer_overflow;
1034         kstat_named_t   stat_tbl_perr;
1035         kstat_named_t   dyn_tbl_perr;
1036         kstat_named_t   buf_tbl_perr;
1037         kstat_named_t   tt_program_err;
1038         kstat_named_t   rsp_tt_index_err;
1039         kstat_named_t   slv_tt_index_err;
1040         kstat_named_t   zcp_tt_index_err;
1041         kstat_named_t   access_fail;
1042         kstat_named_t   cfifo_ecc;
1043 } nxge_zcp_kstat_t, *p_nxge_zcp_kstat_t;
1044
1045 typedef struct _nxge_mac_kstat {
1046         /*
1047          * Transmit MAC statistics.
1048          */
1049         kstat_named_t   tx_frame_cnt;
1050         kstat_named_t   tx_underflow_err;
1051         kstat_named_t   tx_overflow_err;
1052         kstat_named_t   tx_maxpktsize_err;
1053         kstat_named_t   tx_fifo_xfr_err;
1054         kstat_named_t   tx_byte_cnt;
1055
1056         /*
1057          * Receive MAC statistics.
1058          */
1059         kstat_named_t   rx_frame_cnt;
1060         kstat_named_t   rx_underflow_err;
1061         kstat_named_t   rx_overflow_err;
1062         kstat_named_t   rx_len_err_cnt;
1063         kstat_named_t   rx_crc_err_cnt;
1064         kstat_named_t   rx_viol_err_cnt;
1065         kstat_named_t   rx_byte_cnt;
1066         kstat_named_t   rx_hist1_cnt;
1067         kstat_named_t   rx_hist2_cnt;
1068         kstat_named_t   rx_hist3_cnt;
1069         kstat_named_t   rx_hist4_cnt;
1070         kstat_named_t   rx_hist5_cnt;
1071         kstat_named_t   rx_hist6_cnt;
1072         kstat_named_t   rx_hist7_cnt;
1073         kstat_named_t   rx_broadcast_cnt;
1074         kstat_named_t   rx_mult_cnt;
1075         kstat_named_t   rx_frag_cnt;
1076         kstat_named_t   rx_frame_align_err_cnt;
1077         kstat_named_t   rx_linkfault_err_cnt;
1078         kstat_named_t   rx_local_fault_err_cnt;
1079         kstat_named_t   rx_remote_fault_err_cnt;
1080 } nxge_mac_kstat_t, *p_nxge_mac_kstat_t;
1081
1082 typedef struct _nxge_xmac_kstat {
1083         /*
1084          * XMAC statistics.
1085          */
1086         kstat_named_t   tx_frame_cnt;
1087         kstat_named_t   tx_underflow_err;
1088         kstat_named_t   tx_maxpktsize_err;
1089         kstat_named_t   tx_overflow_err;
1090         kstat_named_t   tx_fifo_xfr_err;
1091         kstat_named_t   tx_byte_cnt;
1092         kstat_named_t   rx_frame_cnt;
1093         kstat_named_t   rx_underflow_err;
1094         kstat_named_t   rx_overflow_err;
1095         kstat_named_t   rx_crc_err_cnt;
1096         kstat_named_t   rx_len_err_cnt;
1097         kstat_named_t   rx_viol_err_cnt;
1098         kstat_named_t   rx_byte_cnt;
1099         kstat_named_t   rx_hist1_cnt;
1100         kstat_named_t   rx_hist2_cnt;
1101         kstat_named_t   rx_hist3_cnt;
1102         kstat_named_t   rx_hist4_cnt;
1103         kstat_named_t   rx_hist5_cnt;
1104         kstat_named_t   rx_hist6_cnt;
1105         kstat_named_t   rx_hist7_cnt;
1106         kstat_named_t   rx_broadcast_cnt;
1107         kstat_named_t   rx_mult_cnt;
1108         kstat_named_t   rx_frag_cnt;
1109         kstat_named_t   rx_frame_align_err_cnt;
1110         kstat_named_t   rx_linkfault_err_cnt;
1111         kstat_named_t   rx_remote_fault_err_cnt;
1112         kstat_named_t   rx_local_fault_err_cnt;
1113         kstat_named_t   rx_pause_cnt;
1114         kstat_named_t   xpcs_deskew_err_cnt;
1115         kstat_named_t   xpcs_ln0_symbol_err_cnt;
1116         kstat_named_t   xpcs_ln1_symbol_err_cnt;
1117         kstat_named_t   xpcs_ln2_symbol_err_cnt;
1118         kstat_named_t   xpcs_ln3_symbol_err_cnt;
1119 } nxge_xmac_kstat_t, *p_nxge_xmac_kstat_t;
1120
1121 typedef struct _nxge_bmac_kstat {
1122         /*
1123          * BMAC statistics.
1124          */
1125         kstat_named_t tx_frame_cnt;
1126         kstat_named_t tx_underrun_err;
1127         kstat_named_t tx_max_pkt_err;
1128         kstat_named_t tx_byte_cnt;
1129         kstat_named_t rx_frame_cnt;
1130         kstat_named_t rx_byte_cnt;
1131         kstat_named_t rx_overflow_err;
1132         kstat_named_t rx_align_err_cnt;
1133         kstat_named_t rx_crc_err_cnt;
1134         kstat_named_t rx_len_err_cnt;
1135         kstat_named_t rx_viol_err_cnt;
1136         kstat_named_t rx_pause_cnt;
1137         kstat_named_t tx_pause_state;
1138         kstat_named_t tx_nopause_state;
1139 } nxge_bmac_kstat_t, *p_nxge_bmac_kstat_t;
1140
1141
1142 typedef struct _nxge_fflp_kstat {
1143         /*
1144          * FFLP statistics.
1145          */
1146
1147         kstat_named_t   fflp_tcam_perr;
1148         kstat_named_t   fflp_tcam_ecc_err;
1149         kstat_named_t   fflp_vlan_perr;
1150         kstat_named_t   fflp_hasht_lookup_err;
1151         kstat_named_t   fflp_hasht_data_err[MAX_PARTITION];
1152 } nxge_fflp_kstat_t, *p_nxge_fflp_kstat_t;
1153
1154 typedef struct _nxge_mmac_kstat {
1155         kstat_named_t   mmac_max_addr_cnt;
1156         kstat_named_t   mmac_avail_addr_cnt;
1157         kstat_named_t   mmac_addr1;
1158         kstat_named_t   mmac_addr2;
1159         kstat_named_t   mmac_addr3;
1160         kstat_named_t   mmac_addr4;
1161         kstat_named_t   mmac_addr5;
1162         kstat_named_t   mmac_addr6;
1163         kstat_named_t   mmac_addr7;
1164         kstat_named_t   mmac_addr8;
1165         kstat_named_t   mmac_addr9;
1166         kstat_named_t   mmac_addr10;
1167         kstat_named_t   mmac_addr11;
1168         kstat_named_t   mmac_addr12;
1169         kstat_named_t   mmac_addr13;
1170         kstat_named_t   mmac_addr14;
1171         kstat_named_t   mmac_addr15;
1172         kstat_named_t   mmac_addr16;
1173 } nxge_mmac_kstat_t, *p_nxge_mmac_kstat_t;
1174
1175 /*
1176  * Prototype definitions.
1177  */
1178 nxge_status_t nxge_init(p_nxge_t);
1179 void nxge_uninit(p_nxge_t);
1180 void nxge_get64(p_nxge_t, p_mblk_t);
1181 void nxge_put64(p_nxge_t, p_mblk_t);
1182 void nxge_pio_loop(p_nxge_t, p_mblk_t);
1183
1184 typedef void    (*fptrv_t)();
1185 timeout_id_t    nxge_start_timer(p_nxge_t, fptrv_t, int);
1186 void            nxge_stop_timer(p_nxge_t, timeout_id_t);
1187
1188 #ifdef  __cplusplus
1189 }
1190 #endif
1191
1192 #endif  /* _SYS_NXGE_NXGE_H */