dmake: do not set MAKEFLAGS=k
[unleashed/tickless.git] / usr / src / cmd / fm / eversholt / files / i386 / i86pc / intel.esc
blob2210163a33ab84de3db957a447ceab19afed4517
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
22 /* 
23  * Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved.
24  */ 
26 #pragma dictionary "INTEL" 
29  * Eversholt rules for the intel CPU/Memory
30  */
33  * Ereports for Simple error codes.
34  */
36 #define SMPL_EVENT(leafclass, t) \
37         event ereport.cpu.intel.leafclass@chip/core/strand { within(t) }
39 SMPL_EVENT(unknown, 1s);        
40 SMPL_EVENT(unclassified, 1s);
41 SMPL_EVENT(microcode_rom_parity, 1s);
42 SMPL_EVENT(external, 1s);
43 SMPL_EVENT(frc, 1s);
44 SMPL_EVENT(internal_timer, 1s);
45 SMPL_EVENT(internal_parity, 1s);
46 SMPL_EVENT(internal_unclassified, 1s);
49  * Propogations for all but "external" and "unknown" simple errors.
50  * If the error is uncorrected we produce a fault immediately, otherwise
51  * we diagnose it to an upset and decalre a fault when the SERD engine
52  * trips. prop statement for ereport.cpu.intel.internal_unclassified is
53  * moved to the Nehalem EX section to deal with poison case.
54  */
56 engine serd.cpu.intel.simple@chip/core/strand, N=3, T=72h;
57 event fault.cpu.intel.internal@chip/core/strand,
58     engine=serd.cpu.intel.simple@chip/core/strand;
60 prop fault.cpu.intel.internal@chip/core/strand
61     { payloadprop("error_uncorrected") == 1 ? setserdincrement(4) : 1} (0)->
62     ereport.cpu.intel.microcode_rom_parity@chip/core/strand,
63     ereport.cpu.intel.internal_timer@chip/core/strand,
64     ereport.cpu.intel.internal_parity@chip/core/strand,
65     ereport.cpu.intel.unclassified@chip/core/strand,
66     ereport.cpu.intel.frc@chip/core/strand;
69  * Ereports for Compound error codes.  These are in pairs "foo" and "foo_uc"
70  * for the corrected and uncorrected version of each error type.  All are
71  * detected at chip/core/strand.
72  */
74 #define CMPND_EVENT(leafclass, t) \
75         event ereport.cpu.intel.leafclass@chip/core/strand { within(t) }; \
76         event ereport.cpu.intel.leafclass##_uc@chip/core/strand { within(t) }
79  * Ereports for Compound error codes - intel errors
80  */
81 CMPND_EVENT(l0cache, 1s);
82 CMPND_EVENT(l1cache, 1s);
83 CMPND_EVENT(l2cache, 1s);
84 CMPND_EVENT(cache, 1s);
87  * Ereports for Compound error codes - TLB errors
88  */
89 CMPND_EVENT(l0dtlb, 1s);
90 CMPND_EVENT(l1dtlb, 1s);
91 CMPND_EVENT(l2dtlb, 1s);
92 CMPND_EVENT(dtlb, 1s);
94 CMPND_EVENT(l0itlb, 1s);
95 CMPND_EVENT(l1itlb, 1s);
96 CMPND_EVENT(l2itlb, 1s);
97 CMPND_EVENT(itlb, 1s);
99 CMPND_EVENT(l0tlb, 1s);
100 CMPND_EVENT(l1tlb, 1s);
101 CMPND_EVENT(l2tlb, 1s);
102 CMPND_EVENT(tlb, 1s);
105  * Ereports for Compound error codes - memory hierarchy errors
106  */
107 CMPND_EVENT(l0dcache, 1s);
108 CMPND_EVENT(l1dcache, 1s);
109 CMPND_EVENT(l2dcache, 1s);
110 CMPND_EVENT(dcache, 1s);
112 CMPND_EVENT(l0icache, 1s);
113 CMPND_EVENT(l1icache, 1s);
114 CMPND_EVENT(l2icache, 1s);
115 CMPND_EVENT(icache, 1s);
118  * Ereports for Compound error codes - bus and interconnect errors
119  */
120 CMPND_EVENT(bus_interconnect, 1s);
121 CMPND_EVENT(bus_interconnect_memory, 1s);
122 CMPND_EVENT(bus_interconnect_io, 1s);
125  * Compound error propogations.
127  * We resist the temptation propogate, for example, a single dcache fault
128  * to all ereports mentioning dcache (l0dcache, l1dcache, l2dcache, dcache).
129  * Instead we will diagnose a distinct fault for each possible cache level,
130  * whether or not current chips have dcaches at all levels.
132  * Corrected errors are SERDed and produce a fault when the engine fires;
133  * the same fault is diagnosed immediately for a corresponding uncorrected
134  * error.
135  */
137 #define CMPND_FLT_PROP_1(erptleaf, fltleaf, n, t)                       \
138         engine serd.cpu.intel.fltleaf@chip/core/strand, N=n, T=t;       \
139         event fault.cpu.intel.fltleaf@chip/core/strand,                 \
140             engine=serd.cpu.intel.fltleaf@chip/core/strand;             \
141                                                                         \
142         prop fault.cpu.intel.fltleaf@chip/core/strand (0)->             \
143             ereport.cpu.intel.erptleaf@chip/core/strand;                \
144                                                                         \
145         prop fault.cpu.intel.fltleaf@chip/core/strand                   \
146             { setserdincrement(n + 1) } (0)->                           \
147             ereport.cpu.intel.erptleaf##_uc@chip/core/strand
149 #define CMPND_FLT_PROP_2(erptleaf, fltleaf, n, t)                       \
150         engine serd.cpu.intel.fltleaf@chip/core/strand, N=n, T=t;       \
151         event fault.cpu.intel.fltleaf@chip/core/strand, retire=0, response=0,\
152             engine=serd.cpu.intel.fltleaf@chip/core/strand;             \
153                                                                         \
154         prop fault.cpu.intel.fltleaf@chip/core/strand (0)->             \
155             ereport.cpu.intel.erptleaf@chip/core/strand;                \
156                                                                         \
157         prop fault.cpu.intel.fltleaf@chip/core/strand                   \
158             { setserdincrement(n + 1) } (0)->                           \
159             ereport.cpu.intel.erptleaf##_uc@chip/core/strand
161 CMPND_FLT_PROP_1(l0cache, l0cache, 3, 72h);
162 CMPND_FLT_PROP_1(l1cache, l1cache, 3, 72h);
163 CMPND_FLT_PROP_1(l2cache, l2cache, 3, 72h);
164 CMPND_FLT_PROP_1(cache, cache, 12, 72h);
166 CMPND_FLT_PROP_1(l0dtlb, l0dtlb, 3, 72h);
167 CMPND_FLT_PROP_1(l1dtlb, l1dtlb, 3, 72h);
168 CMPND_FLT_PROP_1(l2dtlb, l2dtlb, 3, 72h);
169 CMPND_FLT_PROP_1(dtlb, dtlb, 12, 72h);
171 CMPND_FLT_PROP_1(l0itlb, l0itlb, 3, 72h);
172 CMPND_FLT_PROP_1(l1itlb, l1itlb, 3, 72h);
173 CMPND_FLT_PROP_1(l2itlb, l2itlb, 3, 72h);
174 CMPND_FLT_PROP_1(itlb, itlb, 12, 72h);
176 CMPND_FLT_PROP_1(l0tlb, l0tlb, 3, 72h);
177 CMPND_FLT_PROP_1(l1tlb, l1tlb, 3, 72h);
178 CMPND_FLT_PROP_1(l2tlb, l2tlb, 3, 72h);
179 CMPND_FLT_PROP_1(tlb, tlb, 12, 72h);
181 CMPND_FLT_PROP_1(l0dcache, l0dcache, 3, 72h);
182 CMPND_FLT_PROP_1(l1dcache, l1dcache, 3, 72h);
183 CMPND_FLT_PROP_1(l2dcache, l2dcache, 3, 72h);
184 CMPND_FLT_PROP_1(dcache, dcache, 12, 72h);
186 CMPND_FLT_PROP_1(l0icache, l0icache, 3, 72h);
187 CMPND_FLT_PROP_1(l1icache, l1icache, 3, 72h);
188 CMPND_FLT_PROP_1(l2icache, l2icache, 3, 72h);
189 CMPND_FLT_PROP_1(icache, icache, 12, 72h);
191 CMPND_FLT_PROP_2(bus_interconnect, bus_interconnect, 10, 72h);
192 CMPND_FLT_PROP_2(bus_interconnect_memory, bus_interconnect_memory, 10, 72h);
193 CMPND_FLT_PROP_2(bus_interconnect_io, bus_interconnect_io, 10, 72h);
195 event upset.discard@chip/core/strand;
197 event ereport.cpu.intel.unknown@chip {within(15s)};
198 prop upset.discard@chip/core/strand (0)->
199     ereport.cpu.intel.external@chip/core/strand,
200     ereport.cpu.intel.unknown@chip/core/strand,
201     ereport.cpu.intel.unknown@chip;
203 /* errors detected in northbridge */
207  * SET_ADDR and SET_OFFSET are used to set a payload value in the fault that
208  * we diagnose for page faults, to record the physical address of the faulting
209  * page.
210  */
211 #define SET_ADDR (!payloadprop_defined("physaddr") || \
212     setpayloadprop("asru-physaddr", payloadprop("physaddr")))
214 #define SET_OFFSET (!payloadprop_defined("offset") || \
215     setpayloadprop("asru-offset", payloadprop("offset")))
217 #define EREPORT_BUS_ERROR                                               \
218     ereport.cpu.intel.bus_interconnect_memory_uc@chip/core/strand,      \
219     ereport.cpu.intel.bus_interconnect_uc@chip/core/strand,             \
220     ereport.cpu.intel.bus_interconnect_memory@chip/core/strand,         \
221     ereport.cpu.intel.bus_interconnect@chip/core/strand,                \
222     ereport.cpu.intel.external@chip/core/strand
224 engine stat.ce_pgflt@memory-controller/dram-channel/dimm;
226 event ereport.cpu.intel.nb.mem_ue@motherboard/memory-controller{within(12s)};
227 event ereport.cpu.intel.nb.ddr2_mem_ue@
228     motherboard/memory-controller{within(12s)};
229 event ereport.cpu.intel.nb.fbd.ma@motherboard/memory-controller{within(12s)};
230 event fault.memory.intel.page_ue@
231     motherboard/memory-controller/dram-channel/dimm/rank,
232     message=0, response=0;
233 event fault.memory.intel.dimm_ue@
234     motherboard/memory-controller/dram-channel/dimm/rank;
236 prop fault.memory.intel.page_ue@
237     motherboard/memory-controller/dram-channel/dimm/rank[rank_num]
238     { payloadprop_defined("rank") && rank_num == payloadprop("rank") &&
239     (payloadprop_defined("physaddr") || payloadprop_defined("offset")) &&
240     SET_ADDR && SET_OFFSET } (1)->
241     ereport.cpu.intel.nb.mem_ue@motherboard/memory-controller,
242     ereport.cpu.intel.nb.ddr2_mem_ue@motherboard/memory-controller,
243     ereport.cpu.intel.nb.fbd.ma@motherboard/memory-controller;
245 prop fault.memory.intel.dimm_ue@
246     motherboard/memory-controller/dram-channel/dimm/rank[rank_num]
247     { payloadprop_defined("rank") && rank_num == payloadprop("rank") } (1)->
248     ereport.cpu.intel.nb.mem_ue@motherboard/memory-controller,
249     ereport.cpu.intel.nb.ddr2_mem_ue@motherboard/memory-controller,
250     ereport.cpu.intel.nb.fbd.ma@motherboard/memory-controller;
252 event upset.memory.intel.discard@motherboard/memory-controller{within(1s)};
254 prop upset.memory.intel.discard@motherboard/memory-controller (0)->
255     ereport.cpu.intel.nb.mem_ue@motherboard/memory-controller,
256     ereport.cpu.intel.nb.ddr2_mem_ue@motherboard/memory-controller,
257     ereport.cpu.intel.nb.fbd.ma@motherboard/memory-controller;
259 prop upset.memory.intel.discard@motherboard/memory-controller (0)->
260     EREPORT_BUS_ERROR;
262 #define PAGE_CE_COUNT   2
263 #define PAGE_CE_TIME    72h
264 #define DIMM_CE_COUNT   10
265 #define DIMM_CE_TIME    1week
267 #define MBDIMM motherboard/memory-controller/dram-channel/dimm
268 event ereport.cpu.intel.nb.mem_ce@MBDIMM/rank{within(12s)};
269 event ereport.cpu.intel.nb.ddr2_mem_ce@MBDIMM/rank{within(12s)};
270 event ereport.cpu.intel.nb.ddr2_mem_ce@
271     motherboard/memory-controller{within(12s)};
273 engine serd.memory.intel.page_ce@MBDIMM/rank, N=PAGE_CE_COUNT, T=PAGE_CE_TIME;
274 event fault.memory.intel.page_ce@MBDIMM/rank, message=0, response=0,
275     count=stat.ce_pgflt@MBDIMM, engine=serd.memory.intel.page_ce@MBDIMM/rank;
276 prop fault.memory.intel.page_ce@MBDIMM/rank
277     { (payloadprop_defined("physaddr") || payloadprop_defined("offset")) &&
278     SET_ADDR && SET_OFFSET } (0)->
279     ereport.cpu.intel.nb.mem_ce@MBDIMM/rank,
280     ereport.cpu.intel.nb.ddr2_mem_ce@MBDIMM/rank;
282 engine serd.memory.intel.dimm_ce@MBDIMM/rank, N=DIMM_CE_COUNT, T=DIMM_CE_TIME;
283 event fault.memory.intel.dimm_ce@MBDIMM/rank,
284     engine=serd.memory.intel.dimm_ce@MBDIMM/rank;
285 prop fault.memory.intel.dimm_ce@MBDIMM/rank
286     { !confprop_defined(MBDIMM, "dimm-size") &&
287     count(stat.ce_pgflt@MBDIMM) > 512 } (1)->
288     ereport.cpu.intel.nb.mem_ce@MBDIMM/rank,
289     ereport.cpu.intel.nb.ddr2_mem_ce@MBDIMM/rank;
290 #define DIMM_CE(dimm_size, n, t, fault_rate) \
291         prop fault.memory.intel.dimm_ce@MBDIMM/rank { \
292             confprop(MBDIMM, "dimm-size") == dimm_size && \
293             count(stat.ce_pgflt@MBDIMM) > fault_rate && \
294             setserdn(n) & setserdt(t) } (1)-> \
295             ereport.cpu.intel.nb.mem_ce@MBDIMM/rank, \
296             ereport.cpu.intel.nb.ddr2_mem_ce@MBDIMM/rank;
297         
298 DIMM_CE("8G", 8, 1week, 2000)
299 DIMM_CE("4G", 4, 1week, 1500)
300 DIMM_CE("2G", 4, 2week, 1000)
301 DIMM_CE("1G", 4, 4week, 500)
302 DIMM_CE("512M", 4, 8week, 250)
303 DIMM_CE("256M", 4, 16week, 125)
305 prop upset.memory.intel.discard@motherboard/memory-controller (0)->
306     ereport.cpu.intel.nb.ddr2_mem_ce@motherboard/memory-controller;
308 event ereport.cpu.intel.nb.fbd.alert@rank{within(12s)};
309 event fault.memory.intel.fbd.alert@rank, retire=0;
311 prop fault.memory.intel.fbd.alert@rank (1)->
312     ereport.cpu.intel.nb.fbd.alert@rank;
314 prop fault.memory.intel.fbd.alert@rank (0)->
315     EREPORT_BUS_ERROR;
317 event ereport.cpu.intel.nb.fbd.crc@rank{within(12s)};
318 event fault.memory.intel.fbd.crc@rank, retire=0;
320 prop fault.memory.intel.fbd.crc@rank (1)->
321     ereport.cpu.intel.nb.fbd.crc@rank;
323 prop fault.memory.intel.fbd.crc@rank (0)-> EREPORT_BUS_ERROR;
325 event ereport.cpu.intel.nb.fbd.reset_timeout@memory-controller {within(12s)};
326 event fault.memory.intel.fbd.reset_timeout@memory-controller, retire=0;
328 prop fault.memory.intel.fbd.reset_timeout@memory-controller (1)->
329     ereport.cpu.intel.nb.fbd.reset_timeout@memory-controller;
331 prop fault.memory.intel.fbd.reset_timeout@memory-controller (0)->
332     EREPORT_BUS_ERROR;
334 event ereport.cpu.intel.nb.fbd.ch@dram-channel {within(12s)};
335 engine serd.cpu.intel.nb.fbd.ch@dram-channel, N=2, T=1month;
336 event fault.memory.intel.fbd.ch@dram-channel, retire=0,
337     engine=serd.cpu.intel.nb.fbd.ch@dram-channel;
339 prop fault.memory.intel.fbd.ch@dram-channel (1)->
340     ereport.cpu.intel.nb.fbd.ch@dram-channel;
342 prop fault.memory.intel.fbd.ch@dram-channel (0)->
343     EREPORT_BUS_ERROR;
345 event ereport.cpu.intel.nb.fbd.otf@dram-channel {within(12s)};
346 engine serd.cpu.intel.nb.fbd_otf@dram-channel, N=2, T=1week;
347 event fault.memory.intel.fbd.otf@dram-channel, retire=0, response=0,
348     engine=serd.cpu.intel.nb.fbd_otf@dram-channel;
350 prop fault.memory.intel.fbd.otf@dram-channel (1)->
351     ereport.cpu.intel.nb.fbd.otf@dram-channel;
353 event ereport.cpu.intel.nb.otf@motherboard {within(12s)};
354 event fault.cpu.intel.nb.otf@motherboard, retire=0, response=0;
356 prop fault.cpu.intel.nb.otf@motherboard (1)->
357     ereport.cpu.intel.nb.otf@motherboard;
359 event ereport.cpu.intel.nb.unknown@motherboard {within(12s)};
360 event ereport.cpu.intel.nb.unknown@memory-controller {within(12s)};
361 event ereport.cpu.intel.nb.unknown@memory-controller/dram-channel {within(12s)};
362 event ereport.cpu.intel.nb.spd@memory-controller/dram-channel {within(12s)};
363 event ereport.cpu.intel.nb.ddr2_spd@
364     memory-controller/dram-channel {within(12s)};
365 event upset.discard@memory-controller;
367 prop upset.discard@memory-controller (0)->
368     ereport.cpu.intel.nb.unknown@motherboard,
369     ereport.cpu.intel.nb.unknown@memory-controller,
370     ereport.cpu.intel.nb.unknown@memory-controller/dram-channel,
371     ereport.cpu.intel.nb.spd@memory-controller/dram-channel,
372     ereport.cpu.intel.nb.ddr2_spd@memory-controller/dram-channel;
374 event ereport.cpu.intel.nb.mem_ds@memory-controller{within(30s)};
375 event ereport.cpu.intel.nb.ddr2_mem_ds@memory-controller{within(30s)};
376 event fault.memory.intel.fbd.mem_ds@memory-controller/dram-channel/dimm/rank,
377     retire=0;
379 prop fault.memory.intel.fbd.mem_ds@
380     memory-controller/dram-channel/dimm/rank[rank_num]
381     { payloadprop_defined("rank") && rank_num == payloadprop("rank") } (1)->
382     ereport.cpu.intel.nb.mem_ds@memory-controller,
383     ereport.cpu.intel.nb.ddr2_mem_ds@memory-controller;
385 event ereport.cpu.intel.nb.fsb@chip{within(12s)};
386 event fault.cpu.intel.nb.fsb@chip, retire=0;
388 prop fault.cpu.intel.nb.fsb@chip (1)->
389     ereport.cpu.intel.nb.fsb@chip;
391 prop fault.cpu.intel.nb.fsb@chip (0)-> EREPORT_BUS_ERROR;
393 event ereport.cpu.intel.nb.ie@motherboard{within(12s)};
394 event fault.cpu.intel.nb.ie@motherboard, retire=0;
395 event upset.cpu.intel.nb.ie_ce@motherboard{within(12s)};
397 prop upset.cpu.intel.nb.ie_ce@motherboard
398     { payloadprop("intel-error-list") == "B6" } (0)->
399     ereport.cpu.intel.nb.ie@motherboard;
401 prop fault.cpu.intel.nb.ie@motherboard
402     { payloadprop("intel-error-list") != "B6" } (1)->
403     ereport.cpu.intel.nb.ie@motherboard;
405 prop fault.cpu.intel.nb.ie@motherboard (0)-> EREPORT_BUS_ERROR;
407 event ereport.cpu.intel.nb.dma@motherboard{within(12s)};
408 event upset.cpu.intel.nb.dma@motherboard;
410 prop upset.cpu.intel.nb.dma@motherboard (1)->
411     ereport.cpu.intel.nb.dma@motherboard;
413 event ereport.cpu.intel.nb.esi@motherboard{within(12s)};
414 event ereport.cpu.intel.nb.pex@hostbridge{within(12s)};
415 event upset.cpu.intel.nb.pex@hostbridge;
417 prop upset.cpu.intel.nb.pex@hostbridge (1)->
418     ereport.cpu.intel.nb.esi@motherboard,
419     ereport.cpu.intel.nb.pex@hostbridge;
421 prop upset.cpu.intel.nb.pex@hostbridge (0)-> EREPORT_BUS_ERROR;
423 event ereport.cpu.intel.nb.unknown@rank{within(12s)};
424 event upset.discard@rank;
426 prop upset.discard@rank (1)->
427     ereport.cpu.intel.nb.unknown@rank;
429 prop upset.discard@rank (0)-> EREPORT_BUS_ERROR;
432  * CPU integrated memory controller
433  */
435 #define CONTAINS_RANK (payloadprop_contains("resource", \
436     asru(chip/memory-controller/dram-channel/dimm/rank)) || \
437     payloadprop_contains("resource", \
438     asru(chip/memory-controller/dram-channel/dimm)))
440 #define STAT_CPU_MEM_CE_PGFLTS \
441     stat.ce_pgflt@chip/memory-controller/dram-channel/dimm
443 #define SET_RES_OFFSET \
444     (!payloadprop_defined("resource[0].hc-specific.offset") || \
445     setpayloadprop("asru-offset", \
446     payloadprop("resource[0].hc-specific.offset")))
448 engine STAT_CPU_MEM_CE_PGFLTS;
450 event ereport.cpu.intel.quickpath.mem_ue@chip/memory-controller
451     {within(12s)}, discard_if_config_unknown=1;
453 event fault.memory.intel.page_ue@
454     chip/memory-controller/dram-channel/dimm/rank,
455     message=0, response=0;              /* do not message individual pageflts */
457 prop fault.memory.intel.page_ue@
458     chip/memory-controller/dram-channel/dimm/rank
459     { CONTAINS_RANK && (payloadprop_defined("physaddr") ||
460     payloadprop_defined("resource[0].hc-specific.offset")) &&
461     SET_ADDR && SET_RES_OFFSET } (0)->
462     ereport.cpu.intel.quickpath.mem_ue@chip/memory-controller;
464 #define CHIPDIMM chip/memory-controller/dram-channel/dimm
466 event fault.memory.intel.dimm_ue@CHIPDIMM/rank;
468 event error.memory.intel.dimm_ue_ep@CHIPDIMM/rank;
469 event error.memory.intel.dimm_ue_ex@CHIPDIMM/rank;
471 prop fault.memory.intel.dimm_ue@CHIPDIMM/rank (1)->
472    error.memory.intel.dimm_ue_ep@CHIPDIMM/rank,
473    error.memory.intel.dimm_ue_ex@CHIPDIMM/rank;
475 prop error.memory.intel.dimm_ue_ep@CHIPDIMM/rank
476     { CONTAINS_RANK } (1)->
477     ereport.cpu.intel.quickpath.mem_ue@chip/memory-controller;
479 prop fault.memory.intel.dimm_ue@CHIPDIMM/rank (0)-> EREPORT_BUS_ERROR;
481 event ereport.cpu.intel.quickpath.mem_ce@
482     chip/memory-controller {within(12s)}, discard_if_config_unknown=1;
484 engine serd.memory.intel.page_ce@CHIPDIMM/rank, N=PAGE_CE_COUNT, T=PAGE_CE_TIME;
485 event fault.memory.intel.page_ce@CHIPDIMM/rank, message=0, response=0,
486     count=STAT_CPU_MEM_CE_PGFLTS,
487     engine=serd.memory.intel.page_ce@CHIPDIMM/rank;
488 prop fault.memory.intel.page_ce@CHIPDIMM/rank
489     { CONTAINS_RANK && (payloadprop_defined("physaddr") ||
490     payloadprop_defined("resource[0].hc-specific.offset")) &&
491     SET_ADDR && SET_RES_OFFSET } (0)->
492     ereport.cpu.intel.quickpath.mem_ce@chip/memory-controller;
494 engine serd.memory.intel.dimm_ce@CHIPDIMM, N=PAGE_CE_COUNT, T=PAGE_CE_TIME;
495 event fault.memory.intel.dimm_ce@CHIPDIMM,
496     engine=serd.memory.intel.dimm_ce@CHIPDIMM;
497 prop fault.memory.intel.dimm_ce@CHIPDIMM
498     { !confprop_defined(CHIPDIMM, "dimm-size") &&
499     count(STAT_CPU_MEM_CE_PGFLTS) > 512 } (0)->
500     ereport.cpu.intel.quickpath.mem_ce@chip/memory-controller;
502 #define CPU_MEM_DIMM_CE(dimm_size, n, t, fault_rate) \
503         prop fault.memory.intel.dimm_ce@CHIPDIMM { \
504             confprop(CHIPDIMM, "dimm-size") == dimm_size && \
505             count(STAT_CPU_MEM_CE_PGFLTS) > fault_rate && \
506             setserdn(n) & setserdt(t) } (0)-> \
507             ereport.cpu.intel.quickpath.mem_ce@ \
508             chip/memory-controller;
510 CPU_MEM_DIMM_CE("16G", 16, 1week, 2000)
511 CPU_MEM_DIMM_CE("8G", 8, 1week, 2000)
512 CPU_MEM_DIMM_CE("4G", 4, 1week, 1500)
513 CPU_MEM_DIMM_CE("2G", 4, 2week, 1000)
514 CPU_MEM_DIMM_CE("1G", 4, 4week, 500)
515 CPU_MEM_DIMM_CE("512M", 4, 8week, 250)
517 event ereport.cpu.intel.quickpath.mem_unknown@chip/memory-controller
518     {within(12s)}, discard_if_config_unknown=1;
519 event ereport.cpu.intel.quickpath.mem_unknown@
520     chip/memory-controller/dram-channel {within(12s)},
521     discard_if_config_unknown=1;
522 event ereport.cpu.intel.quickpath.mem_unknown@
523     chip/memory-controller/dram-channel/dimm/rank{within(12s)};
524 event upset.discard@chip/memory-controller;
525 event upset.discard@chip/memory-controller/dram-channel/dimm/rank;
527 prop upset.discard@chip/memory-controller (0)->
528     ereport.cpu.intel.quickpath.mem_unknown@chip/memory-controller,
529     ereport.cpu.intel.quickpath.mem_unknown@
530     chip/memory-controller/dram-channel;
532 prop upset.discard@
533     chip/memory-controller/dram-channel/dimm/rank (1)->
534     ereport.cpu.intel.quickpath.mem_unknown@
535     chip/memory-controller/dram-channel/dimm/rank;
537 event ereport.cpu.intel.quickpath.mem_parity@chip/memory-controller
538     {within(1s)}, discard_if_config_unknown=1;
539 event fault.cpu.intel.quickpath.mem_parity@chip/memory-controller;
541 prop fault.cpu.intel.quickpath.mem_parity@chip/memory-controller (1)->
542     ereport.cpu.intel.quickpath.mem_parity@chip/memory-controller;
544 event ereport.cpu.intel.quickpath.mem_addr_parity@chip/memory-controller
545     {within(1s)}, discard_if_config_unknown=1;
546 event fault.cpu.intel.quickpath.mem_addr_parity@
547     chip/memory-controller;
548 event fault.cpu.intel.quickpath.mem_addr_parity@CHIPDIMM;
549 event fault.cpu.intel.quickpath.mem_addr_parity@CHIPDIMM/rank;
551 prop fault.cpu.intel.quickpath.mem_addr_parity@
552     chip/memory-controller (1)->
553     ereport.cpu.intel.quickpath.mem_addr_parity@chip/memory-controller;
555 prop fault.cpu.intel.quickpath.mem_addr_parity@CHIPDIMM
556     { payloadprop_contains("resource", asru(CHIPDIMM)) } (1)->
557     ereport.cpu.intel.quickpath.mem_addr_parity@chip/memory-controller;
559 prop fault.cpu.intel.quickpath.mem_addr_parity@CHIPDIMM/rank
560     { payloadprop_contains("resource", asru(CHIPDIMM/rank)) } (1)->
561     ereport.cpu.intel.quickpath.mem_addr_parity@chip/memory-controller;
563 event ereport.cpu.intel.quickpath.mem_bad_addr@chip/memory-controller
564     {within(1s)}, discard_if_config_unknown=1;
565 event fault.cpu.intel.quickpath.mem_bad_addr@chip/memory-controller;
567 prop fault.cpu.intel.quickpath.mem_bad_addr@chip/memory-controller (1)->
568     ereport.cpu.intel.quickpath.mem_bad_addr@chip/memory-controller;
570 event ereport.cpu.intel.quickpath.mem_spare@chip/memory-controller
571     {within(1s)}, discard_if_config_unknown=1;
572 event fault.cpu.intel.quickpath.mem_spare@
573     chip/memory-controller/dram-channel/dimm;
575 prop fault.cpu.intel.quickpath.mem_spare@
576     chip/memory-controller/dram-channel/dimm (1)->
577     ereport.cpu.intel.quickpath.mem_spare@chip/memory-controller;
579 event ereport.cpu.intel.quickpath.mem_bad_id@chip/memory-controller
580     {within(1s)}, discard_if_config_unknown=1;
581 event fault.cpu.intel.quickpath.mem_bad_id@chip/memory-controller;
583 prop fault.cpu.intel.quickpath.mem_bad_id@chip/memory-controller (1)->
584     ereport.cpu.intel.quickpath.mem_bad_id@chip/memory-controller;
586 event ereport.cpu.intel.quickpath.mem_redundant@chip/memory-controller
587     {within(1s)}, discard_if_config_unknown=1;
588 engine serd.cpu.intel.quickpath.mem_redundant@CHIPDIMM, N=2, T=72h;
589 event fault.cpu.intel.quickpath.mem_redundant@CHIPDIMM,
590     engine=serd.cpu.intel.quickpath.mem_redundant@CHIPDIMM;
592 event error.cpu.intel.quickpath.mem_redundant@CHIPDIMM/rank;
594 prop fault.cpu.intel.quickpath.mem_redundant@CHIPDIMM (1)->
595     error.cpu.intel.quickpath.mem_redundant@CHIPDIMM/rank<>;
596 prop error.cpu.intel.quickpath.mem_redundant@CHIPDIMM/rank
597     { CONTAINS_RANK } (1)->
598     ereport.cpu.intel.quickpath.mem_redundant@
599     chip/memory-controller;
601 #define STATUS_UC       (payloadprop("error_uncorrected") == 1)
602 event ereport.cpu.intel.quickpath.interconnect@chip
603     {within(1s)};
604 event upset.cpu.intel.quickpath.interconnect@chip;
605 /* Diagnose corrected events to upsets */
606 prop upset.cpu.intel.quickpath.interconnect@chip
607     { !STATUS_UC } (1)->
608     ereport.cpu.intel.quickpath.interconnect@chip;
610 engine serd.cpu.intel.quickpath.interconnect@chip,
611         N=3, T=72h;
612 event fault.cpu.intel.quickpath.interconnect@chip,
613     engine=serd.cpu.intel.quickpath.interconnect@chip;
615 /* Diagnose uncorrected events to faults */
616 prop fault.cpu.intel.quickpath.interconnect@chip
617     { STATUS_UC } (0)->
618     ereport.cpu.intel.quickpath.interconnect@chip;
622  * Nehalem EX specific rules
623  */
624 /* MBox errors */
625 #define EX_MEM_EVENT(leafclass, t) \
626         event ereport.cpu.intel.quickpath.leafclass@ \
627         chip/memory-controller { within(t) }, discard_if_config_unknown=1
629 EX_MEM_EVENT(mem_lnktrns, 1s);
630 EX_MEM_EVENT(mem_lnkpers, 1s);
631 EX_MEM_EVENT(mem_sbfbdlinkerr, 1s);
632 EX_MEM_EVENT(mem_nbfbdlnkerr, 1s);
633 EX_MEM_EVENT(mem_lnkcrcvld, 1s);
635 engine serd.cpu.intel.quickpath.mem_link_ce@chip/memory-controller,
636       N=500, T=1week;
637 event fault.cpu.intel.quickpath.mem_link_ce@chip/memory-controller,
638       engine=serd.cpu.intel.quickpath.mem_link_ce@chip/memory-controller,
639       retire=0, response=0;
641 prop fault.cpu.intel.quickpath.mem_link_ce@chip/memory-controller ->
642     ereport.cpu.intel.quickpath.mem_lnktrns@chip/memory-controller,
643     ereport.cpu.intel.quickpath.mem_lnkpers@chip/memory-controller,
644     ereport.cpu.intel.quickpath.mem_sbfbdlinkerr@chip/memory-controller,
645     ereport.cpu.intel.quickpath.mem_nbfbdlnkerr@chip/memory-controller,
646     ereport.cpu.intel.quickpath.mem_lnkcrcvld@chip/memory-controller;
648 EX_MEM_EVENT(mem_lnkuncorr_uc, 1s);
649 EX_MEM_EVENT(mem_lnkpers_uc, 1s);
650 EX_MEM_EVENT(mem_sbfbdlinkerr_uc, 1s);
651 EX_MEM_EVENT(mem_nbfbdlnkerr_uc, 1s);
652 EX_MEM_EVENT(mem_lnkcrcvld_uc, 1s);
654 event fault.cpu.intel.quickpath.mem_link_ue@chip/memory-controller,
655       retire=0;
657 prop fault.cpu.intel.quickpath.mem_link_ue@chip/memory-controller ->
658     ereport.cpu.intel.quickpath.mem_lnkuncorr_uc@chip/memory-controller,
659     ereport.cpu.intel.quickpath.mem_lnkpers_uc@chip/memory-controller,
660     ereport.cpu.intel.quickpath.mem_sbfbdlinkerr_uc@chip/memory-controller,
661     ereport.cpu.intel.quickpath.mem_nbfbdlnkerr_uc@chip/memory-controller,
662     ereport.cpu.intel.quickpath.mem_lnkcrcvld_uc@chip/memory-controller;
664 EX_MEM_EVENT(mem_ptrl_fsm_err, 1s);
665 EX_MEM_EVENT(mem_errflw_fsm_fail, 1s);
666 EX_MEM_EVENT(mem_vberr, 1s);
668 engine serd.cpu.intel.quickpath.mem_controller_ce@chip/memory-controller,
669       N=500, T=1week;
670 event fault.cpu.intel.quickpath.mem_controller_ce@chip/memory-controller,
671       engine=serd.cpu.intel.quickpath.mem_controller_ce@chip/memory-controller,
672       retire=0, response=0;
674 prop fault.cpu.intel.quickpath.mem_controller_ce@chip/memory-controller ->
675     ereport.cpu.intel.quickpath.mem_ptrl_fsm_err@chip/memory-controller,
676     ereport.cpu.intel.quickpath.mem_errflw_fsm_fail@chip/memory-controller,
677     ereport.cpu.intel.quickpath.mem_vberr@chip/memory-controller;
679 EX_MEM_EVENT(mem_ptrl_fsm_err_uc, 1s);
680 EX_MEM_EVENT(mem_errflw_fsm_fail_uc, 1s);
681 EX_MEM_EVENT(mem_mcpar_fsmerr_uc, 1s);
682 EX_MEM_EVENT(mem_vberr_uc, 1s);
683 EX_MEM_EVENT(mem_fberr_uc, 1s);
685 event fault.cpu.intel.quickpath.mem_controller_ue@chip/memory-controller,
686       retire=0;
688 prop fault.cpu.intel.quickpath.mem_controller_ue@chip/memory-controller ->
689     ereport.cpu.intel.quickpath.mem_ptrl_fsm_err_uc@chip/memory-controller,
690     ereport.cpu.intel.quickpath.mem_errflw_fsm_fail_uc@chip/memory-controller,
691     ereport.cpu.intel.quickpath.mem_mcpar_fsmerr_uc@chip/memory-controller,
692     ereport.cpu.intel.quickpath.mem_vberr_uc@chip/memory-controller,
693     ereport.cpu.intel.quickpath.mem_fberr_uc@chip/memory-controller;
695 EX_MEM_EVENT(mem_scrubbing_uc, 1s);
696 event fault.cpu.intel.quickpath.mem_scrubbing@
697     chip/memory-controller/dram-channel/dimm/rank,
698     response=0;
700 prop fault.cpu.intel.quickpath.mem_scrubbing@
701     chip/memory-controller/dram-channel/dimm/rank[rank_num]
702     { payloadprop_defined("rank") && rank_num == payloadprop("rank") &&
703       (payloadprop_defined("physaddr") || payloadprop_defined("offset")) &&
704       SET_ADDR && SET_OFFSET } (1)->
705     ereport.cpu.intel.quickpath.mem_scrubbing_uc@chip/memory-controller;
707 EX_MEM_EVENT(mem_ecc_uc, 12s);
708 EX_MEM_EVENT(mem_even_parity_uc, 1s);
710 EX_MEM_EVENT(mem_ecc, 12s);
711 EX_MEM_EVENT(mem_even_parity, 1s);
713 event error.memory.intel.ex_dimm_ce@
714     chip/memory-controller/dram-channel/dimm/rank;
716 prop fault.memory.intel.page_ue@
717     chip/memory-controller/dram-channel/dimm/rank[rank_num]
718     { payloadprop_defined("rank") && rank_num == payloadprop("rank") &&
719       (payloadprop_defined("physaddr") || payloadprop_defined("offset")) &&
720       SET_ADDR && SET_OFFSET } (0)->
721     ereport.cpu.intel.quickpath.mem_ecc_uc@chip/memory-controller,
722     ereport.cpu.intel.quickpath.mem_even_parity_uc@chip/memory-controller;
724 prop fault.memory.intel.page_ce@
725     chip/memory-controller/dram-channel/dimm/rank[rank_num]
726     { payloadprop_defined("rank") && rank_num == payloadprop("rank") &&
727       (payloadprop_defined("physaddr") || payloadprop_defined("offset")) &&
728       SET_ADDR && SET_OFFSET } (0)->
729     ereport.cpu.intel.quickpath.mem_ecc@chip/memory-controller,
730     ereport.cpu.intel.quickpath.mem_even_parity@chip/memory-controller;
732 prop error.memory.intel.dimm_ue_ex@
733     chip/memory-controller/dram-channel/dimm/rank[rank_num]
734     { payloadprop_defined("rank") && rank_num == payloadprop("rank") } (1)->
735     ereport.cpu.intel.quickpath.mem_ecc_uc@chip/memory-controller,
736     ereport.cpu.intel.quickpath.mem_even_parity_uc@chip/memory-controller;
738 prop fault.memory.intel.dimm_ce@
739     chip/memory-controller/dram-channel/dimm
740     { !confprop_defined(chip/memory-controller/dram-channel/dimm,
741     "dimm-size") && setserdn(10) & setserdt(1week) } (0)->
742     error.memory.intel.ex_dimm_ce@
743      chip/memory-controller/dram-channel/dimm/rank;
744 prop error.memory.intel.ex_dimm_ce@
745     chip/memory-controller/dram-channel/dimm/rank[rank_num]
746     { payloadprop_defined("rank") && rank_num == payloadprop("rank") &&
747       !confprop_defined(chip/memory-controller/dram-channel/dimm,
748     "dimm-size") &&
749     count(STAT_CPU_MEM_CE_PGFLTS) > 512 } (1)->
750     ereport.cpu.intel.quickpath.mem_ecc@chip/memory-controller,
751     ereport.cpu.intel.quickpath.mem_even_parity@chip/memory-controller;
753 #define EX_CPU_MEM_DIMM_CE(dimm_size, n, t, fault_rate) \
754         prop fault.memory.intel.dimm_ce@ \
755             chip/memory-controller/dram-channel/dimm { \
756             confprop(chip/memory-controller/dram-channel/dimm, \
757             "dimm-size") == dimm_size && \
758             setserdn(n) & setserdt(t) } (0)-> \
759             error.memory.intel.ex_dimm_ce@ \
760             chip/memory-controller/dram-channel/dimm/rank; \
761         prop error.memory.intel.ex_dimm_ce@ \
762             chip/memory-controller/dram-channel/dimm/rank[rank_num] { \
763             payloadprop_defined("rank") && rank_num == payloadprop("rank") && \
764             confprop(chip/memory-controller/dram-channel/dimm, \
765             "dimm-size") == dimm_size && \
766             count(STAT_CPU_MEM_CE_PGFLTS) > fault_rate } (1)-> \
767             ereport.cpu.intel.quickpath.mem_ecc@chip/memory-controller, \
768             ereport.cpu.intel.quickpath.mem_even_parity@chip/memory-controller;
770 EX_CPU_MEM_DIMM_CE("16G", 16, 1week, 2000)
771 EX_CPU_MEM_DIMM_CE("8G", 8, 1week, 2000)
772 EX_CPU_MEM_DIMM_CE("4G", 4, 1week, 1500)
773 EX_CPU_MEM_DIMM_CE("2G", 4, 2week, 1000)
774 EX_CPU_MEM_DIMM_CE("1G", 4, 4week, 500)
776 event upset.memory.intel.discard@chip/memory-controller{within(1s)};
778 prop upset.memory.intel.discard@chip/memory-controller (0)->
779     ereport.cpu.intel.quickpath.mem_scrubbing_uc@chip/memory-controller,
780     ereport.cpu.intel.quickpath.mem_ecc_uc@chip/memory-controller,
781     ereport.cpu.intel.quickpath.mem_even_parity_uc@chip/memory-controller,
782     ereport.cpu.intel.quickpath.mem_ecc@chip/memory-controller,
783     ereport.cpu.intel.quickpath.mem_even_parity@chip/memory-controller;
785 EX_MEM_EVENT(mem_failover_mir, 1s);
786 event fault.cpu.intel.quickpath.mem_failover_mir@chip/memory-controller,
787       retire=0;
789 prop fault.cpu.intel.quickpath.mem_failover_mir@chip/memory-controller ->
790     ereport.cpu.intel.quickpath.mem_failover_mir@chip/memory-controller;
793  * RBox errors
794  */
795 #define EX_EVENT(leafclass, t) \
796         event ereport.cpu.intel.quickpath.leafclass@chip { within(t) }
798 engine serd.cpu.intel.quickpath.bus_interconnect@chip,
799         N=3, T=72h;
800 event fault.cpu.intel.quickpath.bus_interconnect@chip,
801     engine=serd.cpu.intel.quickpath.bus_interconnect@chip,
802     retire=0;
804 EX_EVENT(bus_retry_abort, 1s);
805 EX_EVENT(bus_link_init_ce, 1s);
806 event upset.cpu.intel.quickpath.discard@chip;
808 prop upset.cpu.intel.quickpath.discard@chip (0)->
809     ereport.cpu.intel.quickpath.bus_retry_abort@chip,
810     ereport.cpu.intel.quickpath.bus_link_init_ce@chip;
812 EX_EVENT(bus_unknown, 1s);
813 EX_EVENT(bus_single_ecc, 1s);
814 EX_EVENT(bus_crc_flit, 1s);
816 prop fault.cpu.intel.quickpath.bus_interconnect@chip (0)->
817     ereport.cpu.intel.quickpath.bus_unknown@chip,
818     ereport.cpu.intel.quickpath.bus_single_ecc@chip,
819     ereport.cpu.intel.quickpath.bus_crc_flit@chip;
821 EX_EVENT(bus_unknown_external, 1s);
822 EX_EVENT(bus_crc_flit_external, 1s);
823 prop upset.cpu.intel.quickpath.discard@chip (0)->
824     ereport.cpu.intel.quickpath.bus_unknown_external@chip,
825     ereport.cpu.intel.quickpath.bus_crc_flit_external@chip;
827 EX_EVENT(bus_unknown_uc, 1s);
828 EX_EVENT(bus_opr_poison_err, 1s);
829 EX_EVENT(bus_eot_parity, 1s);
830 EX_EVENT(bus_rta_parity, 1s);
831 EX_EVENT(bus_bad_sbu_route, 1s);
832 EX_EVENT(bus_bad_msg, 1s);
833 EX_EVENT(bus_bad_vn_credit, 1s);
834 EX_EVENT(bus_hdr_double_ecc, 1s);
835 EX_EVENT(bus_link_retry_err, 1s);
837 prop fault.cpu.intel.quickpath.bus_interconnect@chip
838     { setserdincrement(4) } (0)->
839     ereport.cpu.intel.quickpath.bus_unknown_uc@chip,
840     ereport.cpu.intel.quickpath.bus_opr_poison_err@chip,
841     ereport.cpu.intel.quickpath.bus_eot_parity@chip,
842     ereport.cpu.intel.quickpath.bus_rta_parity@chip,
843     ereport.cpu.intel.quickpath.bus_bad_sbu_route@chip,
844     ereport.cpu.intel.quickpath.bus_bad_msg@chip,
845     ereport.cpu.intel.quickpath.bus_bad_vn_credit@chip,
846     ereport.cpu.intel.quickpath.bus_hdr_double_ecc@chip,
847     ereport.cpu.intel.quickpath.bus_link_retry_err@chip;
849 EX_EVENT(bus_unknown_uc_external, 1s);
850 EX_EVENT(bus_opr_poison_err_external, 1s);
851 EX_EVENT(bus_eot_parity_external, 1s);
852 EX_EVENT(bus_rta_parity_external, 1s);
853 EX_EVENT(bus_bad_sbu_route_external, 1s);
854 EX_EVENT(bus_bad_msg_external, 1s);
855 EX_EVENT(bus_bad_vn_credit_external, 1s);
856 EX_EVENT(bus_hdr_double_ecc_external, 1s);
857 EX_EVENT(bus_link_retry_err_external, 1s);
859 prop upset.cpu.intel.quickpath.discard@chip (0)->
860     ereport.cpu.intel.quickpath.bus_unknown_uc_external@chip,
861     ereport.cpu.intel.quickpath.bus_opr_poison_err_external@chip,
862     ereport.cpu.intel.quickpath.bus_eot_parity_external@chip,
863     ereport.cpu.intel.quickpath.bus_rta_parity_external@chip,
864     ereport.cpu.intel.quickpath.bus_bad_sbu_route_external@chip,
865     ereport.cpu.intel.quickpath.bus_bad_msg_external@chip,
866     ereport.cpu.intel.quickpath.bus_bad_vn_credit_external@chip,
867     ereport.cpu.intel.quickpath.bus_hdr_double_ecc_external@chip,
868     ereport.cpu.intel.quickpath.bus_link_retry_err_external@chip;
871  * CBox errors
872  */
873 EX_EVENT(llc_ewb_uc, 1s);
874 event fault.cpu.intel.quickpath.llc_ewb@chip,
875       retire=0, response=0;
877 prop fault.cpu.intel.quickpath.llc_ewb@chip 
878     { (payloadprop_defined("physaddr") || payloadprop_defined("offset")) &&
879     SET_ADDR && SET_OFFSET } (1)->
880     ereport.cpu.intel.quickpath.llc_ewb_uc@chip;
882 prop upset.cpu.intel.quickpath.discard@chip (0)->
883     ereport.cpu.intel.quickpath.llc_ewb_uc@chip;
886  * SBox errors
887  */
888 EX_EVENT(system_cache_uc, 1s);
889 event fault.cpu.intel.quickpath.system_cache@chip,
890       retire=0, response=0;
891 prop fault.cpu.intel.quickpath.system_cache@chip ->
892     ereport.cpu.intel.quickpath.system_cache_uc@chip;
895  * BBox errors
896  */
897 EX_EVENT(home_agent_uc, 1s);
898 event fault.cpu.intel.quickpath.home_agent@chip,
899       retire=0, response=0;
900 prop fault.cpu.intel.quickpath.home_agent@chip ->
901     ereport.cpu.intel.quickpath.home_agent_uc@chip;
904  * UBox errors
905  */
906 EX_EVENT(sys_cfg_cfa_ecc, 1s);
907 EX_EVENT(sys_cfg_uc, 1s);
909 engine serd.cpu.intel.quickpath.sys_cfg@chip,
910       N=2, T=72h;
911 event fault.cpu.intel.quickpath.sys_cfg@chip,
912       engine=serd.cpu.intel.quickpath.sys_cfg@chip,
913       retire=0, response=0;
915 prop fault.cpu.intel.quickpath.sys_cfg@chip (0)->
916     ereport.cpu.intel.quickpath.sys_cfg_cfa_ecc@chip;
918 prop fault.cpu.intel.quickpath.sys_cfg@chip
919     { setserdincrement(3) } (0)->
920     ereport.cpu.intel.quickpath.sys_cfg_uc@chip;
923  * Handling poison errors
924  */
925 engine stat.has_poison@motherboard;
926 event fault.cpu.intel.has_poison@motherboard,
927       count=stat.has_poison@motherboard[0],
928       message=0, retire=0, response=0;
929 engine stat.discard_fatal@motherboard;
930 event fault.cpu.intel.discard_fatal@motherboard,
931       count=stat.discard_fatal@motherboard[0],
932       message=0, retire=0, response=0;
934 prop fault.cpu.intel.has_poison@motherboard
935     { payloadprop_defined("poison") && 1 == payloadprop("poison") } (1)->
936     ereport.cpu.intel.quickpath.mem_scrubbing_uc@chip<>/memory-controller<>,
937     ereport.cpu.intel.quickpath.llc_ewb_uc@chip<>,
938     ereport.cpu.intel.quickpath.system_cache_uc@chip<>,
939     ereport.cpu.intel.quickpath.bus_opr_poison_err@chip<>,
940     ereport.cpu.intel.quickpath.bus_opr_poison_err_external@chip<>;
942 prop fault.cpu.intel.discard_fatal@motherboard
943     { count(stat.has_poison@motherboard[0]) > count(stat.discard_fatal@motherboard[0]) &&
944       payloadprop_defined("bank_number") && 5 == payloadprop("bank_number") &&
945       payloadprop_defined("processor_context_corrupt") &&
946       1 == payloadprop("processor_context_corrupt") } (0)->
947     ereport.cpu.intel.internal_unclassified@chip<>/core<>/strand<> {within(10s)};
949 prop fault.cpu.intel.internal@chip/core/strand
950     { (count(stat.has_poison@motherboard[0]) <= count(stat.discard_fatal@motherboard[0]) ||
951       !payloadprop_defined("bank_number") || 5 != payloadprop("bank_number") ||
952       !payloadprop_defined("processor_context_corrupt") ||
953       0 == payloadprop("processor_context_corrupt")) &&
954       (payloadprop("error_uncorrected") == 1 ? setserdincrement(4) : 1) } (0)->
955     ereport.cpu.intel.internal_unclassified@chip/core/strand;