?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
drd/tests/swapcontext: Improve the portability of this test further
[valgrind.git] / none / tests / ppc32 / jm-insns.c
blob5316ce318d769cb4f7bc614bfc0071017650f342
1
2 /* HOW TO COMPILE:
3
4 * 32bit build:
5 gcc -Winline -Wall -g -O -mregnames -maltivec
6 * 64bit build:
7 gcc -Winline -Wall -g -O -mregnames -maltivec -m64
8
9 This program is useful, but the register usage conventions in
10 it are a complete dog. In particular, _patch_op_imm has to
11 be inlined, else you wind up with it segfaulting in
12 completely different places due to corruption (of r20 in the
13 case I chased).
14 */
15
16 /*
17 * test-ppc.c:
18 * PPC tests for qemu-PPC CPU emulation checks
19 *
20 * Copyright (c) 2005 Jocelyn Mayer
21 *
22 * This program is free software; you can redistribute it and/or
23 * modify it under the terms of the GNU General Public License V2
24 * as published by the Free Software Foundation
25 *
26 * This program is distributed in the hope that it will be useful,
27 * but WITHOUT ANY WARRANTY; without even the implied warranty of
28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29 * GNU General Public License for more details.
30 *
31 * You should have received a copy of the GNU General Public License
32 * along with this program; if not, see <http://www.gnu.org/licenses/>.
33 */
34
35 /*
36 * Theory of operations:
37 * a few registers are reserved for the test program:
38 * r14 => r18
39 * f14 => f18
40 * I do preload test values in r14 thru r17 (or less, depending on the number
41 * of register operands needed), patch the test opcode if any immediate
42 * operands are required, execute the tested opcode.
43 * XER, CCR and FPSCR are cleared before every test.
44 * I always get the result in r17 and also save XER and CCR for fixed-point
45 * operations. I also check FPSCR for floating points operations.
46 *
47 * Improvements:
48 * a more clever FPSCR management is needed: for now, I always test
49 * the round-to-zero case. Other rounding modes also need to be tested.
50 */
51
52 /*
53 * Operation details
54 * -----------------
55 * The 'test' functions (via all_tests[]) are wrappers of single asm instns
56 *
57 * The 'loops' (e.g. int_loops) do the actual work:
58 * - loops over as many arguments as the instn needs (regs | imms)
59 * - sets up the environment (reset cr,xer, assign src regs...)
60 * - maybe modifies the asm instn to test different imm args
61 * - calls the test function
62 * - retrieves relevant register data (rD,cr,xer,...)
63 * - prints argument and result data.
64 *
65 * More specifically...
66 *
67 * all_tests[i] holds insn tests
68 * - of which each holds: {instn_test_arr[], description, flags}
69 *
70 * flags hold 3 instn classifiers: {family, type, arg_type}
71 *
72 * // The main test loop:
73 * do_tests( user_ctl_flags ) {
74 * foreach(curr_test = all_test[i]) {
75 *
76 * // flags are used to control what tests are run:
77 * if (curr_test->flags && !user_ctl_flags)
78 * continue;
79 *
80 * // a 'loop_family_arr' is chosen based on the 'family' flag...
81 * switch(curr_test->flags->family) {
82 * case x: loop_family_arr = int_loops;
83 * ...
84 * }
85 *
86 * // ...and the actual test_loop to run is found by indexing into
87 * // the loop_family_arr with the 'arg_type' flag:
88 * test_loop = loop_family[curr_test->flags->arg_type]
89 *
90 * // finally, loop over all instn tests for this test:
91 * foreach (instn_test = curr_test->instn_test_arr[i]) {
92 *
93 * // and call the test_loop with the current instn_test function,name
94 * test_loop( instn_test->func, instn_test->name )
95 * }
96 * }
97 * }
98 *
99 *
100 * Details of instruction patching for immediate operands
101 * -----------------------------------------------------
102 * All the immediate insn test functions are of the form {imm_insn, blr}
103 * In order to patch one of these functions, we simply copy both insns
104 * to a stack buffer, and rewrite the immediate part of imm_insn.
105 * We then execute our stack buffer.
106 * All ppc instructions are 32bits wide, which makes this fairly easy.
107 *
108 * Example:
109 * extern void test_addi (void);
110 * asm(".section \".text\"\n"
111 * " .align 2\n"
112 * " .type test_addi,@function\n"
113 * "test_addi:\n"
114 * " addi\n"
115 * " blr\n"
116 * " .previous\n"
117 * );
118 *
119 * We are interested only in:
120 * " addi 17, 14, 0\n"
121 * " blr\n"
122 *
123 * In a loop test, we may see:
124 * uint32_t func_buf[2]; // our new stack based 'function'
125 * for imm... // loop over imm
126 * init_function( &func, func_buf ); // copy insns, set func ptr
127 * patch_op_imm16(&func_buf[0], imm); // patch 'addi' insn
128 * ...
129 * (*func)(); // exec our rewritten code
130 *
131 * patch_op_imm16() itself simply takes the uint32_t insn and overwrites
132 * the immediate field with the new value (which, for 'addi', is the
133 * low 16 bits).
134 *
135 * So in the loop test, if 'imm' is currently 9, and p[0] is:
136 * 0x3A2E0000 => addi 17, 14, 0
137 *
138 * after patch_op_imm16(), func_buf[0] becomes:
139 * 0x3A2E0009 => addi 17, 14, 9
140 *
141 * Note: init_function() needs to be called on every iteration
142 * - don't ask me why!
143 */
144
145
146 /**********************************************************************/
147 /* Uncomment to enable many arguments for altivec insns */
148 #define USAGE_SIMPLE
149
150 /* Uncomment to enable many arguments for altivec insns */
151 //#define ALTIVEC_ARGS_LARGE
152
153 /* Uncomment to enable output of CR flags for float tests */
154 //#define TEST_FLOAT_FLAGS
155
156 /* Uncomment to enable debug output */
157 //#define DEBUG_ARGS_BUILD
158 //#define DEBUG_FILTER
159
160 /* These should be set at build time */
161 //#define NO_FLOAT
162 //#define HAS_ALTIVEC // CFLAGS += -maltivec
163 //#define IS_PPC405
164 /**********************************************************************/
165
166
167 #include <stdint.h>
168 #include "tests/sys_mman.h"
169 #include "tests/malloc.h" // memalign16
170 #include "./opcodes.h"
171
172 #define STATIC_ASSERT(e) sizeof(struct { int:-!(e); })
173
174 /* Something of the same size as void*, so can be safely be coerced
175 * to/from a pointer type. Also same size as the host's gp registers.
176 * According to the AltiVec section of the GCC manual, the syntax does
177 * not allow the use of a typedef name as a type specifier in conjunction
178 * with the vector keyword, so typedefs uint[32|64]_t are #undef'ed here
179 * and redefined using #define.
180 */
181 #undef uint32_t
182 #undef uint64_t
183 #define uint32_t unsigned int
184 #define uint64_t unsigned long long int
185
186 #ifndef __powerpc64__
187 typedef uint32_t HWord_t;
188 #else
189 typedef uint64_t HWord_t;
190 #endif /* __powerpc64__ */
191
192 enum {
193 compile_time_test1 = STATIC_ASSERT(sizeof(uint32_t) == 4),
194 compile_time_test2 = STATIC_ASSERT(sizeof(uint64_t) == 8),
195 };
196
197 #define ALLCR "cr0","cr1","cr2","cr3","cr4","cr5","cr6","cr7"
198
199 #define SET_CR(_arg) \
200 __asm__ __volatile__ ("mtcr %0" : : "b"(_arg) : ALLCR );
201
202 #define SET_XER(_arg) \
203 __asm__ __volatile__ ("mtxer %0" : : "b"(_arg) : "xer" );
204
205 #define GET_CR(_lval) \
206 __asm__ __volatile__ ("mfcr %0" : "=b"(_lval) )
207
208 #define GET_XER(_lval) \
209 __asm__ __volatile__ ("mfxer %0" : "=b"(_lval) )
210
211 #define GET_CR_XER(_lval_cr,_lval_xer) \
212 do { GET_CR(_lval_cr); GET_XER(_lval_xer); } while (0)
213
214 #define SET_CR_ZERO \
215 SET_CR(0)
216
217 #define SET_XER_ZERO \
218 SET_XER(0)
219
220 #define SET_CR_XER_ZERO \
221 do { SET_CR_ZERO; SET_XER_ZERO; } while (0)
222
223 #define SET_FPSCR_ZERO \
224 do { double _d = 0.0; \
225 __asm__ __volatile__ ("mtfsf 0xFF, %0" : : "f"(_d) ); \
226 } while (0)
227
228
229 /* XXXX these must all be callee-save regs! */
230 register double f14 __asm__ ("fr14");
231 register double f15 __asm__ ("fr15");
232 register double f16 __asm__ ("fr16");
233 register double f17 __asm__ ("fr17");
234 register HWord_t r14 __asm__ ("r14");
235 register HWord_t r15 __asm__ ("r15");
236 register HWord_t r16 __asm__ ("r16");
237 register HWord_t r17 __asm__ ("r17");
238
239 #include "config.h" // HAS_ALTIVEC
240 #if defined (HAS_ALTIVEC)
241 # include <altivec.h>
242 #endif
243 #include <assert.h>
244 #include <ctype.h> // isspace
245 #include <stdio.h>
246 #include <stdlib.h>
247 #include <string.h>
248 #include <unistd.h> // getopt
249
250
251 #ifndef __powerpc64__
252 #define ASSEMBLY_FUNC(__fname, __insn) \
253 asm(".section \".text\"\n" \
254 "\t.align 2\n" \
255 "\t.type "__fname",@function\n" \
256 __fname":\n" \
257 "\t"__insn"\n" \
258 "\tblr\n" \
259 "\t.previous\n" \
260 )
261 #else
262 #if defined(VGP_ppc64be_linux)
263 #define ASSEMBLY_FUNC(__fname, __insn) \
264 asm(".section \".text\"\n" \
265 "\t.align 2\n" \
266 "\t.global "__fname"\n" \
267 "\t.section \".opd\",\"aw\"\n" \
268 "\t.align 3\n" \
269 ""__fname":\n" \
270 "\t.quad ."__fname",.TOC.@tocbase,0\n" \
271 "\t.previous\n" \
272 "\t.type ."__fname",@function\n" \
273 "\t.global ."__fname"\n" \
274 "."__fname":\n" \
275 "\t"__insn"\n" \
276 "\tblr\n" \
277 )
278 #elif defined(VGP_ppc64le_linux)
279 #define ASSEMBLY_FUNC(__fname, __insn) \
280 asm(".section \".text\"\n" \
281 "\t.align 2\n" \
282 "\t.global "__fname"\n" \
283 ""__fname":\n" \
284 "\t"__insn"\n" \
285 "\tblr\n" \
286 )
287 #endif // VGP_ppc64 or VGP_ppc64le
288 #endif // #ifndef __powerpc64__
289
290
291 /* Return a pointer to a 1-page area where is is safe to both write
292 and execute instructions. Area is filled with 'trap' insns. */
293 static
294 uint32_t* get_rwx_area ( void )
295 {
296 int i;
297 static uint32_t* p = NULL;
298 if (p == NULL) {
299 p = mmap(NULL, 4096, PROT_READ|PROT_WRITE|PROT_EXEC,
300 MAP_PRIVATE|MAP_ANONYMOUS, -1, 0);
301 assert(p != MAP_FAILED);
302 }
303
304 for (i = 0; i < 4096/sizeof(uint32_t); i++)
305 p[i] = 0x7fe00008; /* trap */
306
307 return p;
308 }
309
310
311 /* -------------- BEGIN #include "test-ppc.h" -------------- */
312 /*
313 * test-ppc.h:
314 * PPC tests for qemu-PPC CPU emulation checks - definitions
315 *
316 * Copyright (c) 2005 Jocelyn Mayer
317 *
318 * This program is free software; you can redistribute it and/or
319 * modify it under the terms of the GNU General Public License V2
320 * as published by the Free Software Foundation
321 *
322 * This program is distributed in the hope that it will be useful,
323 * but WITHOUT ANY WARRANTY; without even the implied warranty of
324 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
325 * GNU General Public License for more details.
326 *
327 * You should have received a copy of the GNU General Public License
328 * along with this program; if not, see <http://www.gnu.org/licenses/>.
329 */
330
331 #if !defined (__TEST_PPC_H__)
332 #define __TEST_PPC_H__
333
334 #include <stdint.h>
335
336 typedef void (*test_func_t) (void);
337 typedef struct test_t test_t;
338 typedef struct test_table_t test_table_t;
339 struct test_t {
340 test_func_t func;
341 const char *name;
342 };
343
344 struct test_table_t {
345 test_t *tests;
346 const char *name;
347 uint32_t flags;
348 };
349
350 typedef void (*test_loop_t) (const char *name, test_func_t func,
351 uint32_t flags);
352
353 enum test_flags {
354 /* Nb arguments */
355 PPC_ONE_ARG = 0x00000001,
356 PPC_TWO_ARGS = 0x00000002,
357 PPC_THREE_ARGS = 0x00000003,
358 PPC_CMP_ARGS = 0x00000004, // family: compare
359 PPC_CMPI_ARGS = 0x00000005, // family: compare
360 PPC_TWO_I16 = 0x00000006, // family: arith/logical
361 PPC_SPECIAL = 0x00000007, // family: logical
362 PPC_LD_ARGS = 0x00000008, // family: ldst
363 PPC_LDX_ARGS = 0x00000009, // family: ldst
364 PPC_ST_ARGS = 0x0000000A, // family: ldst
365 PPC_STX_ARGS = 0x0000000B, // family: ldst
366 PPC_ONE_IMM = 0x0000000C, // PPC_MISC family
367 PPC_NB_ARGS = 0x0000000F,
368 /* Type */
369 PPC_ARITH = 0x00000100,
370 PPC_LOGICAL = 0x00000200,
371 PPC_COMPARE = 0x00000300,
372 PPC_CROP = 0x00000400,
373 PPC_LDST = 0x00000500,
374 PPC_POPCNT = 0x00000600,
375 PPC_ANY = 0x00000700,
376 PPC_TYPE = 0x00000F00,
377 /* Family */
378 PPC_INTEGER = 0x00010000,
379 PPC_FLOAT = 0x00020000,
380 PPC_405 = 0x00030000,
381 PPC_ALTIVEC = 0x00040000,
382 PPC_FALTIVEC = 0x00050000,
383 PPC_MISC = 0x00060000,
384 PPC_FAMILY = 0x000F0000,
385 /* Flags: these may be combined, so use separate bitfields. */
386 PPC_CR = 0x01000000,
387 PPC_XER_CA = 0x02000000,
388 };
389
390 #endif /* !defined (__TEST_PPC_H__) */
391
392 /* -------------- END #include "test-ppc.h" -------------- */
393
394
395
396
397 #if defined (DEBUG_ARGS_BUILD)
398 #define AB_DPRINTF(fmt, args...) do { fprintf(stderr, fmt , ##args); } while (0)
399 #else
400 #define AB_DPRINTF(fmt, args...) do { } while (0)
401 #endif
402
403 #if defined (DEBUG_FILTER)
404 #define FDPRINTF(fmt, args...) do { fprintf(stderr, fmt , ##args); } while (0)
405 #else
406 #define FDPRINTF(fmt, args...) do { } while (0)
407 #endif
408
409
410 /* Produce the 64-bit pattern corresponding to the supplied double. */
411 static uint64_t double_to_bits ( double d )
412 {
413 union { uint64_t i; double d; } u;
414 assert(8 == sizeof(uint64_t));
415 assert(8 == sizeof(double));
416 assert(8 == sizeof(u));
417 u.d = d;
418 return u.i;
419 }
420
421 #if 0
422 static float bits_to_float ( uint32_t i )
423 {
424 union { uint32_t i; float f; } u;
425 assert(4 == sizeof(uint32_t));
426 assert(4 == sizeof(float));
427 assert(4 == sizeof(u));
428 u.i = i;
429 return u.f;
430 }
431 #endif
432
433
434 #if defined (HAS_ALTIVEC)
435 static void AB_DPRINTF_VEC32x4 ( vector unsigned int v )
436 {
437 #if defined (DEBUG_ARGS_BUILD)
438 int i;
439 unsigned int* p_int = (unsigned int*)&v;
440 AB_DPRINTF("val");
441 for (i=0; i<4; i++) {
442 AB_DPRINTF(" %08x", p_int[i]);
443 }
444 AB_DPRINTF("\n");
445 #endif
446 }
447 #endif
448
449
450 #define unused __attribute__ (( unused ))
451
452
453 /* -------------- BEGIN #include "ops-ppc.c" -------------- */
454
455 /* #include "test-ppc.h" */
456
457 static void test_add (void)
458 {
459 __asm__ __volatile__ ("add 17, 14, 15");
460 }
461
462 static void test_addo (void)
463 {
464 __asm__ __volatile__ ("addo 17, 14, 15");
465 }
466
467 static void test_addc (void)
468 {
469 __asm__ __volatile__ ("addc 17, 14, 15");
470 }
471
472 static void test_addco (void)
473 {
474 __asm__ __volatile__ ("addco 17, 14, 15");
475 }
476
477 static void test_divw (void)
478 {
479 __asm__ __volatile__ ("divw 17, 14, 15");
480 }
481
482 static void test_divwo (void)
483 {
484 __asm__ __volatile__ ("divwo 17, 14, 15");
485 }
486
487 static void test_divwu (void)
488 {
489 __asm__ __volatile__ ("divwu 17, 14, 15");
490 }
491
492 static void test_divwuo (void)
493 {
494 __asm__ __volatile__ ("divwuo 17, 14, 15");
495 }
496
497 static void test_mulhw (void)
498 {
499 __asm__ __volatile__ ("mulhw 17, 14, 15");
500 }
501
502 static void test_mulhwu (void)
503 {
504 __asm__ __volatile__ ("mulhwu 17, 14, 15");
505 }
506
507 static void test_mullw (void)
508 {
509 __asm__ __volatile__ ("mullw 17, 14, 15");
510 }
511
512 static void test_mullwo (void)
513 {
514 __asm__ __volatile__ ("mullwo 17, 14, 15");
515 }
516
517 static void test_subf (void)
518 {
519 __asm__ __volatile__ ("subf 17, 14, 15");
520 }
521
522 static void test_subfo (void)
523 {
524 __asm__ __volatile__ ("subfo 17, 14, 15");
525 }
526
527 static void test_subfc (void)
528 {
529 __asm__ __volatile__ ("subfc 17, 14, 15");
530 }
531
532 static void test_subfco (void)
533 {
534 __asm__ __volatile__ ("subfco 17, 14, 15");
535 }
536
537 #ifdef __powerpc64__
538 static void test_mulld (void)
539 {
540 __asm__ __volatile__ ("mulld 17, 14, 15");
541 }
542
543 static void test_mulldo (void)
544 {
545 __asm__ __volatile__ ("mulldo 17, 14, 15");
546 }
547
548 static void test_mulhd (void)
549 {
550 __asm__ __volatile__ ("mulhd 17, 14, 15");
551 }
552
553 static void test_mulhdu (void)
554 {
555 __asm__ __volatile__ ("mulhdu 17, 14, 15");
556 }
557
558 static void test_divd (void)
559 {
560 __asm__ __volatile__ ("divd 17, 14, 15");
561 }
562
563 static void test_divdu (void)
564 {
565 __asm__ __volatile__ ("divdu 17, 14, 15");
566 }
567
568 static void test_divdo (void)
569 {
570 __asm__ __volatile__ ("divdo 17, 14, 15");
571 }
572
573 static void test_divduo (void)
574 {
575 __asm__ __volatile__ ("divduo 17, 14, 15");
576 }
577 #endif // #ifdef __powerpc64__
578
579 static test_t tests_ia_ops_two[] = {
580 { &test_add , " add", },
581 { &test_addo , " addo", },
582 { &test_addc , " addc", },
583 { &test_addco , " addco", },
584 { &test_divw , " divw", },
585 { &test_divwo , " divwo", },
586 { &test_divwu , " divwu", },
587 { &test_divwuo , " divwuo", },
588 { &test_mulhw , " mulhw", },
589 { &test_mulhwu , " mulhwu", },
590 { &test_mullw , " mullw", },
591 { &test_mullwo , " mullwo", },
592 { &test_subf , " subf", },
593 { &test_subfo , " subfo", },
594 { &test_subfc , " subfc", },
595 { &test_subfco , " subfco", },
596 #ifdef __powerpc64__
597 { &test_mulhd , " mulhd", },
598 { &test_mulhdu , " mulhdu", },
599 { &test_mulld , " mulld", },
600 { &test_mulldo , " mulldo", },
601 { &test_divd , " divd", },
602 { &test_divdu , " divdu", },
603 { &test_divdo , " divdo", },
604 { &test_divduo , " divduo", },
605 #endif // #ifdef __powerpc64__
606 { NULL, NULL, },
607 };
608
609 static void test_add_ (void)
610 {
611 __asm__ __volatile__ ("add. 17, 14, 15");
612 }
613
614 static void test_addo_ (void)
615 {
616 __asm__ __volatile__ ("addo. 17, 14, 15");
617 }
618
619 static void test_addc_ (void)
620 {
621 __asm__ __volatile__ ("addc. 17, 14, 15");
622 }
623
624 static void test_addco_ (void)
625 {
626 __asm__ __volatile__ ("addco. 17, 14, 15");
627 }
628
629 static void test_divw_ (void)
630 {
631 __asm__ __volatile__ ("divw. 17, 14, 15");
632 }
633
634 static void test_divwo_ (void)
635 {
636 __asm__ __volatile__ ("divwo. 17, 14, 15");
637 }
638
639 static void test_divwu_ (void)
640 {
641 __asm__ __volatile__ ("divwu. 17, 14, 15");
642 }
643
644 static void test_divwuo_ (void)
645 {
646 __asm__ __volatile__ ("divwuo. 17, 14, 15");
647 }
648
649 static void test_mulhw_ (void)
650 {
651 __asm__ __volatile__ ("mulhw. 17, 14, 15");
652 }
653
654 static void test_mulhwu_ (void)
655 {
656 __asm__ __volatile__ ("mulhwu. 17, 14, 15");
657 }
658
659 static void test_mullw_ (void)
660 {
661 __asm__ __volatile__ ("mullw. 17, 14, 15");
662 }
663
664 static void test_mullwo_ (void)
665 {
666 __asm__ __volatile__ ("mullwo. 17, 14, 15");
667 }
668
669 static void test_subf_ (void)
670 {
671 __asm__ __volatile__ ("subf. 17, 14, 15");
672 }
673
674 static void test_subfo_ (void)
675 {
676 __asm__ __volatile__ ("subfo. 17, 14, 15");
677 }
678
679 static void test_subfc_ (void)
680 {
681 __asm__ __volatile__ ("subfc. 17, 14, 15");
682 }
683
684 static void test_subfco_ (void)
685 {
686 __asm__ __volatile__ ("subfco. 17, 14, 15");
687 }
688
689 #ifdef __powerpc64__
690 static void test_mulhd_ (void)
691 {
692 __asm__ __volatile__ ("mulhd. 17, 14, 15");
693 }
694
695 static void test_mulhdu_ (void)
696 {
697 __asm__ __volatile__ ("mulhdu. 17, 14, 15");
698 }
699
700 static void test_mulld_ (void)
701 {
702 __asm__ __volatile__ ("mulld. 17, 14, 15");
703 }
704
705 static void test_mulldo_ (void)
706 {
707 __asm__ __volatile__ ("mulldo. 17, 14, 15");
708 }
709
710 static void test_divd_ (void)
711 {
712 __asm__ __volatile__ ("divd. 17, 14, 15");
713 }
714
715 static void test_divdu_ (void)
716 {
717 __asm__ __volatile__ ("divdu. 17, 14, 15");
718 }
719
720 static void test_divdo_ (void)
721 {
722 __asm__ __volatile__ ("divdo. 17, 14, 15");
723 }
724
725 static void test_divduo_ (void)
726 {
727 __asm__ __volatile__ ("divduo. 17, 14, 15");
728 }
729 #endif // #ifdef __powerpc64__
730
731 static test_t tests_iar_ops_two[] = {
732 { &test_add_ , " add.", },
733 { &test_addo_ , " addo.", },
734 { &test_addc_ , " addc.", },
735 { &test_addco_ , " addco.", },
736 { &test_divw_ , " divw.", },
737 { &test_divwo_ , " divwo.", },
738 { &test_divwu_ , " divwu.", },
739 { &test_divwuo_ , " divwuo.", },
740 { &test_mulhw_ , " mulhw.", },
741 { &test_mulhwu_ , " mulhwu.", },
742 { &test_mullw_ , " mullw.", },
743 { &test_mullwo_ , " mullwo.", },
744 { &test_subf_ , " subf.", },
745 { &test_subfo_ , " subfo.", },
746 { &test_subfc_ , " subfc.", },
747 { &test_subfco_ , " subfco.", },
748 #ifdef __powerpc64__
749 { &test_mulhd_ , " mulhd.", },
750 { &test_mulhdu_ , " mulhdu.", },
751 { &test_mulld_ , " mulld.", },
752 { &test_mulldo_ , " mulldo.", },
753 { &test_divd_ , " divd.", },
754 { &test_divdu_ , " divdu.", },
755 { &test_divdo_ , " divdo.", },
756 { &test_divduo_ , " divduo.", },
757 #endif // #ifdef __powerpc64__
758 { NULL, NULL, },
759 };
760
761 static void test_adde (void)
762 {
763 __asm__ __volatile__ ("adde 17, 14, 15");
764 }
765
766 static void test_addeo (void)
767 {
768 __asm__ __volatile__ ("addeo 17, 14, 15");
769 }
770
771 static void test_subfe (void)
772 {
773 __asm__ __volatile__ ("subfe 17, 14, 15");
774 }
775
776 static void test_subfeo (void)
777 {
778 __asm__ __volatile__ ("subfeo 17, 14, 15");
779 }
780
781 static test_t tests_iac_ops_two[] = {
782 { &test_adde , " adde", },
783 { &test_addeo , " addeo", },
784 { &test_subfe , " subfe", },
785 { &test_subfeo , " subfeo", },
786 { NULL, NULL, },
787 };
788
789 static void test_adde_ (void)
790 {
791 __asm__ __volatile__ ("adde. 17, 14, 15");
792 }
793
794 static void test_addeo_ (void)
795 {
796 __asm__ __volatile__ ("addeo. 17, 14, 15");
797 }
798
799 static void test_subfe_ (void)
800 {
801 __asm__ __volatile__ ("subfe. 17, 14, 15");
802 }
803
804 static void test_subfeo_ (void)
805 {
806 __asm__ __volatile__ ("subfeo. 17, 14, 15");
807 }
808
809 static test_t tests_iacr_ops_two[] = {
810 { &test_adde_ , " adde.", },
811 { &test_addeo_ , " addeo.", },
812 { &test_subfe_ , " subfe.", },
813 { &test_subfeo_ , " subfeo.", },
814 { NULL, NULL, },
815 };
816
817 static void test_and (void)
818 {
819 __asm__ __volatile__ ("and 17, 14, 15");
820 }
821
822 static void test_andc (void)
823 {
824 __asm__ __volatile__ ("andc 17, 14, 15");
825 }
826
827 static void test_eqv (void)
828 {
829 __asm__ __volatile__ ("eqv 17, 14, 15");
830 }
831
832 static void test_nand (void)
833 {
834 __asm__ __volatile__ ("nand 17, 14, 15");
835 }
836
837 static void test_nor (void)
838 {
839 __asm__ __volatile__ ("nor 17, 14, 15");
840 }
841
842 static void test_or (void)
843 {
844 __asm__ __volatile__ ("or 17, 14, 15");
845 }
846
847 static void test_orc (void)
848 {
849 __asm__ __volatile__ ("orc 17, 14, 15");
850 }
851
852 static void test_xor (void)
853 {
854 __asm__ __volatile__ ("xor 17, 14, 15");
855 }
856
857 static void test_slw (void)
858 {
859 __asm__ __volatile__ ("slw 17, 14, 15");
860 }
861
862 static void test_sraw (void)
863 {
864 __asm__ __volatile__ ("sraw 17, 14, 15");
865 }
866
867 static void test_srw (void)
868 {
869 __asm__ __volatile__ ("srw 17, 14, 15");
870 }
871
872 #ifdef __powerpc64__
873 static void test_sld (void)
874 {
875 __asm__ __volatile__ ("sld 17, 14, 15");
876 }
877
878 static void test_srad (void)
879 {
880 __asm__ __volatile__ ("srad 17, 14, 15");
881 }
882
883 static void test_srd (void)
884 {
885 __asm__ __volatile__ ("srd 17, 14, 15");
886 }
887 #endif // #ifdef __powerpc64__
888
889 static test_t tests_il_ops_two[] = {
890 { &test_and , " and", },
891 { &test_andc , " andc", },
892 { &test_eqv , " eqv", },
893 { &test_nand , " nand", },
894 { &test_nor , " nor", },
895 { &test_or , " or", },
896 { &test_orc , " orc", },
897 { &test_xor , " xor", },
898 { &test_slw , " slw", },
899 { &test_sraw , " sraw", },
900 { &test_srw , " srw", },
901 #ifdef __powerpc64__
902 { &test_sld , " sld", },
903 { &test_srad , " srad", },
904 { &test_srd , " srd", },
905 #endif // #ifdef __powerpc64__
906 { NULL, NULL, },
907 };
908
909 static void test_and_ (void)
910 {
911 __asm__ __volatile__ ("and. 17, 14, 15");
912 }
913
914 static void test_andc_ (void)
915 {
916 __asm__ __volatile__ ("andc. 17, 14, 15");
917 }
918
919 static void test_eqv_ (void)
920 {
921 __asm__ __volatile__ ("eqv. 17, 14, 15");
922 }
923
924 static void test_nand_ (void)
925 {
926 __asm__ __volatile__ ("nand. 17, 14, 15");
927 }
928
929 static void test_nor_ (void)
930 {
931 __asm__ __volatile__ ("nor. 17, 14, 15");
932 }
933
934 static void test_or_ (void)
935 {
936 __asm__ __volatile__ ("or. 17, 14, 15");
937 }
938
939 static void test_orc_ (void)
940 {
941 __asm__ __volatile__ ("orc. 17, 14, 15");
942 }
943
944 static void test_xor_ (void)
945 {
946 __asm__ __volatile__ ("xor. 17, 14, 15");
947 }
948
949 static void test_slw_ (void)
950 {
951 __asm__ __volatile__ ("slw. 17, 14, 15");
952 }
953
954 static void test_sraw_ (void)
955 {
956 __asm__ __volatile__ ("sraw. 17, 14, 15");
957 }
958
959 static void test_srw_ (void)
960 {
961 __asm__ __volatile__ ("srw. 17, 14, 15");
962 }
963
964 #ifdef __powerpc64__
965 static void test_sld_ (void)
966 {
967 __asm__ __volatile__ ("sld. 17, 14, 15");
968 }
969
970 static void test_srad_ (void)
971 {
972 __asm__ __volatile__ ("srad. 17, 14, 15");
973 }
974
975 static void test_srd_ (void)
976 {
977 __asm__ __volatile__ ("srd. 17, 14, 15");
978 }
979 #endif // #ifdef __powerpc64__
980
981 static test_t tests_ilr_ops_two[] = {
982 { &test_and_ , " and.", },
983 { &test_andc_ , " andc.", },
984 { &test_eqv_ , " eqv.", },
985 { &test_nand_ , " nand.", },
986 { &test_nor_ , " nor.", },
987 { &test_or_ , " or.", },
988 { &test_orc_ , " orc.", },
989 { &test_xor_ , " xor.", },
990 { &test_slw_ , " slw.", },
991 { &test_sraw_ , " sraw.", },
992 { &test_srw_ , " srw.", },
993 #ifdef __powerpc64__
994 { &test_sld_ , " sld.", },
995 { &test_srad_ , " srad.", },
996 { &test_srd_ , " srd.", },
997 #endif // #ifdef __powerpc64__
998 { NULL, NULL, },
999 };
1000
1001 static void test_cmpw (void)
1002 {
1003 __asm__ __volatile__ ("cmpw 2, 14, 15");
1004 }
1005
1006 static void test_cmplw (void)
1007 {
1008 __asm__ __volatile__ ("cmplw 2, 14, 15");
1009 }
1010
1011 #ifdef __powerpc64__
1012 static void test_cmpd (void)
1013 {
1014 __asm__ __volatile__ ("cmpd 2, 14, 15");
1015 }
1016
1017 static void test_cmpld (void)
1018 {
1019 __asm__ __volatile__ ("cmpld 2, 14, 15");
1020 }
1021 #endif // #ifdef __powerpc64__
1022
1023 static test_t tests_icr_ops_two[] = {
1024 { &test_cmpw , " cmpw", },
1025 { &test_cmplw , " cmplw", },
1026 #ifdef __powerpc64__
1027 { &test_cmpd , " cmpd", },
1028 { &test_cmpld , " cmpld", },
1029 #endif // #ifdef __powerpc64__
1030 { NULL, NULL, },
1031 };
1032
1033 extern void test_cmpwi (void);
1034 ASSEMBLY_FUNC("test_cmpwi", "cmpwi 2, 14, 0");
1035
1036 extern void test_cmplwi (void);
1037 ASSEMBLY_FUNC("test_cmplwi", "cmplwi 2, 14, 0");
1038
1039 #ifdef __powerpc64__
1040 extern void test_cmpdi (void);
1041 ASSEMBLY_FUNC("test_cmpdi", "cmpdi 2, 14, 0");
1042
1043 extern void test_cmpldi (void);
1044 ASSEMBLY_FUNC("test_cmpldi", "cmpldi 2, 14, 0");
1045 #endif // #ifdef __powerpc64__
1046
1047 static test_t tests_icr_ops_two_i16[] = {
1048 { &test_cmpwi , " cmpwi", },
1049 { &test_cmplwi , " cmplwi", },
1050 #ifdef __powerpc64__
1051 { &test_cmpdi , " cmpdi", },
1052 { &test_cmpldi , " cmpldi", },
1053 #endif // #ifdef __powerpc64__
1054 { NULL, NULL, },
1055 };
1056
1057 extern void test_addi (void);
1058 ASSEMBLY_FUNC("test_addi", "addi 17, 14, 0");
1059
1060 extern void test_addic (void);
1061 ASSEMBLY_FUNC("test_addic", "addic 17, 14, 0");
1062
1063 extern void test_addis (void);
1064 ASSEMBLY_FUNC("test_addis", "addis 17, 14, 0");
1065
1066 extern void test_mulli (void);
1067 ASSEMBLY_FUNC("test_mulli", "mulli 17, 14, 0");
1068
1069 extern void test_subfic (void);
1070 ASSEMBLY_FUNC("test_subfic", "subfic 17, 14, 0");
1071
1072 static test_t tests_ia_ops_two_i16[] = {
1073 { &test_addi , " addi", },
1074 { &test_addic , " addic", },
1075 { &test_addis , " addis", },
1076 { &test_mulli , " mulli", },
1077 { &test_subfic , " subfic", },
1078 { NULL, NULL, },
1079 };
1080
1081 extern void test_addic_ (void);
1082 ASSEMBLY_FUNC("test_addic_", "addic. 17, 14, 0");
1083
1084 static test_t tests_iar_ops_two_i16[] = {
1085 { &test_addic_ , " addic.", },
1086 { NULL, NULL, },
1087 };
1088
1089 extern void test_ori (void);
1090 ASSEMBLY_FUNC("test_ori", "ori 17, 14, 0");
1091
1092 extern void test_oris (void);
1093 ASSEMBLY_FUNC("test_oris", "oris 17, 14, 0");
1094
1095 extern void test_xori (void);
1096 ASSEMBLY_FUNC("test_xori", "xori 17, 14, 0");
1097
1098 extern void test_xoris (void);
1099 ASSEMBLY_FUNC("test_xoris", "xoris 17, 14, 0");
1100
1101 static test_t tests_il_ops_two_i16[] = {
1102 { &test_ori , " ori", },
1103 { &test_oris , " oris", },
1104 { &test_xori , " xori", },
1105 { &test_xoris , " xoris", },
1106 { NULL, NULL, },
1107 };
1108
1109 extern void test_andi_ (void);
1110 ASSEMBLY_FUNC("test_andi_", "andi. 17, 14, 0");
1111
1112 extern void test_andis_ (void);
1113 ASSEMBLY_FUNC("test_andis_", "andis. 17, 14, 0");
1114
1115 static test_t tests_ilr_ops_two_i16[] = {
1116 { &test_andi_ , " andi.", },
1117 { &test_andis_ , " andis.", },
1118 { NULL, NULL, },
1119 };
1120
1121 static void test_crand (void)
1122 {
1123 __asm__ __volatile__ ("crand 17, 14, 15");
1124 }
1125
1126 static void test_crandc (void)
1127 {
1128 __asm__ __volatile__ ("crandc 17, 14, 15");
1129 }
1130
1131 static void test_creqv (void)
1132 {
1133 __asm__ __volatile__ ("creqv 17, 14, 15");
1134 }
1135
1136 static void test_crnand (void)
1137 {
1138 __asm__ __volatile__ ("crnand 17, 14, 15");
1139 }
1140
1141 static void test_crnor (void)
1142 {
1143 __asm__ __volatile__ ("crnor 17, 14, 15");
1144 }
1145
1146 static void test_cror (void)
1147 {
1148 __asm__ __volatile__ ("cror 17, 14, 15");
1149 }
1150
1151 static void test_crorc (void)
1152 {
1153 __asm__ __volatile__ ("crorc 17, 14, 15");
1154 }
1155
1156 static void test_crxor (void)
1157 {
1158 __asm__ __volatile__ ("crxor 17, 14, 15");
1159 }
1160
1161 static test_t tests_crl_ops_two[] = {
1162 { &test_crand , " crand", },
1163 { &test_crandc , " crandc", },
1164 { &test_creqv , " creqv", },
1165 { &test_crnand , " crnand", },
1166 { &test_crnor , " crnor", },
1167 { &test_cror , " cror", },
1168 { &test_crorc , " crorc", },
1169 { &test_crxor , " crxor", },
1170 { NULL, NULL, },
1171 };
1172
1173 static void test_addme (void)
1174 {
1175 __asm__ __volatile__ ("addme 17, 14");
1176 }
1177
1178 static void test_addmeo (void)
1179 {
1180 __asm__ __volatile__ ("addmeo 17, 14");
1181 }
1182
1183 static void test_addze (void)
1184 {
1185 __asm__ __volatile__ ("addze 17, 14");
1186 }
1187
1188 static void test_addzeo (void)
1189 {
1190 __asm__ __volatile__ ("addzeo 17, 14");
1191 }
1192
1193 static void test_subfme (void)
1194 {
1195 __asm__ __volatile__ ("subfme 17, 14");
1196 }
1197
1198 static void test_subfmeo (void)
1199 {
1200 __asm__ __volatile__ ("subfmeo 17, 14");
1201 }
1202
1203 static void test_subfze (void)
1204 {
1205 __asm__ __volatile__ ("subfze 17, 14");
1206 }
1207
1208 static void test_subfzeo (void)
1209 {
1210 __asm__ __volatile__ ("subfzeo 17, 14");
1211 }
1212
1213 static test_t tests_iac_ops_one[] = {
1214 { &test_addme , " addme", },
1215 { &test_addmeo , " addmeo", },
1216 { &test_addze , " addze", },
1217 { &test_addzeo , " addzeo", },
1218 { &test_subfme , " subfme", },
1219 { &test_subfmeo , " subfmeo", },
1220 { &test_subfze , " subfze", },
1221 { &test_subfzeo , " subfzeo", },
1222 { NULL, NULL, },
1223 };
1224
1225 static void test_addme_ (void)
1226 {
1227 __asm__ __volatile__ ("addme. 17, 14");
1228 }
1229
1230 static void test_addmeo_ (void)
1231 {
1232 __asm__ __volatile__ ("addmeo. 17, 14");
1233 }
1234
1235 static void test_addze_ (void)
1236 {
1237 __asm__ __volatile__ ("addze. 17, 14");
1238 }
1239
1240 static void test_addzeo_ (void)
1241 {
1242 __asm__ __volatile__ ("addzeo. 17, 14");
1243 }
1244
1245 static void test_subfme_ (void)
1246 {
1247 __asm__ __volatile__ ("subfme. 17, 14");
1248 }
1249
1250 static void test_subfmeo_ (void)
1251 {
1252 __asm__ __volatile__ ("subfmeo. 17, 14");
1253 }
1254
1255 static void test_subfze_ (void)
1256 {
1257 __asm__ __volatile__ ("subfze. 17, 14");
1258 }
1259
1260 static void test_subfzeo_ (void)
1261 {
1262 __asm__ __volatile__ ("subfzeo. 17, 14");
1263 }
1264
1265 static test_t tests_iacr_ops_one[] = {
1266 { &test_addme_ , " addme.", },
1267 { &test_addmeo_ , " addmeo.", },
1268 { &test_addze_ , " addze.", },
1269 { &test_addzeo_ , " addzeo.", },
1270 { &test_subfme_ , " subfme.", },
1271 { &test_subfmeo_ , " subfmeo.", },
1272 { &test_subfze_ , " subfze.", },
1273 { &test_subfzeo_ , " subfzeo.", },
1274 { NULL, NULL, },
1275 };
1276
1277 static void test_cntlzw (void)
1278 {
1279 __asm__ __volatile__ ("cntlzw 17, 14");
1280 }
1281
1282 static void test_extsb (void)
1283 {
1284 __asm__ __volatile__ ("extsb 17, 14");
1285 }
1286
1287 static void test_extsh (void)
1288 {
1289 __asm__ __volatile__ ("extsh 17, 14");
1290 }
1291
1292 static void test_neg (void)
1293 {
1294 __asm__ __volatile__ ("neg 17, 14");
1295 }
1296
1297 static void test_nego (void)
1298 {
1299 __asm__ __volatile__ ("nego 17, 14");
1300 }
1301
1302 #ifdef __powerpc64__
1303 static void test_cntlzd (void)
1304 {
1305 __asm__ __volatile__ ("cntlzd 17, 14");
1306 }
1307
1308 static void test_extsw (void)
1309 {
1310 __asm__ __volatile__ ("extsw 17, 14");
1311 }
1312 #endif // #ifdef __powerpc64__
1313
1314 static test_t tests_il_ops_one[] = {
1315 { &test_cntlzw , " cntlzw", },
1316 { &test_extsb , " extsb", },
1317 { &test_extsh , " extsh", },
1318 { &test_neg , " neg", },
1319 { &test_nego , " nego", },
1320 #ifdef __powerpc64__
1321 { &test_cntlzd , " cntlzd", },
1322 { &test_extsw , " extsw", },
1323 #endif // #ifdef __powerpc64__
1324 { NULL, NULL, },
1325 };
1326
1327 static void test_cntlzw_ (void)
1328 {
1329 __asm__ __volatile__ ("cntlzw. 17, 14");
1330 }
1331
1332 static void test_extsb_ (void)
1333 {
1334 __asm__ __volatile__ ("extsb. 17, 14");
1335 }
1336
1337 static void test_extsh_ (void)
1338 {
1339 __asm__ __volatile__ ("extsh. 17, 14");
1340 }
1341
1342 static void test_neg_ (void)
1343 {
1344 __asm__ __volatile__ ("neg. 17, 14");
1345 }
1346
1347 static void test_nego_ (void)
1348 {
1349 __asm__ __volatile__ ("nego. 17, 14");
1350 }
1351
1352 #ifdef __powerpc64__
1353 static void test_cntlzd_ (void)
1354 {
1355 __asm__ __volatile__ ("cntlzd. 17, 14");
1356 }
1357
1358 static void test_extsw_ (void)
1359 {
1360 __asm__ __volatile__ ("extsw. 17, 14");
1361 }
1362 #endif // #ifdef __powerpc64__
1363
1364 static test_t tests_ilr_ops_one[] = {
1365 { &test_cntlzw_ , " cntlzw.", },
1366 { &test_extsb_ , " extsb.", },
1367 { &test_extsh_ , " extsh.", },
1368 { &test_neg_ , " neg.", },
1369 { &test_nego_ , " nego.", },
1370 #ifdef __powerpc64__
1371 { &test_cntlzd_ , " cntlzd.", },
1372 { &test_extsw_ , " extsw.", },
1373 #endif // #ifdef __powerpc64__
1374 { NULL, NULL, },
1375 };
1376
1377 extern void test_rlwimi (void);
1378 ASSEMBLY_FUNC("test_rlwimi", "rlwimi 17, 14, 0, 0, 0");
1379
1380 extern void test_rlwinm (void);
1381 ASSEMBLY_FUNC("test_rlwinm", "rlwinm 17, 14, 0, 0, 0");
1382
1383 extern void test_rlwnm (void);
1384 ASSEMBLY_FUNC("test_rlwnm", "rlwnm 17, 14, 15, 0, 0");
1385
1386 extern void test_srawi (void);
1387 ASSEMBLY_FUNC("test_srawi", "srawi 17, 14, 0");
1388
1389 static void test_mfcr (void)
1390 {
1391 __asm__ __volatile__ ("mfcr 17");
1392 }
1393
1394 static void test_mfspr (void)
1395 {
1396 __asm__ __volatile__ ("mfspr 17, 1");
1397 }
1398
1399 static void test_mtspr (void)
1400 {
1401 __asm__ __volatile__ ("mtspr 1, 14");
1402 }
1403
1404 #ifdef __powerpc64__
1405 extern void test_rldcl (void);
1406 ASSEMBLY_FUNC("test_rldcl", "rldcl 17, 14, 15, 0");
1407
1408 extern void test_rldcr (void);
1409 ASSEMBLY_FUNC("test_rldcr", "rldcr 17, 14, 15, 0");
1410
1411 extern void test_rldic (void);
1412 ASSEMBLY_FUNC("test_rldic", "rldic 17, 14, 0, 0");
1413
1414 extern void test_rldicl (void);
1415 ASSEMBLY_FUNC("test_rldicl", "rldicl 17, 14, 0, 0");
1416
1417 extern void test_rldicr (void);
1418 ASSEMBLY_FUNC("test_rldicr", "rldicr 17, 14, 0, 0");
1419
1420 extern void test_rldimi (void);
1421 ASSEMBLY_FUNC("test_rldimi", "rldimi 17, 14, 0, 0");
1422
1423 extern void test_sradi (void);
1424 ASSEMBLY_FUNC("test_sradi", "sradi 17, 14, 0");
1425 #endif // #ifdef __powerpc64__
1426
1427 static test_t tests_il_ops_spe[] = {
1428 { &test_rlwimi , " rlwimi", },
1429 { &test_rlwinm , " rlwinm", },
1430 { &test_rlwnm , " rlwnm", },
1431 { &test_srawi , " srawi", },
1432 { &test_mfcr , " mfcr", },
1433 { &test_mfspr , " mfspr", },
1434 { &test_mtspr , " mtspr", },
1435 #ifdef __powerpc64__
1436 { &test_rldcl , " rldcl", },
1437 { &test_rldcr , " rldcr", },
1438 { &test_rldic , " rldic", },
1439 { &test_rldicl , " rldicl", },
1440 { &test_rldicr , " rldicr", },
1441 { &test_rldimi , " rldimi", },
1442 { &test_sradi , " sradi", },
1443 #endif // #ifdef __powerpc64__
1444 { NULL, NULL, },
1445 };
1446
1447 extern void test_rlwimi_ (void);
1448 ASSEMBLY_FUNC("test_rlwimi_", "rlwimi. 17, 14, 0, 0, 0");
1449
1450 extern void test_rlwinm_ (void);
1451 ASSEMBLY_FUNC("test_rlwinm_", "rlwinm. 17, 14, 0, 0, 0");
1452
1453 extern void test_rlwnm_ (void);
1454 ASSEMBLY_FUNC("test_rlwnm_", "rlwnm. 17, 14, 15, 0, 0");
1455
1456 extern void test_srawi_ (void);
1457 ASSEMBLY_FUNC("test_srawi_", "srawi. 17, 14, 0");
1458
1459 extern void test_mcrf (void);
1460 ASSEMBLY_FUNC("test_mcrf", "mcrf 0, 0");
1461
1462 extern void test_mcrxr (void);
1463 ASSEMBLY_FUNC("test_mcrxr", "mcrxr 0");
1464
1465 extern void test_mtcrf (void);
1466 ASSEMBLY_FUNC("test_mtcrf", "mtcrf 0, 14");
1467
1468 #ifdef __powerpc64__
1469 extern void test_rldcl_ (void);
1470 ASSEMBLY_FUNC("test_rldcl_", "rldcl. 17, 14, 15, 0");
1471
1472 extern void test_rldcr_ (void);
1473 ASSEMBLY_FUNC("test_rldcr_", "rldcr. 17, 14, 15, 0");
1474
1475 extern void test_rldic_ (void);
1476 ASSEMBLY_FUNC("test_rldic_", "rldic. 17, 14, 0, 0");
1477
1478 extern void test_rldicl_ (void);
1479 ASSEMBLY_FUNC("test_rldicl_", "rldicl. 17, 14, 0, 0");
1480
1481 extern void test_rldicr_ (void);
1482 ASSEMBLY_FUNC("test_rldicr_", "rldicr. 17, 14, 0, 0");
1483
1484 extern void test_rldimi_ (void);
1485 ASSEMBLY_FUNC("test_rldimi_", "rldimi. 17, 14, 0, 0");
1486
1487 extern void test_sradi_ (void);
1488 ASSEMBLY_FUNC("test_sradi_", "sradi. 17, 14, 0");
1489 #endif // #ifdef __powerpc64__
1490
1491 static test_t tests_ilr_ops_spe[] = {
1492 { &test_rlwimi_ , " rlwimi.", },
1493 { &test_rlwinm_ , " rlwinm.", },
1494 { &test_rlwnm_ , " rlwnm.", },
1495 { &test_srawi_ , " srawi.", },
1496 { &test_mcrf , " mcrf", },
1497 { &test_mcrxr , " mcrxr", },
1498 { &test_mtcrf , " mtcrf", },
1499 #ifdef __powerpc64__
1500 { &test_rldcl_ , " rldcl.", },
1501 { &test_rldcr_ , " rldcr.", },
1502 { &test_rldic_ , " rldic.", },
1503 { &test_rldicl_ , " rldicl.", },
1504 { &test_rldicr_ , " rldicr.", },
1505 { &test_rldimi_ , " rldimi.", },
1506 { &test_sradi_ , " sradi.", },
1507 #endif // #ifdef __powerpc64__
1508 { NULL, NULL, },
1509 };
1510
1511 extern void test_lbz (void);
1512 ASSEMBLY_FUNC("test_lbz", "lbz 17,0(14)");
1513
1514 extern void test_lbzu (void);
1515 ASSEMBLY_FUNC("test_lbzu", "lbzu 17,0(14)");
1516
1517 extern void test_lha (void);
1518 ASSEMBLY_FUNC("test_lha", "lha 17,0(14)");
1519
1520 extern void test_lhau (void);
1521 ASSEMBLY_FUNC("test_lhau", "lhau 17,0(14)");
1522
1523 extern void test_lhz (void);
1524 ASSEMBLY_FUNC("test_lhz", "lhz 17,0(14)");
1525
1526 extern void test_lhzu (void);
1527 ASSEMBLY_FUNC("test_lhzu", "lhzu 17,0(14)");
1528
1529 extern void test_lwz (void);
1530 ASSEMBLY_FUNC("test_lwz", "lwz 17,0(14)");
1531
1532 extern void test_lwzu (void);
1533 ASSEMBLY_FUNC("test_lwzu", "lwzu 17,0(14)");
1534
1535 #ifdef __powerpc64__
1536 extern void test_ld (void);
1537 ASSEMBLY_FUNC("test_ld", "ld 17,0(14)");
1538
1539 extern void test_ldu (void);
1540 ASSEMBLY_FUNC("test_ldu", "ldu 17,0(14)");
1541
1542 extern void test_lwa (void);
1543 ASSEMBLY_FUNC("test_lwa", "lwa 17,0(14)");
1544 #endif // #ifdef __powerpc64__
1545
1546 static test_t tests_ild_ops_two_i16[] = {
1547 { &test_lbz , " lbz", },
1548 { &test_lbzu , " lbzu", },
1549 { &test_lha , " lha", },
1550 { &test_lhau , " lhau", },
1551 { &test_lhz , " lhz", },
1552 { &test_lhzu , " lhzu", },
1553 { &test_lwz , " lwz", },
1554 { &test_lwzu , " lwzu", },
1555 #ifdef __powerpc64__
1556 { &test_ld , " ld", },
1557 { &test_ldu , " ldu", },
1558 { &test_lwa , " lwa", },
1559 #endif // #ifdef __powerpc64__
1560 { NULL, NULL, },
1561 };
1562
1563 static void test_lbzx (void)
1564 {
1565 __asm__ __volatile__ ("lbzx 17,14,15");
1566 }
1567
1568 static void test_lbzux (void)
1569 {
1570 __asm__ __volatile__ ("lbzux 17,14,15");
1571 }
1572
1573 static void test_lhax (void)
1574 {
1575 __asm__ __volatile__ ("lhax 17,14,15");
1576 }
1577
1578 static void test_lhaux (void)
1579 {
1580 __asm__ __volatile__ ("lhaux 17,14,15");
1581 }
1582
1583 static void test_lhzx (void)
1584 {
1585 __asm__ __volatile__ ("lhzx 17,14,15");
1586 }
1587
1588 static void test_lhzux (void)
1589 {
1590 __asm__ __volatile__ ("lhzux 17,14,15");
1591 }
1592
1593 static void test_lwzx (void)
1594 {
1595 __asm__ __volatile__ ("lwzx 17,14,15");
1596 }
1597
1598 static void test_lwzux (void)
1599 {
1600 __asm__ __volatile__ ("lwzux 17,14,15");
1601 }
1602
1603 #ifdef __powerpc64__
1604 static void test_ldx (void)
1605 {
1606 __asm__ __volatile__ ("ldx 17,14,15");
1607 }
1608
1609 static void test_ldux (void)
1610 {
1611 __asm__ __volatile__ ("ldux 17,14,15");
1612 }
1613
1614 static void test_lwax (void)
1615 {
1616 __asm__ __volatile__ ("lwax 17,14,15");
1617 }
1618
1619 static void test_lwaux (void)
1620 {
1621 __asm__ __volatile__ ("lwaux 17,14,15");
1622 }
1623 #endif // #ifdef __powerpc64__
1624
1625 static test_t tests_ild_ops_two[] = {
1626 { &test_lbzx , " lbzx", },
1627 { &test_lbzux , " lbzux", },
1628 { &test_lhax , " lhax", },
1629 { &test_lhaux , " lhaux", },
1630 { &test_lhzx , " lhzx", },
1631 { &test_lhzux , " lhzux", },
1632 { &test_lwzx , " lwzx", },
1633 { &test_lwzux , " lwzux", },
1634 #ifdef __powerpc64__
1635 { &test_ldx , " ldx", },
1636 { &test_ldux , " ldux", },
1637 { &test_lwax , " lwax", },
1638 { &test_lwaux , " lwaux", },
1639 #endif // #ifdef __powerpc64__
1640 { NULL, NULL, },
1641 };
1642
1643 extern void test_stb (void);
1644 ASSEMBLY_FUNC("test_stb", "stb 14,0(15)");
1645
1646 extern void test_stbu (void);
1647 ASSEMBLY_FUNC("test_stbu", "stbu 14,0(15)");
1648
1649 extern void test_sth (void);
1650 ASSEMBLY_FUNC("test_sth", "sth 14,0(15)");
1651
1652 extern void test_sthu (void);
1653 ASSEMBLY_FUNC("test_sthu", "sthu 14,0(15)");
1654
1655 extern void test_stw (void);
1656 ASSEMBLY_FUNC("test_stw", "stw 14,0(15)");
1657
1658 extern void test_stwu (void);
1659 ASSEMBLY_FUNC("test_stwu", "stwu 14,0(15)");
1660
1661 #ifdef __powerpc64__
1662 extern void test_std (void);
1663 ASSEMBLY_FUNC("test_std", "std 14,0(15)");
1664
1665 extern void test_stdu (void);
1666 ASSEMBLY_FUNC("test_stdu", "stdu 14,0(15)");
1667 #endif // #ifdef __powerpc64__
1668
1669 static test_t tests_ist_ops_three_i16[] = {
1670 { &test_stb , " stb", },
1671 { &test_stbu , " stbu", },
1672 { &test_sth , " sth", },
1673 { &test_sthu , " sthu", },
1674 { &test_stw , " stw", },
1675 { &test_stwu , " stwu", },
1676 #ifdef __powerpc64__
1677 { &test_std , " std", },
1678 { &test_stdu , " stdu", },
1679 #endif // #ifdef __powerpc64__
1680 { NULL, NULL, },
1681 };
1682
1683 static void test_stbx (void)
1684 {
1685 __asm__ __volatile__ ("stbx 14,15,16");
1686 }
1687
1688 static void test_stbux (void)
1689 {
1690 __asm__ __volatile__ ("stbux 14,15,16");
1691 }
1692
1693 static void test_sthx (void)
1694 {
1695 __asm__ __volatile__ ("sthx 14,15,16");
1696 }
1697
1698 static void test_sthux (void)
1699 {
1700 __asm__ __volatile__ ("sthux 14,15,16");
1701 }
1702
1703 static void test_stwx (void)
1704 {
1705 __asm__ __volatile__ ("stwx 14,15,16");
1706 }
1707
1708 static void test_stwux (void)
1709 {
1710 __asm__ __volatile__ ("stwux 14,15,16");
1711 }
1712
1713 #ifdef __powerpc64__
1714 static void test_stdx (void)
1715 {
1716 __asm__ __volatile__ ("stdx 14,15,16");
1717 }
1718
1719 static void test_stdux (void)
1720 {
1721 __asm__ __volatile__ ("stdux 14,15,16");
1722 }
1723 #endif // #ifdef __powerpc64__
1724
1725 static test_t tests_ist_ops_three[] = {
1726 { &test_stbx , " stbx", },
1727 { &test_stbux , " stbux", },
1728 { &test_sthx , " sthx", },
1729 { &test_sthux , " sthux", },
1730 { &test_stwx , " stwx", },
1731 { &test_stwux , " stwux", },
1732 #ifdef __powerpc64__
1733 { &test_stdx , " stdx", },
1734 { &test_stdux , " stdux", },
1735 #endif // #ifdef __powerpc64__
1736 { NULL, NULL, },
1737 };
1738
1739 static void
1740 tests_popcnt_one(void)
1741 {
1742 __asm__ __volatile__ ("popcntb 17, 14");
1743 }
1744
1745 static test_t tests_popcnt_ops_one[] = {
1746 { &tests_popcnt_one , " popcntb", },
1747 { NULL, NULL, },
1748 };
1749
1750 #if !defined (NO_FLOAT)
1751 static void test_fsel (void)
1752 {
1753 __asm__ __volatile__ ("fsel 17, 14, 15, 16");
1754 }
1755
1756 static void test_fmadd (void)
1757 {
1758 __asm__ __volatile__ ("fmadd 17, 14, 15, 16");
1759 }
1760
1761 static void test_fmadds (void)
1762 {
1763 __asm__ __volatile__ ("fmadds 17, 14, 15, 16");
1764 }
1765
1766 static void test_fmsub (void)
1767 {
1768 __asm__ __volatile__ ("fmsub 17, 14, 15, 16");
1769 }
1770
1771 static void test_fmsubs (void)
1772 {
1773 __asm__ __volatile__ ("fmsubs 17, 14, 15, 16");
1774 }
1775
1776 static void test_fnmadd (void)
1777 {
1778 __asm__ __volatile__ ("fnmadd 17, 14, 15, 16");
1779 }
1780
1781 static void test_fnmadds (void)
1782 {
1783 __asm__ __volatile__ ("fnmadds 17, 14, 15, 16");
1784 }
1785
1786 static void test_fnmsub (void)
1787 {
1788 __asm__ __volatile__ ("fnmsub 17, 14, 15, 16");
1789 }
1790
1791 static void test_fnmsubs (void)
1792 {
1793 __asm__ __volatile__ ("fnmsubs 17, 14, 15, 16");
1794 }
1795
1796 static test_t tests_fa_ops_three[] = {
1797 { &test_fsel , " fsel", },
1798 { &test_fmadd , " fmadd", },
1799 { &test_fmadds , " fmadds", },
1800 { &test_fmsub , " fmsub", },
1801 { &test_fmsubs , " fmsubs", },
1802 { &test_fnmadd , " fnmadd", },
1803 { &test_fnmadds , " fnmadds", },
1804 { &test_fnmsub , " fnmsub", },
1805 { &test_fnmsubs , " fnmsubs", },
1806 { NULL, NULL, },
1807 };
1808 #endif /* !defined (NO_FLOAT) */
1809
1810 #if !defined (NO_FLOAT)
1811 static void test_fsel_ (void)
1812 {
1813 __asm__ __volatile__ ("fsel. 17, 14, 15, 16");
1814 }
1815
1816 static void test_fmadd_ (void)
1817 {
1818 __asm__ __volatile__ ("fmadd. 17, 14, 15, 16");
1819 }
1820
1821 static void test_fmadds_ (void)
1822 {
1823 __asm__ __volatile__ ("fmadds. 17, 14, 15, 16");
1824 }
1825
1826 static void test_fmsub_ (void)
1827 {
1828 __asm__ __volatile__ ("fmsub. 17, 14, 15, 16");
1829 }
1830
1831 static void test_fmsubs_ (void)
1832 {
1833 __asm__ __volatile__ ("fmsubs. 17, 14, 15, 16");
1834 }
1835
1836 static void test_fnmadd_ (void)
1837 {
1838 __asm__ __volatile__ ("fnmadd. 17, 14, 15, 16");
1839 }
1840
1841 static void test_fnmadds_ (void)
1842 {
1843 __asm__ __volatile__ ("fnmadds. 17, 14, 15, 16");
1844 }
1845
1846 static void test_fnmsub_ (void)
1847 {
1848 __asm__ __volatile__ ("fnmsub. 17, 14, 15, 16");
1849 }
1850
1851 static void test_fnmsubs_ (void)
1852 {
1853 __asm__ __volatile__ ("fnmsubs. 17, 14, 15, 16");
1854 }
1855
1856 static test_t tests_far_ops_three[] = {
1857 { &test_fsel_ , " fsel.", },
1858 { &test_fmadd_ , " fmadd.", },
1859 { &test_fmadds_ , " fmadds.", },
1860 { &test_fmsub_ , " fmsub.", },
1861 { &test_fmsubs_ , " fmsubs.", },
1862 { &test_fnmadd_ , " fnmadd.", },
1863 { &test_fnmadds_ , " fnmadds.", },
1864 { &test_fnmsub_ , " fnmsub.", },
1865 { &test_fnmsubs_ , " fnmsubs.", },
1866 { NULL, NULL, },
1867 };
1868 #endif /* !defined (NO_FLOAT) */
1869
1870 #if !defined (NO_FLOAT)
1871 static void test_fadd (void)
1872 {
1873 __asm__ __volatile__ ("fadd 17, 14, 15");
1874 }
1875
1876 static void test_fadds (void)
1877 {
1878 __asm__ __volatile__ ("fadds 17, 14, 15");
1879 }
1880
1881 static void test_fsub (void)
1882 {
1883 __asm__ __volatile__ ("fsub 17, 14, 15");
1884 }
1885
1886 static void test_fsubs (void)
1887 {
1888 __asm__ __volatile__ ("fsubs 17, 14, 15");
1889 }
1890
1891 static void test_fmul (void)
1892 {
1893 __asm__ __volatile__ ("fmul 17, 14, 15");
1894 }
1895
1896 static void test_fmuls (void)
1897 {
1898 __asm__ __volatile__ ("fmuls 17, 14, 15");
1899 }
1900
1901 static void test_fdiv (void)
1902 {
1903 __asm__ __volatile__ ("fdiv 17, 14, 15");
1904 }
1905
1906 static void test_fdivs (void)
1907 {
1908 __asm__ __volatile__ ("fdivs 17, 14, 15");
1909 }
1910
1911 static test_t tests_fa_ops_two[] = {
1912 { &test_fadd , " fadd", },
1913 { &test_fadds , " fadds", },
1914 { &test_fsub , " fsub", },
1915 { &test_fsubs , " fsubs", },
1916 { &test_fmul , " fmul", },
1917 { &test_fmuls , " fmuls", },
1918 { &test_fdiv , " fdiv", },
1919 { &test_fdivs , " fdivs", },
1920 { NULL, NULL, },
1921 };
1922 #endif /* !defined (NO_FLOAT) */
1923
1924 #if !defined (NO_FLOAT)
1925 static void test_fadd_ (void)
1926 {
1927 __asm__ __volatile__ ("fadd. 17, 14, 15");
1928 }
1929
1930 static void test_fadds_ (void)
1931 {
1932 __asm__ __volatile__ ("fadds. 17, 14, 15");
1933 }
1934
1935 static void test_fsub_ (void)
1936 {
1937 __asm__ __volatile__ ("fsub. 17, 14, 15");
1938 }
1939
1940 static void test_fsubs_ (void)
1941 {
1942 __asm__ __volatile__ ("fsubs. 17, 14, 15");
1943 }
1944
1945 static void test_fmul_ (void)
1946 {
1947 __asm__ __volatile__ ("fmul. 17, 14, 15");
1948 }
1949
1950 static void test_fmuls_ (void)
1951 {
1952 __asm__ __volatile__ ("fmuls. 17, 14, 15");
1953 }
1954
1955 static void test_fdiv_ (void)
1956 {
1957 __asm__ __volatile__ ("fdiv. 17, 14, 15");
1958 }
1959
1960 static void test_fdivs_ (void)
1961 {
1962 __asm__ __volatile__ ("fdivs. 17, 14, 15");
1963 }
1964
1965 static test_t tests_far_ops_two[] = {
1966 { &test_fadd_ , " fadd.", },
1967 { &test_fadds_ , " fadds.", },
1968 { &test_fsub_ , " fsub.", },
1969 { &test_fsubs_ , " fsubs.", },
1970 { &test_fmul_ , " fmul.", },
1971 { &test_fmuls_ , " fmuls.", },
1972 { &test_fdiv_ , " fdiv.", },
1973 { &test_fdivs_ , " fdivs.", },
1974 { NULL, NULL, },
1975 };
1976 #endif /* !defined (NO_FLOAT) */
1977
1978 #if !defined (NO_FLOAT)
1979 static void test_fcmpo (void)
1980 {
1981 __asm__ __volatile__ ("fcmpo 2, 14, 15");
1982 }
1983
1984 static void test_fcmpu (void)
1985 {
1986 __asm__ __volatile__ ("fcmpu 2, 14, 15");
1987 }
1988
1989 static test_t tests_fcr_ops_two[] = {
1990 { &test_fcmpo , " fcmpo", },
1991 { &test_fcmpu , " fcmpu", },
1992 { NULL, NULL, },
1993 };
1994 #endif /* !defined (NO_FLOAT) */
1995
1996 #if !defined (NO_FLOAT)
1997
1998 static void test_fres (void)
1999 {
2000 __asm__ __volatile__ ("fres 17, 14");
2001 }
2002
2003 static void test_frsqrte (void)
2004 {
2005 __asm__ __volatile__ ("frsqrte 17, 14");
2006 }
2007
2008 static void test_frsp (void)
2009 {
2010 __asm__ __volatile__ ("frsp 17, 14");
2011 }
2012
2013 static void test_fctiw (void)
2014 {
2015 __asm__ __volatile__ ("fctiw 17, 14");
2016 }
2017
2018 static void test_fctiwz (void)
2019 {
2020 __asm__ __volatile__ ("fctiwz 17, 14");
2021 }
2022
2023 static void test_fmr (void)
2024 {
2025 __asm__ __volatile__ ("fmr 17, 14");
2026 }
2027
2028 static void test_fneg (void)
2029 {
2030 __asm__ __volatile__ ("fneg 17, 14");
2031 }
2032
2033 static void test_fabs (void)
2034 {
2035 __asm__ __volatile__ ("fabs 17, 14");
2036 }
2037
2038 static void test_fnabs (void)
2039 {
2040 __asm__ __volatile__ ("fnabs 17, 14");
2041 }
2042
2043 static void test_fsqrt (void)
2044 {
2045 __asm__ __volatile__ ("fsqrt 17, 14");
2046 }
2047
2048 #ifdef __powerpc64__
2049 static void test_fcfid (void)
2050 {
2051 __asm__ __volatile__ ("fcfid 17, 14");
2052 }
2053
2054 static void test_fctid (void)
2055 {
2056 __asm__ __volatile__ ("fctid 17, 14");
2057 }
2058
2059 static void test_fctidz (void)
2060 {
2061 __asm__ __volatile__ ("fctidz 17, 14");
2062 }
2063 #endif // #ifdef __powerpc64__
2064
2065 static test_t tests_fa_ops_one[] = {
2066 { &test_fres , " fres", },
2067 { &test_frsqrte , " frsqrte", },
2068 { &test_frsp , " frsp", },
2069 { &test_fctiw , " fctiw", },
2070 { &test_fctiwz , " fctiwz", },
2071 { &test_fmr , " fmr", },
2072 { &test_fneg , " fneg", },
2073 { &test_fabs , " fabs", },
2074 { &test_fnabs , " fnabs", },
2075 { &test_fsqrt , " fsqrt", },
2076 #ifdef __powerpc64__
2077 { &test_fcfid , " fcfid", },
2078 { &test_fctid , " fctid", },
2079 { &test_fctidz , " fctidz", },
2080 #endif // #ifdef __powerpc64__
2081 { NULL, NULL, },
2082 };
2083 #endif /* !defined (NO_FLOAT) */
2084
2085 #if !defined (NO_FLOAT)
2086
2087 static void test_fres_ (void)
2088 {
2089 __asm__ __volatile__ ("fres. 17, 14");
2090 }
2091
2092 static void test_frsqrte_ (void)
2093 {
2094 __asm__ __volatile__ ("frsqrte. 17, 14");
2095 }
2096
2097 static void test_frsp_ (void)
2098 {
2099 __asm__ __volatile__ ("frsp. 17, 14");
2100 }
2101
2102 static void test_fctiw_ (void)
2103 {
2104 __asm__ __volatile__ ("fctiw. 17, 14");
2105 }
2106
2107 static void test_fctiwz_ (void)
2108 {
2109 __asm__ __volatile__ ("fctiwz. 17, 14");
2110 }
2111
2112 static void test_fmr_ (void)
2113 {
2114 __asm__ __volatile__ ("fmr. 17, 14");
2115 }
2116
2117 static void test_fneg_ (void)
2118 {
2119 __asm__ __volatile__ ("fneg. 17, 14");
2120 }
2121
2122 static void test_fabs_ (void)
2123 {
2124 __asm__ __volatile__ ("fabs. 17, 14");
2125 }
2126
2127 static void test_fnabs_ (void)
2128 {
2129 __asm__ __volatile__ ("fnabs. 17, 14");
2130 }
2131
2132 #ifdef __powerpc64__
2133 static void test_fcfid_ (void)
2134 {
2135 __asm__ __volatile__ ("fcfid. 17, 14");
2136 }
2137
2138 static void test_fctid_ (void)
2139 {
2140 __asm__ __volatile__ ("fctid. 17, 14");
2141 }
2142
2143 static void test_fctidz_ (void)
2144 {
2145 __asm__ __volatile__ ("fctidz. 17, 14");
2146 }
2147 #endif // #ifdef __powerpc64__
2148
2149 static test_t tests_far_ops_one[] = {
2150 { &test_fres_ , " fres.", },
2151 { &test_frsqrte_ , " frsqrte.", },
2152 { &test_frsp_ , " frsp.", },
2153 { &test_fctiw_ , " fctiw.", },
2154 { &test_fctiwz_ , " fctiwz.", },
2155 { &test_fmr_ , " fmr.", },
2156 { &test_fneg_ , " fneg.", },
2157 { &test_fabs_ , " fabs.", },
2158 { &test_fnabs_ , " fnabs.", },
2159 #ifdef __powerpc64__
2160 { &test_fcfid_ , " fcfid.", },
2161 { &test_fctid_ , " fctid.", },
2162 { &test_fctidz_ , " fctidz.", },
2163 #endif // #ifdef __powerpc64__
2164 { NULL, NULL, },
2165 };
2166 #endif /* !defined (NO_FLOAT) */
2167
2168 #if !defined (NO_FLOAT)
2169 static test_t tests_fl_ops_spe[] = {
2170 { NULL, NULL, },
2171 };
2172 #endif /* !defined (NO_FLOAT) */
2173
2174 #if !defined (NO_FLOAT)
2175 static test_t tests_flr_ops_spe[] = {
2176 { NULL, NULL, },
2177 };
2178 #endif /* !defined (NO_FLOAT) */
2179
2180
2181 #if !defined (NO_FLOAT)
2182 extern void test_lfs (void);
2183 ASSEMBLY_FUNC("test_lfs", "lfs 17,0(14)");
2184
2185 extern void test_lfsu (void);
2186 ASSEMBLY_FUNC("test_lfsu", "lfsu 17,0(14)");
2187
2188 extern void test_lfd (void);
2189 ASSEMBLY_FUNC("test_lfd", "lfd 17,0(14)");
2190
2191 extern void test_lfdu (void);
2192 ASSEMBLY_FUNC("test_lfdu", "lfdu 17,0(14)");
2193
2194 static test_t tests_fld_ops_two_i16[] = {
2195 { &test_lfs , " lfs", },
2196 { &test_lfsu , " lfsu", },
2197 { &test_lfd , " lfd", },
2198 { &test_lfdu , " lfdu", },
2199 { NULL, NULL, },
2200 };
2201 #endif /* !defined (NO_FLOAT) */
2202
2203 #if !defined (NO_FLOAT)
2204 static void test_lfsx (void)
2205 {
2206 __asm__ __volatile__ ("lfsx 17,14,15");
2207 }
2208
2209 static void test_lfsux (void)
2210 {
2211 __asm__ __volatile__ ("lfsux 17,14,15");
2212 }
2213
2214 static void test_lfdx (void)
2215 {
2216 __asm__ __volatile__ ("lfdx 17,14,15");
2217 }
2218
2219 static void test_lfdux (void)
2220 {
2221 __asm__ __volatile__ ("lfdux 17,14,15");
2222 }
2223
2224 static test_t tests_fld_ops_two[] = {
2225 { &test_lfsx , " lfsx", },
2226 { &test_lfsux , " lfsux", },
2227 { &test_lfdx , " lfdx", },
2228 { &test_lfdux , " lfdux", },
2229 { NULL, NULL, },
2230 };
2231 #endif /* !defined (NO_FLOAT) */
2232
2233 #if !defined (NO_FLOAT)
2234 extern void test_stfs (void);
2235 ASSEMBLY_FUNC("test_stfs", "stfs 14,0(15)");
2236
2237 extern void test_stfsu (void);
2238 ASSEMBLY_FUNC("test_stfsu", "stfsu 14,0(15)");
2239
2240 extern void test_stfd (void);
2241 ASSEMBLY_FUNC("test_stfd", "stfd 14,0(15)");
2242
2243 extern void test_stfdu (void);
2244 ASSEMBLY_FUNC("test_stfdu", "stfdu 14,0(15)");
2245
2246 static test_t tests_fst_ops_three_i16[] = {
2247 { &test_stfs , " stfs", },
2248 { &test_stfsu , " stfsu", },
2249 { &test_stfd , " stfd", },
2250 { &test_stfdu , " stfdu", },
2251 { NULL, NULL, },
2252 };
2253 #endif /* !defined (NO_FLOAT) */
2254
2255 #if !defined (NO_FLOAT)
2256 static void test_stfsx (void)
2257 {
2258 __asm__ __volatile__ ("stfsx 14,15,16");
2259 }
2260
2261 static void test_stfsux (void)
2262 {
2263 __asm__ __volatile__ ("stfsux 14,15,16");
2264 }
2265
2266 static void test_stfdx (void)
2267 {
2268 __asm__ __volatile__ ("stfdx 14,15,16");
2269 }
2270
2271 static void test_stfdux (void)
2272 {
2273 __asm__ __volatile__ ("stfdux 14,15,16");
2274 }
2275
2276 static test_t tests_fst_ops_three[] = {
2277 { &test_stfsx , " stfsx", },
2278 { &test_stfsux , " stfsux", },
2279 { &test_stfdx , " stfdx", },
2280 { &test_stfdux , " stfdux", },
2281 { NULL, NULL, },
2282 };
2283 #endif /* !defined (NO_FLOAT) */
2284
2285
2286 #if defined (HAS_ALTIVEC)
2287 static void test_vmhaddshs (void)
2288 {
2289 __asm__ __volatile__ ("vmhaddshs 17, 14, 15, 16");
2290 }
2291
2292 static void test_vmhraddshs (void)
2293 {
2294 __asm__ __volatile__ ("vmhraddshs 17, 14, 15, 16");
2295 }
2296
2297 static void test_vmladduhm (void)
2298 {
2299 __asm__ __volatile__ ("vmladduhm 17, 14, 15, 16");
2300 }
2301
2302 static void test_vmsumubm (void)
2303 {
2304 __asm__ __volatile__ ("vmsumubm 17, 14, 15, 16");
2305 }
2306
2307 static void test_vmsumuhm (void)
2308 {
2309 __asm__ __volatile__ ("vmsumuhm 17, 14, 15, 16");
2310 }
2311
2312 static void test_vmsumshs (void)
2313 {
2314 __asm__ __volatile__ ("vmsumshs 17, 14, 15, 16");
2315 }
2316
2317 static void test_vmsumuhs (void)
2318 {
2319 __asm__ __volatile__ ("vmsumuhs 17, 14, 15, 16");
2320 }
2321
2322 static void test_vmsummbm (void)
2323 {
2324 __asm__ __volatile__ ("vmsummbm 17, 14, 15, 16");
2325 }
2326
2327 static void test_vmsumshm (void)
2328 {
2329 __asm__ __volatile__ ("vmsumshm 17, 14, 15, 16");
2330 }
2331
2332 static test_t tests_aa_ops_three[] = {
2333 { &test_vmhaddshs , " vmhaddshs", },
2334 { &test_vmhraddshs , " vmhraddshs", },
2335 { &test_vmladduhm , " vmladduhm", },
2336 { &test_vmsumubm , " vmsumubm", },
2337 { &test_vmsumuhm , " vmsumuhm", },
2338 { &test_vmsumshs , " vmsumshs", },
2339 { &test_vmsumuhs , " vmsumuhs", },
2340 { &test_vmsummbm , " vmsummbm", },
2341 { &test_vmsumshm , " vmsumshm", },
2342 { NULL, NULL, },
2343 };
2344 #endif /* defined (HAS_ALTIVEC) */
2345
2346 #if defined (HAS_ALTIVEC)
2347 static void test_vperm (void)
2348 {
2349 __asm__ __volatile__ ("vperm 17, 14, 15, 16");
2350 }
2351
2352 static void test_vsel (void)
2353 {
2354 __asm__ __volatile__ ("vsel 17, 14, 15, 16");
2355 }
2356
2357 static test_t tests_al_ops_three[] = {
2358 { &test_vperm , " vperm", },
2359 { &test_vsel , " vsel", },
2360 { NULL, NULL, },
2361 };
2362 #endif /* defined (HAS_ALTIVEC) */
2363
2364 #if defined (HAS_ALTIVEC)
2365 static void test_vaddubm (void)
2366 {
2367 __asm__ __volatile__ ("vaddubm 17, 14, 15");
2368 }
2369
2370 static void test_vadduhm (void)
2371 {
2372 __asm__ __volatile__ ("vadduhm 17, 14, 15");
2373 }
2374
2375 static void test_vadduwm (void)
2376 {
2377 __asm__ __volatile__ ("vadduwm 17, 14, 15");
2378 }
2379
2380 static void test_vaddubs (void)
2381 {
2382 __asm__ __volatile__ ("vaddubs 17, 14, 15");
2383 }
2384
2385 static void test_vadduhs (void)
2386 {
2387 __asm__ __volatile__ ("vadduhs 17, 14, 15");
2388 }
2389
2390 static void test_vadduws (void)
2391 {
2392 __asm__ __volatile__ ("vadduws 17, 14, 15");
2393 }
2394
2395 static void test_vaddsbs (void)
2396 {
2397 __asm__ __volatile__ ("vaddsbs 17, 14, 15");
2398 }
2399
2400 static void test_vaddshs (void)
2401 {
2402 __asm__ __volatile__ ("vaddshs 17, 14, 15");
2403 }
2404
2405 static void test_vaddsws (void)
2406 {
2407 __asm__ __volatile__ ("vaddsws 17, 14, 15");
2408 }
2409
2410 static void test_vaddcuw (void)
2411 {
2412 __asm__ __volatile__ ("vaddcuw 17, 14, 15");
2413 }
2414
2415 static void test_vsububm (void)
2416 {
2417 __asm__ __volatile__ ("vsububm 17, 14, 15");
2418 }
2419
2420 static void test_vsubuhm (void)
2421 {
2422 __asm__ __volatile__ ("vsubuhm 17, 14, 15");
2423 }
2424
2425 static void test_vsubuwm (void)
2426 {
2427 __asm__ __volatile__ ("vsubuwm 17, 14, 15");
2428 }
2429
2430 static void test_vsububs (void)
2431 {
2432 __asm__ __volatile__ ("vsububs 17, 14, 15");
2433 }
2434
2435 static void test_vsubuhs (void)
2436 {
2437 __asm__ __volatile__ ("vsubuhs 17, 14, 15");
2438 }
2439
2440 static void test_vsubuws (void)
2441 {
2442 __asm__ __volatile__ ("vsubuws 17, 14, 15");
2443 }
2444
2445 static void test_vsubsbs (void)
2446 {
2447 __asm__ __volatile__ ("vsubsbs 17, 14, 15");
2448 }
2449
2450 static void test_vsubshs (void)
2451 {
2452 __asm__ __volatile__ ("vsubshs 17, 14, 15");
2453 }
2454
2455 static void test_vsubsws (void)
2456 {
2457 __asm__ __volatile__ ("vsubsws 17, 14, 15");
2458 }
2459
2460 static void test_vsubcuw (void)
2461 {
2462 __asm__ __volatile__ ("vsubcuw 17, 14, 15");
2463 }
2464
2465 static void test_vmuloub (void)
2466 {
2467 __asm__ __volatile__ ("vmuloub 17, 14, 15");
2468 }
2469
2470 static void test_vmulouh (void)
2471 {
2472 __asm__ __volatile__ ("vmulouh 17, 14, 15");
2473 }
2474
2475 static void test_vmulosb (void)
2476 {
2477 __asm__ __volatile__ ("vmulosb 17, 14, 15");
2478 }
2479
2480 static void test_vmulosh (void)
2481 {
2482 __asm__ __volatile__ ("vmulosh 17, 14, 15");
2483 }
2484
2485 static void test_vmuleub (void)
2486 {
2487 __asm__ __volatile__ ("vmuleub 17, 14, 15");
2488 }
2489
2490 static void test_vmuleuh (void)
2491 {
2492 __asm__ __volatile__ ("vmuleuh 17, 14, 15");
2493 }
2494
2495 static void test_vmulesb (void)
2496 {
2497 __asm__ __volatile__ ("vmulesb 17, 14, 15");
2498 }
2499
2500 static void test_vmulesh (void)
2501 {
2502 __asm__ __volatile__ ("vmulesh 17, 14, 15");
2503 }
2504
2505 static void test_vsumsws (void)
2506 {
2507 __asm__ __volatile__ ("vsumsws 17, 14, 15");
2508 }
2509
2510 static void test_vsum2sws (void)
2511 {
2512 __asm__ __volatile__ ("vsum2sws 17, 14, 15");
2513 }
2514
2515 static void test_vsum4ubs (void)
2516 {
2517 __asm__ __volatile__ ("vsum4ubs 17, 14, 15");
2518 }
2519
2520 static void test_vsum4sbs (void)
2521 {
2522 __asm__ __volatile__ ("vsum4sbs 17, 14, 15");
2523 }
2524
2525 static void test_vsum4shs (void)
2526 {
2527 __asm__ __volatile__ ("vsum4shs 17, 14, 15");
2528 }
2529
2530 static void test_vavgub (void)
2531 {
2532 __asm__ __volatile__ ("vavgub 17, 14, 15");
2533 }
2534
2535 static void test_vavguh (void)
2536 {
2537 __asm__ __volatile__ ("vavguh 17, 14, 15");
2538 }
2539
2540 static void test_vavguw (void)
2541 {
2542 __asm__ __volatile__ ("vavguw 17, 14, 15");
2543 }
2544
2545 static void test_vavgsb (void)
2546 {
2547 __asm__ __volatile__ ("vavgsb 17, 14, 15");
2548 }
2549
2550 static void test_vavgsh (void)
2551 {
2552 __asm__ __volatile__ ("vavgsh 17, 14, 15");
2553 }
2554
2555 static void test_vavgsw (void)
2556 {
2557 __asm__ __volatile__ ("vavgsw 17, 14, 15");
2558 }
2559
2560 static void test_vmaxub (void)
2561 {
2562 __asm__ __volatile__ ("vmaxub 17, 14, 15");
2563 }
2564
2565 static void test_vmaxuh (void)
2566 {
2567 __asm__ __volatile__ ("vmaxuh 17, 14, 15");
2568 }
2569
2570 static void test_vmaxuw (void)
2571 {
2572 __asm__ __volatile__ ("vmaxuw 17, 14, 15");
2573 }
2574
2575 static void test_vmaxsb (void)
2576 {
2577 __asm__ __volatile__ ("vmaxsb 17, 14, 15");
2578 }
2579
2580 static void test_vmaxsh (void)
2581 {
2582 __asm__ __volatile__ ("vmaxsh 17, 14, 15");
2583 }
2584
2585 static void test_vmaxsw (void)
2586 {
2587 __asm__ __volatile__ ("vmaxsw 17, 14, 15");
2588 }
2589
2590 static void test_vminub (void)
2591 {
2592 __asm__ __volatile__ ("vminub 17, 14, 15");
2593 }
2594
2595 static void test_vminuh (void)
2596 {
2597 __asm__ __volatile__ ("vminuh 17, 14, 15");
2598 }
2599
2600 static void test_vminuw (void)
2601 {
2602 __asm__ __volatile__ ("vminuw 17, 14, 15");
2603 }
2604
2605 static void test_vminsb (void)
2606 {
2607 __asm__ __volatile__ ("vminsb 17, 14, 15");
2608 }
2609
2610 static void test_vminsh (void)
2611 {
2612 __asm__ __volatile__ ("vminsh 17, 14, 15");
2613 }
2614
2615 static void test_vminsw (void)
2616 {
2617 __asm__ __volatile__ ("vminsw 17, 14, 15");
2618 }
2619
2620 static test_t tests_aa_ops_two[] = {
2621 { &test_vaddubm , " vaddubm", },
2622 { &test_vadduhm , " vadduhm", },
2623 { &test_vadduwm , " vadduwm", },
2624 { &test_vaddubs , " vaddubs", },
2625 { &test_vadduhs , " vadduhs", },
2626 { &test_vadduws , " vadduws", },
2627 { &test_vaddsbs , " vaddsbs", },
2628 { &test_vaddshs , " vaddshs", },
2629 { &test_vaddsws , " vaddsws", },
2630 { &test_vaddcuw , " vaddcuw", },
2631 { &test_vsububm , " vsububm", },
2632 { &test_vsubuhm , " vsubuhm", },
2633 { &test_vsubuwm , " vsubuwm", },
2634 { &test_vsububs , " vsububs", },
2635 { &test_vsubuhs , " vsubuhs", },
2636 { &test_vsubuws , " vsubuws", },
2637 { &test_vsubsbs , " vsubsbs", },
2638 { &test_vsubshs , " vsubshs", },
2639 { &test_vsubsws , " vsubsws", },
2640 { &test_vsubcuw , " vsubcuw", },
2641 { &test_vmuloub , " vmuloub", },
2642 { &test_vmulouh , " vmulouh", },
2643 { &test_vmulosb , " vmulosb", },
2644 { &test_vmulosh , " vmulosh", },
2645 { &test_vmuleub , " vmuleub", },
2646 { &test_vmuleuh , " vmuleuh", },
2647 { &test_vmulesb , " vmulesb", },
2648 { &test_vmulesh , " vmulesh", },
2649 { &test_vsumsws , " vsumsws", },
2650 { &test_vsum2sws , " vsum2sws", },
2651 { &test_vsum4ubs , " vsum4ubs", },
2652 { &test_vsum4sbs , " vsum4sbs", },
2653 { &test_vsum4shs , " vsum4shs", },
2654 { &test_vavgub , " vavgub", },
2655 { &test_vavguh , " vavguh", },
2656 { &test_vavguw , " vavguw", },
2657 { &test_vavgsb , " vavgsb", },
2658 { &test_vavgsh , " vavgsh", },
2659 { &test_vavgsw , " vavgsw", },
2660 { &test_vmaxub , " vmaxub", },
2661 { &test_vmaxuh , " vmaxuh", },
2662 { &test_vmaxuw , " vmaxuw", },
2663 { &test_vmaxsb , " vmaxsb", },
2664 { &test_vmaxsh , " vmaxsh", },
2665 { &test_vmaxsw , " vmaxsw", },
2666 { &test_vminub , " vminub", },
2667 { &test_vminuh , " vminuh", },
2668 { &test_vminuw , " vminuw", },
2669 { &test_vminsb , " vminsb", },
2670 { &test_vminsh , " vminsh", },
2671 { &test_vminsw , " vminsw", },
2672 { NULL, NULL, },
2673 };
2674 #endif /* defined (HAS_ALTIVEC) */
2675
2676 #if defined (HAS_ALTIVEC)
2677 static void test_vand (void)
2678 {
2679 __asm__ __volatile__ ("vand 17, 14, 15");
2680 }
2681
2682 static void test_vor (void)
2683 {
2684 __asm__ __volatile__ ("vor 17, 14, 15");
2685 }
2686
2687 static void test_vxor (void)
2688 {
2689 __asm__ __volatile__ ("vxor 17, 14, 15");
2690 }
2691
2692 static void test_vandc (void)
2693 {
2694 __asm__ __volatile__ ("vandc 17, 14, 15");
2695 }
2696
2697 static void test_vnor (void)
2698 {
2699 __asm__ __volatile__ ("vnor 17, 14, 15");
2700 }
2701
2702 static void test_vrlb (void)
2703 {
2704 __asm__ __volatile__ ("vrlb 17, 14, 15");
2705 }
2706
2707 static void test_vrlh (void)
2708 {
2709 __asm__ __volatile__ ("vrlh 17, 14, 15");
2710 }
2711
2712 static void test_vrlw (void)
2713 {
2714 __asm__ __volatile__ ("vrlw 17, 14, 15");
2715 }
2716
2717 static void test_vslb (void)
2718 {
2719 __asm__ __volatile__ ("vslb 17, 14, 15");
2720 }
2721
2722 static void test_vslh (void)
2723 {
2724 __asm__ __volatile__ ("vslh 17, 14, 15");
2725 }
2726
2727 static void test_vslw (void)
2728 {
2729 __asm__ __volatile__ ("vslw 17, 14, 15");
2730 }
2731
2732 static void test_vsrb (void)
2733 {
2734 __asm__ __volatile__ ("vsrb 17, 14, 15");
2735 }
2736
2737 static void test_vsrh (void)
2738 {
2739 __asm__ __volatile__ ("vsrh 17, 14, 15");
2740 }
2741
2742 static void test_vsrw (void)
2743 {
2744 __asm__ __volatile__ ("vsrw 17, 14, 15");
2745 }
2746
2747 static void test_vsrab (void)
2748 {
2749 __asm__ __volatile__ ("vsrab 17, 14, 15");
2750 }
2751
2752 static void test_vsrah (void)
2753 {
2754 __asm__ __volatile__ ("vsrah 17, 14, 15");
2755 }
2756
2757 static void test_vsraw (void)
2758 {
2759 __asm__ __volatile__ ("vsraw 17, 14, 15");
2760 }
2761
2762 static void test_vpkuhum (void)
2763 {
2764 __asm__ __volatile__ ("vpkuhum 17, 14, 15");
2765 }
2766
2767 static void test_vpkuwum (void)
2768 {
2769 __asm__ __volatile__ ("vpkuwum 17, 14, 15");
2770 }
2771
2772 static void test_vpkuhus (void)
2773 {
2774 __asm__ __volatile__ ("vpkuhus 17, 14, 15");
2775 }
2776
2777 static void test_vpkuwus (void)
2778 {
2779 __asm__ __volatile__ ("vpkuwus 17, 14, 15");
2780 }
2781
2782 static void test_vpkshus (void)
2783 {
2784 __asm__ __volatile__ ("vpkshus 17, 14, 15");
2785 }
2786
2787 static void test_vpkswus (void)
2788 {
2789 __asm__ __volatile__ ("vpkswus 17, 14, 15");
2790 }
2791
2792 static void test_vpkshss (void)
2793 {
2794 __asm__ __volatile__ ("vpkshss 17, 14, 15");
2795 }
2796
2797 static void test_vpkswss (void)
2798 {
2799 __asm__ __volatile__ ("vpkswss 17, 14, 15");
2800 }
2801
2802 static void test_vpkpx (void)
2803 {
2804 __asm__ __volatile__ ("vpkpx 17, 14, 15");
2805 }
2806
2807 static void test_vmrghb (void)
2808 {
2809 __asm__ __volatile__ ("vmrghb 17, 14, 15");
2810 }
2811
2812 static void test_vmrghh (void)
2813 {
2814 __asm__ __volatile__ ("vmrghh 17, 14, 15");
2815 }
2816
2817 static void test_vmrghw (void)
2818 {
2819 __asm__ __volatile__ ("vmrghw 17, 14, 15");
2820 }
2821
2822 static void test_vmrglb (void)
2823 {
2824 __asm__ __volatile__ ("vmrglb 17, 14, 15");
2825 }
2826
2827 static void test_vmrglh (void)
2828 {
2829 __asm__ __volatile__ ("vmrglh 17, 14, 15");
2830 }
2831
2832 static void test_vmrglw (void)
2833 {
2834 __asm__ __volatile__ ("vmrglw 17, 14, 15");
2835 }
2836
2837 static void test_vslo (void)
2838 {
2839 __asm__ __volatile__ ("vslo 17, 14, 15");
2840 }
2841
2842 static void test_vsro (void)
2843 {
2844 __asm__ __volatile__ ("vsro 17, 14, 15");
2845 }
2846
2847 static test_t tests_al_ops_two[] = {
2848 { &test_vand , " vand", },
2849 { &test_vor , " vor", },
2850 { &test_vxor , " vxor", },
2851 { &test_vandc , " vandc", },
2852 { &test_vnor , " vnor", },
2853 { &test_vrlb , " vrlb", },
2854 { &test_vrlh , " vrlh", },
2855 { &test_vrlw , " vrlw", },
2856 { &test_vslb , " vslb", },
2857 { &test_vslh , " vslh", },
2858 { &test_vslw , " vslw", },
2859 { &test_vsrb , " vsrb", },
2860 { &test_vsrh , " vsrh", },
2861 { &test_vsrw , " vsrw", },
2862 { &test_vsrab , " vsrab", },
2863 { &test_vsrah , " vsrah", },
2864 { &test_vsraw , " vsraw", },
2865 { &test_vpkuhum , " vpkuhum", },
2866 { &test_vpkuwum , " vpkuwum", },
2867 { &test_vpkuhus , " vpkuhus", },
2868 { &test_vpkuwus , " vpkuwus", },
2869 { &test_vpkshus , " vpkshus", },
2870 { &test_vpkswus , " vpkswus", },
2871 { &test_vpkshss , " vpkshss", },
2872 { &test_vpkswss , " vpkswss", },
2873 { &test_vpkpx , " vpkpx", },
2874 { &test_vmrghb , " vmrghb", },
2875 { &test_vmrghh , " vmrghh", },
2876 { &test_vmrghw , " vmrghw", },
2877 { &test_vmrglb , " vmrglb", },
2878 { &test_vmrglh , " vmrglh", },
2879 { &test_vmrglw , " vmrglw", },
2880 { &test_vslo , " vslo", },
2881 { &test_vsro , " vsro", },
2882 { NULL, NULL, },
2883 };
2884 #endif /* defined (HAS_ALTIVEC) */
2885
2886 #if defined (HAS_ALTIVEC)
2887 static void test_vupkhsb (void)
2888 {
2889 __asm__ __volatile__ ("vupkhsb 17, 14");
2890 }
2891
2892 static void test_vupkhsh (void)
2893 {
2894 __asm__ __volatile__ ("vupkhsh 17, 14");
2895 }
2896
2897 static void test_vupkhpx (void)
2898 {
2899 __asm__ __volatile__ ("vupkhpx 17, 14");
2900 }
2901
2902 static void test_vupklsb (void)
2903 {
2904 __asm__ __volatile__ ("vupklsb 17, 14");
2905 }
2906
2907 static void test_vupklsh (void)
2908 {
2909 __asm__ __volatile__ ("vupklsh 17, 14");
2910 }
2911
2912 static void test_vupklpx (void)
2913 {
2914 __asm__ __volatile__ ("vupklpx 17, 14");
2915 }
2916
2917 static test_t tests_al_ops_one[] = {
2918 { &test_vupkhsb , " vupkhsb", },
2919 { &test_vupkhsh , " vupkhsh", },
2920 { &test_vupkhpx , " vupkhpx", },
2921 { &test_vupklsb , " vupklsb", },
2922 { &test_vupklsh , " vupklsh", },
2923 { &test_vupklpx , " vupklpx", },
2924 { NULL, NULL, },
2925 };
2926 #endif /* defined (HAS_ALTIVEC) */
2927
2928 #if defined (HAS_ALTIVEC)
2929 static void test_vcmpgtub (void)
2930 {
2931 __asm__ __volatile__ ("vcmpgtub 17, 14, 15");
2932 }
2933
2934 static void test_vcmpgtuh (void)
2935 {
2936 __asm__ __volatile__ ("vcmpgtuh 17, 14, 15");
2937 }
2938
2939 static void test_vcmpgtuw (void)
2940 {
2941 __asm__ __volatile__ ("vcmpgtuw 17, 14, 15");
2942 }
2943
2944 static void test_vcmpgtsb (void)
2945 {
2946 __asm__ __volatile__ ("vcmpgtsb 17, 14, 15");
2947 }
2948
2949 static void test_vcmpgtsh (void)
2950 {
2951 __asm__ __volatile__ ("vcmpgtsh 17, 14, 15");
2952 }
2953
2954 static void test_vcmpgtsw (void)
2955 {
2956 __asm__ __volatile__ ("vcmpgtsw 17, 14, 15");
2957 }
2958
2959 static void test_vcmpequb (void)
2960 {
2961 __asm__ __volatile__ ("vcmpequb 17, 14, 15");
2962 }
2963
2964 static void test_vcmpequh (void)
2965 {
2966 __asm__ __volatile__ ("vcmpequh 17, 14, 15");
2967 }
2968
2969 static void test_vcmpequw (void)
2970 {
2971 __asm__ __volatile__ ("vcmpequw 17, 14, 15");
2972 }
2973
2974 static test_t tests_ac_ops_two[] = {
2975 { &test_vcmpgtub , " vcmpgtub", },
2976 { &test_vcmpgtuh , " vcmpgtuh", },
2977 { &test_vcmpgtuw , " vcmpgtuw", },
2978 { &test_vcmpgtsb , " vcmpgtsb", },
2979 { &test_vcmpgtsh , " vcmpgtsh", },
2980 { &test_vcmpgtsw , " vcmpgtsw", },
2981 { &test_vcmpequb , " vcmpequb", },
2982 { &test_vcmpequh , " vcmpequh", },
2983 { &test_vcmpequw , " vcmpequw", },
2984 { NULL, NULL, },
2985 };
2986 #endif /* defined (HAS_ALTIVEC) */
2987
2988 #if defined (HAS_ALTIVEC)
2989 static void test_vcmpgtub_ (void)
2990 {
2991 __asm__ __volatile__ ("vcmpgtub. 17, 14, 15");
2992 }
2993
2994 static void test_vcmpgtuh_ (void)
2995 {
2996 __asm__ __volatile__ ("vcmpgtuh. 17, 14, 15");
2997 }
2998
2999 static void test_vcmpgtuw_ (void)
3000 {
3001 __asm__ __volatile__ ("vcmpgtuw. 17, 14, 15");
3002 }
3003
3004 static void test_vcmpgtsb_ (void)
3005 {
3006 __asm__ __volatile__ ("vcmpgtsb. 17, 14, 15");
3007 }
3008
3009 static void test_vcmpgtsh_ (void)
3010 {
3011 __asm__ __volatile__ ("vcmpgtsh. 17, 14, 15");
3012 }
3013
3014 static void test_vcmpgtsw_ (void)
3015 {
3016 __asm__ __volatile__ ("vcmpgtsw. 17, 14, 15");
3017 }
3018
3019 static void test_vcmpequb_ (void)
3020 {
3021 __asm__ __volatile__ ("vcmpequb. 17, 14, 15");
3022 }
3023
3024 static void test_vcmpequh_ (void)
3025 {
3026 __asm__ __volatile__ ("vcmpequh. 17, 14, 15");
3027 }
3028
3029 static void test_vcmpequw_ (void)
3030 {
3031 __asm__ __volatile__ ("vcmpequw. 17, 14, 15");
3032 }
3033
3034 static test_t tests_acr_ops_two[] = {
3035 { &test_vcmpgtub_ , " vcmpgtub.", },
3036 { &test_vcmpgtuh_ , " vcmpgtuh.", },
3037 { &test_vcmpgtuw_ , " vcmpgtuw.", },
3038 { &test_vcmpgtsb_ , " vcmpgtsb.", },
3039 { &test_vcmpgtsh_ , " vcmpgtsh.", },
3040 { &test_vcmpgtsw_ , " vcmpgtsw.", },
3041 { &test_vcmpequb_ , " vcmpequb.", },
3042 { &test_vcmpequh_ , " vcmpequh.", },
3043 { &test_vcmpequw_ , " vcmpequw.", },
3044 { NULL, NULL, },
3045 };
3046 #endif /* defined (HAS_ALTIVEC) */
3047
3048 #if defined (HAS_ALTIVEC)
3049 static void test_vsl (void)
3050 {
3051 __asm__ __volatile__ ("vsl 17, 14, 15");
3052 }
3053
3054 static void test_vsr (void)
3055 {
3056 __asm__ __volatile__ ("vsr 17, 14, 15");
3057 }
3058
3059 extern void test_vspltb (void);
3060 ASSEMBLY_FUNC("test_vspltb", "vspltb 17, 14, 0");
3061
3062 extern void test_vsplth (void);
3063 ASSEMBLY_FUNC("test_vsplth", "vsplth 17, 14, 0");
3064
3065 extern void test_vspltw (void);
3066 ASSEMBLY_FUNC("test_vspltw", "vspltw 17, 14, 0");
3067
3068 extern void test_vspltisb (void);
3069 ASSEMBLY_FUNC("test_vspltisb", "vspltisb 17, 0");
3070
3071 extern void test_vspltish (void);
3072 ASSEMBLY_FUNC("test_vspltish", "vspltish 17, 0");
3073
3074 extern void test_vspltisw (void);
3075 ASSEMBLY_FUNC("test_vspltisw", "vspltisw 17, 0");
3076
3077 extern void test_vsldoi (void);
3078 ASSEMBLY_FUNC("test_vsldoi", "vsldoi 17, 14, 15, 0");
3079
3080 static void test_lvsl (void)
3081 {
3082 __asm__ __volatile__ ("lvsl 17, 14, 15");
3083 }
3084
3085 static void test_lvsr (void)
3086 {
3087 __asm__ __volatile__ ("lvsr 17, 14, 15");
3088 }
3089
3090 static test_t tests_av_int_ops_spe[] = {
3091 { &test_vsl , " vsl", },
3092 { &test_vsr , " vsr", },
3093 { &test_vspltb , " vspltb", },
3094 { &test_vsplth , " vsplth", },
3095 { &test_vspltw , " vspltw", },
3096 { &test_vspltisb , " vspltisb", },
3097 { &test_vspltish , " vspltish", },
3098 { &test_vspltisw , " vspltisw", },
3099 { &test_vsldoi , " vsldoi", },
3100 { &test_lvsl , " lvsl", },
3101 { &test_lvsr , " lvsr", },
3102 { NULL, NULL, },
3103 };
3104 #endif /* defined (HAS_ALTIVEC) */
3105
3106 #if defined (HAS_ALTIVEC)
3107 static void test_lvebx (void)
3108 {
3109 __asm__ __volatile__ ("lvebx 17,14,15");
3110 }
3111
3112 static void test_lvehx (void)
3113 {
3114 __asm__ __volatile__ ("lvehx 17,14,15");
3115 }
3116
3117 static void test_lvewx (void)
3118 {
3119 __asm__ __volatile__ ("lvewx 17,14,15");
3120 }
3121
3122 static void test_lvx (void)
3123 {
3124 __asm__ __volatile__ ("lvx 17,14,15");
3125 }
3126
3127 static void test_lvxl (void)
3128 {
3129 __asm__ __volatile__ ("lvxl 17,14,15");
3130 }
3131
3132 static test_t tests_ald_ops_two[] = {
3133 { &test_lvebx , " lvebx", },
3134 { &test_lvehx , " lvehx", },
3135 { &test_lvewx , " lvewx", },
3136 { &test_lvx , " lvx", },
3137 { &test_lvxl , " lvxl", },
3138 { NULL, NULL, },
3139 };
3140 #endif /* defined (HAS_ALTIVEC) */
3141
3142 #if defined (HAS_ALTIVEC)
3143 static void test_stvebx (void)
3144 {
3145 __asm__ __volatile__ ("stvebx 14,15,16");
3146 }
3147
3148 static void test_stvehx (void)
3149 {
3150 __asm__ __volatile__ ("stvehx 14,15,16");
3151 }
3152
3153 static void test_stvewx (void)
3154 {
3155 __asm__ __volatile__ ("stvewx 14,15,16");
3156 }
3157
3158 static void test_stvx (void)
3159 {
3160 __asm__ __volatile__ ("stvx 14,15,16");
3161 }
3162
3163 static void test_stvxl (void)
3164 {
3165 __asm__ __volatile__ ("stvxl 14,15,16");
3166 }
3167
3168 static test_t tests_ast_ops_three[] = {
3169 { &test_stvebx , " stvebx", },
3170 { &test_stvehx , " stvehx", },
3171 { &test_stvewx , " stvewx", },
3172 { &test_stvx , " stvx", },
3173 { &test_stvxl , " stvxl", },
3174 { NULL, NULL, },
3175 };
3176 #endif /* defined (HAS_ALTIVEC) */
3177
3178 #if defined (HAS_ALTIVEC)
3179 #if 1
3180 static void test_vmaddfp (void)
3181 {
3182 __asm__ __volatile__ ("vmaddfp 17, 14, 15, 16");
3183 }
3184
3185 static void test_vnmsubfp (void)
3186 {
3187 __asm__ __volatile__ ("vnmsubfp 17, 14, 15, 16");
3188 }
3189 #endif
3190
3191 static test_t tests_afa_ops_three[] = {
3192 { &test_vmaddfp , " vmaddfp", },
3193 { &test_vnmsubfp , " vnmsubfp", },
3194 { NULL, NULL, },
3195 };
3196 #endif /* defined (HAS_ALTIVEC) */
3197
3198 #if defined (HAS_ALTIVEC)
3199 static void test_vaddfp (void)
3200 {
3201 __asm__ __volatile__ ("vaddfp 17, 14, 15");
3202 }
3203
3204 static void test_vsubfp (void)
3205 {
3206 __asm__ __volatile__ ("vsubfp 17, 14, 15");
3207 }
3208
3209 static void test_vmaxfp (void)
3210 {
3211 __asm__ __volatile__ ("vmaxfp 17, 14, 15");
3212 }
3213
3214 static void test_vminfp (void)
3215 {
3216 __asm__ __volatile__ ("vminfp 17, 14, 15");
3217 }
3218
3219 static test_t tests_afa_ops_two[] = {
3220 { &test_vaddfp , " vaddfp", },
3221 { &test_vsubfp , " vsubfp", },
3222 { &test_vmaxfp , " vmaxfp", },
3223 { &test_vminfp , " vminfp", },
3224 { NULL, NULL, },
3225 };
3226 #endif /* defined (HAS_ALTIVEC) */
3227
3228 #if defined (HAS_ALTIVEC)
3229 static void test_vrfin (void)
3230 {
3231 __asm__ __volatile__ ("vrfin 17, 14");
3232 }
3233
3234 static void test_vrfiz (void)
3235 {
3236 __asm__ __volatile__ ("vrfiz 17, 14");
3237 }
3238
3239 static void test_vrfip (void)
3240 {
3241 __asm__ __volatile__ ("vrfip 17, 14");
3242 }
3243
3244 static void test_vrfim (void)
3245 {
3246 __asm__ __volatile__ ("vrfim 17, 14");
3247 }
3248
3249 static void test_vrefp (void)
3250 {
3251 __asm__ __volatile__ ("vrefp 17, 14");
3252 }
3253
3254 static void test_vrsqrtefp (void)
3255 {
3256 __asm__ __volatile__ ("vrsqrtefp 17, 14");
3257 }
3258
3259 static void test_vlogefp (void)
3260 {
3261 __asm__ __volatile__ ("vlogefp 17, 14");
3262 }
3263
3264 static void test_vexptefp (void)
3265 {
3266 __asm__ __volatile__ ("vexptefp 17, 14");
3267 }
3268
3269 static test_t tests_afa_ops_one[] = {
3270 { &test_vrfin , " vrfin", },
3271 { &test_vrfiz , " vrfiz", },
3272 { &test_vrfip , " vrfip", },
3273 { &test_vrfim , " vrfim", },
3274 { &test_vrefp , " vrefp", },
3275 { &test_vrsqrtefp , " vrsqrtefp", },
3276 { &test_vlogefp , " vlogefp", },
3277 { &test_vexptefp , " vexptefp", },
3278 { NULL, NULL, },
3279 };
3280 #endif /* defined (HAS_ALTIVEC) */
3281
3282 #if defined (HAS_ALTIVEC)
3283 static void test_vcmpgtfp (void)
3284 {
3285 __asm__ __volatile__ ("vcmpgtfp 17, 14, 15");
3286 }
3287
3288 static void test_vcmpeqfp (void)
3289 {
3290 __asm__ __volatile__ ("vcmpeqfp 17, 14, 15");
3291 }
3292
3293 static void test_vcmpgefp (void)
3294 {
3295 __asm__ __volatile__ ("vcmpgefp 17, 14, 15");
3296 }
3297
3298 static void test_vcmpbfp (void)
3299 {
3300 __asm__ __volatile__ ("vcmpbfp 17, 14, 15");
3301 }
3302
3303 static test_t tests_afc_ops_two[] = {
3304 { &test_vcmpgtfp , " vcmpgtfp", },
3305 { &test_vcmpeqfp , " vcmpeqfp", },
3306 { &test_vcmpgefp , " vcmpgefp", },
3307 { &test_vcmpbfp , " vcmpbfp", },
3308 { NULL, NULL, },
3309 };
3310 #endif /* defined (HAS_ALTIVEC) */
3311
3312 #if defined (HAS_ALTIVEC)
3313 static void test_vcmpgtfp_ (void)
3314 {
3315 __asm__ __volatile__ ("vcmpgtfp. 17, 14, 15");
3316 }
3317
3318 static void test_vcmpeqfp_ (void)
3319 {
3320 __asm__ __volatile__ ("vcmpeqfp. 17, 14, 15");
3321 }
3322
3323 static void test_vcmpgefp_ (void)
3324 {
3325 __asm__ __volatile__ ("vcmpgefp. 17, 14, 15");
3326 }
3327
3328 static void test_vcmpbfp_ (void)
3329 {
3330 __asm__ __volatile__ ("vcmpbfp. 17, 14, 15");
3331 }
3332
3333 static test_t tests_afcr_ops_two[] = {
3334 { &test_vcmpgtfp_ , " vcmpgtfp.", },
3335 { &test_vcmpeqfp_ , " vcmpeqfp.", },
3336 { &test_vcmpgefp_ , " vcmpgefp.", },
3337 { &test_vcmpbfp_ , " vcmpbfp.", },
3338 { NULL, NULL, },
3339 };
3340 #endif /* defined (HAS_ALTIVEC) */
3341
3342 #if defined (HAS_ALTIVEC)
3343 extern void test_vcfux (void);
3344 ASSEMBLY_FUNC("test_vcfux", "vcfux 17, 14, 0");
3345
3346 extern void test_vcfsx (void);
3347 ASSEMBLY_FUNC("test_vcfsx", "vcfsx 17, 14, 0");
3348
3349 extern void test_vctuxs (void);
3350 ASSEMBLY_FUNC("test_vctuxs", "vctuxs 17, 14, 0");
3351
3352 extern void test_vctsxs (void);
3353 ASSEMBLY_FUNC("test_vctsxs", "vctsxs 17, 14, 0");
3354
3355 static test_t tests_av_float_ops_spe[] = {
3356 { &test_vcfux , " vcfux", },
3357 { &test_vcfsx , " vcfsx", },
3358 { &test_vctuxs , " vctuxs", },
3359 { &test_vctsxs , " vctsxs", },
3360 { NULL, NULL, },
3361 };
3362 #endif /* defined (HAS_ALTIVEC) */
3363
3364 /* Power ISA 2.03 support dcbtct and dcbtstct with valid hint values b00000 - 0b00111.
3365 * The ISA 2.06 added support for more valid hint values, but rather than tie ourselves
3366 * in knots trying to test all permutations of ISAs and valid hint values, we'll just
3367 * verify some of the base hint values from ISA 2.03.
3368 *
3369 * In a similar vein, in ISA 2.03, dcbtds had valid values of 0b01000 - 0b01010, whereas
3370 * ISA 2.06 expanded the range of valid hint values to 0b01000 - 0b01111. We just test
3371 * one of the ISA 2.03-supported values for dcbtds.
3372 */
3373 static void test_dcbtct (void)
3374 {
3375 /* dcbt RA, RB, TH */
3376 ASM_DCBT(17, 14, 1);
3377 ASM_DCBT(17, 14, 7);
3378 }
3379
3380 static void test_dcbtds (void)
3381 {
3382 /* dcbt RA, RB, TH */
3383 ASM_DCBT(17, 14, 10);
3384 ASM_DCBT(17, 14, 0);
3385 ASM_DCBT(17, 14, 16);
3386 }
3387
3388 static void test_dcbtst (void)
3389 {
3390 /* dcbtst RA, RB, TH */
3391 ASM_DCBTST(17, 14, 6);
3392 ASM_DCBTST(17, 14, 15);
3393 }
3394
3395
3396 static test_t tests_dcbt[] = {
3397 { &test_dcbtct , " dcbtct", },
3398 { &test_dcbtds , " dcbtds", },
3399 { &test_dcbtst , " dcbtst", },
3400 { NULL, NULL, },
3401 };
3402
3403
3404 #if defined (IS_PPC405)
3405 static void test_macchw (void)
3406 {
3407 __asm__ __volatile__ ("macchw 17, 14, 15");
3408 }
3409
3410 static void test_macchwo (void)
3411 {
3412 __asm__ __volatile__ ("macchwo 17, 14, 15");
3413 }
3414
3415 static void test_macchws (void)
3416 {
3417 __asm__ __volatile__ ("macchws 17, 14, 15");
3418 }
3419
3420 static void test_macchwso (void)
3421 {
3422 __asm__ __volatile__ ("macchwso 17, 14, 15");
3423 }
3424
3425 static void test_macchwsu (void)
3426 {
3427 __asm__ __volatile__ ("macchwsu 17, 14, 15");
3428 }
3429
3430 static void test_macchwsuo (void)
3431 {
3432 __asm__ __volatile__ ("macchwsuo 17, 14, 15");
3433 }
3434
3435 static void test_macchwu (void)
3436 {
3437 __asm__ __volatile__ ("macchwu 17, 14, 15");
3438 }
3439
3440 static void test_macchwuo (void)
3441 {
3442 __asm__ __volatile__ ("macchwuo 17, 14, 15");
3443 }
3444
3445 static void test_machhw (void)
3446 {
3447 __asm__ __volatile__ ("machhw 17, 14, 15");
3448 }
3449
3450 static void test_machhwo (void)
3451 {
3452 __asm__ __volatile__ ("machhwo 17, 14, 15");
3453 }
3454
3455 static void test_machhws (void)
3456 {
3457 __asm__ __volatile__ ("machhws 17, 14, 15");
3458 }
3459
3460 static void test_machhwso (void)
3461 {
3462 __asm__ __volatile__ ("machhwso 17, 14, 15");
3463 }
3464
3465 static void test_machhwsu (void)
3466 {
3467 __asm__ __volatile__ ("machhwsu 17, 14, 15");
3468 }
3469
3470 static void test_machhwsuo (void)
3471 {
3472 __asm__ __volatile__ ("machhwsuo 17, 14, 15");
3473 }
3474
3475 static void test_machhwu (void)
3476 {
3477 __asm__ __volatile__ ("machhwu 17, 14, 15");
3478 }
3479
3480 static void test_machhwuo (void)
3481 {
3482 __asm__ __volatile__ ("machhwuo 17, 14, 15");
3483 }
3484
3485 static void test_maclhw (void)
3486 {
3487 __asm__ __volatile__ ("maclhw 17, 14, 15");
3488 }
3489
3490 static void test_maclhwo (void)
3491 {
3492 __asm__ __volatile__ ("maclhwo 17, 14, 15");
3493 }
3494
3495 static void test_maclhws (void)
3496 {
3497 __asm__ __volatile__ ("maclhws 17, 14, 15");
3498 }
3499
3500 static void test_maclhwso (void)
3501 {
3502 __asm__ __volatile__ ("maclhwso 17, 14, 15");
3503 }
3504
3505 static void test_maclhwsu (void)
3506 {
3507 __asm__ __volatile__ ("maclhwsu 17, 14, 15");
3508 }
3509
3510 static void test_maclhwsuo (void)
3511 {
3512 __asm__ __volatile__ ("maclhwsuo 17, 14, 15");
3513 }
3514
3515 static void test_maclhwu (void)
3516 {
3517 __asm__ __volatile__ ("maclhwu 17, 14, 15");
3518 }
3519
3520 static void test_maclhwuo (void)
3521 {
3522 __asm__ __volatile__ ("maclhwuo 17, 14, 15");
3523 }
3524
3525 static void test_mulchw (void)
3526 {
3527 __asm__ __volatile__ ("mulchw 17, 14, 15");
3528 }
3529
3530 static void test_mulchwu (void)
3531 {
3532 __asm__ __volatile__ ("mulchwu 17, 14, 15");
3533 }
3534
3535 static void test_mulhhw (void)
3536 {
3537 __asm__ __volatile__ ("mulhhw 17, 14, 15");
3538 }
3539
3540 static void test_mulhhwu (void)
3541 {
3542 __asm__ __volatile__ ("mulhhwu 17, 14, 15");
3543 }
3544
3545 static void test_mullhw (void)
3546 {
3547 __asm__ __volatile__ ("mullhw 17, 14, 15");
3548 }
3549
3550 static void test_mullhwu (void)
3551 {
3552 __asm__ __volatile__ ("mullhwu 17, 14, 15");
3553 }
3554
3555 static void test_nmacchw (void)
3556 {
3557 __asm__ __volatile__ ("nmacchw 17, 14, 15");
3558 }
3559
3560 static void test_nmacchwo (void)
3561 {
3562 __asm__ __volatile__ ("nmacchwo 17, 14, 15");
3563 }
3564
3565 static void test_nmacchws (void)
3566 {
3567 __asm__ __volatile__ ("nmacchws 17, 14, 15");
3568 }
3569
3570 static void test_nmacchwso (void)
3571 {
3572 __asm__ __volatile__ ("nmacchwso 17, 14, 15");
3573 }
3574
3575 static void test_nmachhw (void)
3576 {
3577 __asm__ __volatile__ ("nmachhw 17, 14, 15");
3578 }
3579
3580 static void test_nmachhwo (void)
3581 {
3582 __asm__ __volatile__ ("nmachhwo 17, 14, 15");
3583 }
3584
3585 static void test_nmachhws (void)
3586 {
3587 __asm__ __volatile__ ("nmachhws 17, 14, 15");
3588 }
3589
3590 static void test_nmachhwso (void)
3591 {
3592 __asm__ __volatile__ ("nmachhwso 17, 14, 15");
3593 }
3594
3595 static void test_nmaclhw (void)
3596 {
3597 __asm__ __volatile__ ("nmaclhw 17, 14, 15");
3598 }
3599
3600 static void test_nmaclhwo (void)
3601 {
3602 __asm__ __volatile__ ("nmaclhwo 17, 14, 15");
3603 }
3604
3605 static void test_nmaclhws (void)
3606 {
3607 __asm__ __volatile__ ("nmaclhws 17, 14, 15");
3608 }
3609
3610 static void test_nmaclhwso (void)
3611 {
3612 __asm__ __volatile__ ("nmaclhwso 17, 14, 15");
3613 }
3614
3615 static test_t tests_p4m_ops_two[] = {
3616 { &test_macchw , " macchw", },
3617 { &test_macchwo , " macchwo", },
3618 { &test_macchws , " macchws", },
3619 { &test_macchwso , " macchwso", },
3620 { &test_macchwsu , " macchwsu", },
3621 { &test_macchwsuo , " macchwsuo", },
3622 { &test_macchwu , " macchwu", },
3623 { &test_macchwuo , " macchwuo", },
3624 { &test_machhw , " machhw", },
3625 { &test_machhwo , " machhwo", },
3626 { &test_machhws , " machhws", },
3627 { &test_machhwso , " machhwso", },
3628 { &test_machhwsu , " machhwsu", },
3629 { &test_machhwsuo , " machhwsuo", },
3630 { &test_machhwu , " machhwu", },
3631 { &test_machhwuo , " machhwuo", },
3632 { &test_maclhw , " maclhw", },
3633 { &test_maclhwo , " maclhwo", },
3634 { &test_maclhws , " maclhws", },
3635 { &test_maclhwso , " maclhwso", },
3636 { &test_maclhwsu , " maclhwsu", },
3637 { &test_maclhwsuo , " maclhwsuo", },
3638 { &test_maclhwu , " maclhwu", },
3639 { &test_maclhwuo , " maclhwuo", },
3640 { &test_mulchw , " mulchw", },
3641 { &test_mulchwu , " mulchwu", },
3642 { &test_mulhhw , " mulhhw", },
3643 { &test_mulhhwu , " mulhhwu", },
3644 { &test_mullhw , " mullhw", },
3645 { &test_mullhwu , " mullhwu", },
3646 { &test_nmacchw , " nmacchw", },
3647 { &test_nmacchwo , " nmacchwo", },
3648 { &test_nmacchws , " nmacchws", },
3649 { &test_nmacchwso , " nmacchwso", },
3650 { &test_nmachhw , " nmachhw", },
3651 { &test_nmachhwo , " nmachhwo", },
3652 { &test_nmachhws , " nmachhws", },
3653 { &test_nmachhwso , " nmachhwso", },
3654 { &test_nmaclhw , " nmaclhw", },
3655 { &test_nmaclhwo , " nmaclhwo", },
3656 { &test_nmaclhws , " nmaclhws", },
3657 { &test_nmaclhwso , " nmaclhwso", },
3658 { NULL, NULL, },
3659 };
3660 #endif /* defined (IS_PPC405) */
3661
3662 #if defined (IS_PPC405)
3663 static void test_macchw_ (void)
3664 {
3665 __asm__ __volatile__ ("macchw. 17, 14, 15");
3666 }
3667
3668 static void test_macchwo_ (void)
3669 {
3670 __asm__ __volatile__ ("macchwo. 17, 14, 15");
3671 }
3672
3673 static void test_macchws_ (void)
3674 {
3675 __asm__ __volatile__ ("macchws. 17, 14, 15");
3676 }
3677
3678 static void test_macchwso_ (void)
3679 {
3680 __asm__ __volatile__ ("macchwso. 17, 14, 15");
3681 }
3682
3683 static void test_macchwsu_ (void)
3684 {
3685 __asm__ __volatile__ ("macchwsu. 17, 14, 15");
3686 }
3687
3688 static void test_macchwsuo_ (void)
3689 {
3690 __asm__ __volatile__ ("macchwsuo. 17, 14, 15");
3691 }
3692
3693 static void test_macchwu_ (void)
3694 {
3695 __asm__ __volatile__ ("macchwu. 17, 14, 15");
3696 }
3697
3698 static void test_macchwuo_ (void)
3699 {
3700 __asm__ __volatile__ ("macchwuo. 17, 14, 15");
3701 }
3702
3703 static void test_machhw_ (void)
3704 {
3705 __asm__ __volatile__ ("machhw. 17, 14, 15");
3706 }
3707
3708 static void test_machhwo_ (void)
3709 {
3710 __asm__ __volatile__ ("machhwo. 17, 14, 15");
3711 }
3712
3713 static void test_machhws_ (void)
3714 {
3715 __asm__ __volatile__ ("machhws. 17, 14, 15");
3716 }
3717
3718 static void test_machhwso_ (void)
3719 {
3720 __asm__ __volatile__ ("machhwso. 17, 14, 15");
3721 }
3722
3723 static void test_machhwsu_ (void)
3724 {
3725 __asm__ __volatile__ ("machhwsu. 17, 14, 15");
3726 }
3727
3728 static void test_machhwsuo_ (void)
3729 {
3730 __asm__ __volatile__ ("machhwsuo. 17, 14, 15");
3731 }
3732
3733 static void test_machhwu_ (void)
3734 {
3735 __asm__ __volatile__ ("machhwu. 17, 14, 15");
3736 }
3737
3738 static void test_machhwuo_ (void)
3739 {
3740 __asm__ __volatile__ ("machhwuo. 17, 14, 15");
3741 }
3742
3743 static void test_maclhw_ (void)
3744 {
3745 __asm__ __volatile__ ("maclhw. 17, 14, 15");
3746 }
3747
3748 static void test_maclhwo_ (void)
3749 {
3750 __asm__ __volatile__ ("maclhwo. 17, 14, 15");
3751 }
3752
3753 static void test_maclhws_ (void)
3754 {
3755 __asm__ __volatile__ ("maclhws. 17, 14, 15");
3756 }
3757
3758 static void test_maclhwso_ (void)
3759 {
3760 __asm__ __volatile__ ("maclhwso. 17, 14, 15");
3761 }
3762
3763 static void test_maclhwsu_ (void)
3764 {
3765 __asm__ __volatile__ ("maclhwsu. 17, 14, 15");
3766 }
3767
3768 static void test_maclhwsuo_ (void)
3769 {
3770 __asm__ __volatile__ ("maclhwsuo. 17, 14, 15");
3771 }
3772
3773 static void test_maclhwu_ (void)
3774 {
3775 __asm__ __volatile__ ("maclhwu. 17, 14, 15");
3776 }
3777
3778 static void test_maclhwuo_ (void)
3779 {
3780 __asm__ __volatile__ ("maclhwuo. 17, 14, 15");
3781 }
3782
3783 static void test_mulchw_ (void)
3784 {
3785 __asm__ __volatile__ ("mulchw. 17, 14, 15");
3786 }
3787
3788 static void test_mulchwu_ (void)
3789 {
3790 __asm__ __volatile__ ("mulchwu. 17, 14, 15");
3791 }
3792
3793 static void test_mulhhw_ (void)
3794 {
3795 __asm__ __volatile__ ("mulhhw. 17, 14, 15");
3796 }
3797
3798 static void test_mulhhwu_ (void)
3799 {
3800 __asm__ __volatile__ ("mulhhwu. 17, 14, 15");
3801 }
3802
3803 static void test_mullhw_ (void)
3804 {
3805 __asm__ __volatile__ ("mullhw. 17, 14, 15");
3806 }
3807
3808 static void test_mullhwu_ (void)
3809 {
3810 __asm__ __volatile__ ("mullhwu. 17, 14, 15");
3811 }
3812
3813 static void test_nmacchw_ (void)
3814 {
3815 __asm__ __volatile__ ("nmacchw. 17, 14, 15");
3816 }
3817
3818 static void test_nmacchwo_ (void)
3819 {
3820 __asm__ __volatile__ ("nmacchwo. 17, 14, 15");
3821 }
3822
3823 static void test_nmacchws_ (void)
3824 {
3825 __asm__ __volatile__ ("nmacchws. 17, 14, 15");
3826 }
3827
3828 static void test_nmacchwso_ (void)
3829 {
3830 __asm__ __volatile__ ("nmacchwso. 17, 14, 15");
3831 }
3832
3833 static void test_nmachhw_ (void)
3834 {
3835 __asm__ __volatile__ ("nmachhw. 17, 14, 15");
3836 }
3837
3838 static void test_nmachhwo_ (void)
3839 {
3840 __asm__ __volatile__ ("nmachhwo. 17, 14, 15");
3841 }
3842
3843 static void test_nmachhws_ (void)
3844 {
3845 __asm__ __volatile__ ("nmachhws. 17, 14, 15");
3846 }
3847
3848 static void test_nmachhwso_ (void)
3849 {
3850 __asm__ __volatile__ ("nmachhwso. 17, 14, 15");
3851 }
3852
3853 static void test_nmaclhw_ (void)
3854 {
3855 __asm__ __volatile__ ("nmaclhw. 17, 14, 15");
3856 }
3857
3858 static void test_nmaclhwo_ (void)
3859 {
3860 __asm__ __volatile__ ("nmaclhwo. 17, 14, 15");
3861 }
3862
3863 static void test_nmaclhws_ (void)
3864 {
3865 __asm__ __volatile__ ("nmaclhws. 17, 14, 15");
3866 }
3867
3868 static void test_nmaclhwso_ (void)
3869 {
3870 __asm__ __volatile__ ("nmaclhwso. 17, 14, 15");
3871 }
3872
3873 static test_t tests_p4mc_ops_two[] = {
3874 { &test_macchw_ , " macchw.", },
3875 { &test_macchwo_ , " macchwo.", },
3876 { &test_macchws_ , " macchws.", },
3877 { &test_macchwso_ , " macchwso.", },
3878 { &test_macchwsu_ , " macchwsu.", },
3879 { &test_macchwsuo_ , " macchwsuo.", },
3880 { &test_macchwu_ , " macchwu.", },
3881 { &test_macchwuo_ , " macchwuo.", },
3882 { &test_machhw_ , " machhw.", },
3883 { &test_machhwo_ , " machhwo.", },
3884 { &test_machhws_ , " machhws.", },
3885 { &test_machhwso_ , " machhwso.", },
3886 { &test_machhwsu_ , " machhwsu.", },
3887 { &test_machhwsuo_ , " machhwsuo.", },
3888 { &test_machhwu_ , " machhwu.", },
3889 { &test_machhwuo_ , " machhwuo.", },
3890 { &test_maclhw_ , " maclhw.", },
3891 { &test_maclhwo_ , " maclhwo.", },
3892 { &test_maclhws_ , " maclhws.", },
3893 { &test_maclhwso_ , " maclhwso.", },
3894 { &test_maclhwsu_ , " maclhwsu.", },
3895 { &test_maclhwsuo_ , " maclhwsuo.", },
3896 { &test_maclhwu_ , " maclhwu.", },
3897 { &test_maclhwuo_ , " maclhwuo.", },
3898 { &test_mulchw_ , " mulchw.", },
3899 { &test_mulchwu_ , " mulchwu.", },
3900 { &test_mulhhw_ , " mulhhw.", },
3901 { &test_mulhhwu_ , " mulhhwu.", },
3902 { &test_mullhw_ , " mullhw.", },
3903 { &test_mullhwu_ , " mullhwu.", },
3904 { &test_nmacchw_ , " nmacchw.", },
3905 { &test_nmacchwo_ , " nmacchwo.", },
3906 { &test_nmacchws_ , " nmacchws.", },
3907 { &test_nmacchwso_ , " nmacchwso.", },
3908 { &test_nmachhw_ , " nmachhw.", },
3909 { &test_nmachhwo_ , " nmachhwo.", },
3910 { &test_nmachhws_ , " nmachhws.", },
3911 { &test_nmachhwso_ , " nmachhwso.", },
3912 { &test_nmaclhw_ , " nmaclhw.", },
3913 { &test_nmaclhwo_ , " nmaclhwo.", },
3914 { &test_nmaclhws_ , " nmaclhws.", },
3915 { &test_nmaclhwso_ , " nmaclhwso.", },
3916 { NULL, NULL, },
3917 };
3918 #endif /* defined (IS_PPC405) */
3919
3920 static test_table_t all_tests[] = {
3921 {
3922 tests_ia_ops_two ,
3923 "PPC integer arith insns with two args",
3924 0x00010102,
3925 },
3926 {
3927 tests_iar_ops_two ,
3928 "PPC integer arith insns with two args with flags update",
3929 0x01010102,
3930 },
3931 {
3932 tests_iac_ops_two ,
3933 "PPC integer arith insns with two args and carry",
3934 0x02010102,
3935 },
3936 {
3937 tests_iacr_ops_two ,
3938 "PPC integer arith insns with two args and carry with flags update",
3939 0x03010102,
3940 },
3941 {
3942 tests_il_ops_two ,
3943 "PPC integer logical insns with two args",
3944 0x00010202,
3945 },
3946 {
3947 tests_ilr_ops_two ,
3948 "PPC integer logical insns with two args with flags update",
3949 0x01010202,
3950 },
3951 {
3952 tests_icr_ops_two ,
3953 "PPC integer compare insns (two args)",
3954 0x01010304,
3955 },
3956 {
3957 tests_icr_ops_two_i16 ,
3958 "PPC integer compare with immediate insns (two args)",
3959 0x01010305,
3960 },
3961 {
3962 tests_ia_ops_two_i16 ,
3963 "PPC integer arith insns\n with one register + one 16 bits immediate args",
3964 0x00010106,
3965 },
3966 {
3967 tests_iar_ops_two_i16 ,
3968 "PPC integer arith insns\n with one register + one 16 bits immediate args with flags update",
3969 0x01010106,
3970 },
3971 {
3972 tests_il_ops_two_i16 ,
3973 "PPC integer logical insns\n with one register + one 16 bits immediate args",
3974 0x00010206,
3975 },
3976 {
3977 tests_ilr_ops_two_i16 ,
3978 "PPC integer logical insns\n with one register + one 16 bits immediate args with flags update",
3979 0x01010206,
3980 },
3981 {
3982 tests_crl_ops_two ,
3983 "PPC condition register logical insns - two operands",
3984 0x01010202,
3985 },
3986 {
3987 tests_iac_ops_one ,
3988 "PPC integer arith insns with one arg and carry",
3989 0x02010101,
3990 },
3991 {
3992 tests_iacr_ops_one ,
3993 "PPC integer arith insns with one arg and carry with flags update",
3994 0x03010101,
3995 },
3996 {
3997 tests_il_ops_one ,
3998 "PPC integer logical insns with one arg",
3999 0x00010201,
4000 },
4001 {
4002 tests_ilr_ops_one ,
4003 "PPC integer logical insns with one arg with flags update",
4004 0x01010201,
4005 },
4006 {
4007 tests_il_ops_spe ,
4008 "PPC logical insns with special forms",
4009 0x00010207,
4010 },
4011 {
4012 tests_ilr_ops_spe ,
4013 "PPC logical insns with special forms with flags update",
4014 0x01010207,
4015 },
4016 {
4017 tests_ild_ops_two_i16 ,
4018 "PPC integer load insns\n with one register + one 16 bits immediate args with flags update",
4019 0x00010508,
4020 },
4021 {
4022 tests_ild_ops_two ,
4023 "PPC integer load insns with two register args",
4024 0x00010509,
4025 },
4026 {
4027 tests_ist_ops_three_i16,
4028 "PPC integer store insns\n with one register + one 16 bits immediate args with flags update",
4029 0x0001050a,
4030 },
4031 {
4032 tests_ist_ops_three ,
4033 "PPC integer store insns with three register args",
4034 0x0001050b,
4035 },
4036 {
4037 tests_popcnt_ops_one ,
4038 "PPC integer population count with one register args, no flags",
4039 0x00010601,
4040 },
4041 #if !defined (NO_FLOAT)
4042 {
4043 tests_fa_ops_three ,
4044 "PPC floating point arith insns with three args",
4045 0x00020103,
4046 },
4047 #endif /* !defined (NO_FLOAT) */
4048 #if !defined (NO_FLOAT)
4049 {
4050 tests_far_ops_three ,
4051 "PPC floating point arith insns\n with three args with flags update",
4052 0x01020103,
4053 },
4054 #endif /* !defined (NO_FLOAT) */
4055 #if !defined (NO_FLOAT)
4056 {
4057 tests_fa_ops_two ,
4058 "PPC floating point arith insns with two args",
4059 0x00020102,
4060 },
4061 #endif /* !defined (NO_FLOAT) */
4062 #if !defined (NO_FLOAT)
4063 {
4064 tests_far_ops_two ,
4065 "PPC floating point arith insns\n with two args with flags update",
4066 0x01020102,
4067 },
4068 #endif /* !defined (NO_FLOAT) */
4069 #if !defined (NO_FLOAT)
4070 {
4071 tests_fcr_ops_two ,
4072 "PPC floating point compare insns (two args)",
4073 0x01020304,
4074 },
4075 #endif /* !defined (NO_FLOAT) */
4076 #if !defined (NO_FLOAT)
4077 {
4078 tests_fa_ops_one ,
4079 "PPC floating point arith insns with one arg",
4080 0x00020101,
4081 },
4082 #endif /* !defined (NO_FLOAT) */
4083 #if !defined (NO_FLOAT)
4084 {
4085 tests_far_ops_one ,
4086 "PPC floating point arith insns\n with one arg with flags update",
4087 0x01020101,
4088 },
4089 #endif /* !defined (NO_FLOAT) */
4090 #if !defined (NO_FLOAT)
4091 {
4092 tests_fl_ops_spe ,
4093 "PPC floating point status register manipulation insns",
4094 0x00020207,
4095 },
4096 #endif /* !defined (NO_FLOAT) */
4097 #if !defined (NO_FLOAT)
4098 {
4099 tests_flr_ops_spe ,
4100 "PPC floating point status register manipulation insns\n with flags update",
4101 0x01020207,
4102 },
4103 #endif /* !defined (NO_FLOAT) */
4104 #if !defined (NO_FLOAT)
4105 {
4106 tests_fld_ops_two_i16 ,
4107 "PPC float load insns\n with one register + one 16 bits immediate args with flags update",
4108 0x00020508,
4109 },
4110 #endif /* !defined (NO_FLOAT) */
4111 #if !defined (NO_FLOAT)
4112 {
4113 tests_fld_ops_two ,
4114 "PPC float load insns with two register args",
4115 0x00020509,
4116 },
4117 #endif /* !defined (NO_FLOAT) */
4118 #if !defined (NO_FLOAT)
4119 {
4120 tests_fst_ops_three_i16,
4121 "PPC float store insns\n with one register + one 16 bits immediate args with flags update",
4122 0x0002050a,
4123 },
4124 #endif /* !defined (NO_FLOAT) */
4125 #if !defined (NO_FLOAT)
4126 {
4127 tests_fst_ops_three ,
4128 "PPC float store insns with three register args",
4129 0x0002050b,
4130 },
4131 #endif /* !defined (NO_FLOAT) */
4132 #if defined (HAS_ALTIVEC)
4133 {
4134 tests_aa_ops_three ,
4135 "PPC altivec integer arith insns with three args",
4136 0x00040103,
4137 },
4138 #endif /* defined (HAS_ALTIVEC) */
4139 #if defined (HAS_ALTIVEC)
4140 {
4141 tests_al_ops_three ,
4142 "PPC altivec integer logical insns with three args",
4143 0x00040203,
4144 },
4145 #endif /* defined (HAS_ALTIVEC) */
4146 #if defined (HAS_ALTIVEC)
4147 {
4148 tests_aa_ops_two ,
4149 "PPC altivec integer arith insns with two args",
4150 0x00040102,
4151 },
4152 #endif /* defined (HAS_ALTIVEC) */
4153 #if defined (HAS_ALTIVEC)
4154 {
4155 tests_al_ops_two ,
4156 "PPC altivec integer logical insns with two args",
4157 0x00040202,
4158 },
4159 #endif /* defined (HAS_ALTIVEC) */
4160 #if defined (HAS_ALTIVEC)
4161 {
4162 tests_al_ops_one ,
4163 "PPC altivec integer logical insns with one arg",
4164 0x00040201,
4165 },
4166 #endif /* defined (HAS_ALTIVEC) */
4167 #if defined (HAS_ALTIVEC)
4168 {
4169 tests_ac_ops_two ,
4170 "Altivec integer compare insns",
4171 0x00040302,
4172 },
4173 #endif /* defined (HAS_ALTIVEC) */
4174 #if defined (HAS_ALTIVEC)
4175 {
4176 tests_acr_ops_two ,
4177 "Altivec integer compare insns with flags update",
4178 0x01040302,
4179 },
4180 #endif /* defined (HAS_ALTIVEC) */
4181 #if defined (HAS_ALTIVEC)
4182 {
4183 tests_av_int_ops_spe ,
4184 "Altivec integer special insns",
4185 0x00040207,
4186 },
4187 #endif /* defined (HAS_ALTIVEC) */
4188 #if defined (HAS_ALTIVEC)
4189 {
4190 tests_ald_ops_two ,
4191 "Altivec load insns with two register args",
4192 0x00040509,
4193 },
4194 #endif /* defined (HAS_ALTIVEC) */
4195 #if defined (HAS_ALTIVEC)
4196 {
4197 tests_ast_ops_three ,
4198 "Altivec store insns with three register args",
4199 0x0004050b,
4200 },
4201 #endif /* defined (HAS_ALTIVEC) */
4202 #if defined (HAS_ALTIVEC)
4203 {
4204 tests_afa_ops_two ,
4205 "Altivec floating point arith insns with two args",
4206 0x00050102,
4207 },
4208 #endif /* defined (HAS_ALTIVEC) */
4209 #if defined (HAS_ALTIVEC)
4210 {
4211 tests_afa_ops_three ,
4212 "Altivec floating point arith insns with three args",
4213 0x00050103,
4214 },
4215 #endif /* defined (HAS_ALTIVEC) */
4216 #if defined (HAS_ALTIVEC)
4217 {
4218 tests_afa_ops_one ,
4219 "Altivec floating point arith insns with one arg",
4220 0x00050101,
4221 },
4222 #endif /* defined (HAS_ALTIVEC) */
4223 #if defined (HAS_ALTIVEC)
4224 {
4225 tests_afc_ops_two ,
4226 "Altivec floating point compare insns",
4227 0x00050302,
4228 },
4229 #endif /* defined (HAS_ALTIVEC) */
4230 #if defined (HAS_ALTIVEC)
4231 {
4232 tests_afcr_ops_two ,
4233 "Altivec floating point compare insns with flags update",
4234 0x01050302,
4235 },
4236 #endif /* defined (HAS_ALTIVEC) */
4237 #if defined (HAS_ALTIVEC)
4238 {
4239 tests_av_float_ops_spe,
4240 "Altivec float special insns",
4241 0x00050207,
4242 },
4243 #endif /* defined (HAS_ALTIVEC) */
4244 {
4245 tests_dcbt,
4246 "Miscellaneous test: Data cache insns",
4247 0x0006070C,
4248 },
4249 #if defined (IS_PPC405)
4250 {
4251 tests_p4m_ops_two ,
4252 "PPC 405 mac insns with three args",
4253 0x00030102,
4254 },
4255 #endif /* defined (IS_PPC405) */
4256 #if defined (IS_PPC405)
4257 {
4258 tests_p4mc_ops_two ,
4259 "PPC 405 mac insns with three args with flags update",
4260 0x01030102,
4261 },
4262 #endif /* defined (IS_PPC405) */
4263 { NULL, NULL, 0x00000000, },
4264 };
4265
4266 /* -------------- END #include "ops-ppc.c" -------------- */
4267
4268 static int verbose = 0;
4269 static int arg_list_size = 0;
4270
4271 static double *fargs = NULL;
4272 static int nb_fargs = 0;
4273 static int nb_normal_fargs = 0;
4274 static HWord_t *iargs = NULL;
4275 static int nb_iargs = 0;
4276 static uint16_t *ii16 = NULL;
4277 static int nb_ii16 = 0;
4278
4279 #if defined (HAS_ALTIVEC)
4280 static vector unsigned int* viargs = NULL;
4281 static int nb_viargs = 0;
4282 static vector float* vfargs = NULL;
4283 static int nb_vfargs = 0;
4284
4285 //#define TEST_VSCR_SAT
4286 #endif
4287
4288 static inline void register_farg (void *farg,
4289 int s, uint16_t _exp, uint64_t mant)
4290 {
4291 uint64_t tmp;
4292
4293 tmp = ((uint64_t)s << 63) | ((uint64_t)_exp << 52) | mant;
4294 *(uint64_t *)farg = tmp;
4295 #ifndef __powerpc64__
4296 AB_DPRINTF("%d %03x %013llx => %016llx %0e\n",
4297 #else
4298 AB_DPRINTF("%d %03x %013lx => %016lx %0e\n",
4299 #endif
4300 s, _exp, mant, *(uint64_t *)farg, *(double *)farg);
4301 }
4302
4303 static void build_fargs_table (void)
4304 {
4305 /* Double precision:
4306 * Sign goes from zero to one (1 bit)
4307 * Exponent goes from 0 to ((1 << 12) - 1) (11 bits)
4308 * Mantissa goes from 1 to ((1 << 52) - 1) (52 bits)
4309 * + special values:
4310 * +0.0 : 0 0x000 0x0000000000000 => 0x0000000000000000
4311 * -0.0 : 1 0x000 0x0000000000000 => 0x8000000000000000
4312 * +infinity : 0 0x7FF 0x0000000000000 => 0x7FF0000000000000
4313 * -infinity : 1 0x7FF 0x0000000000000 => 0xFFF0000000000000
4314 * +QNaN : 0 0x7FF 0x7FFFFFFFFFFFF => 0x7FF7FFFFFFFFFFFF
4315 * -QNaN : 1 0x7FF 0x7FFFFFFFFFFFF => 0xFFF7FFFFFFFFFFFF
4316 * +SNaN : 0 0x7FF 0x8000000000000 => 0x7FF8000000000000
4317 * -SNaN : 1 0x7FF 0x8000000000000 => 0xFFF8000000000000
4318 * (8 values)
4319
4320 * Ref only:
4321 * Single precision
4322 * Sign: 1 bit
4323 * Exponent: 8 bits
4324 * Mantissa: 23 bits
4325 * +0.0 : 0 0x00 0x000000 => 0x00000000
4326 * -0.0 : 1 0x00 0x000000 => 0x80000000
4327 * +infinity : 0 0xFF 0x000000 => 0x7F800000
4328 * -infinity : 1 0xFF 0x000000 => 0xFF800000
4329 * +QNaN : 0 0xFF 0x3FFFFF => 0x7FBFFFFF
4330 * -QNaN : 1 0xFF 0x3FFFFF => 0xFFBFFFFF
4331 * +SNaN : 0 0xFF 0x400000 => 0x7FC00000
4332 * -SNaN : 1 0xFF 0x400000 => 0xFFC00000
4333 */
4334 uint64_t mant;
4335 uint16_t _exp, e0, e1;
4336 int s;
4337 int i=0;
4338
4339 /* Note: VEX isn't so hot with denormals, so don't bother
4340 testing them: set _exp > 0
4341 */
4342
4343 if ( arg_list_size == 1 ) { // Large
4344 fargs = malloc(200 * sizeof(double));
4345 for (s=0; s<2; s++) {
4346 for (e0=0; e0<2; e0++) {
4347 for (e1=0x001; ; e1 = ((e1 + 1) << 2) + 6) {
4348 if (e1 >= 0x400)
4349 e1 = 0x3fe;
4350 _exp = (e0 << 10) | e1;
4351 for (mant = 0x0000000000001ULL; mant < (1ULL << 52);
4352 /* Add 'random' bits */
4353 mant = ((mant + 0x4A6) << 13) + 0x359) {
4354 register_farg(&fargs[i++], s, _exp, mant);
4355 }
4356 if (e1 == 0x3fe)
4357 break;
4358 }
4359 }
4360 }
4361 } else { // Default
4362 fargs = malloc(16 * sizeof(double));
4363 for (s=0; s<2; s++) { // x2
4364 // for (e0=0; e0<2; e0++) {
4365 for (e1=0x001; ; e1 = ((e1 + 1) << 13) + 7) { // x2
4366 // for (e1=0x001; ; e1 = ((e1 + 1) << 5) + 7) { // x3
4367 if (e1 >= 0x400)
4368 e1 = 0x3fe;
4369 // _exp = (e0 << 10) | e1;
4370 _exp = e1;
4371 for (mant = 0x0000000000001ULL; mant < (1ULL << 52);
4372 /* Add 'random' bits */
4373 mant = ((mant + 0x4A6) << 29) + 0x359) { // x2
4374 register_farg(&fargs[i++], s, _exp, mant);
4375 }
4376 if (e1 == 0x3fe)
4377 break;
4378 }
4379 // }
4380 }
4381 }
4382
4383 /* To iterate over non-special values only */
4384 nb_normal_fargs = i;
4385
4386
4387 /* Special values */
4388 /* +0.0 : 0 0x000 0x0000000000000 */
4389 s = 0;
4390 _exp = 0x000;
4391 mant = 0x0000000000000ULL;
4392 register_farg(&fargs[i++], s, _exp, mant);
4393 /* -0.0 : 1 0x000 0x0000000000000 */
4394 s = 1;
4395 _exp = 0x000;
4396 mant = 0x0000000000000ULL;
4397 register_farg(&fargs[i++], s, _exp, mant);
4398 /* +infinity : 0 0x7FF 0x0000000000000 */
4399 s = 0;
4400 _exp = 0x7FF;
4401 mant = 0x0000000000000ULL;
4402 register_farg(&fargs[i++], s, _exp, mant);
4403 /* -infinity : 1 0x7FF 0x0000000000000 */
4404 s = 1;
4405 _exp = 0x7FF;
4406 mant = 0x0000000000000ULL;
4407 register_farg(&fargs[i++], s, _exp, mant);
4408 /* +QNaN : 0 0x7FF 0x7FFFFFFFFFFFF */
4409 s = 0;
4410 _exp = 0x7FF;
4411 mant = 0x7FFFFFFFFFFFFULL;
4412 register_farg(&fargs[i++], s, _exp, mant);
4413 /* -QNaN : 1 0x7FF 0x7FFFFFFFFFFFF */
4414 s = 1;
4415 _exp = 0x7FF;
4416 mant = 0x7FFFFFFFFFFFFULL;
4417 register_farg(&fargs[i++], s, _exp, mant);
4418 /* +SNaN : 0 0x7FF 0x8000000000000 */
4419 s = 0;
4420 _exp = 0x7FF;
4421 mant = 0x8000000000000ULL;
4422 register_farg(&fargs[i++], s, _exp, mant);
4423 /* -SNaN : 1 0x7FF 0x8000000000000 */
4424 s = 1;
4425 _exp = 0x7FF;
4426 mant = 0x8000000000000ULL;
4427 register_farg(&fargs[i++], s, _exp, mant);
4428 AB_DPRINTF("Registered %d fargs values\n", i);
4429
4430 nb_fargs = i;
4431 }
4432
4433 static void build_iargs_table (void)
4434 {
4435 uint64_t tmp;
4436 int i=0;
4437
4438 #ifndef __powerpc64__
4439 if (arg_list_size == 1) { // Large
4440 iargs = malloc(400 * sizeof(HWord_t));
4441 for (tmp=0; ; tmp = tmp + 1 + (tmp >> 1)) {
4442 if (tmp >= 0x100000000ULL)
4443 tmp = 0xFFFFFFFF;
4444 iargs[i++] = (HWord_t)tmp;
4445 AB_DPRINTF("val %08x\n", (HWord_t)tmp);
4446 if (tmp == 0xFFFFFFFF)
4447 break;
4448 }
4449 } else { // Default
4450 iargs = malloc(10 * sizeof(HWord_t));
4451 // for (tmp = 0; ; tmp = 71*tmp + 1 + (tmp>>1)) { // gives 8
4452 // for (tmp = 0; ; tmp = 100000*tmp + 1 + (tmp>>1)) { // gives 4
4453 for (tmp=0; ; tmp = 999999*tmp + 999999) { // gives 3
4454 if (tmp >= 0x100000000ULL)
4455 tmp = 0xFFFFFFFF;
4456 iargs[i++] = (HWord_t)tmp;
4457 AB_DPRINTF("val %08x\n", (HWord_t)tmp);
4458 if (tmp == 0xFFFFFFFF)
4459 break;
4460 }
4461 }
4462 #else
4463 if (arg_list_size == 1) { // Large
4464 iargs = malloc(800 * sizeof(HWord_t));
4465 for (tmp=0; ; tmp = 2*tmp + 1 + (tmp >> 2)) {
4466 if ((long)tmp < 0 )
4467 tmp = 0xFFFFFFFFFFFFFFFFULL;
4468 iargs[i++] = tmp;
4469 AB_DPRINTF("val %016lx\n", tmp);
4470 if (tmp == 0xFFFFFFFFFFFFFFFFULL)
4471 break;
4472 }
4473 } else { // Default
4474 iargs = malloc(20 * sizeof(HWord_t));
4475 // for (tmp=0; ; tmp = 9999*tmp + 999999) { // gives 6
4476 for (tmp = 0; ; tmp = 123456789*tmp + 123456789999) { // gives 3
4477 if ((long)tmp < 0 )
4478 tmp = 0xFFFFFFFFFFFFFFFFULL;
4479 iargs[i++] = tmp;
4480 AB_DPRINTF("val %016lx\n", tmp);
4481 if (tmp == 0xFFFFFFFFFFFFFFFFULL)
4482 break;
4483 }
4484 }
4485 #endif // #ifndef __powerpc64__
4486
4487 AB_DPRINTF("Registered %d iargs values\n", i);
4488 nb_iargs = i;
4489 }
4490
4491 static void build_ii16_table (void)
4492 {
4493 uint32_t tmp;
4494 int i=0;
4495
4496 if (arg_list_size == 1) { // Large
4497 ii16 = malloc(200 * sizeof(uint32_t));
4498 for (tmp=0; ; tmp = tmp + 1 + (tmp >> 2)) {
4499 if (tmp >= 0x10000)
4500 tmp = 0xFFFF;
4501 ii16[i++] = tmp;
4502 AB_DPRINTF("val %04x\n", tmp);
4503 if (tmp == 0xFFFF)
4504 break;
4505 }
4506 } else { // Default
4507 ii16 = malloc(10 * sizeof(uint32_t));
4508 for (tmp=0; ; tmp = 999*tmp + 999) { // gives 3
4509 if (tmp >= 0x10000)
4510 tmp = 0xFFFF;
4511 ii16[i++] = tmp;
4512 AB_DPRINTF("val %04x\n", tmp);
4513 if (tmp == 0xFFFF)
4514 break;
4515 }
4516 }
4517 AB_DPRINTF("Registered %d ii16 values\n", i);
4518 nb_ii16 = i;
4519 }
4520
4521 #if defined (HAS_ALTIVEC)
4522 static void build_viargs_table (void)
4523 {
4524 #if !defined (ALTIVEC_ARGS_LARGE)
4525 unsigned int i=2;
4526 viargs = memalign16(i * sizeof(vector unsigned int));
4527 viargs[0] = (vector unsigned int) { 0x01020304,0x05060708,0x090A0B0C,0x0E0D0E0F };
4528 AB_DPRINTF_VEC32x4( viargs[0] );
4529 viargs[1] = (vector unsigned int) { 0xF1F2F3F4,0xF5F6F7F8,0xF9FAFBFC,0xFEFDFEFF };
4530 AB_DPRINTF_VEC32x4( viargs[1] );
4531 #else
4532 unsigned int i,j;
4533 // build from iargs table (large/default already set)
4534 viargs = malloc(nb_iargs * sizeof(vector unsigned int));
4535 for (i=0; i<nb_iargs; i++) {
4536 j = iargs[i];
4537 viargs[i] = (vector unsigned int){ j, j*2, j*3, j*4 };
4538 AB_DPRINTF_VEC32x4( viargs[i] );
4539 }
4540 #endif
4541
4542 AB_DPRINTF("Registered %d viargs values\n", i);
4543 nb_viargs = i;
4544 }
4545
4546 static inline void register_vfarg (vector float* vfarg,
4547 int s, uint8_t _exp, uint32_t mant)
4548 {
4549 uint32_t tmp;
4550 vector uint32_t* vfargI = (vector uint32_t*)vfarg;
4551
4552 tmp = ((uint64_t)s << 31) | ((uint64_t)_exp << 23) | mant;
4553 *vfargI = (vector uint32_t){ tmp,tmp,tmp,tmp };
4554 AB_DPRINTF("%d %02x %06x => %08x %0e\n",
4555 s, _exp, mant, *((uint32_t*)&tmp), *(float*)&tmp);
4556 }
4557
4558 static void build_vfargs_table (void)
4559 {
4560 /* Sign goes from zero to one
4561 * Exponent goes from 0 to ((1 << 9) - 1)
4562 * Mantissa goes from 1 to ((1 << 24) - 1)
4563 * + special values:
4564 * +0.0 : 0 0x00 0x000000 => 0x00000000
4565 * -0.0 : 1 0x00 0x000000 => 0x80000000
4566 * +infinity : 0 0xFF 0x000000 => 0x7F800000
4567 * -infinity : 1 0xFF 0x000000 => 0xFF800000
4568 * +SNaN : 0 0xFF 0x7FFFFF (non-zero) => 0x7FFFFFFF
4569 * -SNaN : 1 0xFF 0x7FFFFF (non-zero) => 0xFFFFFFFF
4570 * +QNaN : 0 0xFF 0x3FFFFF (non-zero) => 0x7FBFFFFF
4571 * -QNaN : 1 0xFF 0x3FFFFF (non-zero) => 0xFFBFFFFF
4572 * (8 values)
4573 */
4574 uint32_t mant;
4575 uint16_t _exp;
4576 int s;
4577 int i=0;
4578
4579
4580 #if !defined (ALTIVEC_ARGS_LARGE)
4581 nb_vfargs = 12;
4582 vfargs = memalign16(nb_vfargs * sizeof(vector float));
4583
4584 // 4 values:
4585 for (s=0; s<2; s++) {
4586 for (_exp=0x5; ; _exp += 0x9D ) {
4587 if (_exp > 0xDF)
4588 break;
4589 for (mant = 0x3FFFFF; mant < 0x7FFFFF;
4590 mant = /* random */ ((mant + 0x1A6) << 31) + 0x159) {
4591 register_vfarg(&vfargs[i++], s, (uint8_t)_exp, mant);
4592 }
4593 }
4594 }
4595 #else
4596 nb_vfargs = 50;
4597 vfargs = memalign16(nb_vfargs * sizeof(vector float));
4598
4599 for (s=0; s<2; s++) {
4600 for (_exp=0x0; ; _exp += 0x3F ) {
4601 // for (_exp=0; ; _exp = ((_exp + 1) << 1) + 3) {
4602 if (_exp >= 0xFE)
4603 _exp = 0xFE;
4604 for (mant = 0x0; mant < 0x7FFFFF;
4605 mant = /* random */ ((mant + 0x4A6) << 5) + 0x359) {
4606 register_vfarg(&vfargs[i++], s, (uint8_t)_exp, mant);
4607 }
4608 if (_exp >= 0xFE)
4609 break;
4610 }
4611 }
4612 #endif
4613
4614 /* Special values */
4615 /* +0.0 : 0 0x00 0x000000 */
4616 s = 0;
4617 _exp = 0x00;
4618 mant = 0x000000;
4619 register_vfarg(&vfargs[i++], s, _exp, mant);
4620 /* -0.0 : 1 0x00 0x000000 */
4621 s = 1;
4622 _exp = 0x00;
4623 mant = 0x000000;
4624 register_vfarg(&vfargs[i++], s, _exp, mant);
4625
4626 /* +infinity : 0 0xFF 0x000000 */
4627 s = 0;
4628 _exp = 0xFF;
4629 mant = 0x000000;
4630 register_vfarg(&vfargs[i++], s, _exp, mant);
4631 /* -infinity : 1 0xFF 0x000000 */
4632 s = 1;
4633 _exp = 0xFF;
4634 mant = 0x000000;
4635 register_vfarg(&vfargs[i++], s, _exp, mant);
4636
4637 /* NaN: _exponent all 1s, non-zero fraction */
4638 /* SNaN is a NaN with the most significant fraction bit clear.*/
4639 /* +SNaN : 0 0xFF 0x7FFFFF */
4640 s = 0;
4641 _exp = 0xFF;
4642 mant = 0x7FFFFF;
4643 register_vfarg(&vfargs[i++], s, _exp, mant);
4644 /* -SNaN : 1 0xFF 0x7FFFFF */
4645 s = 1;
4646 _exp = 0xFF;
4647 mant = 0x7FFFFF;
4648 register_vfarg(&vfargs[i++], s, _exp, mant);
4649
4650 /* QNaN is a NaN with the most significant fraction bit set */
4651 /* +QNaN : 0 0xFF 0x3F0000 */
4652 s = 0;
4653 _exp = 0xFF;
4654 mant = 0x3FFFFF;
4655 register_vfarg(&vfargs[i++], s, _exp, mant);
4656 /* -QNaN : 1 0xFF 0x3F0000 */
4657 s = 1;
4658 _exp = 0xFF;
4659 mant = 0x3FFFFF;
4660 register_vfarg(&vfargs[i++], s, _exp, mant);
4661 AB_DPRINTF("Registered %d vfargs values\n", i);
4662
4663 assert(i <= nb_vfargs);
4664 nb_vfargs = i;
4665 }
4666 #endif
4667
4668 #if 0
4669 static void dump_iargs (void)
4670 {
4671 int i;
4672 for (i = 0; i < nb_iargs; i++) {
4673 printf("iarg %d: %08x %08x %08x\n", i, iargs[i],
4674 (unsigned int)&iargs[i], (unsigned int)iargs);
4675 }
4676 }
4677
4678 static void dump_iargs16 (void)
4679 {
4680 int i;
4681 for (i = 0; i < nb_ii16; i++) {
4682 printf("iarg16 %d: %08x %08x %08x\n", i, ii16[i],
4683 (unsigned int)&ii16[i], (unsigned int)ii16);
4684 }
4685 }
4686
4687 static void dump_vfargs (void)
4688 {
4689 vector float vf;
4690 float f;
4691 int i=0;
4692 for (i=0; i<nb_vfargs; i++) {
4693 vf = (vector float)vfargs[i];
4694 f = ((float*)&vf)[0];
4695 printf("vfarg %3d: %24f : %08x\n", i, f, ((unsigned int*)&f)[0]);
4696 }
4697 }
4698 #endif
4699
4700 static void test_int_three_args (const char* name, test_func_t func,
4701 unused uint32_t test_flags)
4702 {
4703 volatile HWord_t res;
4704 volatile uint32_t flags, xer;
4705 int i, j, k;
4706
4707 for (i=0; i<nb_iargs; i++) {
4708 for (j=0; j<nb_iargs; j++) {
4709 for (k=0; k<nb_iargs; k++) {
4710 r14 = iargs[i];
4711 r15 = iargs[j];
4712 r16 = iargs[k];
4713
4714 SET_CR_XER_ZERO;
4715 (*func)();
4716 GET_CR_XER(flags,xer);
4717 res = r17;
4718
4719 #ifndef __powerpc64__
4720 printf("%s %08x, %08x, %08x => %08x (%08x %08x)\n",
4721 #else
4722 printf("%s %016llx, %016llx, %016llx => %016llx (%08x %08x)\n",
4723 #endif
4724 name, iargs[i], iargs[j], iargs[k], res, flags, xer);
4725 }
4726 if (verbose) printf("\n");
4727 }
4728 }
4729 }
4730
4731 static void test_int_two_args (const char* name, test_func_t func,
4732 uint32_t test_flags)
4733 {
4734 volatile HWord_t res;
4735 volatile uint32_t flags, xer, xer_orig;
4736 int i, j, is_div;
4737 #ifdef __powerpc64__
4738 int zap_hi32;
4739 #endif
4740
4741 // catches div, divwu, divo, divwu, divwuo, and . variants
4742 is_div = strstr(name, "divw") != NULL;
4743
4744 #ifdef __powerpc64__
4745 zap_hi32 = strstr(name, "mulhw") != NULL;
4746 #endif
4747
4748 xer_orig = 0x00000000;
4749 redo:
4750 for (i=0; i<nb_iargs; i++) {
4751 for (j=0; j<nb_iargs; j++) {
4752
4753 /* result of division by zero is implementation dependent.
4754 don't test it. */
4755 if (is_div && iargs[j] == 0)
4756 continue;
4757
4758 r14 = iargs[i];
4759 r15 = iargs[j];
4760
4761 SET_XER(xer_orig);
4762 SET_CR_ZERO;
4763 (*func)();
4764 GET_CR_XER(flags,xer);
4765 res = r17;
4766
4767 #ifndef __powerpc64__
4768 printf("%s %08x, %08x => %08x (%08x %08x)\n",
4769 #else
4770 if (zap_hi32) res &= 0xFFFFFFFFULL;
4771 printf("%s %016llx, %016llx => %016llx (%08x %08x)\n",
4772 #endif
4773 name, iargs[i], iargs[j], res, flags, xer);
4774 }
4775 if (verbose) printf("\n");
4776 }
4777 if ((test_flags & PPC_XER_CA) && xer_orig == 0x00000000) {
4778 xer_orig = 0x20000000;
4779 goto redo;
4780 }
4781 }
4782
4783 static void test_int_one_arg (const char* name, test_func_t func,
4784 uint32_t test_flags)
4785 {
4786 volatile HWord_t res;
4787 volatile uint32_t flags, xer, xer_orig;
4788 int i;
4789
4790 xer_orig = 0x00000000;
4791 redo:
4792 for (i=0; i<nb_iargs; i++) {
4793 r14 = iargs[i];
4794 SET_XER(xer_orig);
4795 SET_CR_ZERO;
4796 (*func)();
4797 res = r17;
4798 GET_CR_XER(flags,xer);
4799
4800 #ifndef __powerpc64__
4801 printf("%s %08x => %08x (%08x %08x)\n",
4802 #else
4803 printf("%s %016llx => %016llx (%08x %08x)\n",
4804 #endif
4805 name, iargs[i], res, flags, xer);
4806 }
4807 if ((test_flags & PPC_XER_CA) && xer_orig == 0x00000000) {
4808 xer_orig = 0x20000000;
4809 goto redo;
4810 }
4811 }
4812
4813 static inline void invalidate_icache ( void *ptr, int nbytes )
4814 {
4815 HWord_t startaddr = (HWord_t) ptr;
4816 HWord_t endaddr = startaddr + nbytes;
4817 HWord_t cls = 32; /*VG_(cache_line_size_ppc32);*/
4818 HWord_t addr;
4819
4820 startaddr &= ~(cls - 1);
4821 for (addr = startaddr; addr < endaddr; addr += cls)
4822 asm volatile("dcbst 0,%0" : : "r" (addr));
4823 asm volatile("sync");
4824 for (addr = startaddr; addr < endaddr; addr += cls)
4825 asm volatile("icbi 0,%0" : : "r" (addr));
4826 asm volatile("sync; isync");
4827 }
4828
4829 /* for god knows what reason, if this isn't inlined, the
4830 program segfaults. */
4831 static inline
4832 void _patch_op_imm (uint32_t *p_insn, uint16_t imm, int sh, int len)
4833 {
4834 uint32_t mask = ((1 << len) - 1) << sh;
4835 *p_insn = (*p_insn & ~mask) | ((imm<<sh) & mask);
4836 }
4837
4838 static inline
4839 void patch_op_imm (uint32_t* p_insn, uint16_t imm, int sh, int len)
4840 {
4841 _patch_op_imm(p_insn, imm, sh, len);
4842 invalidate_icache(p_insn, 4);
4843 }
4844
4845 static inline
4846 void patch_op_imm16 (uint32_t *p_insn, uint16_t imm)
4847 {
4848 patch_op_imm(p_insn, imm, 0, 16);
4849 }
4850
4851
4852 /* Copy the 2 insn function starting at p_func_F to func_buf[], and
4853 return a possibly different pointer, which, when called, runs the
4854 copy in func_buf[]. */
4855 static inline
4856 test_func_t init_function( test_func_t p_func_F, uint32_t func_buf[] )
4857 {
4858 uint32_t* p_func = (uint32_t*)p_func_F;
4859 #if !defined(__powerpc64__) || _CALL_ELF == 2
4860 func_buf[0] = p_func[0];
4861 func_buf[1] = p_func[1];
4862 return (test_func_t)&func_buf[0];
4863 #else
4864 /* p_func points to a function descriptor, the first word of which
4865 points to the real code. Copy the code itself but not the
4866 descriptor, and just swizzle the descriptor's entry pointer. */
4867 uint64_t* descr = (uint64_t*)p_func;
4868 uint32_t* entry = (uint32_t*)(descr[0]);
4869 func_buf[0] = entry[0];
4870 func_buf[1] = entry[1];
4871 descr[0] = (uint64_t)&func_buf[0];
4872 return (test_func_t)descr;
4873 #endif // #ifndef __powerpc64__
4874 }
4875
4876
4877 static void test_int_one_reg_imm16 (const char* name,
4878 test_func_t func_IN,
4879 unused uint32_t test_flags)
4880 {
4881 volatile test_func_t func;
4882 uint32_t* func_buf = get_rwx_area();
4883 volatile HWord_t res;
4884 volatile uint32_t flags, xer;
4885 int i, j;
4886
4887 for (i=0; i<nb_iargs; i++) {
4888 for (j=0; j<nb_ii16; j++) {
4889 /* Patch up the instruction */
4890 func = init_function( func_IN, func_buf );
4891 patch_op_imm16(&func_buf[0], ii16[j]);
4892
4893 r14 = iargs[i];
4894
4895 SET_CR_XER_ZERO;
4896 (*func)();
4897 GET_CR_XER(flags,xer);
4898 res = r17;
4899
4900 #ifndef __powerpc64__
4901 printf("%s %08x, %08x => %08x (%08x %08x)\n",
4902 #else
4903 printf("%s %016llx, %08x => %016llx (%08x %08x)\n",
4904 #endif
4905 name, iargs[i], ii16[j], res, flags, xer);
4906 }
4907 if (verbose) printf("\n");
4908 }
4909 }
4910
4911 /* Special test cases for:
4912 * rlwimi
4913 * rlwinm
4914 * rlwnm
4915 * srawi
4916 * mcrf
4917 * mcrfs
4918 * mcrxr_cb
4919 * mfcr_cb
4920 * mfspr_cb
4921 * mftb_cb
4922 * mtcrf_cb
4923 * mtspr_cb
4924
4925 __powerpc64__ only:
4926 * rldcl rA,rS,SH,MB
4927 * rldcr rA,rS,SH,ME
4928 * rldic rA,rS,SH,MB
4929 * rldicl rA,rS,SH,MB
4930 * rldicr rA,rS,SH,ME
4931 * rldimi rA,rS,SH,MB
4932 * sradi rA,rS,SH
4933 */
4934
4935 static void rlwi_cb (const char* name, test_func_t func_IN,
4936 unused uint32_t test_flags)
4937 {
4938 volatile test_func_t func;
4939 uint32_t* func_buf = get_rwx_area();
4940 volatile HWord_t res;
4941 volatile uint32_t flags, xer;
4942 int i, j, k, l, arg_step;
4943
4944 arg_step = (arg_list_size == 0) ? 31 : 3;
4945
4946 r17 = 0; // rlwimi takes r17 as input: start with a clean slate.
4947
4948 for (i=0; i<nb_iargs; i++) {
4949 for (j=0; j<32; j+=arg_step) {
4950 for (k=0; k<32; k+=arg_step) {
4951 for (l=0; l<32; l+=arg_step) {
4952 /* Patch up the instruction */
4953 func = init_function( func_IN, func_buf );
4954 _patch_op_imm(&func_buf[0], j, 11, 5);
4955 _patch_op_imm(&func_buf[0], k, 6, 5);
4956 patch_op_imm(&func_buf[0], l, 1, 5);
4957
4958 r14 = iargs[i];
4959
4960 SET_CR_XER_ZERO;
4961 (*func)();
4962 GET_CR_XER(flags,xer);
4963 res = r17;
4964
4965 #ifndef __powerpc64__
4966 printf("%s %08x, %2d, %2d, %2d => %08x (%08x %08x)\n",
4967 #else
4968 printf("%s %016llx, %2d, %2d, %2d => %016llx (%08x %08x)\n",
4969 #endif
4970 name, iargs[i], j, k, l, res, flags, xer);
4971 }
4972 if (verbose) printf("\n");
4973 }
4974 }
4975 }
4976 }
4977
4978 static void rlwnm_cb (const char* name, test_func_t func_IN,
4979 unused uint32_t test_flags)
4980 {
4981 volatile test_func_t func;
4982 uint32_t* func_buf = get_rwx_area();
4983 volatile HWord_t res;
4984 volatile uint32_t flags, xer;
4985 int i, j, k, l, arg_step;
4986
4987 arg_step = (arg_list_size == 0) ? 31 : 3;
4988
4989 for (i=0; i<nb_iargs; i++) {
4990 for (j=0; j<nb_iargs; j++) {
4991 for (k=0; k<32; k+=arg_step) {
4992 for (l=0; l<32; l+=arg_step) {
4993 /* Patch up the instruction */
4994 func = init_function( func_IN, func_buf );
4995 _patch_op_imm(&func_buf[0], k, 6, 5);
4996 patch_op_imm(&func_buf[0], l, 1, 5);
4997
4998 r14 = iargs[i];
4999 r15 = iargs[j];
5000
5001 SET_CR_XER_ZERO;
5002 (*func)();
5003 GET_CR_XER(flags,xer);
5004 res = r17;
5005
5006 #ifndef __powerpc64__
5007 printf("%s %08x, %08x, %2d, %2d => %08x (%08x %08x)\n",
5008 #else
5009 printf("%s %016llx, %016llx, %2d, %2d => %016llx (%08x %08x)\n",
5010 #endif
5011 name, iargs[i], iargs[j], k, l, res, flags, xer);
5012 }
5013 if (verbose) printf("\n");
5014 }
5015 }
5016 }
5017 }
5018
5019 static void srawi_cb (const char* name, test_func_t func_IN,
5020 unused uint32_t test_flags)
5021 {
5022 volatile test_func_t func;
5023 uint32_t* func_buf = get_rwx_area();
5024 volatile HWord_t res;
5025 volatile uint32_t flags, xer;
5026 int i, j, arg_step;
5027
5028 arg_step = (arg_list_size == 0) ? 31 : 1;
5029
5030 for (i=0; i<nb_iargs; i++) {
5031 for (j=0; j<32; j+=arg_step) {
5032 /* Patch up the instruction */
5033 func = init_function( func_IN, func_buf );
5034 patch_op_imm(&func_buf[0], j, 11, 5);
5035
5036 r14 = iargs[i];
5037
5038 SET_CR_XER_ZERO;
5039 (*func)();
5040 GET_CR_XER(flags,xer);
5041 res = r17;
5042
5043 #ifndef __powerpc64__
5044 printf("%s %08x, %2d => %08x (%08x %08x)\n",
5045 #else
5046 printf("%s %016llx, %2d => %016llx (%08x %08x)\n",
5047 #endif
5048 name, iargs[i], j, res, flags, xer);
5049 }
5050 if (verbose) printf("\n");
5051 }
5052 }
5053
5054 static void mcrf_cb (const char* name, test_func_t func_IN,
5055 unused uint32_t test_flags)
5056 {
5057 volatile test_func_t func;
5058 uint32_t* func_buf = get_rwx_area();
5059 volatile uint32_t flags, xer;
5060 int i, j, k, arg_step;
5061
5062 arg_step = (arg_list_size == 0) ? 7 : 1;
5063
5064 for (i=0; i<nb_iargs; i++) {
5065 for (j=0; j<8; j+=arg_step) {
5066 for (k=0; k<8; k+=arg_step) {
5067 /* Patch up the instruction */
5068 func = init_function( func_IN, func_buf );
5069 _patch_op_imm(&func_buf[0], j, 23, 3);
5070 patch_op_imm(&func_buf[0], k, 18, 3);
5071
5072 r14 = iargs[i];
5073
5074 SET_CR(r14);
5075 SET_XER_ZERO;
5076 (*func)();
5077 GET_CR_XER(flags,xer);
5078
5079 #ifndef __powerpc64__
5080 printf("%s %d, %d (%08x) => (%08x %08x)\n",
5081 #else
5082 printf("%s %d, %d (%016llx) => (%08x %08x)\n",
5083 #endif
5084 name, j, k, iargs[i], flags, xer);
5085 }
5086 if (verbose) printf("\n");
5087 }
5088 }
5089 }
5090
5091 static void mcrxr_cb (const char* name, test_func_t func_IN,
5092 unused uint32_t test_flags)
5093 {
5094 volatile test_func_t func;
5095 uint32_t* func_buf = get_rwx_area();
5096 volatile uint32_t flags, xer;
5097 int i, j, k, arg_step;
5098
5099 arg_step = 1; //(arg_list_size == 0) ? 7 : 1;
5100
5101 for (i=0; i<16; i+=arg_step) {
5102 j = i << 28;
5103 for (k=0; k<8; k+=arg_step) {
5104 /* Patch up the instruction */
5105 func = init_function( func_IN, func_buf );
5106 patch_op_imm(&func_buf[0], k, 23, 3);
5107
5108 r14 = j;
5109
5110 SET_CR_ZERO;
5111 SET_XER(r14);
5112 (*func)();
5113 GET_CR_XER(flags,xer);
5114
5115 printf("%s %d (%08x) => (%08x %08x)\n",
5116 name, k, j, flags, xer);
5117 }
5118 if (verbose) printf("\n");
5119 }
5120 }
5121
5122 static void mfcr_cb (const char* name, test_func_t func,
5123 unused uint32_t test_flags)
5124 {
5125 volatile HWord_t res;
5126 volatile uint32_t flags, xer;
5127 int i;
5128
5129 for (i=0; i<nb_iargs; i++) {
5130 r14 = iargs[i];
5131
5132 /* Set up flags for test */
5133 SET_CR(r14);
5134 SET_XER_ZERO;
5135 (*func)();
5136 GET_CR_XER(flags,xer);
5137 res = r17;
5138
5139 #ifndef __powerpc64__
5140 printf("%s (%08x) => %08x (%08x %08x)\n",
5141 #else
5142 printf("%s (%016llx) => %016llx (%08x %08x)\n",
5143 #endif
5144 name, iargs[i], res, flags, xer);
5145 }
5146 }
5147
5148 // NOTE: Not using func: calling function kills lr
5149 static void mfspr_cb (const char* name, test_func_t func,
5150 unused uint32_t test_flags)
5151 {
5152 //volatile uint32_t res, flags, xer, ctr, lr, tmpcr, tmpxer;
5153 volatile HWord_t res;
5154 int j, k;
5155 func = func; // just to stop compiler complaining
5156
5157 // mtxer followed by mfxer
5158 for (k=0; k<nb_iargs; k++) {
5159 j = iargs[k];
5160 __asm__ __volatile__(
5161 "mtxer %1\n"
5162 "\tmfxer %0"
5163 : /*out*/"=b"(res) : /*in*/"b"(j) : /*trashed*/"xer"
5164 );
5165 res &= 0xE000007F; /* rest of the bits are undefined */
5166
5167 #ifndef __powerpc64__
5168 printf("%s 1 (%08x) -> mtxer -> mfxer => %08x\n",
5169 #else
5170 printf("%s 1 (%08x) -> mtxer -> mfxer => %016llx\n",
5171 #endif
5172 name, j, res);
5173 }
5174
5175 // mtlr followed by mflr
5176 for (k=0; k<nb_iargs; k++) {
5177 j = iargs[k];
5178 __asm__ __volatile__(
5179 "mtlr %1\n"
5180 "\tmflr %0"
5181 : /*out*/"=b"(res) : /*in*/"b"(j) : /*trashed*/"lr"
5182 );
5183
5184 #ifndef __powerpc64__
5185 printf("%s 8 (%08x) -> mtlr -> mflr => %08x\n",
5186 #else
5187 printf("%s 8 (%08x) -> mtlr -> mflr => %016llx\n",
5188 #endif
5189 name, j, res);
5190 }
5191
5192 // mtctr followed by mfctr
5193 for (k=0; k<nb_iargs; k++) {
5194 j = iargs[k];
5195 __asm__ __volatile__(
5196 "mtctr %1\n"
5197 "\tmfctr %0"
5198 : /*out*/"=b"(res) : /*in*/"b"(j) : /*trashed*/"ctr"
5199 );
5200
5201 #ifndef __powerpc64__
5202 printf("%s 9 (%08x) -> mtctr -> mfctr => %08x\n",
5203 #else
5204 printf("%s 9 (%08x) -> mtctr -> mfctr => %016llx\n",
5205 #endif
5206 name, j, res);
5207 }
5208 }
5209
5210 static void mtcrf_cb (const char* name, test_func_t func_IN,
5211 unused uint32_t test_flags)
5212 {
5213 volatile test_func_t func;
5214 uint32_t* func_buf = get_rwx_area();
5215 volatile uint32_t flags, xer;
5216 int i, j, arg_step;
5217
5218 arg_step = (arg_list_size == 0) ? 99 : 1;
5219
5220 for (i=0; i<nb_iargs; i++) {
5221 for (j=0; j<256; j+=arg_step) {
5222 /* Patch up the instruction */
5223 func = init_function( func_IN, func_buf );
5224 patch_op_imm(&func_buf[0], j, 12, 8);
5225
5226 r14 = iargs[i];
5227
5228 SET_CR_XER_ZERO;
5229 (*func)();
5230 GET_CR_XER(flags,xer);
5231
5232 #ifndef __powerpc64__
5233 printf("%s %3d, %08x => (%08x %08x)\n",
5234 #else
5235 printf("%s %3d, %016llx => (%08x %08x)\n",
5236 #endif
5237 name, j, iargs[i], flags, xer);
5238 }
5239 if (verbose) printf("\n");
5240 }
5241 }
5242
5243 // NOTE: Not using func: calling function kills lr
5244 static void mtspr_cb (const char* name, test_func_t func,
5245 unused uint32_t test_flags)
5246 {
5247 }
5248
5249 #ifdef __powerpc64__
5250 static void rldc_cb (const char* name, test_func_t func_IN,
5251 unused uint32_t test_flags)
5252 {
5253 volatile test_func_t func;
5254 uint32_t* func_buf = get_rwx_area();
5255 volatile HWord_t res;
5256 volatile uint32_t flags, xer;
5257 int i, j, k, arg_step;
5258
5259 arg_step = (arg_list_size == 0) ? 7 : 3;
5260
5261 for (i=0; i<nb_iargs; i++) {
5262 for (j=0; j<nb_iargs; j++) {
5263 for (k=0; k<64; k+=arg_step) {
5264 /* Patch up the instruction */
5265 func = init_function( func_IN, func_buf );
5266 patch_op_imm(&func_buf[0], (((k & 0x1F)<<1) | ((k>>5)&1)), 5, 6);
5267
5268 r14 = iargs[i];
5269 r15 = iargs[j];
5270
5271 SET_CR_XER_ZERO;
5272 (*func)();
5273 GET_CR_XER(flags,xer);
5274 res = r17;
5275
5276 printf("%s %016llx, %016llx, %2d => %016llx (%08x %08x)\n",
5277 name, iargs[i], iargs[j], k, res, flags, xer);
5278 }
5279 if (verbose) printf("\n");
5280 }
5281 }
5282 }
5283
5284 static void rldi_cb (const char* name, test_func_t func_IN,
5285 unused uint32_t test_flags)
5286 {
5287 volatile test_func_t func;
5288 uint32_t* func_buf = get_rwx_area();
5289 volatile HWord_t res;
5290 volatile uint32_t flags, xer;
5291 int i, j, k, arg_step;
5292
5293 arg_step = (arg_list_size == 0) ? 7 : 3;
5294
5295 for (i=0; i<nb_iargs; i++) {
5296 for (j=0; j<64; j+=arg_step) { // SH
5297 for (k=0; k<64; k+=arg_step) { // MB|ME
5298 /* Patch up the instruction */
5299 func = init_function( func_IN, func_buf );
5300 _patch_op_imm(&func_buf[0], (j & 0x1F), 11, 5);
5301 _patch_op_imm(&func_buf[0], ((j>>5)&1), 1, 1);
5302 patch_op_imm(&func_buf[0], (((k & 0x1F)<<1) | ((k>>5)&1)), 5, 6);
5303
5304 r14 = iargs[i];
5305
5306 SET_CR_XER_ZERO;
5307 (*func)();
5308 GET_CR_XER(flags,xer);
5309 res = r17;
5310
5311 printf("%s %016llx, %2d, %2d => %016llx (%08x %08x)\n",
5312 name, iargs[i], j, k, res, flags, xer);
5313 }
5314 if (verbose) printf("\n");
5315 }
5316 }
5317 }
5318
5319 static void sradi_cb (const char* name, test_func_t func_IN,
5320 unused uint32_t test_flags)
5321 {
5322 volatile test_func_t func;
5323 uint32_t* func_buf = get_rwx_area();
5324 volatile HWord_t res;
5325 volatile uint32_t flags, xer;
5326 int i, j, arg_step;
5327
5328 arg_step = (arg_list_size == 0) ? 7 : 3;
5329
5330 for (i=0; i<nb_iargs; i++) {
5331 for (j=0; j<64; j+=arg_step) { // SH
5332 /* Patch up the instruction */
5333 func = init_function( func_IN, func_buf );
5334 _patch_op_imm(&func_buf[0], (j & 0x1F), 11, 5);
5335 patch_op_imm(&func_buf[0], ((j>>5)&1), 1, 1);
5336
5337 r14 = iargs[i];
5338
5339 SET_CR_XER_ZERO;
5340 (*func)();
5341 GET_CR_XER(flags,xer);
5342 res = r17;
5343
5344 printf("%s %016llx, %2d => %016llx (%08x %08x)\n",
5345 name, iargs[i], j, res, flags, xer);
5346 }
5347 if (verbose) printf("\n");
5348 }
5349 }
5350 #endif // #ifdef __powerpc64__
5351
5352
5353 typedef struct special_t special_t;
5354
5355 struct special_t {
5356 const char *name;
5357 void (*test_cb)(const char* name, test_func_t func,
5358 unused uint32_t test_flags);
5359 };
5360
5361 static void test_special (special_t *table,
5362 const char* name, test_func_t func,
5363 unused uint32_t test_flags)
5364 {
5365 const char *tmp;
5366 int i;
5367
5368 for (tmp = name; isspace(*tmp); tmp++)
5369 continue;
5370 for (i=0; table[i].name != NULL; i++) {
5371 #if 0
5372 fprintf(stderr, "look for handler for '%s' (%s)\n", name,
5373 table[i].name);
5374 #endif
5375 if (strcmp(table[i].name, tmp) == 0) {
5376 (*table[i].test_cb)(name, func, test_flags);
5377 return;
5378 }
5379 }
5380 fprintf(stderr, "ERROR: no test found for op '%s'\n", name);
5381 }
5382
5383 static special_t special_int_ops[] = {
5384 {
5385 "rlwimi", /* One register + 3 5 bits immediate arguments */
5386 &rlwi_cb,
5387 },
5388 {
5389 "rlwimi.", /* One register + 3 5 bits immediate arguments */
5390 &rlwi_cb,
5391 },
5392 {
5393 "rlwinm", /* One register + 3 5 bits immediate arguments */
5394 &rlwi_cb,
5395 },
5396 {
5397 "rlwinm.", /* One register + 3 5 bits immediate arguments */
5398 &rlwi_cb,
5399 },
5400 {
5401 "rlwnm", /* Two registers + 2 5 bits immediate arguments */
5402 &rlwnm_cb,
5403 },
5404 {
5405 "rlwnm.", /* Two registers + 2 5 bits immediate arguments */
5406 &rlwnm_cb,
5407 },
5408 {
5409 "srawi", /* One register + 1 5 bits immediate arguments */
5410 &srawi_cb,
5411 },
5412 {
5413 "srawi.", /* One register + 1 5 bits immediate arguments */
5414 &srawi_cb,
5415 },
5416 {
5417 "mcrf", /* 2 3 bits immediate arguments */
5418 &mcrf_cb,
5419 },
5420 #if 0
5421 {
5422 "mcrfs", /* 2 3 bits immediate arguments */
5423 &mcrfs_cb,
5424 },
5425 #endif
5426 {
5427 "mcrxr", /* 1 3 bits immediate argument */
5428 &mcrxr_cb,
5429 },
5430 {
5431 "mfcr", /* No arguments */
5432 &mfcr_cb,
5433 },
5434 {
5435 "mfspr", /* 1 10 bits immediate argument */
5436 &mfspr_cb,
5437 },
5438 #if 0
5439 { // Move from time base
5440 "mftb", /* 1 10 bits immediate arguments */
5441 &mftb_cb,
5442 },
5443 #endif
5444 {
5445 "mtcrf", /* One register + 1 8 bits immediate arguments */
5446 &mtcrf_cb,
5447 },
5448 {
5449 "mtspr", /* One register + 1 10 bits immediate arguments */
5450 &mtspr_cb,
5451 },
5452 #ifdef __powerpc64__
5453 {
5454 "rldcl", /* Two registers + 1 6 bit immediate argument */
5455 &rldc_cb,
5456 },
5457 {
5458 "rldcl.", /* Two registers + 1 6 bit immediate argument */
5459 &rldc_cb,
5460 },
5461 {
5462 "rldcr", /* Two registers + 1 6 bit immediate argument */
5463 &rldc_cb,
5464 },
5465 {
5466 "rldcr.", /* Two registers + 1 6 bit immediate argument */
5467 &rldc_cb,
5468 },
5469 {
5470 "rldic", /* One register + 2 6 bit immediate arguments */
5471 &rldi_cb,
5472 },
5473 {
5474 "rldic.", /* One register + 2 6 bit immediate arguments */
5475 &rldi_cb,
5476 },
5477 {
5478 "rldicl", /* One register + 2 6 bit immediate arguments */
5479 &rldi_cb,
5480 },
5481 {
5482 "rldicl.", /* One register + 2 6 bit immediate arguments */
5483 &rldi_cb,
5484 },
5485 {
5486 "rldicr", /* One register + 2 6 bit immediate arguments */
5487 &rldi_cb,
5488 },
5489 {
5490 "rldicr.", /* One register + 2 6 bit immediate arguments */
5491 &rldi_cb,
5492 },
5493 {
5494 "rldimi", /* One register + 2 6 bit immediate arguments */
5495 &rldi_cb,
5496 },
5497 {
5498 "rldimi.", /* One register + 2 6 bit immediate arguments */
5499 &rldi_cb,
5500 },
5501 {
5502 "sradi", /* One register + 1 6 bit immediate argument */
5503 &sradi_cb,
5504 },
5505 {
5506 "sradi.", /* One register + 1 6 bit immediate argument */
5507 &sradi_cb,
5508 },
5509 #endif // #ifdef __powerpc64__
5510 {
5511 NULL,
5512 NULL,
5513 },
5514 };
5515
5516 static void test_int_special (const char* name, test_func_t func,
5517 uint32_t test_flags)
5518 {
5519 test_special(special_int_ops, name, func, test_flags);
5520 }
5521
5522
5523 static void test_int_ld_one_reg_imm16 (const char* name,
5524 test_func_t func_IN,
5525 unused uint32_t test_flags)
5526 {
5527 volatile test_func_t func;
5528 uint32_t* func_buf = get_rwx_area();
5529 volatile HWord_t res, base;
5530 volatile uint32_t flags, xer;
5531 int i, offs, shift_offset = 0;
5532
5533 #ifdef __powerpc64__
5534 if (strstr(name, "lwa") || strstr(name, "ld") || strstr(name, "ldu"))
5535 shift_offset = 1;
5536 #endif
5537
5538 // +ve d
5539 base = (HWord_t)&iargs[0];
5540 for (i=0; i<nb_iargs; i++) {
5541 offs = (i == 0) ? i : (i * sizeof(HWord_t)) - 1;
5542
5543 /* Patch up the instruction */
5544 func = init_function( func_IN, func_buf );
5545 if (shift_offset)
5546 patch_op_imm(&func_buf[0], offs>>2, 2, 14);
5547 else
5548 patch_op_imm16(&func_buf[0], offs);
5549
5550 r14 = base;
5551
5552 SET_CR_XER_ZERO;
5553 (*func)();
5554 GET_CR_XER(flags,xer);
5555 res = r17;
5556
5557 #ifndef __powerpc64__
5558 printf("%s %2d, (%08x) => %08x, %2d (%08x %08x)\n",
5559 #else
5560 printf("%s %3d, (%016llx) => %016llx, %3lld (%08x %08x)\n",
5561 #endif
5562 name, offs, iargs[i], res, r14-base, flags, xer);
5563 }
5564 if (verbose) printf("\n");
5565
5566 // -ve d
5567 base = (HWord_t)&iargs[nb_iargs-1];
5568 for (i = 0; i > -nb_iargs; i--) {
5569 offs = (i * sizeof(HWord_t)) + 1;
5570
5571 /* Patch up the instruction */
5572 func = init_function( func, func_buf );
5573 patch_op_imm16(&func_buf[0], offs);
5574
5575 r14 = base;
5576
5577 SET_CR_XER_ZERO;
5578 (*func)();
5579 GET_CR_XER(flags,xer);
5580 res = r17;
5581
5582 #ifndef __powerpc64__
5583 printf("%s %2d, (%08x) => %08x, %2d (%08x %08x)\n",
5584 #else
5585 printf("%s %3d, (%016llx) => %016llx, %3lld (%08x %08x)\n",
5586 #endif
5587 name, offs, iargs[nb_iargs-1 + i], res, r14-base, flags, xer);
5588 }
5589 }
5590
5591 static void test_int_ld_two_regs (const char* name,
5592 test_func_t func,
5593 unused uint32_t test_flags)
5594 {
5595 volatile HWord_t res, base;
5596 volatile uint32_t flags, xer;
5597 int i, offs;
5598
5599 // +ve d
5600 base = (HWord_t)&iargs[0];
5601 for (i=0; i<nb_iargs; i++) {
5602 offs = i * sizeof(HWord_t);
5603 r14 = base;
5604 r15 = offs;
5605
5606 SET_CR_XER_ZERO;
5607 (*func)();
5608 GET_CR_XER(flags,xer);
5609 res = r17;
5610
5611 #ifndef __powerpc64__
5612 printf("%s %d (%08x) => %08x, %d (%08x %08x)\n",
5613 #else
5614 printf("%s %3d, (%016llx) => %016llx, %2lld (%08x %08x)\n",
5615 #endif
5616 name, offs, iargs[i], res, r14-base, flags, xer);
5617 }
5618 }
5619
5620 static void test_int_st_two_regs_imm16 (const char* name,
5621 test_func_t func_IN,
5622 unused uint32_t test_flags)
5623 {
5624 volatile test_func_t func;
5625 uint32_t* func_buf = get_rwx_area();
5626 volatile uint32_t flags, xer;
5627 int i, offs, k;
5628 HWord_t *iargs_priv, base;
5629
5630 // private iargs table to store to
5631 iargs_priv = malloc(nb_iargs * sizeof(HWord_t));
5632
5633 // +ve d
5634 base = (HWord_t)&iargs_priv[0];
5635 for (i=0; i<nb_iargs; i++) {
5636 for (k=0; k<nb_iargs; k++) // clear array
5637 iargs_priv[k] = 0;
5638
5639 offs = i * sizeof(HWord_t);
5640
5641 /* Patch up the instruction */
5642 func = init_function( func_IN, func_buf );
5643 patch_op_imm16(&func_buf[0], offs);
5644
5645 r14 = iargs[i]; // read from iargs
5646 r15 = base; // store to r15 + offs
5647
5648 SET_CR_XER_ZERO;
5649 (*func)();
5650 GET_CR_XER(flags,xer);
5651
5652 #ifndef __powerpc64__
5653 printf("%s %08x, %2d => %08x, %2d (%08x %08x)\n",
5654 #else
5655 printf("%s %016llx, %3d => %016llx, %3lld (%08x %08x)\n",
5656 #endif
5657 name, iargs[i], offs, iargs_priv[i], r15-base, flags, xer);
5658 }
5659 if (verbose) printf("\n");
5660
5661 // -ve d
5662 base = (HWord_t)&iargs_priv[nb_iargs-1];
5663 for (i = -nb_iargs+1; i<=0; i++) {
5664 for (k=0; k<nb_iargs; k++) // clear array
5665 iargs_priv[k] = 0;
5666
5667 offs = i * sizeof(HWord_t);
5668
5669 /* Patch up the instruction */
5670 func = init_function( func, func_buf );
5671 patch_op_imm16(&func_buf[0], offs);
5672
5673 r14 = iargs[nb_iargs-1+i]; // read from iargs
5674 r15 = base; // store to r15 + offs
5675
5676 SET_CR_XER_ZERO;
5677 (*func)();
5678 GET_CR_XER(flags,xer);
5679
5680 #ifndef __powerpc64__
5681 printf("%s %08x, %2d => %08x, %2d (%08x %08x)\n",
5682 #else
5683 printf("%s %016llx, %3d => %016llx, %3lld (%08x %08x)\n",
5684 #endif
5685 name, iargs[nb_iargs-1+i], offs, iargs_priv[nb_iargs-1+i],
5686 r15-base, flags, xer);
5687 }
5688 free(iargs_priv);
5689 }
5690
5691 static void test_int_st_three_regs (const char* name,
5692 test_func_t func,
5693 unused uint32_t test_flags)
5694 {
5695 volatile uint32_t flags, xer;
5696 int i, offs, k;
5697 HWord_t *iargs_priv, base;
5698
5699 // private iargs table to store to
5700 iargs_priv = malloc(nb_iargs * sizeof(HWord_t));
5701
5702 base = (HWord_t)&iargs_priv[0];
5703 for (i=0; i<nb_iargs; i++) {
5704 for (k=0; k<nb_iargs; k++) // clear array
5705 iargs_priv[k] = 0;
5706
5707 offs = i * sizeof(HWord_t);
5708 r14 = iargs[i]; // read from iargs
5709 r15 = base; // store to r15 + offs
5710 r16 = offs;
5711
5712 SET_CR_XER_ZERO;
5713 (*func)();
5714 GET_CR_XER(flags,xer);
5715
5716 #ifndef __powerpc64__
5717 printf("%s %08x, %d => %08x, %d (%08x %08x)\n",
5718 #else
5719 printf("%s %016llx, %3d => %016llx, %2lld (%08x %08x)\n",
5720 #endif
5721 name, iargs[i], offs, iargs_priv[i], r15-base, flags, xer);
5722 }
5723 free(iargs_priv);
5724 }
5725
5726
5727 /* Used in do_tests, indexed by flags->nb_args
5728 Elements correspond to enum test_flags::num args
5729 */
5730 static test_loop_t int_loops[] = {
5731 &test_int_one_arg,
5732 &test_int_two_args,
5733 &test_int_three_args,
5734 &test_int_two_args,
5735 &test_int_one_reg_imm16,
5736 &test_int_one_reg_imm16,
5737 &test_int_special,
5738 &test_int_ld_one_reg_imm16,
5739 &test_int_ld_two_regs,
5740 &test_int_st_two_regs_imm16,
5741 &test_int_st_three_regs,
5742 };
5743
5744 static void test_dcbt_ops (const char* name, test_func_t func,
5745 unused uint32_t test_flags)
5746 {
5747 unsigned long * data = (unsigned long *)malloc(4096 * sizeof(unsigned long));
5748 HWord_t base;
5749
5750 base = (HWord_t)data;
5751 size_t offs = 100 * sizeof(unsigned long); // some arbitrary offset)
5752
5753 r17 = base;
5754 r14 = offs;
5755
5756 (*func)();
5757
5758 printf("%s with various hint values completes with no exceptions\n", name);
5759 free(data);
5760 }
5761
5762 static test_loop_t misc_loops[] = {
5763 &test_dcbt_ops,
5764 };
5765
5766 #if !defined (NO_FLOAT)
5767 static void test_float_three_args (const char* name, test_func_t func,
5768 unused uint32_t test_flags)
5769 {
5770 double res;
5771 uint64_t u0, u1, u2, ur;
5772 volatile uint32_t flags;
5773 int i, j, k;
5774
5775 /* Note: using nb_normal_fargs:
5776 - not testing special values for these insns
5777 */
5778 for (i=0; i<nb_normal_fargs; i+=3) {
5779 for (j=0; j<nb_normal_fargs; j+=5) {
5780 for (k=0; k<nb_normal_fargs; k+=7) {
5781 u0 = *(uint64_t *)(&fargs[i]);
5782 u1 = *(uint64_t *)(&fargs[j]);
5783 u2 = *(uint64_t *)(&fargs[k]);
5784 f14 = fargs[i];
5785 f15 = fargs[j];
5786 f16 = fargs[k];
5787
5788 SET_FPSCR_ZERO;
5789 SET_CR_XER_ZERO;
5790 (*func)();
5791 GET_CR(flags);
5792 res = f17;
5793 ur = *(uint64_t *)(&res);
5794
5795 /* Note: zapping the bottom byte of the result,
5796 as vex's accuracy isn't perfect */
5797 ur &= 0xFFFFFFFFFFFFFF00ULL;
5798
5799 #ifndef __powerpc64__
5800 printf("%s %016llx, %016llx, %016llx => %016llx",
5801 #else
5802 printf("%s %016llx, %016llx, %016llx => %016llx",
5803 #endif
5804 name, u0, u1, u2, ur);
5805 #if defined TEST_FLOAT_FLAGS
5806 printf(" (%08x)", flags);
5807 #endif
5808 printf("\n");
5809 }
5810 if (verbose) printf("\n");
5811 }
5812 }
5813 }
5814
5815 static void test_float_two_args (const char* name, test_func_t func,
5816 unused uint32_t test_flags)
5817 {
5818 double res;
5819 uint64_t u0, u1, ur;
5820 volatile uint32_t flags;
5821 int i, j;
5822
5823 for (i=0; i<nb_fargs; i+=3) {
5824 for (j=0; j<nb_fargs; j+=5) {
5825 u0 = *(uint64_t *)(&fargs[i]);
5826 u1 = *(uint64_t *)(&fargs[j]);
5827 f14 = fargs[i];
5828 f15 = fargs[j];
5829
5830 SET_FPSCR_ZERO;
5831 SET_CR_XER_ZERO;
5832 (*func)();
5833 GET_CR(flags);
5834 res = f17;
5835 ur = *(uint64_t *)(&res);
5836
5837 #ifndef __powerpc64__
5838 printf("%s %016llx, %016llx => %016llx",
5839 #else
5840 printf("%s %016llx, %016llx => %016llx",
5841 #endif
5842 name, u0, u1, ur);
5843 #if defined TEST_FLOAT_FLAGS
5844 printf(" (%08x)", flags);
5845 #endif
5846 printf("\n");
5847 }
5848 if (verbose) printf("\n");
5849 }
5850 }
5851
5852 static void test_float_one_arg (const char* name, test_func_t func,
5853 unused uint32_t test_flags)
5854 {
5855 double res;
5856 uint64_t u0, ur;
5857 volatile uint32_t flags;
5858 int i;
5859 unsigned zap_hi_32bits, zap_lo_44bits, zap_lo_47bits;
5860
5861 /* if we're testing fctiw or fctiwz, zap the hi 32bits,
5862 as they're undefined */
5863 zap_hi_32bits = strstr(name, " fctiw") != NULL ? 1 : 0;
5864 zap_lo_44bits = strstr(name, " fres") != NULL ? 1 : 0;
5865 zap_lo_47bits = strstr(name, " frsqrte") != NULL ? 1 : 0;
5866
5867 assert(zap_hi_32bits + zap_lo_44bits + zap_lo_47bits <= 1);
5868
5869 for (i=0; i<nb_fargs; i++) {
5870 u0 = *(uint64_t *)(&fargs[i]);
5871 f14 = fargs[i];
5872
5873 SET_FPSCR_ZERO;
5874 SET_CR_XER_ZERO;
5875 (*func)();
5876 GET_CR(flags);
5877 res = f17;
5878 ur = *(uint64_t *)(&res);
5879
5880 if (strstr(name, " frsqrte") != NULL)
5881 /* The 32-bit frsqrte instruction is the Floatig Reciprical Square
5882 * Root Estimate instruction. The precision of the estimate will
5883 * vary from Proceesor implementation. The approximation varies in
5884 * bottom two bytes of the 32-bit result.
5885 */
5886 ur &= 0xFFFF000000000000ULL;
5887
5888 if (zap_hi_32bits)
5889 ur &= 0x00000000FFFFFFFFULL;
5890 if (zap_lo_44bits)
5891 ur &= 0xFFFFF00000000000ULL;
5892 if (zap_lo_47bits)
5893 ur &= 0xFFFF800000000000ULL;
5894
5895 #ifndef __powerpc64__
5896 printf("%s %016llx => %016llx",
5897 #else
5898 printf("%s %016llx => %016llx",
5899 #endif
5900 name, u0, ur);
5901 #if defined TEST_FLOAT_FLAGS
5902 printf(" (%08x)", flags);
5903 #endif
5904 printf("\n");
5905 }
5906 }
5907
5908 /* Special test cases for:
5909 * mffs
5910 * mtfsb0
5911 * mtfsb1
5912 */
5913 static special_t special_float_ops[] = {
5914 #if 0
5915 {
5916 "mffs", /* One 5 bits immediate argument */
5917 &mffs_cb,
5918 },
5919 {
5920 "mffs.", /* One 5 bits immediate argument */
5921 &mffs_cb,
5922 },
5923 {
5924 "mtfsb0", /* One 5 bits immediate argument */
5925 &mffs_cb,
5926 },
5927 {
5928 "mtfsb0.", /* One 5 bits immediate argument */
5929 &mffs_cb,
5930 },
5931 {
5932 "mtfsb1", /* One 5 bits immediate argument */
5933 &mffs_cb,
5934 },
5935 {
5936 "mtfsb1.", /* One 5 bits immediate argument */
5937 &mffs_cb,
5938 },
5939 {
5940 "mtfsf", /* One register + 1 8 bits immediate argument */
5941 &mtfsf_cb,
5942 },
5943 {
5944 "mtfsf.", /* One register + 1 8 bits immediate argument */
5945 &mtfsf_cb,
5946 },
5947 {
5948 "mtfsfi", /* One 5 bits argument + 1 5 bits argument */
5949 &mtfsfi_cb,
5950 },
5951 {
5952 "mtfsfi.", /* One 5 bits argument + 1 5 bits argument */
5953 &mtfsfi_cb,
5954 },
5955 #endif
5956 {
5957 NULL,
5958 NULL,
5959 },
5960 };
5961
5962 static void test_float_special (const char* name, test_func_t func,
5963 uint32_t test_flags)
5964 {
5965 test_special(special_float_ops, name, func, test_flags);
5966 }
5967
5968
5969 static void test_float_ld_one_reg_imm16 (const char* name,
5970 test_func_t func_IN,
5971 unused uint32_t test_flags)
5972 {
5973 volatile test_func_t func;
5974 uint32_t* func_buf = get_rwx_area();
5975 HWord_t base;
5976 volatile uint32_t flags, xer;
5977 volatile double src, res;
5978 int i;
5979 uint16_t offs;
5980
5981 /* offset within [1-nb_fargs:nb_fargs] */
5982 for (i=1-nb_fargs; i<nb_fargs; i++) {
5983 offs = i * 8; // offset = i * sizeof(double)
5984 if (i < 0) {
5985 src = fargs[nb_fargs-1 + i];
5986 base = (HWord_t)&fargs[nb_fargs-1];
5987 } else {
5988 src = fargs[i];
5989 base = (HWord_t)&fargs[0];
5990 }
5991
5992 /* Patch up the instruction */
5993 func = init_function( func_IN, func_buf );
5994 patch_op_imm16(&func_buf[0], offs);
5995
5996 // load from fargs[idx] => r14 + offs
5997 r14 = base;
5998
5999 SET_CR_XER_ZERO;
6000 (*func)();
6001 GET_CR_XER(flags,xer);
6002 res = f17;
6003
6004 #ifndef __powerpc64__
6005 printf("%s %016llx, %4d => %016llx, %4d",
6006 #else
6007 printf("%s %016llx, %4d => %016llx, %4lld",
6008 #endif
6009 name, double_to_bits(src), offs,
6010 double_to_bits(res), r14-base);
6011 #if defined TEST_FLOAT_FLAGS
6012 printf(" (%08x %08x)", flags, xer);
6013 #endif
6014 printf("\n");
6015 }
6016 if (verbose) printf("\n");
6017 }
6018
6019 static void test_float_ld_two_regs (const char* name,
6020 test_func_t func,
6021 unused uint32_t test_flags)
6022 {
6023 volatile HWord_t base;
6024 volatile uint32_t flags, xer;
6025 volatile double src, res;
6026 int i, offs;
6027
6028 /* offset within [1-nb_fargs:nb_fargs] */
6029 for (i=1-nb_fargs; i<nb_fargs; i++) {
6030 offs = i * 8; // offset = i * sizeof(double)
6031 if (i < 0) { // base reg = start of array
6032 src = fargs[nb_fargs-1 + i];
6033 base = (HWord_t)&fargs[nb_fargs-1];
6034 } else {
6035 src = fargs[i];
6036 base = (HWord_t)&fargs[0];
6037 }
6038
6039 r14 = base;
6040 r15 = offs;
6041
6042 SET_CR_XER_ZERO;
6043 (*func)();
6044 GET_CR_XER(flags,xer);
6045 res = f17;
6046
6047 #ifndef __powerpc64__
6048 printf("%s %016llx, %4d => %016llx, %4d",
6049 #else
6050 printf("%s %016llx, %4lld => %016llx, %4lld",
6051 #endif
6052 name, double_to_bits(src), r15/*offs*/,
6053 double_to_bits(res), r14-base);
6054 #if defined TEST_FLOAT_FLAGS
6055 printf(" (%08x %08x)", flags, xer);
6056 #endif
6057 printf("\n");
6058 }
6059 }
6060
6061 static void test_float_st_two_regs_imm16 (const char* name,
6062 test_func_t func_IN,
6063 unused uint32_t test_flags)
6064 {
6065 volatile test_func_t func;
6066 uint32_t* func_buf = get_rwx_area();
6067 HWord_t base;
6068 volatile uint32_t flags, xer;
6069 double src, *p_dst;
6070 int i, offs;
6071 double *fargs_priv;
6072 int nb_tmp_fargs = nb_fargs;
6073
6074
6075 /* if we're storing an fp single-precision, don't want nans
6076 - the vex implementation doesn't like them (yet)
6077 Note: This is actually a bigger problem: the vex implementation
6078 rounds these insns twice. This leads to many rounding errors.
6079 For the small fargs set, however, this doesn't show up.
6080 */
6081 if (strstr(name, "stfs") != NULL)
6082 nb_tmp_fargs = nb_normal_fargs;
6083
6084
6085 // private fargs table to store to
6086 fargs_priv = malloc(nb_tmp_fargs * sizeof(double));
6087
6088 /* offset within [1-nb_tmp_fargs:nb_tmp_fargs] */
6089 for (i=1-nb_tmp_fargs; i<nb_tmp_fargs; i++) {
6090 offs = i * 8; // offset = i * sizeof(double)
6091 if (i < 0) {
6092 src = fargs [nb_tmp_fargs-1 + i];
6093 p_dst = &fargs_priv[nb_tmp_fargs-1 + i];
6094 base = (HWord_t)&fargs_priv[nb_tmp_fargs-1];
6095 } else {
6096 src = fargs [i];
6097 p_dst = &fargs_priv[i];
6098 base = (HWord_t)&fargs_priv[0];
6099 }
6100 *p_dst = 0; // clear dst
6101
6102 /* Patch up the instruction */
6103 func = init_function( func_IN, func_buf );
6104 patch_op_imm16(&func_buf[0], offs);
6105
6106 // read from fargs[idx] => f14
6107 // store to fargs_priv[idx] => r15 + offs
6108 f14 = src;
6109 r15 = base;
6110
6111 SET_CR_XER_ZERO;
6112 (*func)();
6113 GET_CR_XER(flags,xer);
6114
6115 #ifndef __powerpc64__
6116 printf("%s %016llx, %4d => %016llx, %4d",
6117 #else
6118 printf("%s %016llx, %4d => %016llx, %4lld",
6119 #endif
6120 name, double_to_bits(src), offs,
6121 double_to_bits(*p_dst), r15-base);
6122 #if defined TEST_FLOAT_FLAGS
6123 printf(" (%08x %08x)", flags, xer);
6124 #endif
6125 printf("\n");
6126 }
6127 free(fargs_priv);
6128 }
6129
6130 static void test_float_st_three_regs (const char* name,
6131 test_func_t func,
6132 unused uint32_t test_flags)
6133 {
6134 volatile HWord_t base;
6135 volatile uint32_t flags, xer;
6136 double src, *p_dst;
6137 int i, offs;
6138 double *fargs_priv;
6139 int nb_tmp_fargs = nb_fargs;
6140
6141
6142 /* if we're storing an fp single-precision, don't want nans
6143 - the vex implementation doesn't like them (yet)
6144 Note: This is actually a bigger problem: the vex implementation
6145 rounds these insns twice. This leads to many rounding errors.
6146 For the small fargs set, however, this doesn't show up.
6147 */
6148 if (strstr(name, "stfs") != NULL) // stfs(u)(x)
6149 nb_tmp_fargs = nb_normal_fargs;
6150
6151
6152 // private fargs table to store to
6153 fargs_priv = malloc(nb_tmp_fargs * sizeof(double));
6154
6155 // /* offset within [1-nb_tmp_fargs:nb_tmp_fargs] */
6156 // for (i=1-nb_tmp_fargs; i<nb_tmp_fargs; i++) {
6157 for (i=0; i<nb_tmp_fargs; i++) {
6158 offs = i * 8; // offset = i * sizeof(double)
6159 if (i < 0) {
6160 src = fargs [nb_tmp_fargs-1 + i];
6161 p_dst = &fargs_priv[nb_tmp_fargs-1 + i];
6162 base = (HWord_t)&fargs_priv[nb_tmp_fargs-1];
6163 } else {
6164 src = fargs [i];
6165 p_dst = &fargs_priv[i];
6166 base = (HWord_t)&fargs_priv[0];
6167 }
6168 *p_dst = 0; // clear dst
6169
6170 f14 = src; // read from fargs
6171 r15 = base; // store to r15 + offs
6172 r16 = offs;
6173
6174 SET_CR_XER_ZERO;
6175 (*func)();
6176 GET_CR_XER(flags,xer);
6177
6178 #ifndef __powerpc64__
6179 printf("%s %016llx, %4d => %016llx, %4d",
6180 #else
6181 printf("%s %016llx, %4lld => %016llx, %4lld",
6182 #endif
6183 name, double_to_bits(src), r16/*offs*/,
6184 double_to_bits(*p_dst), r15-base);
6185 #if defined TEST_FLOAT_FLAGS
6186 printf(" (%08x %08x)", flags, xer);
6187 #endif
6188 printf("\n");
6189
6190
6191 #if 0
6192 // print double precision result
6193 #ifndef __powerpc64__
6194 printf("%s %016llx (%014e), %4d => %016llx (%014e), %08x (%08x %08x)\n",
6195 #else
6196 printf("%s %016llx (%014e), %4d => %016llx (%014e), %08x (%08x %08x)\n",
6197 #endif
6198 name, double_to_bits(src), src, offs,
6199 double_to_bits(*p_dst), *p_dst, r15, flags, xer);
6200
6201 // print single precision result
6202 #ifndef __powerpc64__
6203 printf("%s %016llx (%014e), %4d => %08x (%f), %08x (%08x %08x)\n",
6204 #else
6205 printf("%s %016llx (%014e), %4d => %08x (%f), %08x (%08x %08x)\n",
6206 #endif
6207 name, double_to_bits(src), src, offs,
6208 (uint32_t)(double_to_bits(*p_dst) >> 32),
6209 bits_to_float( (uint32_t)(double_to_bits(*p_dst) >> 32) ),
6210 r15, flags, xer);
6211 #endif
6212 }
6213 free(fargs_priv);
6214 }
6215
6216
6217 /* Used in do_tests, indexed by flags->nb_args
6218 Elements correspond to enum test_flags::num args
6219 */
6220 static test_loop_t float_loops[] = {
6221 &test_float_one_arg,
6222 &test_float_two_args,
6223 &test_float_three_args,
6224 &test_float_two_args,
6225 NULL,
6226 NULL,
6227 &test_float_special,
6228 &test_float_ld_one_reg_imm16,
6229 &test_float_ld_two_regs,
6230 &test_float_st_two_regs_imm16,
6231 &test_float_st_three_regs,
6232 };
6233 #endif /* !defined (NO_FLOAT) */
6234
6235
6236 #if defined (HAS_ALTIVEC)
6237
6238 /* Ref: vector insns to test setting CR, VSCR:
6239 volatile vector unsigned int v1 =
6240 // (vector unsigned int){ 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF };
6241 (vector unsigned int){ 0x80808080,0x80808080,0x80808080,0x80808080 };
6242 volatile vector unsigned int v2 =
6243 // (vector unsigned int){ 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF };
6244 (vector unsigned int){ 0x01010101,0x01010101,0x01010101,0x01010101 };
6245 //__asm__ __volatile__ ("vcmpequw. 31,%0,%1" : : "v" (v1), "v" (v2)); // sets CR[6]
6246 //__asm__ __volatile__ ("vpkswss 31,%0,%1" : : "v" (v1), "v" (v2)); // sets VSCR[SAT]
6247 __asm__ __volatile__ ("vsubsbs 31,%0,%1" : : "v" (v1), "v" (v2)); // sets VSCR[SAT]
6248 */
6249
6250 //#define DEFAULT_VSCR 0x00010000
6251 #define DEFAULT_VSCR 0x0
6252
6253 static void test_av_int_one_arg (const char* name, test_func_t func,
6254 unused uint32_t test_flags)
6255 {
6256 volatile uint32_t flags, tmpcr;
6257 volatile vector unsigned int tmpvscr;
6258 volatile vector unsigned int vec_in, vec_out, vscr;
6259 unsigned int *src, *dst;
6260 int i;
6261 #if defined TEST_VSCR_SAT
6262 unsigned int* p_vscr;
6263 #endif
6264
6265 for (i=0; i<nb_viargs; i++) {
6266 /* Save flags */
6267 __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
6268 __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
6269
6270 vec_in = (vector unsigned int)viargs[i];
6271 vec_out = (vector unsigned int){ 0,0,0,0 };
6272
6273 // reset VSCR and CR
6274 vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
6275 flags = 0;
6276 __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
6277 __asm__ __volatile__ ("mtcr %0" : : "r" (flags));
6278
6279 // load input -> r14
6280 __asm__ __volatile__ ("vor 14,%0,%0" : : "v" (vec_in));
6281
6282 // do stuff
6283 (*func)();
6284
6285 // retrieve output <- r17
6286 __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
6287
6288 // get CR,VSCR flags
6289 __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
6290 __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
6291
6292 /* Restore flags */
6293 __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
6294 __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
6295
6296 src = (unsigned int*)&vec_in;
6297 dst = (unsigned int*)&vec_out;
6298
6299 printf("%s: %08x %08x %08x %08x\n", name,
6300 src[0], src[1], src[2], src[3]);
6301 printf("%s: => %08x %08x %08x %08x ", name,
6302 dst[0], dst[1], dst[2], dst[3]);
6303 #if defined TEST_VSCR_SAT
6304 p_vscr = (unsigned int*)&vscr;
6305 printf("(%08x, %08x)\n", flags, p_vscr[3]);
6306 #else
6307 printf("(%08x)\n", flags);
6308 #endif
6309 }
6310 }
6311
6312 static void test_av_int_two_args (const char* name, test_func_t func,
6313 unused uint32_t test_flags)
6314 {
6315 volatile uint32_t flags, tmpcr;
6316 volatile vector unsigned int tmpvscr;
6317 volatile vector unsigned int vec_in1, vec_in2, vec_out, vscr;
6318 unsigned int *src1, *src2, *dst;
6319 int i,j;
6320 #if defined TEST_VSCR_SAT
6321 unsigned int* p_vscr;
6322 #endif
6323
6324 for (i=0; i<nb_viargs; i++) {
6325 vec_in1 = (vector unsigned int)viargs[i];
6326 for (j=0; j<nb_viargs; j++) {
6327 vec_in2 = (vector unsigned int)viargs[j];
6328 vec_out = (vector unsigned int){ 0,0,0,0 };
6329
6330 /* Save flags */
6331 __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
6332 __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
6333
6334 // reset VSCR and CR
6335 vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
6336 flags = 0;
6337 __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
6338 __asm__ __volatile__ ("mtcr %0" : : "r" (flags));
6339
6340 // load inputs -> r14,r15
6341 __asm__ __volatile__ ("vor 14,%0,%0" : : "v" (vec_in1));
6342 __asm__ __volatile__ ("vor 15,%0,%0" : : "v" (vec_in2));
6343
6344 // do stuff
6345 (*func)();
6346
6347 // retrieve output <- r17
6348 __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
6349
6350 // get CR,VSCR flags
6351 __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
6352 __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
6353
6354 /* Restore flags */
6355 __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
6356 __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
6357
6358 src1 = (unsigned int*)&vec_in1;
6359 src2 = (unsigned int*)&vec_in2;
6360 dst = (unsigned int*)&vec_out;
6361
6362 printf("%s: ", name);
6363 printf("%08x%08x%08x%08x, ", src1[0], src1[1], src1[2], src1[3]);
6364 printf("%08x%08x%08x%08x\n", src2[0], src2[1], src2[2], src2[3]);
6365 printf("%s: => %08x %08x %08x %08x ", name,
6366 dst[0], dst[1], dst[2], dst[3]);
6367 #if defined TEST_VSCR_SAT
6368 p_vscr = (unsigned int*)&vscr;
6369 printf("(%08x, %08x)\n", flags, p_vscr[3]);
6370 #else
6371 printf("(%08x)\n", flags);
6372 #endif
6373 }
6374 if (verbose) printf("\n");
6375 }
6376 }
6377
6378 static void test_av_int_three_args (const char* name, test_func_t func,
6379 unused uint32_t test_flags)
6380 {
6381 volatile uint32_t flags, tmpcr;
6382 volatile vector unsigned int tmpvscr;
6383 volatile vector unsigned int vec_in1, vec_in2, vec_in3, vec_out, vscr;
6384 unsigned int *src1, *src2, *src3, *dst;
6385 int i,j,k;
6386 #if defined TEST_VSCR_SAT
6387 unsigned int* p_vscr;
6388 #endif
6389
6390 for (i=0; i<nb_viargs; i++) {
6391 vec_in1 = (vector unsigned int)viargs[i];
6392 for (j=0; j<nb_viargs; j++) {
6393 vec_in2 = (vector unsigned int)viargs[j];
6394 for (k=0; k<nb_viargs; k++) {
6395 vec_in3 = (vector unsigned int)viargs[k];
6396 vec_out = (vector unsigned int){ 0,0,0,0 };
6397
6398 /* Save flags */
6399 __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
6400 __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
6401
6402 // reset VSCR and CR
6403 vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
6404 flags = 0;
6405 __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
6406 __asm__ __volatile__ ("mtcr %0" : : "r" (flags));
6407
6408 // load inputs -> r14,r15,r16
6409 __asm__ __volatile__ ("vor 14,%0,%0" : : "v" (vec_in1));
6410 __asm__ __volatile__ ("vor 15,%0,%0" : : "v" (vec_in2));
6411 __asm__ __volatile__ ("vor 16,%0,%0" : : "v" (vec_in3));
6412
6413 // do stuff
6414 (*func)();
6415
6416 // retrieve output <- r17
6417 __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
6418
6419 // get CR,VSCR flags
6420 __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
6421 __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
6422
6423 /* Restore flags */
6424 __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
6425 __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
6426
6427 src1 = (unsigned int*)&vec_in1;
6428 src2 = (unsigned int*)&vec_in2;
6429 src3 = (unsigned int*)&vec_in3;
6430 dst = (unsigned int*)&vec_out;
6431
6432 printf("%s: %08x%08x%08x%08x, %08x%08x%08x%08x, %08x%08x%08x%08x\n", name,
6433 src1[0], src1[1], src1[2], src1[3],
6434 src2[0], src2[1], src2[2], src2[3],
6435 src3[0], src3[1], src3[2], src3[3]);
6436
6437 printf("%s: => %08x%08x%08x%08x ", name,
6438 dst[0], dst[1], dst[2], dst[3]);
6439 #if defined TEST_VSCR_SAT
6440 p_vscr = (unsigned int*)&vscr;
6441 printf("(%08x, %08x)\n", flags, p_vscr[3]);
6442 #else
6443 printf("(%08x)\n", flags);
6444 #endif
6445 }
6446 if (verbose) printf("\n");
6447 }
6448 }
6449 }
6450
6451
6452 static void vs128_cb (const char* name, test_func_t func,
6453 unused uint32_t test_flags)
6454 {
6455 volatile uint32_t flags, tmpcr;
6456 volatile vector unsigned int tmpvscr;
6457 volatile vector unsigned char vec_shft;
6458 volatile vector unsigned int vec_in1, vec_out, vscr;
6459 unsigned int *src1, *src2, *dst;
6460 int i,j;
6461 #if defined TEST_VSCR_SAT
6462 unsigned int* p_vscr;
6463 #endif
6464
6465 for (i=0; i<nb_viargs; i++) {
6466 vec_in1 = (vector unsigned int)viargs[i];
6467 for (j=0; j<8; j++) {
6468 /* low-order 3bits of every byte must be the same for the shift vector */
6469 vec_shft = (vector unsigned char) { j,j,j,j, j,j,j,j, j,j,j,j, j,j,j,j };
6470 vec_out = (vector unsigned int){ 0,0,0,0 };
6471
6472 /* Save flags */
6473 __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
6474 __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
6475
6476 // reset VSCR and CR
6477 vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
6478 flags = 0;
6479 __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
6480 __asm__ __volatile__ ("mtcr %0" : : "r" (flags));
6481
6482 // load inputs -> r14,r15
6483 __asm__ __volatile__ ("vor 14,%0,%0" : : "v" (vec_in1));
6484 __asm__ __volatile__ ("vor 15,%0,%0" : : "v" (vec_shft));
6485
6486 // do stuff
6487 (*func)();
6488
6489 // retrieve output <- r17
6490 __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
6491
6492 // get CR,VSCR flags
6493 __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
6494 __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
6495
6496 /* Restore flags */
6497 __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
6498 __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
6499
6500 src1 = (unsigned int*)&vec_in1;
6501 src2 = (unsigned int*)&vec_shft;
6502 dst = (unsigned int*)&vec_out;
6503
6504 printf("%s: ", name);
6505 printf("%08x%08x%08x%08x, ", src1[0], src1[1], src1[2], src1[3]);
6506 printf("%08x%08x%08x%08x\n", src2[0], src2[1], src2[2], src2[3]);
6507
6508 printf("%s: => %08x %08x %08x %08x ", name,
6509 dst[0], dst[1], dst[2], dst[3]);
6510 #if defined TEST_VSCR_SAT
6511 p_vscr = (unsigned int*)&vscr;
6512 printf("(%08x, %08x)\n", flags, p_vscr[3]);
6513 #else
6514 printf("(%08x)\n", flags);
6515 #endif
6516 }
6517 if (verbose) printf("\n");
6518 }
6519 }
6520
6521 static void vsplt_cb (const char* name, test_func_t func_IN,
6522 unused uint32_t test_flags)
6523 {
6524 volatile test_func_t func;
6525 uint32_t* func_buf = get_rwx_area();
6526 volatile uint32_t flags, tmpcr;
6527 volatile vector unsigned int tmpvscr;
6528 volatile vector unsigned int vec_in1, vec_out, vscr;
6529 unsigned int *src1, *dst;
6530 int i,j;
6531 #if defined TEST_VSCR_SAT
6532 unsigned int* p_vscr;
6533 #endif
6534
6535 for (i=0; i<nb_viargs; i++) {
6536 vec_in1 = (vector unsigned int)viargs[i];
6537
6538 for (j=0; j<16; j+=3) {
6539 vec_out = (vector unsigned int){ 0,0,0,0 };
6540
6541 /* Patch up the instruction */
6542 func = init_function( func_IN, func_buf );
6543 patch_op_imm(&func_buf[0], j, 16, 5);
6544
6545 /* Save flags */
6546 __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
6547 __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
6548
6549 // reset VSCR and CR
6550 vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
6551 flags = 0;
6552 __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
6553 __asm__ __volatile__ ("mtcr %0" : : "r" (flags));
6554
6555 // load input -> r14
6556 __asm__ __volatile__ ("vor 14,%0,%0" : : "v" (vec_in1));
6557
6558 // do stuff
6559 (*func)();
6560
6561 // retrieve output <- r17
6562 __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
6563
6564 // get CR,VSCR flags
6565 __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
6566 __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
6567
6568 /* Restore flags */
6569 __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
6570 __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
6571
6572 src1 = (unsigned int*)&vec_in1;
6573 dst = (unsigned int*)&vec_out;
6574
6575 printf("%s: ", name);
6576 printf("%08x %08x %08x %08x, %u\n", src1[0], src1[1], src1[2], src1[3], j);
6577
6578 printf("%s: => %08x %08x %08x %08x ", name,
6579 dst[0], dst[1], dst[2], dst[3]);
6580 #if defined TEST_VSCR_SAT
6581 p_vscr = (unsigned int*)&vscr;
6582 printf("(%08x, %08x)\n", flags, p_vscr[3]);
6583 #else
6584 printf("(%08x)\n", flags);
6585 #endif
6586 }
6587 if (verbose) printf("\n");
6588 }
6589 }
6590
6591 static void vspltis_cb (const char* name, test_func_t func_IN,
6592 unused uint32_t test_flags)
6593 {
6594 volatile test_func_t func;
6595 uint32_t* func_buf = get_rwx_area();
6596 volatile uint32_t flags, tmpcr;
6597 volatile vector unsigned int tmpvscr;
6598 volatile vector unsigned int vec_out, vscr;
6599 unsigned int *dst;
6600 int i;
6601 #if defined TEST_VSCR_SAT
6602 unsigned int* p_vscr;
6603 #endif
6604
6605 for (i=0; i<32; i++) {
6606 vec_out = (vector unsigned int){ 0,0,0,0 };
6607
6608 /* Patch up the instruction */
6609 func = init_function( func_IN, func_buf );
6610 patch_op_imm(&func_buf[0], i, 16, 5);
6611
6612 /* Save flags */
6613 __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
6614 __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
6615
6616 // reset VSCR and CR
6617 vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
6618 flags = 0;
6619 __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
6620 __asm__ __volatile__ ("mtcr %0" : : "r" (flags));
6621
6622 // do stuff
6623 (*func)();
6624
6625 // retrieve output <- r17
6626 __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
6627
6628 // get CR,VSCR flags
6629 __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
6630 __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
6631
6632 /* Restore flags */
6633 __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
6634 __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
6635
6636 dst = (unsigned int*)&vec_out;
6637
6638 printf("%s: %2d => ", name, i);
6639 printf("%08x %08x %08x %08x ", dst[0], dst[1], dst[2], dst[3]);
6640 #if defined TEST_VSCR_SAT
6641 p_vscr = (unsigned int*)&vscr;
6642 printf("(%08x, %08x)\n", flags, p_vscr[3]);
6643 #else
6644 printf("(%08x)\n", flags);
6645 #endif
6646 }
6647 }
6648
6649 static void vsldoi_cb (const char* name, test_func_t func_IN,
6650 unused uint32_t test_flags)
6651 {
6652 volatile test_func_t func;
6653 uint32_t* func_buf = get_rwx_area();
6654 volatile uint32_t flags, tmpcr;
6655 volatile vector unsigned int tmpvscr;
6656 volatile vector unsigned int vec_in1, vec_in2, vec_out, vscr;
6657 unsigned int *src1, *src2, *dst;
6658 int i,j,k;
6659 #if defined TEST_VSCR_SAT
6660 unsigned int* p_vscr;
6661 #endif
6662
6663 for (i=0; i<nb_viargs; i++) {
6664 vec_in1 = (vector unsigned int)viargs[i];
6665 for (j=0; j<nb_viargs; j++) {
6666 vec_in2 = (vector unsigned int)viargs[j];
6667 for (k=0; k<16; k+=14) {
6668 vec_out = (vector unsigned int){ 0,0,0,0 };
6669
6670 /* Patch up the instruction */
6671 func = init_function( func_IN, func_buf );
6672 patch_op_imm(&func_buf[0], k, 6, 4);
6673
6674 /* Save flags */
6675 __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
6676 __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
6677
6678 // reset VSCR and CR
6679 vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
6680 flags = 0;
6681 __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
6682 __asm__ __volatile__ ("mtcr %0" : : "r" (flags));
6683
6684 // load inputs -> r14,r15
6685 __asm__ __volatile__ ("vor 14,%0,%0" : : "v" (vec_in1));
6686 __asm__ __volatile__ ("vor 15,%0,%0" : : "v" (vec_in2));
6687
6688 // do stuff
6689 (*func)();
6690
6691 // retrieve output <- r17
6692 __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
6693
6694 // get CR,VSCR flags
6695 __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
6696 __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
6697
6698 /* Restore flags */
6699 __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
6700 __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
6701
6702 src1 = (unsigned int*)&vec_in1;
6703 src2 = (unsigned int*)&vec_in2;
6704 dst = (unsigned int*)&vec_out;
6705
6706 printf("%s: ", name);
6707 printf("%08x%08x%08x%08x, %08x%08x%08x%08x, %u\n",
6708 src1[0], src1[1], src1[2], src1[3],
6709 src2[0], src2[1], src2[2], src2[3], k);
6710
6711 printf("%s: => %08x %08x %08x %08x] ", name,
6712 dst[0], dst[1], dst[2], dst[3]);
6713 #if defined TEST_VSCR_SAT
6714 p_vscr = (unsigned int*)&vscr;
6715 printf("(%08x, %08x)\n", flags, p_vscr[3]);
6716 #else
6717 printf("(%08x)\n", flags);
6718 #endif
6719 }
6720 if (verbose) printf("\n");
6721 }
6722 }
6723 }
6724
6725 /* lvsl, lvsr */
6726 static void lvs_cb (const char *name, test_func_t func,
6727 unused uint32_t test_flags)
6728 {
6729 volatile uint32_t flags, tmpcr;
6730 volatile vector unsigned int tmpvscr;
6731 volatile vector unsigned int vec_out, vscr;
6732 unsigned shift;
6733 unsigned char * dst;
6734 int i, j;
6735 #if defined TEST_VSCR_SAT
6736 unsigned int* p_vscr;
6737 #endif
6738
6739 for (i=-1; i<17; i++) {
6740 vec_out = (vector unsigned int){ 0,0,0,0 };
6741
6742 // make sure start address is 16 aligned - use viargs[0]
6743 HWord_t * r15_in_ptr = (HWord_t *)&viargs[0];
6744 r15 = *r15_in_ptr;
6745 r14 = i;
6746
6747 /* Save flags */
6748 __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
6749 __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
6750
6751 // reset VSCR and CR
6752 vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
6753 flags = 0;
6754 __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
6755 __asm__ __volatile__ ("mtcr %0" : : "r" (flags));
6756
6757 // do stuff
6758 (*func)();
6759
6760 // retrieve output <- r17
6761 __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
6762
6763 // get CR,VSCR flags
6764 __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
6765 __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
6766
6767 /* Restore flags */
6768 __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
6769 __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
6770
6771 dst = (unsigned char*)&vec_out;
6772
6773 shift = ((unsigned int)i + *r15_in_ptr) & 0xf;
6774 printf("%s %x, %3d", name, shift, 0);
6775 printf(" => 0x");
6776 for (j = 0; j < 16; j++) {
6777 printf("%02x", dst[j]);
6778 if (j == 7)
6779 printf(" 0x");
6780 }
6781
6782 printf(" (%08x)\n", flags);
6783 }
6784 if (verbose) printf("\n");
6785 }
6786
6787 static special_t special_av_int_ops[] = {
6788 {
6789 "vsr", /* Two registers arguments */
6790 &vs128_cb,
6791 },
6792 {
6793 "vsl", /* Two registers arguments */
6794 &vs128_cb,
6795 },
6796 {
6797 "vspltb", /* One reg, one 5-bit uimm arguments */
6798 &vsplt_cb,
6799 },
6800 {
6801 "vsplth", /* One reg, one 5-bit uimm arguments */
6802 &vsplt_cb,
6803 },
6804 {
6805 "vspltw", /* One reg, one 5-bit uimm arguments */
6806 &vsplt_cb,
6807 },
6808 {
6809 "vspltisb", /* One reg, one 5-bit uimm arguments */
6810 &vspltis_cb,
6811 },
6812 {
6813 "vspltish", /* One reg, one 5-bit uimm arguments */
6814 &vspltis_cb,
6815 },
6816 {
6817 "vspltisw", /* One reg, one 5-bit uimm arguments */
6818 &vspltis_cb,
6819 },
6820 {
6821 "vsldoi", /* Two regs, one 4-bit uimm arguments */
6822 &vsldoi_cb,
6823 },
6824 {
6825 "lvsl", /* Two regs */
6826 &lvs_cb,
6827 },
6828 {
6829 "lvsr", /* Two regs */
6830 &lvs_cb,
6831 },
6832 {
6833 NULL,
6834 NULL,
6835 },
6836 };
6837
6838 static void test_av_int_special (const char* name, test_func_t func,
6839 uint32_t test_flags)
6840 {
6841 test_special(special_av_int_ops, name, func, test_flags);
6842 }
6843
6844 static void test_av_int_ld_two_regs (const char *name,
6845 test_func_t func,
6846 unused uint32_t test_flags)
6847 {
6848 volatile uint32_t flags, tmpcr;
6849 volatile vector unsigned int tmpvscr;
6850 volatile vector unsigned int vec_in, vec_out, vscr;
6851 unsigned int *src, *dst;
6852 int i,j, k, do_mask;
6853
6854 do_mask = 0;
6855 if (strstr(name, "lvebx") != NULL) do_mask = 1;
6856 if (strstr(name, "lvehx") != NULL) do_mask = 2;
6857 if (strstr(name, "lvewx") != NULL) do_mask = 4;
6858
6859 for (i=0; i<nb_viargs; i++) {
6860 for (j=0; j<16; j+=7) {
6861 vec_out = (vector unsigned int){ 0,0,0,0 };
6862
6863 // load from viargs array + some dis-alignment
6864 r15 = (HWord_t)&viargs[0];
6865 r14 = i*16 + j;
6866
6867 /* Save flags */
6868 __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
6869 __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
6870
6871 // reset VSCR and CR
6872 vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
6873 flags = 0;
6874 __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
6875 __asm__ __volatile__ ("mtcr %0" : : "r" (flags));
6876
6877 // do stuff
6878 (*func)();
6879
6880 // retrieve output <- r17
6881 __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
6882
6883 // get CR,VSCR flags
6884 __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
6885 __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
6886
6887 /* Restore flags */
6888 __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
6889 __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
6890
6891 vec_in = (vector unsigned int)viargs[i];
6892 src = (unsigned int*)&vec_in;
6893 dst = (unsigned int*)&vec_out;
6894
6895 /* For lvebx/lvehx/lvewx, as per the documentation, all of
6896 the dest reg except the loaded bits are undefined
6897 afterwards. And different CPUs really do produce
6898 different results. So mask out bits of the result that
6899 are undefined so as to make the test work reliably. */
6900 if (do_mask == 1) {
6901 char* p = (char*)dst;
6902 for (k = 0; k < 16; k++)
6903 if (k != j)
6904 p[k] = (char)0;
6905 }
6906 if (do_mask == 2) {
6907 short* p = (short*)dst;
6908 for (k = 0; k < 8; k++)
6909 if (k != (j>>1))
6910 p[k] = (short)0;
6911 }
6912 if (do_mask == 4) {
6913 int* p = (int*)dst;
6914 for (k = 0; k < 4; k++)
6915 if (k != (j>>2))
6916 p[k] = (int)0;
6917 }
6918
6919 printf("%s %3d, %08x %08x %08x %08x", name, j, src[0], src[1], src[2], src[3]);
6920 printf(" => %08x %08x %08x %08x ", dst[0], dst[1], dst[2], dst[3]);
6921 printf("(%08x)\n", flags);
6922 }
6923 if (verbose) printf("\n");
6924 }
6925 }
6926
6927
6928 static void test_av_int_st_three_regs (const char *name,
6929 test_func_t func,
6930 unused uint32_t test_flags)
6931 {
6932 volatile uint32_t flags, tmpcr;
6933 volatile vector unsigned int tmpvscr;
6934 volatile vector unsigned int vec_in, vec_out, vscr;
6935 unsigned int *src, *dst;
6936 int i,j;
6937 vector unsigned int* viargs_priv;
6938
6939 // private viargs table to store to
6940 viargs_priv = memalign16(nb_viargs * sizeof(vector unsigned int));
6941 for (i=0; i<nb_viargs; i++)
6942 viargs_priv[i] = (vector unsigned int) { 0,0,0,0 };
6943
6944 for (i=0; i<nb_viargs; i++) {
6945 for (j=0; j<16; j+=7) {
6946 // read from viargs
6947 vec_in = (vector unsigned int)viargs[i];
6948
6949 // store to viargs_priv[0] + some dis-alignment
6950 r16 = (HWord_t)&viargs_priv[0];
6951 r15 = i*16 + j;
6952
6953 /* Save flags */
6954 __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
6955 __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
6956
6957 // reset VSCR and CR
6958 vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
6959 flags = 0;
6960 __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
6961 __asm__ __volatile__ ("mtcr %0" : : "r" (flags));
6962
6963 // load inputs -> r14
6964 __asm__ __volatile__ ("vor 14,%0,%0" : : "v" (vec_in));
6965
6966 // do stuff
6967 (*func)();
6968
6969 // Output stored in viargs_priv
6970
6971 // get CR,VSCR flags
6972 __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
6973 __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
6974
6975 /* Restore flags */
6976 __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
6977 __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
6978
6979 vec_out = (vector unsigned int)viargs_priv[i];
6980 src = (unsigned int*)&vec_in;
6981 dst = (unsigned int*)&vec_out;
6982
6983 printf("%s %3d, %08x %08x %08x %08x", name, j, src[0], src[1], src[2], src[3]);
6984 printf(" => %08x %08x %08x %08x ", dst[0], dst[1], dst[2], dst[3]);
6985 printf("(%08x)\n", flags);
6986 }
6987 if (verbose) printf("\n");
6988 }
6989 }
6990
6991 /* Used in do_tests, indexed by flags->nb_args
6992 Elements correspond to enum test_flags::num args
6993 */
6994 static test_loop_t altivec_int_loops[] = {
6995 &test_av_int_one_arg,
6996 &test_av_int_two_args,
6997 &test_av_int_three_args,
6998 &test_av_int_two_args,
6999 NULL,
7000 NULL,
7001 &test_av_int_special,
7002 NULL,
7003 &test_av_int_ld_two_regs,
7004 NULL,
7005 test_av_int_st_three_regs,
7006 };
7007
7008
7009 static void test_av_float_one_arg (const char* name, test_func_t func,
7010 unused uint32_t test_flags)
7011 {
7012 volatile uint32_t flags, tmpcr;
7013 volatile vector unsigned int tmpvscr;
7014 volatile vector float vec_in, vec_out;
7015 volatile vector unsigned int vscr;
7016 unsigned int *src, *dst;
7017 int i;
7018 #if defined TEST_VSCR_SAT
7019 unsigned int* p_vscr;
7020 #endif
7021
7022 /* if we're doing an estimation operation, arrange to zap the
7023 bottom 10-bits of the result as it's basically garbage, and differs
7024 between cpus */
7025 unsigned int mask
7026 = (strstr(name,"vrsqrtefp") != NULL ||
7027 strstr(name, "vrefp") != NULL)
7028 ? 0xFFFFC000 : 0xFFFFFFFF;
7029
7030 for (i=0; i<nb_vfargs; i++) {
7031 vec_in = (vector float)vfargs[i];
7032 vec_out = (vector float){ 0.0, 0.0, 0.0, 0.0 };
7033
7034 /* Save flags */
7035 __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
7036 __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
7037
7038 // reset VSCR and CR
7039 vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
7040 flags = 0;
7041 __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
7042 __asm__ __volatile__ ("mtcr %0" : : "r" (flags));
7043
7044 // load input -> r14
7045 __asm__ __volatile__ ("vor 14,%0,%0" : : "v" (vec_in));
7046
7047 // do stuff
7048 (*func)();
7049
7050 // retrieve output <- r17
7051 __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
7052
7053 // get CR,VSCR flags
7054 __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
7055 __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
7056
7057 /* Restore flags */
7058 __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
7059 __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
7060
7061 src = (unsigned int*)&vec_in;
7062 dst = (unsigned int*)&vec_out;
7063
7064 printf("%s: %08x %08x %08x %08x\n", name,
7065 src[0], src[1], src[2], src[3]);
7066 printf("%s: => %08x %08x %08x %08x ", name,
7067 dst[0] & mask, dst[1] & mask, dst[2] & mask, dst[3] & mask);
7068 #if defined TEST_VSCR_SAT
7069 p_vscr = (unsigned int*)&vscr;
7070 printf("(%08x, %08x)\n", flags, p_vscr[3]);
7071 #else
7072 printf("(%08x)\n", flags);
7073 #endif
7074 }
7075 }
7076
7077 static void test_av_float_two_args (const char* name, test_func_t func,
7078 unused uint32_t test_flags)
7079 {
7080 volatile uint32_t flags, tmpcr;
7081 volatile vector unsigned int tmpvscr;
7082 volatile vector float vec_in1, vec_in2, vec_out;
7083 volatile vector unsigned int vscr;
7084 unsigned int *src1, *src2, *dst;
7085 int i,j;
7086 #if defined TEST_VSCR_SAT
7087 unsigned int* p_vscr;
7088 #endif
7089
7090 for (i=0; i<nb_vfargs; i++) {
7091 for (j=0; j<nb_vfargs; j+=3) {
7092 vec_in1 = (vector float)vfargs[i];
7093 vec_in2 = (vector float)vfargs[j];
7094 vec_out = (vector float){ 0.0, 0.0, 0.0, 0.0 };
7095
7096 /* Save flags */
7097 __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
7098 __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
7099
7100 // reset VSCR and CR
7101 vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
7102 flags = 0;
7103 __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
7104 __asm__ __volatile__ ("mtcr %0" : : "r" (flags));
7105
7106 // load inputs -> r14,r15
7107 __asm__ __volatile__ ("vor 14,%0,%0" : : "v" (vec_in1));
7108 __asm__ __volatile__ ("vor 15,%0,%0" : : "v" (vec_in2));
7109
7110 // do stuff
7111 (*func)();
7112
7113 // retrieve output <- r17
7114 __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
7115
7116 // get CR,VSCR flags
7117 __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
7118 __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
7119
7120 /* Restore flags */
7121 __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
7122 __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
7123
7124 src1 = (unsigned int*)&vec_in1;
7125 src2 = (unsigned int*)&vec_in2;
7126 dst = (unsigned int*)&vec_out;
7127
7128 printf("%s: %08x%08x%08x%08x, %08x%08x%08x%08x\n", name,
7129 src1[0], src1[1], src1[2], src1[3],
7130 src2[0], src2[1], src2[2], src2[3]);
7131 printf("%s: => %08x %08x %08x %08x ", name,
7132 dst[0], dst[1], dst[2], dst[3]);
7133 #if defined TEST_VSCR_SAT
7134 p_vscr = (unsigned int*)&vscr;
7135 printf("(%08x, %08x)\n", flags, p_vscr[3]);
7136 #else
7137 printf("(%08x)\n", flags);
7138 #endif
7139 }
7140 if (verbose) printf("\n");
7141 }
7142 }
7143
7144 static void test_av_float_three_args (const char* name, test_func_t func,
7145 unused uint32_t test_flags)
7146 {
7147 volatile uint32_t flags, tmpcr;
7148 volatile vector unsigned int tmpvscr;
7149 volatile vector float vec_in1, vec_in2, vec_in3, vec_out;
7150 volatile vector unsigned int vscr;
7151 unsigned int *src1, *src2, *src3, *dst;
7152 int i,j,k,n;
7153 #if defined TEST_VSCR_SAT
7154 unsigned int* p_vscr;
7155 #endif
7156
7157 for (i=0; i<nb_vfargs; i++) {
7158 for (j=0; j<nb_vfargs; j+=3) {
7159 for (k=0; k<nb_vfargs; k+=5) {
7160 vec_in1 = (vector float)vfargs[i];
7161 vec_in2 = (vector float)vfargs[j];
7162 vec_in3 = (vector float)vfargs[k];
7163 vec_out = (vector float){ 0.0, 0.0, 0.0, 0.0 };
7164
7165 /* Save flags */
7166 __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
7167 __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
7168
7169 // reset VSCR and CR
7170 vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
7171 flags = 0;
7172 __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
7173 __asm__ __volatile__ ("mtcr %0" : : "r" (flags));
7174
7175 // load inputs -> r14,r15,r16
7176 __asm__ __volatile__ ("vor 14,%0,%0" : : "v" (vec_in1));
7177 __asm__ __volatile__ ("vor 15,%0,%0" : : "v" (vec_in2));
7178 __asm__ __volatile__ ("vor 16,%0,%0" : : "v" (vec_in3));
7179
7180 // do stuff
7181 (*func)();
7182
7183 // retrieve output <- r17
7184 __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
7185
7186 // get CR,VSCR flags
7187 __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
7188 __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
7189
7190 /* Restore flags */
7191 __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
7192 __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
7193
7194 src1 = (unsigned int*)&vec_in1;
7195 src2 = (unsigned int*)&vec_in2;
7196 src3 = (unsigned int*)&vec_in3;
7197 dst = (unsigned int*)&vec_out;
7198
7199 /* Valgrind emulation for vmaddfp and vnmsubfp generates negative
7200 * NAN. Technically, NAN is not positive or negative so mask off
7201 * the sign bit to eliminate false errors. The lower 22-bits of
7202 * the 23-bit significand are a don't care for a NAN. Mask them off.
7203 *
7204 * Valgrind emulation is creating negative zero. Mask off negative
7205 * from zero result.
7206 *
7207 * These are only an issue as we are printing the result in hex.
7208 *
7209 * The VEX emulation accuracy for the vmaddfp and vnmsubfp
7210 * instructions is off by a single bit in the least significant
7211 * bit position of the result. Mask off the LSB.
7212 */
7213
7214 for (n=0; n<4; n++) {
7215 /* NAN result*/
7216 if (((dst[n] & 0x7F800000) == 0x7F800000) &&
7217 ((dst[n] & 0x7FFFFF) != 0))
7218 dst[n] &= 0x7FC00000;
7219
7220 /* Negative zero result */
7221 else if (dst[n] == 0x80000000)
7222 dst[n] = 0x0;
7223
7224 else
7225 /* The actual result and the emulated result for the
7226 * vmaddfp and vnmsubfp instructions sometimes differ
7227 * in the least significant bit. Mask off the bit.
7228 */
7229 dst[n] &= 0xFFFFFFFE;
7230 }
7231
7232 printf("%s: %08x%08x%08x%08x, %08x%08x%08x%08x, %08x%08x%08x%08x\n", name,
7233 src1[0], src1[1], src1[2], src1[3],
7234 src2[0], src2[1], src2[2], src2[3],
7235 src3[0], src3[1], src3[2], src3[3]);
7236 printf("%s: => %08x %08x %08x %08x ", name,
7237 dst[0], dst[1], dst[2], dst[3]);
7238 #if defined TEST_VSCR_SAT
7239 p_vscr = (unsigned int*)&vscr;
7240 printf("(%08x, %08x)\n", flags, p_vscr[3]);
7241 #else
7242 printf("(%08x)\n", flags);
7243 #endif
7244 }
7245 if (verbose) printf("\n");
7246 }
7247 }
7248 }
7249
7250 static void vcvt_cb (const char* name, test_func_t func_IN,
7251 unused uint32_t test_flags)
7252 {
7253 volatile test_func_t func;
7254 uint32_t* func_buf = get_rwx_area();
7255 volatile uint32_t flags, tmpcr;
7256 volatile vector unsigned int tmpvscr;
7257 volatile vector unsigned int vec_in, vec_out, vscr;
7258 unsigned int *src, *dst;
7259 int i,j;
7260 #if defined TEST_VSCR_SAT
7261 unsigned int* p_vscr;
7262 #endif
7263
7264 for (i=0; i<nb_vfargs; i++) {
7265 vec_in = (vector unsigned int)vfargs[i];
7266
7267 for (j=0; j<32; j+=9) {
7268 vec_out = (vector unsigned int){ 0,0,0,0 };
7269
7270 /* Patch up the instruction */
7271 func = init_function( func_IN, func_buf );
7272 patch_op_imm(&func_buf[0], j, 16, 5);
7273
7274 /* Save flags */
7275 __asm__ __volatile__ ("mfcr %0" : "=r" (tmpcr));
7276 __asm__ __volatile__ ("mfvscr %0" : "=v" (tmpvscr));
7277
7278 // reset VSCR and CR
7279 vscr = (vector unsigned int){ 0,0,0,DEFAULT_VSCR };
7280 flags = 0;
7281 __asm__ __volatile__ ("mtvscr %0" : : "v" (vscr) );
7282 __asm__ __volatile__ ("mtcr %0" : : "r" (flags));
7283
7284 // load input -> r14
7285 __asm__ __volatile__ ("vor 14,%0,%0" : : "v" (vec_in));
7286
7287 // do stuff
7288 (*func)();
7289
7290 // retrieve output <- r17
7291 __asm__ __volatile__ ("vor %0,17,17" : "=v" (vec_out));
7292
7293 // get CR,VSCR flags
7294 __asm__ __volatile__ ("mfcr %0" : "=r" (flags));
7295 __asm__ __volatile__ ("mfvscr %0" : "=v" (vscr));
7296
7297 /* Restore flags */
7298 __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
7299 __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
7300
7301 src = (unsigned int*)&vec_in;
7302 dst = (unsigned int*)&vec_out;
7303
7304 printf("%s: %08x (%13e), %2u", name, src[0], *(float*)(&src[0]), j);
7305 printf(" => %08x (%13e) ", dst[0], *(float*)(&dst[0]));
7306 // printf(" => %08x ", dst[0]);
7307 #if defined TEST_VSCR_SAT
7308 p_vscr = (unsigned int*)&vscr;
7309 printf("(%08x, %08x)\n", flags, p_vscr[3]);
7310 #else
7311 printf("(%08x)\n", flags);
7312 #endif
7313 }
7314 if (verbose) printf("\n");
7315 }
7316 }
7317
7318 static special_t special_av_float_ops[] = {
7319 {
7320 "vcfux", /* One reg, one 5-bit uimm argument */
7321 &vcvt_cb,
7322 },
7323 {
7324 "vcfsx", /* One reg, one 5-bit uimm argument */
7325 &vcvt_cb,
7326 },
7327 {
7328 "vctuxs", /* One reg, one 5-bit uimm argument */
7329 &vcvt_cb,
7330 },
7331 {
7332 "vcfux", /* One reg, one 5-bit uimm argument */
7333 &vcvt_cb,
7334 },
7335 {
7336 "vctsxs", /* One reg, one 5-bit uimm argument */
7337 &vcvt_cb,
7338 },
7339 {
7340 NULL,
7341 NULL,
7342 },
7343 };
7344
7345 static void test_av_float_special (const char* name, test_func_t func,
7346 uint32_t test_flags)
7347 {
7348 test_special(special_av_float_ops, name, func, test_flags);
7349 }
7350
7351 /* Used in do_tests, indexed by flags->nb_args
7352 Elements correspond to enum test_flags::num args
7353 */
7354 static test_loop_t altivec_float_loops[] = {
7355 &test_av_float_one_arg,
7356 &test_av_float_two_args,
7357 &test_av_float_three_args,
7358 &test_av_float_two_args,
7359 NULL,
7360 NULL,
7361 &test_av_float_special,
7362 NULL,
7363 NULL,
7364 NULL,
7365 NULL,
7366 };
7367
7368 #endif /* defined (HAS_ALTIVEC) */
7369
7370
7371 #if defined (IS_PPC405)
7372 static void test_ppc405 (const char* name, test_func_t func,
7373 unused uint32_t test_flags)
7374 {
7375 volatile uint32_t res, flags, xer, tmpcr, tmpxer;
7376 int i, j, k;
7377
7378 for (i=0; i<nb_iargs; i++) {
7379 for (j=0; j<nb_iargs; j++) {
7380 for (k=0; k<nb_iargs; k++) {
7381 r14 = iargs[i];
7382 r15 = iargs[j];
7383 /* Beware: the third argument and the result
7384 * are in the same register
7385 */
7386 r17 = iargs[k];
7387
7388 /* Save flags */
7389 __asm__ __volatile__ ("mfcr 18");
7390 tmpcr = r18;
7391 __asm__ __volatile__ ("mfxer 18");
7392 tmpxer = r18;
7393
7394 /* Set up flags for test */
7395 r18 = 0;
7396 __asm__ __volatile__ ("mtcr 18");
7397 __asm__ __volatile__ ("mtxer 18");
7398 (*func)();
7399 __asm__ __volatile__ ("mfcr 18");
7400 flags = r18;
7401 __asm__ __volatile__ ("mfxer 18");
7402 xer = r18;
7403 res = r17;
7404
7405 /* Restore flags */
7406 r18 = tmpcr;
7407 __asm__ __volatile__ ("mtcr 18");
7408 r18 = tmpxer;
7409 __asm__ __volatile__ ("mtxer 18");
7410
7411 printf("%s %08x, %08x, %08x => %08x (%08x %08x)\n",
7412 name, iargs[i], iargs[j], iargs[k], res, flags, xer);
7413 }
7414 if (verbose) printf("\n");
7415 }
7416 }
7417 }
7418 #endif /* defined (IS_PPC405) */
7419
7420 static int check_filter (char *filter)
7421 {
7422 char *c;
7423 int ret = 1;
7424
7425 if (filter != NULL) {
7426 c = strchr(filter, '*');
7427 if (c != NULL) {
7428 *c = '\0';
7429 ret = 0;
7430 }
7431 }
7432
7433 return ret;
7434 }
7435
7436 static int check_name (const char* name, const char *filter,
7437 int exact)
7438 {
7439 int nlen, flen;
7440 int ret = 0;
7441
7442 if (filter != NULL) {
7443 for (; isspace(*name); name++)
7444 continue;
7445 FDPRINTF("Check '%s' againt '%s' (%s match)\n",
7446 name, filter, exact ? "exact" : "starting");
7447 nlen = strlen(name);
7448 flen = strlen(filter);
7449 if (exact) {
7450 if (nlen == flen && memcmp(name, filter, flen) == 0)
7451 ret = 1;
7452 } else {
7453 if (flen <= nlen && memcmp(name, filter, flen) == 0)
7454 ret = 1;
7455 }
7456 } else {
7457 ret = 1;
7458 }
7459 return ret;
7460 }
7461
7462
7463
7464 typedef struct insn_sel_flags_t_struct {
7465 int one_arg, two_args, three_args;
7466 int arith, logical, compare, ldst;
7467 int integer, floats, p405, altivec, faltivec, misc;
7468 int cr;
7469 } insn_sel_flags_t;
7470
7471 static void do_tests ( insn_sel_flags_t seln_flags,
7472 char *filter)
7473 {
7474 #if defined (IS_PPC405)
7475 test_loop_t tmpl;
7476 #endif
7477 test_loop_t *loop;
7478 test_t *tests;
7479 int nb_args, type, family;
7480 int i, j, n;
7481 int exact;
7482
7483 exact = check_filter(filter);
7484 n = 0;
7485 for (i=0; all_tests[i].name != NULL; i++) {
7486 nb_args = all_tests[i].flags & PPC_NB_ARGS;
7487 /* Check number of arguments */
7488 if ((nb_args == 1 && !seln_flags.one_arg) ||
7489 (nb_args == 2 && !seln_flags.two_args) ||
7490 (nb_args == 3 && !seln_flags.three_args))
7491 continue;
7492 /* Check instruction type */
7493 type = all_tests[i].flags & PPC_TYPE;
7494 if ((type == PPC_ARITH && !seln_flags.arith) ||
7495 (type == PPC_LOGICAL && !seln_flags.logical) ||
7496 (type == PPC_COMPARE && !seln_flags.compare) ||
7497 (type == PPC_LDST && !seln_flags.ldst) ||
7498 (type == PPC_POPCNT && !seln_flags.arith))
7499 continue;
7500 /* Check instruction family */
7501 family = all_tests[i].flags & PPC_FAMILY;
7502 if ((family == PPC_INTEGER && !seln_flags.integer) ||
7503 (family == PPC_FLOAT && !seln_flags.floats) ||
7504 (family == PPC_405 && !seln_flags.p405) ||
7505 (family == PPC_ALTIVEC && !seln_flags.altivec) ||
7506 (family == PPC_MISC && !seln_flags.misc) ||
7507 (family == PPC_FALTIVEC && !seln_flags.faltivec))
7508 continue;
7509 /* Check flags update */
7510 if (((all_tests[i].flags & PPC_CR) && seln_flags.cr == 0) ||
7511 (!(all_tests[i].flags & PPC_CR) && seln_flags.cr == 1))
7512 continue;
7513 /* All passed, do the tests */
7514 tests = all_tests[i].tests;
7515 /* Select the test loop */
7516 switch (family) {
7517 case PPC_INTEGER:
7518 loop = &int_loops[nb_args - 1];
7519 break;
7520 case PPC_MISC:
7521 loop = &misc_loops[0];
7522 break;
7523 case PPC_FLOAT:
7524 #if !defined (NO_FLOAT)
7525 loop = &float_loops[nb_args - 1];
7526 break;
7527 #else
7528 fprintf(stderr, "Sorry. "
7529 "PPC floating point instructions tests "
7530 "are disabled on your host\n");
7531 #endif /* !defined (NO_FLOAT) */
7532
7533 case PPC_405:
7534 #if defined (IS_PPC405)
7535 tmpl = &test_ppc405;
7536 loop = &tmpl;
7537 break;
7538 #else
7539 fprintf(stderr, "Sorry. "
7540 "PPC405 instructions tests are disabled on your host\n");
7541 continue;
7542 #endif /* defined (IS_PPC405) */
7543 case PPC_ALTIVEC:
7544 #if defined (HAS_ALTIVEC)
7545 loop = &altivec_int_loops[nb_args - 1];
7546 break;
7547 #else
7548 fprintf(stderr, "Sorry. "
7549 "Altivec instructions tests are disabled on your host\n");
7550 continue;
7551 #endif
7552 case PPC_FALTIVEC:
7553 #if defined (HAS_ALTIVEC)
7554 loop = &altivec_float_loops[nb_args - 1];
7555 break;
7556 #else
7557 fprintf(stderr, "Sorry. "
7558 "Altivec float instructions tests "
7559 "are disabled on your host\n");
7560 #endif
7561 continue;
7562 default:
7563 printf("ERROR: unknown insn family %08x\n", family);
7564 continue;
7565 }
7566 if (1 || verbose > 0)
7567 printf("%s:\n", all_tests[i].name);
7568 for (j=0; tests[j].name != NULL; j++) {
7569 if (check_name(tests[j].name, filter, exact)) {
7570 if (verbose > 1)
7571 printf("Test instruction %s\n", tests[j].name);
7572 (*loop)(tests[j].name, tests[j].func, all_tests[i].flags);
7573 printf("\n");
7574 n++;
7575 }
7576 }
7577 if (verbose) printf("\n");
7578 }
7579 printf("All done. Tested %d different instructions\n", n);
7580 }
7581
7582
7583 static void usage (void)
7584 {
7585 #if !defined (USAGE_SIMPLE)
7586 fprintf(stderr,
7587 "jm-insns [-1] [-2] [-3] [-*] [-t <type>] [-f <family>] [-u] "
7588 "[-n <filter>] [-r <test_rigour>] [-h]\n"
7589 "\t-1: test opcodes with one argument\n"
7590 "\t-2: test opcodes with two arguments\n"
7591 "\t-3: test opcodes with three arguments\n"
7592 "\t-*: launch test without checking the number of arguments\n"
7593 "\t-t: launch test for instructions of type <type>\n"
7594 "\t recognized types:\n"
7595 "\t\tarith (or a)\n"
7596 "\t\tlogical (or l)\n"
7597 "\t\tcompare (or c)\n"
7598 "\t\tstoreload (or s)\n"
7599 "\t-f: launch test for instructions of family <family>\n"
7600 "\t recognized families:\n"
7601 "\t\tinteger (or i)\n"
7602 "\t\tfloat (or f)\n"
7603 "\t\tppc405 (or mac)\n"
7604 "\t\taltivec (or a)\n"
7605 "\t-u: test instructions that update flags\n"
7606 "\t-n: filter instructions with <filter>\n"
7607 "\t <filter> can be in two forms:\n"
7608 "\t\tname : filter functions that exactly match <name>\n"
7609 "\t\tname* : filter functions that start with <name>\n"
7610 "\t-r: set size of arg tables to use to define <test_rigour>\n"
7611 "\t recognized types:\n"
7612 "\t\tlarge (or l)\n"
7613 "\t\tsmall (or s) - default\n"
7614 "\t-v: verbose (-v -v for more)\n"
7615 "\t-h: print this help\n"
7616 );
7617 #else // #if !defined (USAGE_SIMPLE)
7618 fprintf(stderr,
7619 "Usage: jm-insns [OPTION]\n"
7620 "\t-i: test integer arithmetic instructions (default)\n"
7621 "\t-l: test integer logical instructions (default)\n"
7622 "\t-c: test integer compare instructions (default)\n"
7623 "\t-L: test integer load/store instructions (default)\n"
7624 "\t-f: test floating point instructions\n"
7625 "\t-a: test altivec instructions\n"
7626 "\t-m: test miscellaneous instructions\n"
7627 "\t-A: test all (int, fp, altivec) instructions\n"
7628 "\t-v: be verbose\n"
7629 "\t-h: display this help and exit\n"
7630 );
7631 #endif // #if !defined (USAGE_SIMPLE)
7632 }
7633
7634
7635
7636 int main (int argc, char **argv)
7637 {
7638 #if !defined (USAGE_SIMPLE)
7639 ////////////////////////////////////////////////////////////////////////
7640 unsigned char *tmp, *filter = NULL;
7641 insn_sel_flags_t flags;
7642 int c;
7643
7644 // check HWord_t really is a host word
7645 assert(sizeof(void*) == sizeof(HWord_t));
7646
7647 flags.one_arg = 0;
7648 flags.two_args = 0;
7649 flags.three_args = 0;
7650 flags.arith = 0;
7651 flags.logical = 0;
7652 flags.compare = 0;
7653 flags.ldst = 0;
7654 flags.integer = 0;
7655 flags.floats = 0;
7656 flags.p405 = 0;
7657 flags.altivec = 0;
7658 flags.faltivec = 0;
7659 flags.cr = -1;
7660
7661 while ((c = getopt(argc, argv, "123t:f:n:r:uvh")) != -1) {
7662 switch (c) {
7663 case '1':
7664 flags.one_arg = 1;
7665 break;
7666 case '2':
7667 flags.two_args = 1;
7668 break;
7669 case '3':
7670 flags.three_args = 1;
7671 break;
7672 case 't':
7673 tmp = optarg;
7674 if (strcmp(tmp, "arith") == 0 || strcmp(tmp, "a") == 0) {
7675 flags.arith = 1;
7676 } else if (strcmp(tmp, "logical") == 0 || strcmp(tmp, "l") == 0) {
7677 flags.logical = 1;
7678 } else if (strcmp(tmp, "compare") == 0 || strcmp(tmp, "c") == 0) {
7679 flags.compare = 1;
7680 } else if (strcmp(tmp, "storeload") == 0 || strcmp(tmp, "s") == 0) {
7681 flags.ldst = 1;
7682 } else {
7683 goto bad_arg;
7684 }
7685 break;
7686 case 'f':
7687 tmp = optarg;
7688 if (strcmp(tmp, "integer") == 0 || strcmp(tmp, "i") == 0) {
7689 flags.integer = 1;
7690 } else if (strcmp(tmp, "float") == 0 || strcmp(tmp, "f") == 0) {
7691 flags.floats = 1;
7692 } else if (strcmp(tmp, "ppc405") == 0 || strcmp(tmp, "mac") == 0) {
7693 flags.p405 = 1;
7694 } else if (strcmp(tmp, "altivec") == 0 || strcmp(tmp, "a") == 0) {
7695 flags.altivec = 1;
7696 flags.faltivec = 1;
7697 } else {
7698 goto bad_arg;
7699 }
7700 break;
7701 case 'n':
7702 filter = optarg;
7703 break;
7704 case 'r':
7705 tmp = optarg;
7706 if (strcmp(tmp, "large") == 0 || strcmp(tmp, "l") == 0) {
7707 arg_list_size = 1;
7708 } else if (strcmp(tmp, "small") == 0 || strcmp(tmp, "s") == 0) {
7709 arg_list_size = 0;
7710 } else {
7711 goto bad_arg;
7712 }
7713 break;
7714
7715 case 'u':
7716 flags.cr = 1;
7717 break;
7718 case 'h':
7719 usage();
7720 return 0;
7721 case 'v':
7722 verbose++;
7723 break;
7724 default:
7725 usage();
7726 fprintf(stderr, "Unknown argument: '%c'\n", c);
7727 return 1;
7728 bad_arg:
7729 usage();
7730 fprintf(stderr, "Bad argument for '%c': '%s'\n", c, tmp);
7731 return 1;
7732 }
7733 }
7734 if (argc != optind) {
7735 usage();
7736 fprintf(stderr, "Bad number of arguments\n");
7737 return 1;
7738 }
7739
7740 // Default n_args
7741 if (flags.one_arg == 0 && flags.two_args == 0 && flags.three_args == 0) {
7742 flags.one_arg = 1;
7743 flags.two_args = 1;
7744 flags.three_args = 1;
7745 }
7746 // Default type
7747 if (flags.arith == 0 && flags.logical == 0 &&
7748 flags.compare == 0 && flags.ldst == 0) {
7749 flags.arith = 1;
7750 flags.logical = 1;
7751 flags.compare = 1;
7752 flags.ldst = 1;
7753 }
7754 // Default family
7755 if (flags.integer == 0 && flags.floats == 0 &&
7756 flags.p405 == 0 && flags.altivec == 0 && flags.faltivec == 0) {
7757 flags.integer = 1;
7758 flags.floats = 1;
7759 flags.p405 = 1;
7760 flags.altivec = 1;
7761 flags.faltivec = 1;
7762 }
7763 // Default cr update
7764 if (flags.cr == -1)
7765 flags.cr = 2; // both
7766
7767 #else // #if !defined (USAGE_SIMPLE)
7768 ////////////////////////////////////////////////////////////////////////
7769 /* Simple usage:
7770 ./jm-insns -i => int arithmetic insns
7771 ./jm-insns -l => int logical insns
7772 ./jm-insns -f => fp insns
7773 ./jm-insns -a => av insns
7774 ./jm-insns -m => miscellaneous insns
7775 ./jm-insns -A => int, fp and avinsns
7776 */
7777 char *filter = NULL;
7778 insn_sel_flags_t flags;
7779 int c;
7780
7781 // Args
7782 flags.one_arg = 1;
7783 flags.two_args = 1;
7784 flags.three_args = 1;
7785 // Type
7786 flags.arith = 0;
7787 flags.logical = 0;
7788 flags.compare = 0;
7789 flags.ldst = 0;
7790 // Family
7791 flags.integer = 0;
7792 flags.floats = 0;
7793 flags.misc = 0;
7794 flags.p405 = 0;
7795 flags.altivec = 0;
7796 flags.faltivec = 0;
7797 // Flags
7798 flags.cr = 2;
7799
7800 while ((c = getopt(argc, argv, "ilcLfmahvA")) != -1) {
7801 switch (c) {
7802 case 'i':
7803 flags.arith = 1;
7804 flags.integer = 1;
7805 break;
7806 case 'l':
7807 flags.logical = 1;
7808 flags.integer = 1;
7809 break;
7810 case 'c':
7811 flags.compare = 1;
7812 flags.integer = 1;
7813 break;
7814 case 'L':
7815 flags.ldst = 1;
7816 flags.integer = 1;
7817 break;
7818 case 'f':
7819 flags.arith = 1;
7820 flags.logical = 1;
7821 flags.compare = 1;
7822 flags.ldst = 1;
7823 flags.floats = 1;
7824 break;
7825 case 'a':
7826 flags.arith = 1;
7827 flags.logical = 1;
7828 flags.compare = 1;
7829 flags.ldst = 1;
7830 flags.altivec = 1;
7831 flags.faltivec = 1;
7832 break;
7833 case 'm':
7834 flags.arith = 1;
7835 flags.logical = 1;
7836 flags.compare = 1;
7837 flags.ldst = 1;
7838 flags.misc = 1;
7839 break;
7840 case 'A':
7841 flags.arith = 1;
7842 flags.logical = 1;
7843 flags.compare = 1;
7844 flags.ldst = 1;
7845 flags.integer = 1;
7846 flags.floats = 1;
7847 flags.altivec = 1;
7848 flags.faltivec = 1;
7849 break;
7850 case 'h':
7851 usage();
7852 return 0;
7853 case 'v':
7854 verbose++;
7855 break;
7856 default:
7857 usage();
7858 fprintf(stderr, "Unknown argument: '%c'\n", c);
7859 return 1;
7860 }
7861 }
7862
7863 arg_list_size = 0;
7864 #endif // #if !defined (USAGE_SIMPLE)
7865
7866
7867 build_iargs_table();
7868 build_fargs_table();
7869 build_ii16_table();
7870 #if defined (HAS_ALTIVEC)
7871 if (flags.altivec || flags.faltivec) {
7872 build_viargs_table();
7873 build_vfargs_table();
7874 }
7875 #endif
7876 // dump_iargs();
7877 // dump_iargs16();
7878 // dump_vfargs();
7879
7880 if (verbose > 1) {
7881 printf("\nInstruction Selection:\n");
7882 printf(" n_args: \n");
7883 printf(" one_arg = %d\n", flags.one_arg);
7884 printf(" two_args = %d\n", flags.two_args);
7885 printf(" three_args = %d\n", flags.three_args);
7886 printf(" type: \n");
7887 printf(" arith = %d\n", flags.arith);
7888 printf(" logical = %d\n", flags.logical);
7889 printf(" compare = %d\n", flags.compare);
7890 printf(" ldst = %d\n", flags.ldst);
7891 printf(" family: \n");
7892 printf(" integer = %d\n", flags.integer);
7893 printf(" floats = %d\n", flags.floats);
7894 printf(" p405 = %d\n", flags.p405);
7895 printf(" altivec = %d\n", flags.altivec);
7896 printf(" faltivec = %d\n", flags.faltivec);
7897 printf(" cr update: \n");
7898 printf(" cr = %d\n", flags.cr);
7899 printf("\n");
7900 printf(" num args: \n");
7901 printf(" iargs - %d\n", nb_iargs);
7902 printf(" fargs - %d\n", nb_fargs);
7903 #if defined (HAS_ALTIVEC)
7904 printf(" viargs - %d\n", nb_viargs);
7905 printf(" vfargs - %d\n", nb_vfargs);
7906 #endif
7907 printf("\n");
7908 }
7909
7910 do_tests( flags, filter );
7911
7912 return 0;
7913 }
Instrumentation framework for detecting many memory management and threading bugs, and profile your programs in detail.