bit_synchronizer.vhd

   1 library ieee;
   2     use ieee.std_logic_1164.all;
   3     use ieee.numeric_std.all;
   4
   5 entity bit_synchronizer is
   6     generic (
   7         LENGTH : integer := 1
   8     );
   9     port (
  10         clk     : in  std_logic;
  11         rst     : in  std_logic;
  12         d       : in  std_logic;
  13         q       : out std_logic
  14     );
  15 end entity bit_synchronizer;
  16
  17 architecture arch of bit_synchronizer is
  18
  19     type PIPE is array (LENGTH - 1 downto 0) of std_logic;
  20
  21     signal bit_shift : PIPE;
  22
  23 begin
  24
  25     LENGTH_OFF : if (LENGTH = 0) generate
  26
  27         q <= d;
  28
  29     end generate;
  30
  31     LENGTH_ON : if (LENGTH /= 0) generate
  32
  33         sync : process( clk, rst )
  34         begin
  35             if (rst = '1') then
  36                 bit_shift <= ((others => '0');
  37             elsif rising_edge(clk) then
  38                 bit_shift <= bit_shift(bit_shift'HIGH - 1 downto 0) & d;
  39             end if;
  40         end process;
  41
  42         q <= bit_shift(bit_shift'HIGH);
  43
  44     end generate;
  45
  46 end architecture;