amd/gcn/pm4/regs.h

   1 #ifndef REGS_H
   2 #define REGS_H
   3 /*****************************************************************************/
   4 /* GFX6 */
   5 /*
   6  * ABBREVIATIONS:
   7  *
   8  * AA : AntiAliasing? (MSAA?)
   9  * ADDR : ADDRess
  10  * ADJ : ADJustment ?
  11  * BARYC : BARYCentric
  12  * BR : Bottom Right
  13  * CB : Color Block
  14  * CL : CLipper
  15  * CNTL: CoNTroL
  16  * COL : COLor
  17  * CONFIG : CONFIGuration
  18  * DB : Depth Block
  19  * DISC : DISCipline ?
  20  * EN/ENA : ENAble
  21  * GB : Guard Band
  22  * GS : Geometry Shader ?
  23  * HI : HIgh ("high 32 bits of a 64 bits word)
  24  * HORZ : HORiZontal
  25  * IB : Indirect Buffer
  26  * IN : INput
  27  * INFO : INFOrmation
  28  * INTERP : INTERPolator
  29  * LO : LOw ("low 32 bits" of a 64 bits word)
  30  * LOCS : LOCationS
  31  * OFF : OFFset
  32  * PA : Primitive Assembler
  33  * PGM : ProGraM
  34  * POS : POSition
  35  * PRIM : PRIMitive
  36  * PS : Pixel Shader
  37  * RECT : RECTangle
  38  * RSRC : ReSouRCe
  39  * SC : Scan Converter
  40  * SPI : Shader Processor Interpolator
  41  * SU : Setup Unit
  42  * TE : Transform Engine
  43  * TL : Top Left
  44  * TMP : TeMPorary
  45  * VERT : VERTical
  46  * VGT : Vertex Grouper Tesselator
  47  * VPORT : ViewPORT
  48  * VS : Vertex Shader
  49  * VTE : Vertex TEsselator?
  50  * VTX : VerTeX ?
  51  */
  52 /*****************************************************************************/
  53 constant {
  54         reg_blk_lo = 0,
  55         reg_blk_cfg = 1, /* only 1 unlike ctxs */
  56         reg_blk_sh = 2,
  57         reg_blk_ctx = 3 /* there are N (depends on GFX) ctxs */
  58 };
  59
  60 /*
  61  * gfx[6-10]
  62  * 64KiB reg space:
  63  * low 32KiB, use PKT0:
  64  *   0x00000000-0x00007ffff byte ofts
  65  *   0x00000000-0x00001ffff w ofts
  66  * hi 32KiB, use PKT3 with the right SET_* opcode
  67  *   0x00008000-0x0000fffff byte ofts
  68  *   0x00002000-0x00003ffff w ofts
  69  */
  70 u64 reg_blk_w_ofts[] = {
  71         [reg_blk_lo]    = 0,
  72         /*-------------------------------------------------------------------*/
  73         [reg_blk_cfg]   = 0x0000000000002000,
  74         [reg_blk_sh]    = 0x0000000000002c00,
  75         [reg_blk_ctx]   = 0x000000000000a000,
  76 };
  77
  78 struct reg_desc {
  79         u8 blk;
  80         u64 w_oft;
  81         u8 *name;
  82 };
  83
  84 /* may add a gfx blk version mask, gfx6 for now */
  85 struct reg_desc reg_descs[] = {
  86         {
  87                 reg_blk_cfg,
  88                 0x256,
  89                 "VGT_PRIMITIVE_TYPE"
  90         },
  91         /*-------------------------------------------------------------------*/
  92         {
  93                 reg_blk_sh,
  94                 0x8,
  95                 "SPI_SHADER_PGM_LO_PS"
  96         },
  97         {
  98                 reg_blk_sh,
  99                 0x9,
 100                 "SPI_SHADER_PGM_HI_PS"
 101         },
 102         {
 103                 reg_blk_sh,
 104                 0xa,
 105                 "SPI_SHADER_PGM_RSRC1_PS"
 106         },
 107         {
 108                 reg_blk_sh,
 109                 0xb,
 110                 "SPI_SHADER_PGM_RSRC2_PS"
 111         },
 112         {
 113                 reg_blk_sh,
 114                 0xe,
 115                 "SPI_SHADER_USER_DATA_PS_2"
 116         },
 117         {
 118                 reg_blk_sh,
 119                 0xf,
 120                 "SPI_SHADER_USER_DATA_PS_3"
 121         },
 122         {
 123                 reg_blk_sh,
 124                 0x48,
 125                 "SPI_SHADER_PGM_LO_VS"
 126         },
 127         {
 128                 reg_blk_sh,
 129                 0x49,
 130                 "SPI_SHADER_PGM_HI_VS"
 131         },
 132         {
 133                 reg_blk_sh,
 134                 0x4a,
 135                 "SPI_SHADER_PGM_RSRC1_VS"
 136         },
 137         {
 138                 reg_blk_sh,
 139                 0x4b,
 140                 "SPI_SHADER_PGM_RSRC2_VS"
 141         },
 142         {
 143                 reg_blk_sh,
 144                 0x4e,
 145                 "SPI_SHADER_USER_DATA_VS_2"
 146         },
 147         {
 148                 reg_blk_sh,
 149                 0x4f,
 150                 "SPI_SHADER_USER_DATA_VS_3"
 151         },
 152         {
 153                 reg_blk_sh,
 154                 0x50,
 155                 "SPI_SHADER_USER_DATA_VS_4"
 156         },
 157         {
 158                 reg_blk_sh,
 159                 0x51,
 160                 "SPI_SHADER_USER_DATA_VS_5"
 161         },
 162         {
 163                 reg_blk_sh,
 164                 0x52,
 165                 "SPI_SHADER_USER_DATA_VS_6"
 166         },
 167         {
 168                 reg_blk_sh,
 169                 0x53,
 170                 "SPI_SHADER_USER_DATA_VS_7"
 171         },
 172         /*-------------------------------------------------------------------*/
 173         {
 174                 reg_blk_ctx,
 175                 0x0,
 176                 "DB_RENDER_CONTROL"
 177         },
 178         {
 179                 reg_blk_ctx,
 180                 0x3,
 181                 "DB_RENDER_OVERRIDE"
 182         },
 183         {
 184                 reg_blk_ctx,
 185                 0x4,
 186                 "DB_RENDER_OVERRIDE2"
 187         },
 188         {
 189                 reg_blk_ctx,
 190                 0x10,
 191                 "DB_Z_INFO"
 192         },
 193         {
 194                 reg_blk_ctx,
 195                 0x11,
 196                 "DB_STENCIL_INFO"
 197         },
 198         {
 199                 reg_blk_ctx,
 200                 0x82,
 201                 "PA_SC_WINDOW_SCISSOR_BR"
 202         },
 203         {
 204                 reg_blk_ctx,
 205                 0x8e,
 206                 "CB_TARGET_MASK"
 207         },
 208         {
 209                 reg_blk_ctx,
 210                 0x83,
 211                 "PA_SC_CLIPRECT_RULE"
 212         },
 213         {
 214                 reg_blk_ctx,
 215                 0x8f,
 216                 "CB_SHADER_MASK"
 217         },
 218         {
 219                 reg_blk_ctx,
 220                 0x94,
 221                 "PA_SC_VPORT_SCISSOR_0_TL"
 222         },
 223         {
 224                 reg_blk_ctx,
 225                 0x95,
 226                 "PA_SC_VPORT_SCISSOR_0_BR"
 227         },
 228         {
 229                 reg_blk_ctx,
 230                 0xb4,
 231                 "PA_SC_VPORT_ZMIN_0"
 232         },
 233         {
 234                 reg_blk_ctx,
 235                 0xb5,
 236                 "PA_SC_VPORT_ZMAX_0"
 237         },
 238         {
 239                 reg_blk_ctx,
 240                 0x10b,
 241                 "DB_STENCIL_CONTROL"
 242         },
 243         {
 244                 reg_blk_ctx,
 245                 0x10f,
 246                 "PA_CL_VPORT_XSCALE"
 247         },
 248         {
 249                 reg_blk_ctx,
 250                 0x110,
 251                 "PA_CL_VPORT_XOFFSET"
 252         },
 253         {
 254                 reg_blk_ctx,
 255                 0x111,
 256                 "PA_CL_VPORT_YSCALE"
 257         },
 258         {
 259                 reg_blk_ctx,
 260                 0x112,
 261                 "PA_CL_VPORT_YOFFSET"
 262         },
 263         {
 264                 reg_blk_ctx,
 265                 0x113,
 266                 "PA_CL_VPORT_ZSCALE"
 267         },
 268         {
 269                 reg_blk_ctx,
 270                 0x114,
 271                 "PA_CL_VPORT_ZOFFSET"
 272         },
 273         {
 274                 reg_blk_ctx,
 275                 0x191,
 276                 "SPI_PS_INPUT_CNTL_0"
 277         },
 278         {
 279                 reg_blk_ctx,
 280                 0x1b1,
 281                 "SPI_VS_OUT_CONFIG"
 282         },
 283         {
 284                 reg_blk_ctx,
 285                 0x1b3,
 286                 "SPI_PS_INPUT_ENA"
 287         },
 288         {
 289                 reg_blk_ctx,
 290                 0x1b4,
 291                 "SPI_PS_INPUT_ADDR"
 292         },
 293         {
 294                 reg_blk_ctx,
 295                 0x1b5,
 296                 "SPI_INTERP_CONTROL_0"
 297         },
 298         {
 299                 reg_blk_ctx,
 300                 0x1b6,
 301                 "SPI_PS_IN_CONTROL"
 302         },
 303         {
 304                 reg_blk_ctx,
 305                 0x1b8,
 306                 "SPI_BARYC_CNTL"
 307         },
 308         {
 309                 reg_blk_ctx,
 310                 0x1ba,
 311                 "SPI_TMPRING_SIZE"
 312         },
 313         {
 314                 reg_blk_ctx,
 315                 0x1c3,
 316                 "SPI_SHADER_POS_FORMAT"
 317         },
 318         {
 319                 reg_blk_ctx,
 320                 0x1c4,
 321                 "SPI_SHADER_Z_FORMAT"
 322         },
 323         {
 324                 reg_blk_ctx,
 325                 0x1c5,
 326                 "SPI_SHADER_COL_FORMAT"
 327         },
 328         {
 329                 reg_blk_ctx,
 330                 0x1e0,
 331                 "CB_BLEND0_CONTROL"
 332         },
 333         {
 334                 reg_blk_ctx,
 335                 0x1e1,
 336                 "CB_BLEND1_CONTROL"
 337         },
 338         {
 339                 reg_blk_ctx,
 340                 0x1e2,
 341                 "CB_BLEND2_CONTROL"
 342         },
 343         {
 344                 reg_blk_ctx,
 345                 0x1e3,
 346                 "CB_BLEND3_CONTROL"
 347         },
 348         {
 349                 reg_blk_ctx,
 350                 0x1e4,
 351                 "CB_BLEND4_CONTROL"
 352         },
 353         {
 354                 reg_blk_ctx,
 355                 0x1e5,
 356                 "CB_BLEND5_CONTROL"
 357         },
 358         {
 359                 reg_blk_ctx,
 360                 0x1e6,
 361                 "CB_BLEND6_CONTROL"
 362         },
 363         {
 364                 reg_blk_ctx,
 365                 0x1e7,
 366                 "CB_BLEND7_CONTROL"
 367         },
 368         {
 369                 reg_blk_ctx,
 370                 0x200,
 371                 "DB_DEPTH_CONTROL"
 372         },
 373         {
 374                 reg_blk_ctx,
 375                 0x201,
 376                 "DB_EQAA"
 377         },
 378         {
 379                 reg_blk_ctx,
 380                 0x202,
 381                 "CB_COLOR_CONTROL"
 382         },
 383         {
 384                 reg_blk_ctx,
 385                 0x203,
 386                 "DB_SHADER_CONTROL"
 387         },
 388         {
 389                 reg_blk_ctx,
 390                 0x204,
 391                 "PA_CL_CLIP_CNTL"
 392         },
 393         {
 394                 reg_blk_ctx,
 395                 0x205,
 396                 "PA_SU_SC_MODE_CNTL"
 397         },
 398         {
 399                 reg_blk_ctx,
 400                 0x206,
 401                 "PA_CL_VTE_CNTL"
 402         },
 403         {
 404                 reg_blk_ctx,
 405                 0x207,
 406                 "PA_CL_VS_OUT_CNTL"
 407         },
 408         {
 409                 reg_blk_ctx,
 410                 0x20b,
 411                 "PA_SU_PRIM_FILTER_CNTL"
 412         },
 413         {
 414                 reg_blk_ctx,
 415                 0x290,
 416                 "VGT_GS_MODE"
 417         },
 418         {
 419                 reg_blk_ctx,
 420                 0x292,
 421                 "PA_SC_MODE_CNTL_0"
 422         },
 423         {
 424                 reg_blk_ctx,
 425                 0x293,
 426                 "PA_SC_MODE_CNTL_1"
 427         },
 428         {
 429                 reg_blk_ctx,
 430                 0x29b,
 431                 "VGT_GS_OUT_PRIM_TYPE"
 432         },
 433         {
 434                 reg_blk_ctx,
 435                 0x2a1,
 436                 "VGT_PRIMITIVEID_EN"
 437         },
 438         {
 439                 reg_blk_ctx,
 440                 0x2a5,
 441                 "VGT_MULTI_PRIM_IB_RESET_EN"
 442         },
 443         {
 444                 reg_blk_ctx,
 445                 0x2aa,
 446                 "IA_MULTI_VGT_PARAM"
 447         },
 448         {
 449                 reg_blk_ctx,
 450                 0x2ad,
 451                 "VGT_REUSE_OFF"
 452         },
 453         {
 454                 reg_blk_ctx,
 455                 0x2d5,
 456                 "VGT_SHADER_STAGES_EN"
 457         },
 458         {
 459                 reg_blk_ctx,
 460                 0x2dc,
 461                 "DB_ALPHA_TO_MASK"
 462         },
 463         {
 464                 reg_blk_ctx,
 465                 0x2f5,
 466                 "PA_SC_CENTROID_PRIORITY_0"
 467         },
 468         {
 469                 reg_blk_ctx,
 470                 0x2f6,
 471                 "PA_SC_CENTROID_PRIORITY_1"
 472         },
 473         {
 474                 reg_blk_ctx,
 475                 0x2f7,
 476                 "PA_SC_LINE_CNTL"
 477         },
 478         {
 479                 reg_blk_ctx,
 480                 0x2f8,
 481                 "PA_SC_AA_CONFIG"
 482         },
 483         {
 484                 reg_blk_ctx,
 485                 0x2f9,
 486                 "PA_SU_VTX_CNTL"
 487         },
 488         {
 489                 reg_blk_ctx,
 490                 0x2fa,
 491                 "PA_CL_GB_VERT_CLIP_ADJ"
 492         },
 493         {
 494                 reg_blk_ctx,
 495                 0x2fb,
 496                 "PA_CL_GB_VERT_DISC_ADJ"
 497         },
 498         {
 499                 reg_blk_ctx,
 500                 0x2fc,
 501                 "PA_CL_GB_HORZ_CLIP_ADJ"
 502         },
 503         {
 504                 reg_blk_ctx,
 505                 0x2fd,
 506                 "PA_CL_GB_HORZ_DISC_ADJ"
 507         },
 508         {
 509                 reg_blk_ctx,
 510                 0x2fe,
 511                 "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0"
 512         },
 513         {
 514                 reg_blk_ctx,
 515                 0x302,
 516                 "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0"
 517         },
 518         {
 519                 reg_blk_ctx,
 520                 0x306,
 521                 "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0"
 522         },
 523         {
 524                 reg_blk_ctx,
 525                 0x30a,
 526                 "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0"
 527         },
 528         {
 529                 reg_blk_ctx,
 530                 0x30e,
 531                 "PA_SC_AA_MASK_X0Y0_X1Y0"
 532         },
 533         {
 534                 reg_blk_ctx,
 535                 0x30f,
 536                 "PA_SC_AA_MASK_X0Y1_X1Y1"
 537         },
 538         {
 539                 reg_blk_ctx,
 540                 0x313,
 541                 "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL"
 542         },
 543         {
 544                 reg_blk_ctx,
 545                 0x318,
 546                 "CB_COLOR0_BASE"
 547         },
 548         {
 549                 reg_blk_ctx,
 550                 0x319,
 551                 "CB_COLOR0_PITCH"
 552         },
 553         {
 554                 reg_blk_ctx,
 555                 0x31a,
 556                 "CB_COLOR0_SLICE"
 557         },
 558         {
 559                 reg_blk_ctx,
 560                 0x31b,
 561                 "CB_COLOR0_VIEW"
 562         },
 563         {
 564                 reg_blk_ctx,
 565                 0x31c,
 566                 "CB_COLOR0_INFO"
 567         },
 568         {
 569                 reg_blk_ctx,
 570                 0x31d,
 571                 "CB_COLOR0_ATTRIB"
 572         },
 573         {
 574                 reg_blk_ctx,
 575                 0x31e,
 576                 "CB_COLOR0_DCC_CONTROL"
 577         },
 578         {
 579                 reg_blk_ctx,
 580                 0x31f,
 581                 "CB_COLOR0_CMASK"
 582         },
 583         {
 584                 reg_blk_ctx,
 585                 0x320,
 586                 "CB_COLOR0_CMASK_SLICE"
 587         },
 588         {
 589                 reg_blk_ctx,
 590                 0x321,
 591                 "CB_COLOR0_FMASK"
 592         },
 593         {
 594                 reg_blk_ctx,
 595                 0x322,
 596                 "CB_COLOR0_FMASK_SLICE"
 597         },
 598         {
 599                 reg_blk_ctx,
 600                 0x32b,
 601                 "CB_COLOR1_INFO"
 602         },
 603         {
 604                 reg_blk_ctx,
 605                 0x33a,
 606                 "CB_COLOR2_INFO"
 607         },
 608         {
 609                 reg_blk_ctx,
 610                 0x349,
 611                 "CB_COLOR3_INFO"
 612         },
 613         {
 614                 reg_blk_ctx,
 615                 0x358,
 616                 "CB_COLOR4_INFO"
 617         },
 618         {
 619                 reg_blk_ctx,
 620                 0x367,
 621                 "CB_COLOR5_INFO"
 622         },
 623         {
 624                 reg_blk_ctx,
 625                 0x376,
 626                 "CB_COLOR6_INFO"
 627         },
 628         {
 629                 reg_blk_ctx,
 630                 0x385,
 631                 "CB_COLOR7_INFO"
 632         },
 633 };
 634 #endif