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commit	1a84fe6928d29dd9e12783004341c434604a92f6
author	Rodrigo Peixoto <rodrigopex@urano.(none)>
	Fri, 18 Apr 2008 17:43:58 +0000 (18 14:43 -0300)
committer	Rodrigo Peixoto <rodrigopex@urano.(none)>
	Fri, 18 Apr 2008 17:43:58 +0000 (18 14:43 -0300)
tree	c22ab5aa950e46d2135217cb54c16f84d0b9cdfd	tree \| snapshot (tar.gz zip)
parent	adf4681032dc334c3d35e98680de5bd70066f384	commit \| diff

improves

17 files changed:

src/gen/b.mem	[new file with mode: 0644]	blob
src/gen/fulladder.v	[new file with mode: 0644]	blob
src/gen/makefile		diff \| blob \| blame \| history
src/gen/overflow.mem	[new file with mode: 0644]	blob
src/gen/result.mem	[new file with mode: 0644]	blob
src/gen/verilog.log		diff \| blob \| blame \| history
src/gen/vut_fulladder.v	[new file with mode: 0644]	blob
src/gen/waveform.vcd	[new file with mode: 0644]	blob
src/tags		diff \| blob \| blame \| history
src/testando.py	[new file with mode: 0644]	blob
src/utils.py		diff \| blob \| blame \| history
src/utils.pyc		diff \| blob \| blame \| history
src/vut_front_end.py	[changed mode: 0755->0644]	diff \| blob \| blame \| history
src/vut_front_end.pyc		diff \| blob \| blame \| history
src/vut_generator.py		diff \| blob \| blame \| history
src/vut_generator.pyc		diff \| blob \| blame \| history
src/waveform.vcd	[deleted file]	blob \| blame \| history

Verilog Unit Test generator