From 302b28447ef55ba01ad2f9ef50a95d8b4c5928fa Mon Sep 17 00:00:00 2001 From: Rodrigo Peixoto Date: Wed, 9 Apr 2008 01:06:40 -0300 Subject: [PATCH] melhorias. --- src/doc/.zim.cache | 4 +- src/doc/.zim.history.cache | 14 +++---- src/doc/grammar.txt | 14 +++---- src/gen/i_a.mem | 17 +++++++-- src/gen/i_b.mem | 14 +++++-- src/gen/o_overflow.mem | 1 + src/gen/o_result.mem | 9 +++-- src/gen/vut_fulladder.v | 91 +++++++++++++++++++++++++++++++++++++++++++++ src/teste.vut | 14 +++---- src/utils.py | 2 + src/utils.pyc | Bin 3895 -> 3856 bytes src/vut_checker.py | 2 +- src/vut_parser.py | 28 ++++++++++---- 13 files changed, 166 insertions(+), 44 deletions(-) create mode 100644 src/gen/vut_fulladder.v diff --git a/src/doc/.zim.cache b/src/doc/.zim.cache index 0c741e8..3fef852 100644 --- a/src/doc/.zim.cache +++ b/src/doc/.zim.cache @@ -1,4 +1,4 @@ zim: version 0.23 -: 1207598390 / -:grammar 1207708586 > +: 1207713294 / +:grammar 1207713294 > :VUTg 1207709463 > :Unit_Tests :grammar :verilog diff --git a/src/doc/.zim.history.cache b/src/doc/.zim.history.cache index dad0753..3aed456 100644 --- a/src/doc/.zim.history.cache +++ b/src/doc/.zim.history.cache @@ -1,10 +1,8 @@ zim: version 0.20 -point: 1 -hist: 5 +point: 2 +hist: 3 :Home 507 -:VUTg 556 -:grammar 0 -:VUTg 556 -:teste 36 -:grammar 0 -:VUTg 556 +:VUTg 702 +:grammar 4754 +:VUTg 702 +:grammar 4754 diff --git a/src/doc/grammar.txt b/src/doc/grammar.txt index 033d0ef..d10d5a1 100644 --- a/src/doc/grammar.txt +++ b/src/doc/grammar.txt @@ -99,11 +99,11 @@ There are two output signal formats, it is showed below. It will appear things l * Using high level language to substitute the reference model: - [sig_name] [bitslice] i@|val1|val2|val3|...|valk|ref_function(ref_f_name)| + [sig_name] [bitslice] i@|val1|val2|val3|...|valk|ref_function()| Examples: - data_out i@|1|0|1|1|0|0|1|1|1|0|1|ref_function(exp1)| - data [31:0] i@|ffa5e21d|00011ae2|ffffffff|bb03faa2|ref_function(tool3)| + data_out i@|1|0|1|1|0|0|1|1|1|0|1|ref_function()| + data [31:0] i@|ffa5e21d|00011ae2|ffffffff|bb03faa2|ref_function()| @@ -136,7 +136,7 @@ It appeared symbols called Rn where these "represent" random values. The random === Python code tag === This tag represents the reference model that will implement functions for emulating the module builded. You have to implement a Python function which executes the specification. For example a inc module that icrements 1 to the input value (input sinal name inp_val), the reference function must be "lambda inp_val: inp_val + 1" - + [...content...] @@ -157,9 +157,9 @@ It will necessary to implement a method called reference_model into the python f include_python_file("finonacci.py") include_python_file("fat.py") include_python_file("mod.py") - - - + + + ===== Examples ===== diff --git a/src/gen/i_a.mem b/src/gen/i_a.mem index 0463db2..17c8845 100644 --- a/src/gen/i_a.mem +++ b/src/gen/i_a.mem @@ -1,4 +1,13 @@ -0 -0 -1 -1 +00 +00 +FF +FF +R1 +R2 +R4 +R6 +R2 +random_alloc([R1,R2],10) +R1 +ff +ff diff --git a/src/gen/i_b.mem b/src/gen/i_b.mem index 5565ed6..9abd66d 100644 --- a/src/gen/i_b.mem +++ b/src/gen/i_b.mem @@ -1,4 +1,10 @@ -0 -1 -0 -1 +00 +FF +00 +FF +R3 +R4 +R1 +R1 +R5 +include_memory("teste.mem") diff --git a/src/gen/o_overflow.mem b/src/gen/o_overflow.mem index 530a8a7..0c87cfc 100644 --- a/src/gen/o_overflow.mem +++ b/src/gen/o_overflow.mem @@ -2,3 +2,4 @@ 0 0 1 +...tmp diff --git a/src/gen/o_result.mem b/src/gen/o_result.mem index f2599a7..3e0ec87 100644 --- a/src/gen/o_result.mem +++ b/src/gen/o_result.mem @@ -1,4 +1,5 @@ -0 -1 -1 -0 +00 +FF +FF +00 +...res diff --git a/src/gen/vut_fulladder.v b/src/gen/vut_fulladder.v new file mode 100644 index 0000000..07f38c0 --- /dev/null +++ b/src/gen/vut_fulladder.v @@ -0,0 +1,91 @@ + +/* +@The skeleton was generated by VUTGenerator@ +======================================= +module_name: vut_fulladder +--------------------------------------- +Author: +Data: +--------------------------------------- +Description: +======================================= +*/ + +module vut_fulladder(); +//Inputs + + +//Outputs + + +//Wires + wire [7:0] result; + wire overflow; + +//Regs + reg [7:0] a; + reg [7:0] b; + +//Behavior + + + reg [7:0] mem_a [0:12]; + reg [7:0] mem_b [0:9]; + reg [7:0] mem_result [0:4]; + reg mem_overflow [0:4]; + reg [7:0] tmp_result; + reg tmp_overflow; + integer k; + event send, ready; + + fulladder test( + .a(a), + .b(b), + .result(result), + .overflow(overflow)); + + initial $readmemh("i_a.mem",mem_a); + initial $readmemh("i_b.mem",mem_b); + initial $readmemh("o_result.mem",mem_result); + initial $readmemh("o_overflow.mem",mem_overflow); + + initial begin + $dumpfile ("waveform.vcd"); + $dumpvars; + #1; + a = 0; + b = 0; + k = -1; + #4 -> ready; + end + + + always @ ready begin + k = k + 1; + a = mem_a[k]; + b = mem_b[k]; + tmp_result = mem_result[k]; + tmp_overflow = mem_overflow[k]; + if (k >= 13) begin + $display("|VUT_OK| > All the signals are right-right!\n\n By Rodrigo Peixoto\n"); + #5 $finish; + end //if + else #2 -> send; + end + + + always @ send begin + if (result !== tmp_result) begin + $display("|VUT_FAIL|> Error in result value at time %0dns!!!",$time); + $finish; + end //if + if (overflow !== tmp_overflow) begin + $display("|VUT_FAIL|> Error in overflow value at time %0dns!!!",$time); + $finish; + end //if + #3 -> ready; + end + + + +endmodule diff --git a/src/teste.vut b/src/teste.vut index 9d5521d..fa8d5d2 100644 --- a/src/teste.vut +++ b/src/teste.vut @@ -7,9 +7,9 @@ -------------------------------------------- b[7:0] i@|00|FF|00|FF|R3|R4|R1|R1|R5|include_memory("teste.mem")| ============================================ - result[7:0]o@|00|FF|FF|00|...res| + result[7:0]o@|00|FF|FF|00|ref_function()| -------------------------------------------- - overflow o@|0 |0 |0 |1 |...tmp| + overflow o@|0 |0 |0 |1 |ref_function()| ============================================ @@ -17,13 +17,13 @@ R2 = (5,10A) R3 = (30,150) R4 = (2,6) - lambda a,b: a + b - include_python_file("teste.py") - - lambda a,b: (a+b) > 255 and 1 or 0 + lambda a,b: a + b + include_python_file("overflow.py") + # + # lambda a,b: (a+b) > 255 and 1 or 0 #Eh o mesmo que if (a + b) > 255: return 1; else: return 0 #uma estencao seria res = python_code_file{dut.py} - + # diff --git a/src/utils.py b/src/utils.py index f8ab3c5..69e2e16 100644 --- a/src/utils.py +++ b/src/utils.py @@ -23,6 +23,8 @@ class VerilogModule(object): self.time_slice=() #Must be ((division, unit) ,(precision, unit)) self.in_ports_behavior=[] self.out_ports_behavior=[] + self.ran_range = {} + self.ref_models = {} def set_in_ports_behavior(self, behav): self.in_ports_behavior=behav diff --git a/src/utils.pyc b/src/utils.pyc index bef13b5d88e8a0631db03e396f143cfc978ef611..0a1add8a49558aaaaf32fbfe26af7c2bf585a67f 100644 GIT binary patch delta 589 zcwXBsH$jel^Cw;|Y1=;=+5a*!`b=hJvQ*AsV5nhWh-YJfGT0eX7#M;zm>3us{4{_B zg9gWBf2L&F5>6nyC^0V{h|^O`xInzrwD{col+>K!$(xuo8O( z%*brODF8Bnk&}^gvKh0B6i81AE09P^%}6YR7!D$eF?7mLzQHWXB@2=RIfP-d1GB+o zZ5A$3kP$(=FpW5M_pwMZDokFYwgN~Rv#VlJ!WINFOLOufc2g-4kmZaZ0|~iBezGYCKcntsSB_K? zbjfK4fr8n90Tx({8lW%^5(E)KAOh?!aeQ843laudu(_Y}I}4-mydczUb= delta 648 zcwU@ol9Ay8RaG)WVtQCL9`~m5|G;X_@dN;qWE~l z$zND?RJcI)f_xFg3nKVX3?pQsJ|oBE32ZBXq$Rs5p0JW<1zDp$c|NqeK>;1F+$!B c3pu~DFbYo2 parsing waveform..." waves = map(str.strip, args[0].text.splitlines()) @@ -61,11 +69,10 @@ class VUTParser: print " parsing gen_with..." ran = map(str.strip, args[0].text.splitlines()) ran = [x for x in ran if((x!= "") and (x[0]!="#"))] - ran = self.clear_comments(ran) - + #ran = self.clear_comments(ran) for i in ran: - assert re.match(r'R\d+\*?( )*\=( )*\([0-9A-Fa-f]+\,[0-9A-Fa-f]+\)', i), "Invalid Attribution in %s" % i - + self.vmodule.ran_range[re.findall(r'R\d+', i)[0]] = (int(re.findall(r'[0-9A-Fa-f]+\,', i)[0][:-1],16), int(re.findall(r'[0-9A-Fa-f]+\s*\)', i)[0][:-1],16)) + print self.vmodule.ran_range for code in args[0].getchildren(): var = code.get("var") assert var, """Var not defined in python_code tag.\nUsage ...code...!""" @@ -126,14 +133,21 @@ Usage !""" def python_code_parser(self, pycode): #TODO: Ajsutar isso aqui!!! - print " parsing python code..." + print "checking python code..." code = self.clear_comments(pycode.splitlines()) code = [x for x in code if(x!= "")] - exec("\n".join(code)) + try: + if re.match(r"\s*include_python_file\(\"(((\/\w+)+|\.)\/)?\w+.py[oc]?\"\)\s*$",pycode): + print pycode.strip() + else: + exec("\n".join(code)) + print "Fetching reference model: ", "\n".join(code) + except: + print "Python reference model code error: ", sys.exc_info() if __name__ == '__main__': - test = VUTParser(sys.argv[1]) + test = VUTParser("teste.vut") vm = test.parse_all() VUTGenerator(vm).gen() -- 2.11.4.GIT