From 5036c18df105ac21e1db695b7d3cb81384518772 Mon Sep 17 00:00:00 2001 From: Rodrigo Peixoto Date: Tue, 8 Apr 2008 20:59:05 -0300 Subject: [PATCH] teste --- src/doc/.zim.cache | 4 ++ src/doc/.zim.config | 7 ++ src/doc/.zim.history.cache | 10 +++ src/doc/VUTg.txt | 155 +++++++++++++++++++++++++++++++++++++++++++ src/doc/grammar.txt | 138 ++++++++++++++++++++++++++++++++++++++ src/example1.vut | 14 ++++ src/gen/fulladder_1bit.v | 35 ++++++++++ src/gen/i_a.mem | 4 ++ src/gen/i_b.mem | 4 ++ src/gen/o_overflow.mem | 4 ++ src/gen/o_result.mem | 4 ++ src/gen/vut_fulladder_1bit.v | 91 +++++++++++++++++++++++++ src/teste.vut | 31 +++++++++ src/vut_checker.py | 17 ++++- src/vut_checker.pyc | Bin 5225 -> 5119 bytes src/vut_front_end.py | 2 +- 16 files changed, 517 insertions(+), 3 deletions(-) create mode 100644 src/doc/.zim.cache create mode 100644 src/doc/.zim.config create mode 100644 src/doc/.zim.history.cache create mode 100644 src/doc/VUTg.txt create mode 100644 src/doc/grammar.txt create mode 100644 src/example1.vut create mode 100644 src/gen/fulladder_1bit.v create mode 100644 src/gen/i_a.mem create mode 100644 src/gen/i_b.mem create mode 100644 src/gen/o_overflow.mem create mode 100644 src/gen/o_result.mem create mode 100644 src/gen/vut_fulladder_1bit.v create mode 100644 src/teste.vut diff --git a/src/doc/.zim.cache b/src/doc/.zim.cache new file mode 100644 index 0000000..caff09c --- /dev/null +++ b/src/doc/.zim.cache @@ -0,0 +1,4 @@ +zim: version 0.23 +: 1207598390 / +:VUTg 1207695871 > :Unit_Tests :grammar :verilog +:grammar 1207696516 > diff --git a/src/doc/.zim.config b/src/doc/.zim.config new file mode 100644 index 0000000..bacb5f8 --- /dev/null +++ b/src/doc/.zim.config @@ -0,0 +1,7 @@ +export_dir=/home/rodrigopex/Desktop/vut_doc +export_format=html +export_index=index_ +export_media=relative +export_template=Default +home=:Home +name=Verilog Unit Test Documentation diff --git a/src/doc/.zim.history.cache b/src/doc/.zim.history.cache new file mode 100644 index 0000000..fb33730 --- /dev/null +++ b/src/doc/.zim.history.cache @@ -0,0 +1,10 @@ +zim: version 0.20 +point: 2 +hist: 5 +:Home 507 +:VUTg 4191 +:grammar 4336 +:VUTg 4191 +:teste 36 +:grammar 4336 +:VUTg 4191 diff --git a/src/doc/VUTg.txt b/src/doc/VUTg.txt new file mode 100644 index 0000000..d5a06e1 --- /dev/null +++ b/src/doc/VUTg.txt @@ -0,0 +1,155 @@ +====== Verilog Unit Test Generator(VUTg) ====== + +This tool provides a easy way to build Test Benches ([[Unit_Tests]]) to [[verilog]] modules. Based on the rule file we can generate the tests. +This article explains how to use the Generator. //Verilog Unit Test Generator//(VUTg) is my conclusion work of the degree. This is homologade at the GPLCver Verilog compiler. My name is Rodrigo J. S. Peixoto. All is under GPL licence. Have a fun! + + +=== Rule File === +Describes the structure, behavior, high level reference model and range of the random values according with the [[grammar]]. The files are based on xml language and has the "vut" extension. Below we have a very simple example, the classic fulladder. + + + + + ===================== + a i@|0|0|1|1| + --------------------- + b i@|0|1|0|1| + ===================== + result o@|0|1|1|0| + --------------------- + overflow o@|0|0|0|1| + ===================== + + + +This example generates also the module's skeleton and its testbench. + + +=== Module's Skeleton === +It's one of the possible genetarion's results. The skeleton is described into rule file when the developer defines the input and output signals. At the before example we can observe that has define two input signal '**a**' and '**b**' both with just one bit. The outputs '**resul**' and '**overflow**' It is describe too. The VUTg can uses these information for providing a good module skeleton. Below it shows the skeleton of the fulladder_1bit. + + /* + @The skeleton was generated by VUTGenerator@ + ======================================= + module_name: fulladder_1bit + --------------------------------------- + Author: + Data: + --------------------------------------- + Description: + ======================================= + */ + + module fulladder_1bit(a,b,result,overflow); + //Inputs + input a; + input b; + + //Outputs + output overflow; + output result; + + //Wires + wire a; + wire b; + + //Regs + reg overflow; + reg result; + + //Behavior + U + + + endmodule + + +The developer just needs to code the beha‭vior section. + + +=== TestBench generated === +A test bench is a virtual environment used to verify the correctness or soundness of a design or model [[http://en.wikipedia.org/wiki/Test_bench|[1]]]. This testbench will run exactily the same behavior discribed in VUTg file simulating the desired environment. It has written in "high level" of verilog, this code is not syntetizable. Below it is the result of the same rule file, fulladder_1bit. + + + /* + @The skeleton was generated by VUTGenerator@ + ======================================= + module_name: vut_fulladder_1bit + --------------------------------------- + Author: + Data: + --------------------------------------- + Description: + ======================================= + */ + module vut_fulladder_1bit(); + //Wires + wire overflow; + wire result; + + //Regs + reg a; + reg b; + + //Behavior + + reg mem_a [0:3]; + reg mem_b [0:3]; + reg mem_overflow [0:3]; + reg mem_result [0:3]; + reg tmp_result; + reg tmp_overflow; + integer k; + event send, ready; + + fulladder_1bit test( + .a(a), + .b(b), + .result(result), + .overflow(overflow)); + + initial $readmemh("i_a.mem",mem_a); + initial $readmemh("i_b.mem",mem_b); + initial $readmemh("o_result.mem",mem_result); + initial $readmemh("o_overflow.mem",mem_overflow); + + initial begin + $dumpfile ("waveform.vcd"); + $dumpvars; + #1; + a = 0; + b = 0; + k = -1; + #4 -> ready; + end + + always @ ready begin + k = k + 1; + a = mem_a[k]; + b = mem_b[k]; + tmp_result = mem_result[k]; + tmp_overflow = mem_overflow[k]; + if (k >= 4) begin + $display("|VUT_OK| > All the signals are right-right!\n\n By Rodrigo Peixoto\n"); + #5 $finish; + end //if + else #2 -> send; + end + + always @ send begin + if (result !== tmp_result) begin + $display("|VUT_FAIL|> Error in result value at time %0dns!!!",$time); + $finish; + end //if + if (overflow !== tmp_overflow) begin + $display("|VUT_FAIL|> Error in overflow value at time %0dns!!!",$time); + $finish; + end //if + #3 -> ready; + end + + endmodule + + +=== References === +[1] Test Bench Wikipedia: http://en.wikipedia.org/wiki/Test_bench, last visit april 2008; diff --git a/src/doc/grammar.txt b/src/doc/grammar.txt new file mode 100644 index 0000000..984c80e --- /dev/null +++ b/src/doc/grammar.txt @@ -0,0 +1,138 @@ +====== VUTg Grammar ====== + +The VUTg is xml, it has tags and values. This section will describe the how to use well this tool. There are severals way to describe the virtual environment that you want to submit your module. Using the right tag with the correct value you can build complexes testbenches which will help you to descrease time in your design and it become fast tests building. + + +==== Basics tags ==== +All VUTg file must starts with the xml basic definition: + + + +The relevants definitions must be included in the vut tag, the **module name** must be write accoding the regexp //r'^[a-zA-z][a-zA-Z0-9_]*$'//, it just can starts with letters and only accepts the "_" special character. Examples: "module_name","Module_Name","moduleName","M_ODULEN_AME", and so on. + + + [//...Module definition...//] + + + + + +==== Waveform tag ==== +This tag is the module's behavior description. The tag is called waveform and must follow be as below: + + + ================================= + [...input signal 1...] + --------------------------------- + [...input signal 2...] + --------------------------------- + [...] + --------------------------------- + [...input signal k...] + ================================= + [...output signal 1...] + --------------------------------- + [...output signal 2...] + --------------------------------- + [...] + --------------------------------- + [...output signal k...] + ================================= + + + + + + +=== Input signal === +There are several input signal formats, it is showed below. It will appear random values called 'Rn', that values will be changed by the compiler for random values constrainted by the user. It will be explained in the future. + +* Simple and direct behavior description: + + [sig_name] [bitslice] i@|val1|val2|val3|...|valk| + + Examples: + a i@|1|0|1|1|0|0|1|1|1|0|1|1|0|0|1| + data [31:0] i@|ffa5e21d|00011ae2|ffffffff|bb03faa2| + + +* Manually defined random values: + + [sig_name] [bitslice] i@|val1|...|valk|R1|R2|R3|R2|R3|R3|R4|R4|...|Rk| + + Examples: + a i@|0|0|1|1|1|0|1|0|R1|R2|R3|R2|R2|R3|R1| + data [31:0] i@||ffa5e21d|00011ae2|ffffffff|R1|R2|R3|R2|R3| + + +* Random alocation to the random values, n it is how many times the random values will be applayed:// + + [sig_name] [bitslice] i@|val1|...|valk|random_alloc([R1,R2,...,Rk],n) + + Examples: + a i@|0|0|1|1|1|0|1|0|random_alloc([R1,R2,R3],100) + data [31:0] i@||ffa5e21d|00011ae2|ffffffff|random_alloc([R1,R2,R3,R5,R6,R7,R8,R9,R10],10000) + + +* Using memory to at the val's places + + [sig_name] [bitslice] i@|include_memory("memory_file.mem") + + Examples: + a i@|include_memory("in_a.mem") + data [31:0] i@|include_memory("in_data.mem") + + + + +=== Output signal === +There are two output signal formats, it is showed below. It will appear things like that "ref_function([...])" in the output signals, it will be explained in the future. + +* Simple and direct behavior description: + + [sig_name] [bitslice] o@|val1|val2|val3|...|valk| + + Examples: + overflow o@|1|0|1|1|0|0|1|1|1|0|1|1|0|0|1| + result [31:0] o@|ffa5e21d|00011ae2|ffffffff|bb03faa2| + + +* Using high level language to substitute the reference model: + + [sig_name] [bitslice] i@|val1|val2|val3|...|valk|ref_function(name_name) + + Examples: + data_out i@|1|0|1|1|0|0|1|1|1|0|1|ref_function(exp1) + data [31:0] i@|ffa5e21d|00011ae2|ffffffff|bb03faa2|ref_function(tool3) + + + +==== Gen_with tag ==== +This tag defines the "strange" things that appeared during the text + + + //Randrange values + [rand_name1] = (init_val,end_final) + [rand_name2] = (init_val,end_final) + [...] + [rand_namek] = (init_val,end_final) + + //Reference model functions + [...function1...] + [...function2...] + [...] + [...functionk...] + + +=== Randrange values === +It appeared symbols called Rn where these "represent" random values. The random values are responsible for generating the values used in waverform tag. All the times the values generated will be between the initial and de final values. Each time that the Rn is used the result is generated. The syntax to use it showed below: + Rn = (initial, final) + +=== Python code tag === +This tag represents the reference model that will implement functions for emulating the module builded. You have to implement a Python function which executes the specification. For example a inc module that icrements 1 to the input value (input sinal name inp_val), the reference function must be "lambda inp_val: inp_val + 1" + + +===== Examples ===== + +Eight bits register + diff --git a/src/example1.vut b/src/example1.vut new file mode 100644 index 0000000..4068c99 --- /dev/null +++ b/src/example1.vut @@ -0,0 +1,14 @@ + + + + ================================================================= + a [15:0] i@|0001|0000|ffff|ffff|1000|0001|0aaa|1230|f000|0a01| + ----------------------------------------------------------------- + b[15:0] i@|0001|ffff|0000|ffff|0020|0001|0aaa|0bbc|cb00|5050| + ================================================================= + result[15:0] o@|0002|ffff|ffff|fffe|1020|0002|1554|1dec|bb00|5a51| + ----------------------------------------------------------------- + overflow o@|0 |0 |0 |1 |0 |0 |0 |0 |1 |0 | + ================================================================= + + diff --git a/src/gen/fulladder_1bit.v b/src/gen/fulladder_1bit.v new file mode 100644 index 0000000..7453633 --- /dev/null +++ b/src/gen/fulladder_1bit.v @@ -0,0 +1,35 @@ + +/* +@The skeleton was generated by VUTGenerator@ +======================================= +module_name: fulladder_1bit +--------------------------------------- +Author: +Data: +--------------------------------------- +Description: +======================================= +*/ + +module fulladder_1bit(a,b,result,overflow); +//Inputs + input a; + input b; + +//Outputs + output overflow; + output result; + +//Wires + wire a; + wire b; + +//Regs + reg overflow; + reg result; + +//Behavior + + + +endmodule diff --git a/src/gen/i_a.mem b/src/gen/i_a.mem new file mode 100644 index 0000000..0463db2 --- /dev/null +++ b/src/gen/i_a.mem @@ -0,0 +1,4 @@ +0 +0 +1 +1 diff --git a/src/gen/i_b.mem b/src/gen/i_b.mem new file mode 100644 index 0000000..5565ed6 --- /dev/null +++ b/src/gen/i_b.mem @@ -0,0 +1,4 @@ +0 +1 +0 +1 diff --git a/src/gen/o_overflow.mem b/src/gen/o_overflow.mem new file mode 100644 index 0000000..530a8a7 --- /dev/null +++ b/src/gen/o_overflow.mem @@ -0,0 +1,4 @@ +0 +0 +0 +1 diff --git a/src/gen/o_result.mem b/src/gen/o_result.mem new file mode 100644 index 0000000..f2599a7 --- /dev/null +++ b/src/gen/o_result.mem @@ -0,0 +1,4 @@ +0 +1 +1 +0 diff --git a/src/gen/vut_fulladder_1bit.v b/src/gen/vut_fulladder_1bit.v new file mode 100644 index 0000000..2d5b568 --- /dev/null +++ b/src/gen/vut_fulladder_1bit.v @@ -0,0 +1,91 @@ + +/* +@The skeleton was generated by VUTGenerator@ +======================================= +module_name: vut_fulladder_1bit +--------------------------------------- +Author: +Data: +--------------------------------------- +Description: +======================================= +*/ + +module vut_fulladder_1bit(); +//Inputs + + +//Outputs + + +//Wires + wire overflow; + wire result; + +//Regs + reg a; + reg b; + +//Behavior + + + reg mem_a [0:3]; + reg mem_b [0:3]; + reg mem_overflow [0:3]; + reg mem_result [0:3]; + reg tmp_result; + reg tmp_overflow; + integer k; + event send, ready; + + fulladder_1bit test( + .a(a), + .b(b), + .result(result), + .overflow(overflow)); + + initial $readmemh("i_a.mem",mem_a); + initial $readmemh("i_b.mem",mem_b); + initial $readmemh("o_result.mem",mem_result); + initial $readmemh("o_overflow.mem",mem_overflow); + + initial begin + $dumpfile ("waveform.vcd"); + $dumpvars; + #1; + a = 0; + b = 0; + k = -1; + #4 -> ready; + end + + + always @ ready begin + k = k + 1; + a = mem_a[k]; + b = mem_b[k]; + tmp_result = mem_result[k]; + tmp_overflow = mem_overflow[k]; + if (k >= 4) begin + $display("|VUT_OK| > All the signals are right-right!\n\n By Rodrigo Peixoto\n"); + #5 $finish; + end //if + else #2 -> send; + end + + + always @ send begin + if (result !== tmp_result) begin + $display("|VUT_FAIL|> Error in result value at time %0dns!!!",$time); + $finish; + end //if + if (overflow !== tmp_overflow) begin + $display("|VUT_FAIL|> Error in overflow value at time %0dns!!!",$time); + $finish; + end //if + #3 -> ready; + end + + + +endmodule diff --git a/src/teste.vut b/src/teste.vut new file mode 100644 index 0000000..ea21621 --- /dev/null +++ b/src/teste.vut @@ -0,0 +1,31 @@ + + + + + ============================================ + a[7:0] i@|00|00|FF|FF|R1|R2|R4|R6|R2| + -------------------------------------------- + b[7:0] i@|00|FF|00|FF|R3|R4|R1|R1|R5 + ============================================ + result[7:0]o@|00|FF|FF|00|...res + -------------------------------------------- + overflow o@|0 |0 |0 |1 |...tmp + ============================================ + + + R1 = (0,255) + R2 = (5,10A) + R3 = (30,150) + R4 = (2,6) + R5* = (1000,100000) #o '*'indica uma entrada defeituosa + R6* = (222,555) #o '*' indica uma entrada defeituosa + + lambda a,b: a + b + + lambda a,b: (a+b) > 255 and 1 or 0 + #Eh o mesmo que if (a + b) > 255: return 1; else: return 0 + #uma estencao seria res = python_code_file{dut.py} + + + + diff --git a/src/vut_checker.py b/src/vut_checker.py index af2d77c..bb2b984 100644 --- a/src/vut_checker.py +++ b/src/vut_checker.py @@ -45,7 +45,20 @@ class VUTChercker: #print waves for signal in waves: #Regexp | signal name |separator| signal behavior | - assert re.match(r'(^[a-zA-z])\w*(( )*\[\d+\:\d+\])?( )*[io]\@( )*((\|[0-9A-Fa-f ]*)|(\|R\d+)|(\.\.\.[a-zA-Z][a-zA-Z0-9_]+))*$', signal),"Construction error in the signal: %s" % signal + #assert re.match(r'(^[a-zA-z])\w*(( )*\[\d+\:\d+\])?( )*[io]\@( )*((\|[0-9A-Fa-f ]*)|(\|R\d+)|(\.\.\.[a-zA-Z][a-zA-Z0-9_]+))*$', signal),"Construction error in the signal: %s" % signal + regexp = re.compile(r""" + (^[a-zA-z])\w* #signal name + (\s*\[\d+\:\d+\])?\s* #bit slice + [io]\@\s* #input or output definition + ( + (\|[0-9A-Fa-f ]*)| #hexa values + (\|R\d+)| #random value definition + (\.\.\.[a-zA-Z][a-zA-Z0-9_]+)| #reference function definition + (random_alloc\(\[(R\d+\,)\],\d+\))| + (include_memory\(\"\w*\.mem\"\)) #random randomic values allocation + )*$ + """,re.VERBOSE) + assert regexp.match(signal),"Construction error in the signal: %s" % signal #[a-zA-Z0-9_] = \w waves = map(lambda a : a.replace(" ", ""),waves) @@ -108,6 +121,6 @@ Usage !""" exec("\n".join(code)) if __name__ == '__main__': - test = VUTChercker(sys.argv[1]) + test = VUTChercker("teste.vut")#sys.argv[1]) test.check_all() diff --git a/src/vut_checker.pyc b/src/vut_checker.pyc index a5b0e0f72fd5ccce658a717661099434c9a4264b..05013f770fefdc06f42092aeac2ec05201ffe2d7 100644 GIT binary patch delta 348 zcwT#{@n2nf^Cw=e{FUF_lNq3Z4Tv3pxVUDbbexD317j*1LkcHDGb2M32SX|cLni0O zDc2bpZ6^!zif{xJ8nFr{?5ItoJd6RX6WplgFZbI~Jvrqj|YD z^KvmWV>2e2cL%ylz~XWIbFhlL3W{ThPh?V^yj&<8o3N*_hG;P-Ff2+^i%U}V%1TQ# bKp~{THMv$eYVreNNlZ;DlbuCWn0Ocg3T0mk delta 619 zcwYOj{!&AF^Cw=e!&48qCo@0+8xT7HadGoR={RXc2F6r2hE!&TOb&(=P6o+lMusR( zhEz_5Os_RXB