From 3320b176a40bc12402cb837758de6e5fd3be07bb Mon Sep 17 00:00:00 2001 From: Rodrigo Peixoto Date: Wed, 7 May 2008 22:50:11 -0300 Subject: [PATCH] Improving text messages. --- examples/fulladder/gen/fulladder.v | 2 +- examples/fulladder/gen/verilog.log | 2 +- examples/fulladder/overflow.pyc | Bin 648 -> 0 bytes examples/register/gen/verilog.log | 2 +- examples/register/out_data.py | 30 ++++++++++++++---------------- examples/register/out_data.pyc | Bin 1349 -> 1529 bytes examples/shifter/gen/shifterR.v | 8 -------- examples/shifter/gen/verilog.log | 2 +- examples/shifter/out_data.pyc | Bin 1306 -> 1294 bytes examples/shifter/shifterR.v~ | 8 ++++++-- src/utils.pyc | Bin 8387 -> 8387 bytes src/vut_checker.py | 8 +++++++- src/vut_checker.pyc | Bin 7987 -> 8132 bytes src/vut_front_end.py | 8 ++++---- src/vut_front_end.pyc | Bin 3544 -> 3571 bytes src/vut_generator.pyc | Bin 10196 -> 10196 bytes src/vut_parser.pyc | Bin 8275 -> 8275 bytes src/vutg | 5 ++++- 18 files changed, 39 insertions(+), 36 deletions(-) delete mode 100644 examples/fulladder/overflow.pyc rewrite examples/register/out_data.pyc (66%) diff --git a/examples/fulladder/gen/fulladder.v b/examples/fulladder/gen/fulladder.v index 85aa31d..d1a22da 100644 --- a/examples/fulladder/gen/fulladder.v +++ b/examples/fulladder/gen/fulladder.v @@ -30,6 +30,6 @@ module fulladder(a,b,result,overflow); //Behavior -always @ * {overflow,result} = a+b; +always @ * {overflow, result} = a + b; endmodule diff --git a/examples/fulladder/gen/verilog.log b/examples/fulladder/gen/verilog.log index 605252f..a58e7d1 100644 --- a/examples/fulladder/gen/verilog.log +++ b/examples/fulladder/gen/verilog.log @@ -2,7 +2,7 @@ GPLCVER_2.12a of 05/16/07 (Linux-elf). Copyright (c) 1991-2007 Pragmatic C Software Corp. All Rights reserved. Licensed under the GNU General Public License (GPL). See the 'COPYING' file for details. NO WARRANTY provided. -Today is Thu Apr 24 21:40:41 2008. +Today is Wed May 7 20:51:32 2008. Compiling source file "fulladder.v" Compiling source file "vut_fulladder.v" Highest level modules: diff --git a/examples/fulladder/overflow.pyc b/examples/fulladder/overflow.pyc deleted file mode 100644 index 841e9c2428b70746a27d5a3d15370329cf37f792..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcwPel00001 literal 648 zcwViLO-{ow5QS&lAEAf}2^Od)AS=uP5CXAbRiSpr28GxusggLdol;P`YH!4KH~?!d z05fj0VBbjdY|o6}eDUYcDEj(7c}QXZA;m3)8<8l0Ex;3P5N5HUOv?2hMW5oH`>sel zKpUFIya*U?1gsHMA5;&v2x|czp%u^~P-zwq=+eZqR}%Ck_=QJGpH9TsoUdy-Lcu&`xGeQ6x%fE6q~dtT1nv^}9bJm+s6!juU`GJi`cg(?o~# zk=J1@lREBoNnh@gNwb;`I=Dj;o`yfqwAEFrpR=Y)eQqj-a>KxSj>m&Zc(`fw58!|l Q;aRRrqnbkBgxT!<2b0r@)c^nh diff --git a/examples/register/gen/verilog.log b/examples/register/gen/verilog.log index 9043323..c57f31e 100644 --- a/examples/register/gen/verilog.log +++ b/examples/register/gen/verilog.log @@ -2,7 +2,7 @@ GPLCVER_2.12a of 05/16/07 (Linux-elf). Copyright (c) 1991-2007 Pragmatic C Software Corp. All Rights reserved. Licensed under the GNU General Public License (GPL). See the 'COPYING' file for details. NO WARRANTY provided. -Today is Thu Apr 24 21:43:14 2008. +Today is Wed May 7 22:49:40 2008. Compiling source file "register8b.v" Compiling source file "vut_register8b.v" Highest level modules: diff --git a/examples/register/out_data.py b/examples/register/out_data.py index cd76ff4..977d7dd 100644 --- a/examples/register/out_data.py +++ b/examples/register/out_data.py @@ -8,34 +8,32 @@ clear i@|random_alloc([R4],30)| ------------------------------------------------ load i@|random_alloc([R4],30)| """ -def max_lenght(signals): - ret = min(map(len,signals.itervalues())) +def min_lenght(signals): + ret = min(map(len, signals.itervalues())) print ret return ret -def reference_function(signals): - #ret = [0] - ret = [] - prev_clk = None - for step in range(max_lenght(signals)): +def fetch_signals(signals, step): + return (signals['clear'][step], signals['clk'][step], signals['load'][step], signals['in_data'][step]) - try: - prev_clk = signals['clk'][step-1] - except: - pass +def reference_function(signals): - if signals['clear'][step]: + ret = [] + prev_clk = 0 + for step in range(min_lenght(signals)): + clear, clk, load, in_data = fetch_signals(signals,step) + if clear: ret.append(0) - elif signals['clk'][step] and not prev_clk: - if signals['load'][step]: - ret.append(signals['in_data'][step]) + elif clk and not prev_clk: + if load: + ret.append(in_data) else: ret.append(ret[-1]) else: try: ret.append(ret[-1]) except: ret.append(0) - + prev_clk = clk return ret diff --git a/examples/register/out_data.pyc b/examples/register/out_data.pyc dissimilarity index 66% index 01fb87d5bae008bf045c4cd539f24440bad3e2cf..5548bf78c7073746990074d2ca016d1b3c3c9ffe 100644 GIT binary patch literal 1529 zcwVhk&2G~`5T3OYr!lQ)DLGUes0v6%N^wi+twNPRqFf^69*TgH9LRb=Y09GWIuSlaS%ei1j;^2`3O}6@D8D`fL8~o4jp>gbLgEmQ4N!9dImY4sm!#EXQE|s7NjFtI+RDZ zC`l4$L0Yn3A+#z~3M zT{Y4S%ai+V}4Nxl}a3V;Lh#!e8!HXuS zT|5j}RGWBOzqwT{c02ucdBJ}HYy1|SFFNqo{ZV!ogt(SRz+23Nm7m^+Bc>t&&`YS_ zZBieX0Fps_3r0f}9a{}!S zl_&eMkXb1G{wND|qOw(ry+IiaOITtREF^AAtccsJJBBGb!bHm!^|wc5`hKKB-@j_q dTmGZk`IKDJF!qKj8m00%jf1}|OSGG9^B4IZME(E( delta 576 zcwS{uO-sW-5S_^;X>FCZXj)^Xq6Z0{#JfWQ_vk@yf}k_$2NsvikbQ67?CjgG^i!(%@VSzD`N*C)FkMJdrs!?n6icFJ zsrQv{#By}2?TB92i5|7mSf;4p((X6gUeG$1X)f1eaS=6ixP?l=RY%OdQ)&T>5M0U% z^j|?DNCk!f*T~=T*)xm;4Dt-Q2}%E0?Xmy1lFdoIg>G{Prz9IHYaG##1y2S0|OTEF%flU@ZSIpiaLQcD@k{* zN3I|zsewR;DbkuPbbVXnu1*%F0b6CI(nrIMa5N0S> n); -end//always endmodule diff --git a/examples/shifter/gen/verilog.log b/examples/shifter/gen/verilog.log index 4e79522..65d830f 100644 --- a/examples/shifter/gen/verilog.log +++ b/examples/shifter/gen/verilog.log @@ -2,7 +2,7 @@ GPLCVER_2.12a of 05/16/07 (Linux-elf). Copyright (c) 1991-2007 Pragmatic C Software Corp. All Rights reserved. Licensed under the GNU General Public License (GPL). See the 'COPYING' file for details. NO WARRANTY provided. -Today is Thu Apr 24 21:28:40 2008. +Today is Tue Apr 29 13:59:09 2008. Compiling source file "shifterR.v" Compiling source file "vut_shifterR.v" Highest level modules: diff --git a/examples/shifter/out_data.pyc b/examples/shifter/out_data.pyc index d6b4f96bc143d0068c897a19a07a317016bb59eb..276723d664b0bdb30931e1659200e4003df2c569 100644 GIT binary patch delta 41 mcwU>u)yK8r2_vKR ======================================= */ -module shifterR(clk,in_data,enable,n,out_data); +module shifterR(clk,in_data,enable,reset,n,out_data); //Inputs input [2:0] n; input [7:0] in_data; input clk; input enable; + input reset; //Outputs output [7:0] out_data; @@ -26,6 +27,7 @@ module shifterR(clk,in_data,enable,n,out_data); wire [7:0] in_data; wire clk; wire enable; + wire reset; //Regs reg [7:0] out_data; @@ -36,7 +38,9 @@ module shifterR(clk,in_data,enable,n,out_data); initial out_data <= 0; always @ (posedge clk) begin - if (enable) + if (reset) + out_data <= 0; + else if (enable) out_data <= (in_data >> n); end//always diff --git a/src/utils.pyc b/src/utils.pyc index fe2c139e93483edc21fd561577a5f89f8ed6f055..2d962a174c5093454f4d563af5aa8ce16ff70c16 100644 GIT binary patch delta 16 XcwRf~c-WDB^Cw;|6;Gv&?0XadI1vT! delta 16 XcwRf~c-WDB^Cw=e7Dd60?0XadIcx?N diff --git a/src/vut_checker.py b/src/vut_checker.py index 2943224..8aebf36 100644 --- a/src/vut_checker.py +++ b/src/vut_checker.py @@ -40,10 +40,16 @@ psyco.full() class InvalidTagException(Exception): pass + class VUTChercker: def __init__(self, xml_source): - self.vut = ElementTree(file=xml_source) + try: + print "Openning the vut file..." + self.vut = ElementTree(file=xml_source) + except IOError: + print "|VUT Error| > The file %s is not exists!" % xml_source + raise StopGeneration() self.root = self.vut.getroot() mod = self.root.get("module_name") #assert mod, """Module name not defined in vut tag. Usage '...'""" diff --git a/src/vut_checker.pyc b/src/vut_checker.pyc index 4705cc163ebc6d02330ce2ca218bc9402649dc37..0388d8bb72e3ff8fdc6e140f7401c96be746ff57 100644 GIT binary patch delta 827 zcwSYK&ubG=5XWaW$?hg3>85F7er%d&YibmYMXU;9B(x!^poMMy0U{#ZZMq?DLUt<_ zQVPvQL_GNX54?(?E1o^5H^Kixym}XXlg1Jk-iKl4JMTL?Jiq$+n&SV8MK-U`y;JVX z`!WD5i{ri**v*59&}e!9rUV0oA>aVu0m2=p1VK-Nb_BXvK=GLY5~PJVAY^cW;7EXX zh1^E4gOsDz5YY~SErThN2z%mU33}6jW(XSl6YU7-DPXH$$|M<%RSGoz7n$nV*#uZG zhsE4C-HhN`&vG2wX)$lxVvlz`wqM%y1F)MFi`Y!T`lmcI!sq+YqJ7?0SsXp;~2&`|E7LG zjUR-!u;%{^|CUkbKeSG6o75yOM+A&C;TR#qA0>3r_bj1nQ z<>$;WcNQ&|6o_rPHujDSvY6fEh4^vym%*NVIMH)&!vjkzt02mN100vXC#q~o&#sQ= zA>h~~Srla3-sNlYH~R}49+YDIs&tx99oY?>08RofU;%mgqddboS#p}S0)!?;iUHr> z*cLNTTEL{dM) zyVS5p_d5~>ECO?KrGDK)rH>&Rsj<9#UBA1KL@gskM@V0#9K7d)UQggx6Da^if#D>@ Wu-gyCqB^l7Uo@JgR(x)8j{gEM{&)@m diff --git a/src/vut_front_end.py b/src/vut_front_end.py index b0fb9a1..f38062a 100644 --- a/src/vut_front_end.py +++ b/src/vut_front_end.py @@ -58,7 +58,7 @@ def run_vut_generator(args=[]): #arg = "example5.vut" #args = sys.argv flags = verify_parameters(args) - print flags + #print flags lflags = len(flags) gen_param = [] try: @@ -69,7 +69,7 @@ def run_vut_generator(args=[]): try: gen_param = flags['gen'] - assert set(gen_param).issubset(set(ARGS_CAN_BE)), "Error, the gen's values are wrong!" + assert set(gen_param).issubset(set(ARGS_CAN_BE)), "|VUT ERROR| > The gen's values are wrong!" except KeyError: if lflags == 2: raise InvalidArgumentException() @@ -99,8 +99,8 @@ def run_vut_generator(args=[]): print u"\n\nGeneration complete @VUTGenerator." except InvalidArgumentException: - print "The arguments are not valid. Please, check it out." - print "Usage: ./vutg gen=, vut_file=" + print "|VUT ERROR| > The arguments are not valid. Please, check it out." + print "|VUT INFO| > Usage: ./vutg gen=, vut_file=" except KeyboardInterrupt: print u"\n\nGeneration interrupted! @VUTGenerator." diff --git a/src/vut_front_end.pyc b/src/vut_front_end.pyc index 9f60048899cc22ec159614c90f5af574e6fa78b9..8425647dc35376385a95262daa8e43c75e3c3fe4 100644 GIT binary patch delta 128 zcwW09{aKoQ^Cw;|g8-$C>|yKz{)`L^B@7HT3=GYT47H35lZ)6FF>aeI%5hLwlL06m z78;`98WiLoRHI<05VH9ZM;W7#1BS%p7%pQ$cbKrJpPN5Obn|4clZ+fTKw$=E9;VG{ HJVlHEc32=J delta 101 zcwYM~eM6dk^Cw=eFQ51~vWKyYhA=WPlrS*VFfcSTGSo6M)G#u*drZz{U&Oe3vH-_H z9wi0_2G^pZ{30ENlFd&z${1OUfFhG~xQtn>fQ-!>xK1*1*#TJ$%sh;&jGG&IiWmW$ C>KP6I diff --git a/src/vut_generator.pyc b/src/vut_generator.pyc index 3fd2da5d2229a8f8f2b81d6d84178a5680fb116a..98e398992b5d2119e7facbb36f3830cf2f646020 100644 GIT binary patch delta 16 XcwW2Wf5o4D^Cw;|6;Gv&>}S;hJHQ4- delta 16 XcwW2Wf5o4D^Cw;|dqu&G>}S;hJ2(a> diff --git a/src/vut_parser.pyc b/src/vut_parser.pyc index 79623aaecf9213615fd3e56176d74988794f8850..5aab42815e65117c37234c00a4ad06696b6d73d6 100644 GIT binary patch delta 16 XcwW2gaM^)<^Cw;|6;Gv&>^=$rIQ0dc delta 16 YcwW2gaM^)<^Cw=e+n@M1vim3i06~og>Hq)$ diff --git a/src/vutg b/src/vutg index 4e4814f..a84921f 100755 --- a/src/vutg +++ b/src/vutg @@ -51,6 +51,9 @@ def organize_time(secs): if __name__=="__main__": psyco.full() i = time.time() - vut_front_end.run_vut_generator(sys.argv) + try: + vut_front_end.run_vut_generator(sys.argv) + except: + print "|VUT Error| > ", sys.exc_info()[1] f = time.time() print "Gen duration = %02.f:%02.f:%02.f" % organize_time(f-i) -- 2.11.4.GIT