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Add AppDefaults app selection to control panel
[wine/gsoc-2012-control.git] / programs / winedbg / be_x86_64.c
blob7fae50cd85650d86c80502db7f2750e92ec93d3c
1 /*
2 * Debugger x86_64 specific functions
3 *
4 * Copyright 2004 Vincent Béron
5 * Copyright 2009 Eric Pouech
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA
20 */
21
22 #include "debugger.h"
23 #include "wine/debug.h"
24
25 WINE_DEFAULT_DEBUG_CHANNEL(winedbg);
26
27 #if defined(__x86_64__)
28
29 #define STEP_FLAG 0x00000100 /* single step flag */
30
31 static unsigned be_x86_64_get_addr(HANDLE hThread, const CONTEXT* ctx,
32 enum be_cpu_addr bca, ADDRESS64* addr)
33 {
34 addr->Mode = AddrModeFlat;
35 switch (bca)
36 {
37 case be_cpu_addr_pc:
38 addr->Segment = ctx->SegCs;
39 addr->Offset = ctx->Rip;
40 return TRUE;
41 case be_cpu_addr_stack:
42 addr->Segment = ctx->SegSs;
43 addr->Offset = ctx->Rsp;
44 return TRUE;
45 case be_cpu_addr_frame:
46 addr->Segment = ctx->SegSs;
47 addr->Offset = ctx->Rbp;
48 return TRUE;
49 default:
50 addr->Mode = -1;
51 return FALSE;
52 }
53 }
54
55 static unsigned be_x86_64_get_register_info(int regno, enum be_cpu_addr* kind)
56 {
57 /* this is true when running in 32bit mode... and wrong in 64 :-/ */
58 switch (regno)
59 {
60 case CV_AMD64_RIP: *kind = be_cpu_addr_pc; return TRUE;
61 case CV_AMD64_EBP: *kind = be_cpu_addr_frame; return TRUE;
62 case CV_AMD64_ESP: *kind = be_cpu_addr_stack; return TRUE;
63 }
64 return FALSE;
65 }
66
67 static void be_x86_64_single_step(CONTEXT* ctx, unsigned enable)
68 {
69 if (enable) ctx->EFlags |= STEP_FLAG;
70 else ctx->EFlags &= ~STEP_FLAG;
71 }
72
73 static inline long double m128a_to_longdouble(const M128A m)
74 {
75 /* gcc uses the same IEEE-754 representation as M128A for long double
76 * but 16 byte aligned (hence only the first 10 bytes out of the 16 are used)
77 */
78 return *(long double*)&m;
79 }
80
81 static void be_x86_64_print_context(HANDLE hThread, const CONTEXT* ctx,
82 int all_regs)
83 {
84 static const char mxcsr_flags[16][4] = { "IE", "DE", "ZE", "OE", "UE", "PE", "DAZ", "IM",
85 "DM", "ZM", "OM", "UM", "PM", "R-", "R+", "FZ" };
86 static const char flags[] = "aVR-N--ODITSZ-A-P-C";
87 char buf[33];
88 int i;
89
90 strcpy(buf, flags);
91 for (i = 0; buf[i]; i++)
92 if (buf[i] != '-' && !(ctx->EFlags & (1 << (sizeof(flags) - 2 - i))))
93 buf[i] = ' ';
94
95 dbg_printf("Register dump:\n");
96 dbg_printf(" rip:%016lx rsp:%016lx rbp:%016lx eflags:%08x (%s)\n",
97 ctx->Rip, ctx->Rsp, ctx->Rbp, ctx->EFlags, buf);
98 dbg_printf(" rax:%016lx rbx:%016lx rcx:%016lx rdx:%016lx\n",
99 ctx->Rax, ctx->Rbx, ctx->Rcx, ctx->Rdx);
100 dbg_printf(" rsi:%016lx rdi:%016lx r8:%016lx r9:%016lx r10:%016lx\n",
101 ctx->Rsi, ctx->Rdi, ctx->R8, ctx->R9, ctx->R10 );
102 dbg_printf(" r11:%016lx r12:%016lx r13:%016lx r14:%016lx r15:%016lx\n",
103 ctx->R11, ctx->R12, ctx->R13, ctx->R14, ctx->R15 );
104
105 if (!all_regs) return;
106
107 dbg_printf(" cs:%04x ds:%04x es:%04x fs:%04x gs:%04x ss:%04x\n",
108 ctx->SegCs, ctx->SegDs, ctx->SegEs, ctx->SegFs, ctx->SegGs, ctx->SegSs );
109
110 dbg_printf("Debug:\n");
111 dbg_printf(" dr0:%016lx dr1:%016lx dr2:%016lx dr3:%016lx\n",
112 ctx->Dr0, ctx->Dr1, ctx->Dr2, ctx->Dr3 );
113 dbg_printf(" dr6:%016lx dr7:%016lx\n", ctx->Dr6, ctx->Dr7 );
114
115 dbg_printf("Floating point:\n");
116 dbg_printf(" flcw:%04x ", LOWORD(ctx->u.FltSave.ControlWord));
117 dbg_printf(" fltw:%04x ", LOWORD(ctx->u.FltSave.TagWord));
118 dbg_printf(" flsw:%04x", LOWORD(ctx->u.FltSave.StatusWord));
119
120 dbg_printf("(cc:%d%d%d%d", (ctx->u.FltSave.StatusWord & 0x00004000) >> 14,
121 (ctx->u.FltSave.StatusWord & 0x00000400) >> 10,
122 (ctx->u.FltSave.StatusWord & 0x00000200) >> 9,
123 (ctx->u.FltSave.StatusWord & 0x00000100) >> 8);
124
125 dbg_printf(" top:%01x", (unsigned int) (ctx->u.FltSave.StatusWord & 0x00003800) >> 11);
126
127 if (ctx->u.FltSave.StatusWord & 0x00000001) /* Invalid Fl OP */
128 {
129 if (ctx->u.FltSave.StatusWord & 0x00000040) /* Stack Fault */
130 {
131 if (ctx->u.FltSave.StatusWord & 0x00000200) /* C1 says Overflow */
132 dbg_printf(" #IE(Stack Overflow)");
133 else
134 dbg_printf(" #IE(Stack Underflow)"); /* Underflow */
135 }
136 else dbg_printf(" #IE(Arithmetic error)"); /* Invalid Fl OP */
137 }
138 if (ctx->u.FltSave.StatusWord & 0x00000002) dbg_printf(" #DE"); /* Denormalised OP */
139 if (ctx->u.FltSave.StatusWord & 0x00000004) dbg_printf(" #ZE"); /* Zero Divide */
140 if (ctx->u.FltSave.StatusWord & 0x00000008) dbg_printf(" #OE"); /* Overflow */
141 if (ctx->u.FltSave.StatusWord & 0x00000010) dbg_printf(" #UE"); /* Underflow */
142 if (ctx->u.FltSave.StatusWord & 0x00000020) dbg_printf(" #PE"); /* Precision error */
143 if (ctx->u.FltSave.StatusWord & 0x00000040)
144 if (!(ctx->u.FltSave.StatusWord & 0x00000001))
145 dbg_printf(" #SE"); /* Stack Fault (don't think this can occur) */
146 if (ctx->u.FltSave.StatusWord & 0x00000080) dbg_printf(" #ES"); /* Error Summary */
147 if (ctx->u.FltSave.StatusWord & 0x00008000) dbg_printf(" #FB"); /* FPU Busy */
148 dbg_printf(")\n");
149 dbg_printf(" flerr:%04x:%08x fldata:%04x:%08x\n",
150 ctx->u.FltSave.ErrorSelector, ctx->u.FltSave.ErrorOffset,
151 ctx->u.FltSave.DataSelector, ctx->u.FltSave.DataOffset );
152
153 for (i = 0; i < 4; i++)
154 {
155 dbg_printf(" st%u:%-16Lg ", i, m128a_to_longdouble(ctx->u.FltSave.FloatRegisters[i]));
156 }
157 dbg_printf("\n");
158 for (i = 4; i < 8; i++)
159 {
160 dbg_printf(" st%u:%-16Lg ", i, m128a_to_longdouble(ctx->u.FltSave.FloatRegisters[i]));
161 }
162 dbg_printf("\n");
163
164 dbg_printf(" mxcsr: %04x (", ctx->u.FltSave.MxCsr );
165 for (i = 0; i < 16; i++)
166 if (ctx->u.FltSave.MxCsr & (1 << i)) dbg_printf( " %s", mxcsr_flags[i] );
167 dbg_printf(" )\n");
168
169 for (i = 0; i < 16; i++)
170 {
171 dbg_printf( " %sxmm%u: uint=%016lx%016lx", (i > 9) ? "" : " ", i,
172 ctx->u.FltSave.XmmRegisters[i].High, ctx->u.FltSave.XmmRegisters[i].Low );
173 dbg_printf( " double={%g; %g}", *(double *)&ctx->u.FltSave.XmmRegisters[i].Low,
174 *(double *)&ctx->u.FltSave.XmmRegisters[i].High );
175 dbg_printf( " float={%g; %g; %g; %g}\n",
176 (double)*((float *)&ctx->u.FltSave.XmmRegisters[i] + 0),
177 (double)*((float *)&ctx->u.FltSave.XmmRegisters[i] + 1),
178 (double)*((float *)&ctx->u.FltSave.XmmRegisters[i] + 2),
179 (double)*((float *)&ctx->u.FltSave.XmmRegisters[i] + 3) );
180 }
181 }
182
183 static void be_x86_64_print_segment_info(HANDLE hThread, const CONTEXT* ctx)
184 {
185 }
186
187 static struct dbg_internal_var be_x86_64_ctx[] =
188 {
189 {CV_AMD64_AL, "AL", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rax), dbg_itype_unsigned_char_int},
190 {CV_AMD64_BL, "BL", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbx), dbg_itype_unsigned_char_int},
191 {CV_AMD64_CL, "CL", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rcx), dbg_itype_unsigned_char_int},
192 {CV_AMD64_DL, "DL", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdx), dbg_itype_unsigned_char_int},
193 {CV_AMD64_AH, "AH", (DWORD_PTR*)(FIELD_OFFSET(CONTEXT, Rax)+1), dbg_itype_unsigned_char_int},
194 {CV_AMD64_BH, "BH", (DWORD_PTR*)(FIELD_OFFSET(CONTEXT, Rbx)+1), dbg_itype_unsigned_char_int},
195 {CV_AMD64_CH, "CH", (DWORD_PTR*)(FIELD_OFFSET(CONTEXT, Rcx)+1), dbg_itype_unsigned_char_int},
196 {CV_AMD64_DH, "DH", (DWORD_PTR*)(FIELD_OFFSET(CONTEXT, Rdx)+1), dbg_itype_unsigned_char_int},
197 {CV_AMD64_AX, "AX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rax), dbg_itype_unsigned_short_int},
198 {CV_AMD64_BX, "BX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbx), dbg_itype_unsigned_short_int},
199 {CV_AMD64_CX, "CX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rcx), dbg_itype_unsigned_short_int},
200 {CV_AMD64_DX, "DX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdx), dbg_itype_unsigned_short_int},
201 {CV_AMD64_SP, "SP", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rsp), dbg_itype_unsigned_short_int},
202 {CV_AMD64_BP, "BP", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbp), dbg_itype_unsigned_short_int},
203 {CV_AMD64_SI, "SI", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rsi), dbg_itype_unsigned_short_int},
204 {CV_AMD64_DI, "DI", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdi), dbg_itype_unsigned_short_int},
205 {CV_AMD64_EAX, "EAX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rax), dbg_itype_unsigned_int},
206 {CV_AMD64_EBX, "EBX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbx), dbg_itype_unsigned_int},
207 {CV_AMD64_ECX, "ECX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rcx), dbg_itype_unsigned_int},
208 {CV_AMD64_EDX, "EDX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdx), dbg_itype_unsigned_int},
209 {CV_AMD64_ESP, "ESP", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rsp), dbg_itype_unsigned_int},
210 {CV_AMD64_EBP, "EBP", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbp), dbg_itype_unsigned_int},
211 {CV_AMD64_ESI, "ESI", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rsi), dbg_itype_unsigned_int},
212 {CV_AMD64_EDI, "EDI", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdi), dbg_itype_unsigned_int},
213 {CV_AMD64_ES, "ES", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, SegEs), dbg_itype_unsigned_short_int},
214 {CV_AMD64_CS, "CS", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, SegCs), dbg_itype_unsigned_short_int},
215 {CV_AMD64_SS, "SS", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, SegSs), dbg_itype_unsigned_short_int},
216 {CV_AMD64_DS, "DS", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, SegDs), dbg_itype_unsigned_short_int},
217 {CV_AMD64_FS, "FS", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, SegFs), dbg_itype_unsigned_short_int},
218 {CV_AMD64_GS, "GS", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, SegGs), dbg_itype_unsigned_short_int},
219 {CV_AMD64_FLAGS, "FLAGS", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, EFlags), dbg_itype_unsigned_short_int},
220 {CV_AMD64_EFLAGS, "EFLAGS", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, EFlags), dbg_itype_unsigned_int},
221 {CV_AMD64_RIP, "RIP", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rip), dbg_itype_unsigned_long_int},
222 {CV_AMD64_RAX, "RAX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rax), dbg_itype_unsigned_long_int},
223 {CV_AMD64_RBX, "RBX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbx), dbg_itype_unsigned_long_int},
224 {CV_AMD64_RCX, "RCX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rcx), dbg_itype_unsigned_long_int},
225 {CV_AMD64_RDX, "RDX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdx), dbg_itype_unsigned_long_int},
226 {CV_AMD64_RSP, "RSP", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rsp), dbg_itype_unsigned_long_int},
227 {CV_AMD64_RBP, "RBP", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbp), dbg_itype_unsigned_long_int},
228 {CV_AMD64_RSI, "RSI", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rsi), dbg_itype_unsigned_long_int},
229 {CV_AMD64_RDI, "RDI", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdi), dbg_itype_unsigned_long_int},
230 {CV_AMD64_R8, "R8", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R8), dbg_itype_unsigned_long_int},
231 {CV_AMD64_R9, "R9", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R9), dbg_itype_unsigned_long_int},
232 {CV_AMD64_R10, "R10", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R10), dbg_itype_unsigned_long_int},
233 {CV_AMD64_R11, "R11", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R11), dbg_itype_unsigned_long_int},
234 {CV_AMD64_R12, "R12", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R12), dbg_itype_unsigned_long_int},
235 {CV_AMD64_R13, "R13", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R13), dbg_itype_unsigned_long_int},
236 {CV_AMD64_R14, "R14", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R14), dbg_itype_unsigned_long_int},
237 {CV_AMD64_R15, "R15", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R15), dbg_itype_unsigned_long_int},
238 {0, NULL, 0, dbg_itype_none}
239 };
240
241 #define f_mod(b) ((b)>>6)
242 #define f_reg(b) (((b)>>3)&0x7)
243 #define f_rm(b) ((b)&0x7)
244
245 static unsigned be_x86_64_is_step_over_insn(const void* insn)
246 {
247 BYTE ch;
248
249 for (;;)
250 {
251 if (!dbg_read_memory(insn, &ch, sizeof(ch))) return FALSE;
252
253 switch (ch)
254 {
255 /* Skip all prefixes */
256 case 0x2e: /* cs: */
257 case 0x36: /* ss: */
258 case 0x3e: /* ds: */
259 case 0x26: /* es: */
260 case 0x64: /* fs: */
261 case 0x65: /* gs: */
262 case 0x66: /* opcode size prefix */
263 case 0x67: /* addr size prefix */
264 case 0xf0: /* lock */
265 case 0xf2: /* repne */
266 case 0xf3: /* repe */
267 insn = (const char*)insn + 1;
268 continue;
269
270 /* Handle call instructions */
271 case 0xcd: /* int <intno> */
272 case 0xe8: /* call <offset> */
273 case 0x9a: /* lcall <seg>:<off> */
274 return TRUE;
275
276 case 0xff: /* call <regmodrm> */
277 if (!dbg_read_memory((const char*)insn + 1, &ch, sizeof(ch)))
278 return FALSE;
279 return (((ch & 0x38) == 0x10) || ((ch & 0x38) == 0x18));
280
281 /* Handle string instructions */
282 case 0x6c: /* insb */
283 case 0x6d: /* insw */
284 case 0x6e: /* outsb */
285 case 0x6f: /* outsw */
286 case 0xa4: /* movsb */
287 case 0xa5: /* movsw */
288 case 0xa6: /* cmpsb */
289 case 0xa7: /* cmpsw */
290 case 0xaa: /* stosb */
291 case 0xab: /* stosw */
292 case 0xac: /* lodsb */
293 case 0xad: /* lodsw */
294 case 0xae: /* scasb */
295 case 0xaf: /* scasw */
296 return TRUE;
297
298 default:
299 return FALSE;
300 }
301 }
302 }
303
304 static unsigned be_x86_64_is_function_return(const void* insn)
305 {
306 BYTE c;
307
308 /* sigh... amd64 for prefetch optimization requires 'rep ret' in some cases */
309 if (!dbg_read_memory(insn, &c, sizeof(c))) return FALSE;
310 if (c == 0xF3) /* REP */
311 {
312 insn = (const char*)insn + 1;
313 if (!dbg_read_memory(insn, &c, sizeof(c))) return FALSE;
314 }
315 return c == 0xC2 /* ret */ || c == 0xC3 /* ret NN */;
316 }
317
318 static unsigned be_x86_64_is_break_insn(const void* insn)
319 {
320 BYTE c;
321 return dbg_read_memory(insn, &c, sizeof(c)) && c == 0xCC;
322 }
323
324 static BOOL fetch_value(const char* addr, unsigned sz, int* value)
325 {
326 char value8;
327 short value16;
328
329 switch (sz)
330 {
331 case 8:
332 if (!dbg_read_memory(addr, &value8, sizeof(value8))) return FALSE;
333 *value = value8;
334 break;
335 case 16:
336 if (!dbg_read_memory(addr, &value16, sizeof(value16))) return FALSE;
337 *value = value16;
338 case 32:
339 if (!dbg_read_memory(addr, value, sizeof(*value))) return FALSE;
340 break;
341 default: return FALSE;
342 }
343 return TRUE;
344 }
345
346 static unsigned be_x86_64_is_func_call(const void* insn, ADDRESS64* callee)
347 {
348 BYTE ch;
349 LONG delta;
350 short segment;
351 unsigned op_size = 32, rex = 0;
352 DWORD64 dst;
353
354 /* we assume 64bit mode all over the place */
355 for (;;)
356 {
357 if (!dbg_read_memory(insn, &ch, sizeof(ch))) return FALSE;
358 if (ch == 0x66) op_size = 16;
359 else if (ch == 0x67) WINE_FIXME("prefix not supported %x\n", ch);
360 else if (ch >= 0x40 && ch <= 0x4f) rex = ch & 0xf;
361 else break;
362 insn = (const char*)insn + 1;
363 } while (0);
364
365 /* that's the only mode we support anyway */
366 callee->Mode = AddrModeFlat;
367 callee->Segment = dbg_context.SegCs;
368
369 switch (ch)
370 {
371 case 0xe8: /* relative near call */
372 assert(op_size == 32);
373 if (!fetch_value((const char*)insn + 1, sizeof(delta), &delta))
374 return FALSE;
375 callee->Offset = (DWORD_PTR)insn + 1 + 4 + delta;
376 return TRUE;
377
378 case 0xff:
379 if (!dbg_read_memory((const char*)insn + 1, &ch, sizeof(ch)))
380 return FALSE;
381 WINE_TRACE("Got 0xFF %x (&C7=%x) with rex=%x\n", ch, ch & 0xC7, rex);
382 /* keep only the CALL and LCALL insn:s */
383 switch (f_reg(ch))
384 {
385 case 0x02:
386 segment = dbg_context.SegCs;
387 break;
388 default: return FALSE;
389 }
390 if (rex == 0) switch (ch & 0xC7) /* keep Mod R/M only (skip reg) */
391 {
392 case 0x04:
393 case 0x44:
394 case 0x84:
395 WINE_FIXME("Unsupported yet call insn (0xFF 0x%02x) (SIB bytes) at %p\n", ch, insn);
396 return FALSE;
397 case 0x05: /* addr32 */
398 if (f_reg(ch) == 0x2)
399 {
400 /* rip-relative to next insn */
401 if (!dbg_read_memory((const char*)insn + 2, &delta, sizeof(delta)) ||
402 !dbg_read_memory((const char*)insn + 6 + delta, &dst, sizeof(dst)))
403 return FALSE;
404
405 callee->Offset = dst;
406 return TRUE;
407 }
408 WINE_FIXME("Unsupported yet call insn (0xFF 0x%02x) at %p\n", ch, insn);
409 return FALSE;
410 default:
411 switch (f_rm(ch))
412 {
413 case 0x00: dst = dbg_context.Rax; break;
414 case 0x01: dst = dbg_context.Rcx; break;
415 case 0x02: dst = dbg_context.Rdx; break;
416 case 0x03: dst = dbg_context.Rbx; break;
417 case 0x04: dst = dbg_context.Rsp; break;
418 case 0x05: dst = dbg_context.Rbp; break;
419 case 0x06: dst = dbg_context.Rsi; break;
420 case 0x07: dst = dbg_context.Rdi; break;
421 }
422 if (f_mod(ch) != 0x03)
423 WINE_FIXME("Unsupported yet call insn (0xFF 0x%02x) at %p\n", ch, insn);
424 else
425 {
426 callee->Offset = dst;
427 }
428 break;
429 }
430 else
431 WINE_FIXME("Unsupported yet call insn (rex=0x%02x 0xFF 0x%02x) at %p\n", rex, ch, insn);
432 return FALSE;
433
434 default:
435 return FALSE;
436 }
437 }
438
439 static unsigned be_x86_64_is_jump(const void* insn, ADDRESS64* jumpee)
440 {
441 return FALSE;
442 }
443
444 extern void be_x86_64_disasm_one_insn(ADDRESS64* addr, int display);
445
446 #define DR7_CONTROL_SHIFT 16
447 #define DR7_CONTROL_SIZE 4
448
449 #define DR7_RW_EXECUTE (0x0)
450 #define DR7_RW_WRITE (0x1)
451 #define DR7_RW_READ (0x3)
452
453 #define DR7_LEN_1 (0x0)
454 #define DR7_LEN_2 (0x4)
455 #define DR7_LEN_4 (0xC)
456 #define DR7_LEN_8 (0x8)
457
458 #define DR7_LOCAL_ENABLE_SHIFT 0
459 #define DR7_GLOBAL_ENABLE_SHIFT 1
460 #define DR7_ENABLE_SIZE 2
461
462 #define DR7_LOCAL_ENABLE_MASK (0x55)
463 #define DR7_GLOBAL_ENABLE_MASK (0xAA)
464
465 #define DR7_CONTROL_RESERVED (0xFC00)
466 #define DR7_LOCAL_SLOWDOWN (0x100)
467 #define DR7_GLOBAL_SLOWDOWN (0x200)
468
469 #define DR7_ENABLE_MASK(dr) (1<<(DR7_LOCAL_ENABLE_SHIFT+DR7_ENABLE_SIZE*(dr)))
470 #define IS_DR7_SET(ctrl,dr) ((ctrl)&DR7_ENABLE_MASK(dr))
471
472 static inline int be_x86_64_get_unused_DR(CONTEXT* ctx, DWORD64** r)
473 {
474 if (!IS_DR7_SET(ctx->Dr7, 0))
475 {
476 *r = &ctx->Dr0;
477 return 0;
478 }
479 if (!IS_DR7_SET(ctx->Dr7, 1))
480 {
481 *r = &ctx->Dr1;
482 return 1;
483 }
484 if (!IS_DR7_SET(ctx->Dr7, 2))
485 {
486 *r = &ctx->Dr2;
487 return 2;
488 }
489 if (!IS_DR7_SET(ctx->Dr7, 3))
490 {
491 *r = &ctx->Dr3;
492 return 3;
493 }
494 dbg_printf("All hardware registers have been used\n");
495
496 return -1;
497 }
498
499 static unsigned be_x86_64_insert_Xpoint(HANDLE hProcess, const struct be_process_io* pio,
500 CONTEXT* ctx, enum be_xpoint_type type,
501 void* addr, unsigned long* val, unsigned size)
502 {
503 unsigned char ch;
504 SIZE_T sz;
505 DWORD64 *pr;
506 int reg;
507 unsigned long bits;
508
509 switch (type)
510 {
511 case be_xpoint_break:
512 if (size != 0) return 0;
513 if (!pio->read(hProcess, addr, &ch, 1, &sz) || sz != 1) return 0;
514 *val = ch;
515 ch = 0xcc;
516 if (!pio->write(hProcess, addr, &ch, 1, &sz) || sz != 1) return 0;
517 break;
518 case be_xpoint_watch_exec:
519 bits = DR7_RW_EXECUTE;
520 goto hw_bp;
521 case be_xpoint_watch_read:
522 bits = DR7_RW_READ;
523 goto hw_bp;
524 case be_xpoint_watch_write:
525 bits = DR7_RW_WRITE;
526 hw_bp:
527 if ((reg = be_x86_64_get_unused_DR(ctx, &pr)) == -1) return 0;
528 *pr = (DWORD64)addr;
529 if (type != be_xpoint_watch_exec) switch (size)
530 {
531 case 8: bits |= DR7_LEN_8; break;
532 case 4: bits |= DR7_LEN_4; break;
533 case 2: bits |= DR7_LEN_2; break;
534 case 1: bits |= DR7_LEN_1; break;
535 default: WINE_FIXME("Unsupported xpoint_watch of size %d\n", size); return 0;
536 }
537 *val = reg;
538 /* clear old values */
539 ctx->Dr7 &= ~(0x0F << (DR7_CONTROL_SHIFT + DR7_CONTROL_SIZE * reg));
540 /* set the correct ones */
541 ctx->Dr7 |= bits << (DR7_CONTROL_SHIFT + DR7_CONTROL_SIZE * reg);
542 ctx->Dr7 |= DR7_ENABLE_MASK(reg) | DR7_LOCAL_SLOWDOWN;
543 break;
544 default:
545 dbg_printf("Unknown bp type %c\n", type);
546 return 0;
547 }
548 return 1;
549 }
550
551 static unsigned be_x86_64_remove_Xpoint(HANDLE hProcess, const struct be_process_io* pio,
552 CONTEXT* ctx, enum be_xpoint_type type,
553 void* addr, unsigned long val, unsigned size)
554 {
555 SIZE_T sz;
556 unsigned char ch;
557
558 switch (type)
559 {
560 case be_xpoint_break:
561 if (size != 0) return 0;
562 if (!pio->read(hProcess, addr, &ch, 1, &sz) || sz != 1) return 0;
563 if (ch != (unsigned char)0xCC)
564 WINE_FIXME("Cannot get back %02x instead of 0xCC at %p\n", ch, addr);
565 ch = (unsigned char)val;
566 if (!pio->write(hProcess, addr, &ch, 1, &sz) || sz != 1) return 0;
567 break;
568 case be_xpoint_watch_exec:
569 case be_xpoint_watch_read:
570 case be_xpoint_watch_write:
571 /* simply disable the entry */
572 ctx->Dr7 &= ~DR7_ENABLE_MASK(val);
573 break;
574 default:
575 dbg_printf("Unknown bp type %c\n", type);
576 return 0;
577 }
578 return 1;
579 }
580
581 static unsigned be_x86_64_is_watchpoint_set(const CONTEXT* ctx, unsigned idx)
582 {
583 return ctx->Dr6 & (1 << idx);
584 }
585
586 static void be_x86_64_clear_watchpoint(CONTEXT* ctx, unsigned idx)
587 {
588 ctx->Dr6 &= ~(1 << idx);
589 }
590
591 static int be_x86_64_adjust_pc_for_break(CONTEXT* ctx, BOOL way)
592 {
593 if (way)
594 {
595 ctx->Rip--;
596 return -1;
597 }
598 ctx->Rip++;
599 return 1;
600 }
601
602 static int be_x86_64_fetch_integer(const struct dbg_lvalue* lvalue, unsigned size,
603 unsigned ext_sign, LONGLONG* ret)
604 {
605 if (size != 1 && size != 2 && size != 4 && size != 8 && size != 16)
606 return FALSE;
607
608 memset(ret, 0, sizeof(*ret)); /* clear unread bytes */
609 /* FIXME: this assumes that debuggee and debugger use the same
610 * integral representation
611 */
612 if (!memory_read_value(lvalue, size, ret)) return FALSE;
613
614 /* propagate sign information */
615 if (ext_sign && size < 16 && (*ret >> (size * 8 - 1)) != 0)
616 {
617 ULONGLONG neg = -1;
618 *ret |= neg << (size * 8);
619 }
620 return TRUE;
621 }
622
623 static int be_x86_64_fetch_float(const struct dbg_lvalue* lvalue, unsigned size,
624 long double* ret)
625 {
626 char tmp[sizeof(long double)];
627
628 /* FIXME: this assumes that debuggee and debugger use the same
629 * representation for reals
630 */
631 if (!memory_read_value(lvalue, size, tmp)) return FALSE;
632
633 /* float & double types have to be promoted to a long double */
634 switch (size)
635 {
636 case sizeof(float): *ret = *(float*)tmp; break;
637 case sizeof(double): *ret = *(double*)tmp; break;
638 case sizeof(long double): *ret = *(long double*)tmp; break;
639 default: return FALSE;
640 }
641 return TRUE;
642 }
643
644 static int be_x86_64_store_integer(const struct dbg_lvalue* lvalue, unsigned size,
645 unsigned is_signed, LONGLONG val)
646 {
647 /* this is simple as we're on a little endian CPU */
648 return memory_write_value(lvalue, size, &val);
649 }
650
651 struct backend_cpu be_x86_64 =
652 {
653 IMAGE_FILE_MACHINE_AMD64,
654 8,
655 be_cpu_linearize,
656 be_cpu_build_addr,
657 be_x86_64_get_addr,
658 be_x86_64_get_register_info,
659 be_x86_64_single_step,
660 be_x86_64_print_context,
661 be_x86_64_print_segment_info,
662 be_x86_64_ctx,
663 be_x86_64_is_step_over_insn,
664 be_x86_64_is_function_return,
665 be_x86_64_is_break_insn,
666 be_x86_64_is_func_call,
667 be_x86_64_is_jump,
668 be_x86_64_disasm_one_insn,
669 be_x86_64_insert_Xpoint,
670 be_x86_64_remove_Xpoint,
671 be_x86_64_is_watchpoint_set,
672 be_x86_64_clear_watchpoint,
673 be_x86_64_adjust_pc_for_break,
674 be_x86_64_fetch_integer,
675 be_x86_64_fetch_float,
676 be_x86_64_store_integer,
677 };
678 #endif
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