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Merge git://git.kernel.org/pub/scm/linux/kernel/git/mingo/linux-2.6-sched
[wrt350n-kernel.git] / sound / pci / es1968.c
blob25ccfce45759806a21c8f13d11d4fc192cdf85a5
1 /*
2 * Driver for ESS Maestro 1/2/2E Sound Card (started 21.8.99)
3 * Copyright (c) by Matze Braun <MatzeBraun@gmx.de>.
4 * Takashi Iwai <tiwai@suse.de>
5 *
6 * Most of the driver code comes from Zach Brown(zab@redhat.com)
7 * Alan Cox OSS Driver
8 * Rewritted from card-es1938.c source.
9 *
10 * TODO:
11 * Perhaps Synth
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 *
27 *
28 * Notes from Zach Brown about the driver code
29 *
30 * Hardware Description
31 *
32 * A working Maestro setup contains the Maestro chip wired to a
33 * codec or 2. In the Maestro we have the APUs, the ASSP, and the
34 * Wavecache. The APUs can be though of as virtual audio routing
35 * channels. They can take data from a number of sources and perform
36 * basic encodings of the data. The wavecache is a storehouse for
37 * PCM data. Typically it deals with PCI and interracts with the
38 * APUs. The ASSP is a wacky DSP like device that ESS is loth
39 * to release docs on. Thankfully it isn't required on the Maestro
40 * until you start doing insane things like FM emulation and surround
41 * encoding. The codecs are almost always AC-97 compliant codecs,
42 * but it appears that early Maestros may have had PT101 (an ESS
43 * part?) wired to them. The only real difference in the Maestro
44 * families is external goop like docking capability, memory for
45 * the ASSP, and initialization differences.
46 *
47 * Driver Operation
48 *
49 * We only drive the APU/Wavecache as typical DACs and drive the
50 * mixers in the codecs. There are 64 APUs. We assign 6 to each
51 * /dev/dsp? device. 2 channels for output, and 4 channels for
52 * input.
53 *
54 * Each APU can do a number of things, but we only really use
55 * 3 basic functions. For playback we use them to convert PCM
56 * data fetched over PCI by the wavecahche into analog data that
57 * is handed to the codec. One APU for mono, and a pair for stereo.
58 * When in stereo, the combination of smarts in the APU and Wavecache
59 * decide which wavecache gets the left or right channel.
60 *
61 * For record we still use the old overly mono system. For each in
62 * coming channel the data comes in from the codec, through a 'input'
63 * APU, through another rate converter APU, and then into memory via
64 * the wavecache and PCI. If its stereo, we mash it back into LRLR in
65 * software. The pass between the 2 APUs is supposedly what requires us
66 * to have a 512 byte buffer sitting around in wavecache/memory.
67 *
68 * The wavecache makes our life even more fun. First off, it can
69 * only address the first 28 bits of PCI address space, making it
70 * useless on quite a few architectures. Secondly, its insane.
71 * It claims to fetch from 4 regions of PCI space, each 4 meg in length.
72 * But that doesn't really work. You can only use 1 region. So all our
73 * allocations have to be in 4meg of each other. Booo. Hiss.
74 * So we have a module parameter, dsps_order, that is the order of
75 * the number of dsps to provide. All their buffer space is allocated
76 * on open time. The sonicvibes OSS routines we inherited really want
77 * power of 2 buffers, so we have all those next to each other, then
78 * 512 byte regions for the recording wavecaches. This ends up
79 * wasting quite a bit of memory. The only fixes I can see would be
80 * getting a kernel allocator that could work in zones, or figuring out
81 * just how to coerce the WP into doing what we want.
82 *
83 * The indirection of the various registers means we have to spinlock
84 * nearly all register accesses. We have the main register indirection
85 * like the wave cache, maestro registers, etc. Then we have beasts
86 * like the APU interface that is indirect registers gotten at through
87 * the main maestro indirection. Ouch. We spinlock around the actual
88 * ports on a per card basis. This means spinlock activity at each IO
89 * operation, but the only IO operation clusters are in non critical
90 * paths and it makes the code far easier to follow. Interrupts are
91 * blocked while holding the locks because the int handler has to
92 * get at some of them :(. The mixer interface doesn't, however.
93 * We also have an OSS state lock that is thrown around in a few
94 * places.
95 */
96
97 #include <asm/io.h>
98 #include <linux/delay.h>
99 #include <linux/interrupt.h>
100 #include <linux/init.h>
101 #include <linux/pci.h>
102 #include <linux/dma-mapping.h>
103 #include <linux/slab.h>
104 #include <linux/gameport.h>
105 #include <linux/moduleparam.h>
106 #include <linux/mutex.h>
107
108 #include <sound/core.h>
109 #include <sound/pcm.h>
110 #include <sound/mpu401.h>
111 #include <sound/ac97_codec.h>
112 #include <sound/initval.h>
113
114 #define CARD_NAME "ESS Maestro1/2"
115 #define DRIVER_NAME "ES1968"
116
117 MODULE_DESCRIPTION("ESS Maestro");
118 MODULE_LICENSE("GPL");
119 MODULE_SUPPORTED_DEVICE("{{ESS,Maestro 2e},"
120 "{ESS,Maestro 2},"
121 "{ESS,Maestro 1},"
122 "{TerraTec,DMX}}");
123
124 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
125 #define SUPPORT_JOYSTICK 1
126 #endif
127
128 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 1-MAX */
129 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
130 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
131 static int total_bufsize[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1024 };
132 static int pcm_substreams_p[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 4 };
133 static int pcm_substreams_c[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1 };
134 static int clock[SNDRV_CARDS];
135 static int use_pm[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2};
136 static int enable_mpu[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2};
137 #ifdef SUPPORT_JOYSTICK
138 static int joystick[SNDRV_CARDS];
139 #endif
140
141 module_param_array(index, int, NULL, 0444);
142 MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
143 module_param_array(id, charp, NULL, 0444);
144 MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
145 module_param_array(enable, bool, NULL, 0444);
146 MODULE_PARM_DESC(enable, "Enable " CARD_NAME " soundcard.");
147 module_param_array(total_bufsize, int, NULL, 0444);
148 MODULE_PARM_DESC(total_bufsize, "Total buffer size in kB.");
149 module_param_array(pcm_substreams_p, int, NULL, 0444);
150 MODULE_PARM_DESC(pcm_substreams_p, "PCM Playback substreams for " CARD_NAME " soundcard.");
151 module_param_array(pcm_substreams_c, int, NULL, 0444);
152 MODULE_PARM_DESC(pcm_substreams_c, "PCM Capture substreams for " CARD_NAME " soundcard.");
153 module_param_array(clock, int, NULL, 0444);
154 MODULE_PARM_DESC(clock, "Clock on " CARD_NAME " soundcard. (0 = auto-detect)");
155 module_param_array(use_pm, int, NULL, 0444);
156 MODULE_PARM_DESC(use_pm, "Toggle power-management. (0 = off, 1 = on, 2 = auto)");
157 module_param_array(enable_mpu, int, NULL, 0444);
158 MODULE_PARM_DESC(enable_mpu, "Enable MPU401. (0 = off, 1 = on, 2 = auto)");
159 #ifdef SUPPORT_JOYSTICK
160 module_param_array(joystick, bool, NULL, 0444);
161 MODULE_PARM_DESC(joystick, "Enable joystick.");
162 #endif
163
164
165 #define NR_APUS 64
166 #define NR_APU_REGS 16
167
168 /* NEC Versas ? */
169 #define NEC_VERSA_SUBID1 0x80581033
170 #define NEC_VERSA_SUBID2 0x803c1033
171
172 /* Mode Flags */
173 #define ESS_FMT_STEREO 0x01
174 #define ESS_FMT_16BIT 0x02
175
176 #define DAC_RUNNING 1
177 #define ADC_RUNNING 2
178
179 /* Values for the ESM_LEGACY_AUDIO_CONTROL */
180
181 #define ESS_DISABLE_AUDIO 0x8000
182 #define ESS_ENABLE_SERIAL_IRQ 0x4000
183 #define IO_ADRESS_ALIAS 0x0020
184 #define MPU401_IRQ_ENABLE 0x0010
185 #define MPU401_IO_ENABLE 0x0008
186 #define GAME_IO_ENABLE 0x0004
187 #define FM_IO_ENABLE 0x0002
188 #define SB_IO_ENABLE 0x0001
189
190 /* Values for the ESM_CONFIG_A */
191
192 #define PIC_SNOOP1 0x4000
193 #define PIC_SNOOP2 0x2000
194 #define SAFEGUARD 0x0800
195 #define DMA_CLEAR 0x0700
196 #define DMA_DDMA 0x0000
197 #define DMA_TDMA 0x0100
198 #define DMA_PCPCI 0x0200
199 #define POST_WRITE 0x0080
200 #define PCI_TIMING 0x0040
201 #define SWAP_LR 0x0020
202 #define SUBTR_DECODE 0x0002
203
204 /* Values for the ESM_CONFIG_B */
205
206 #define SPDIF_CONFB 0x0100
207 #define HWV_CONFB 0x0080
208 #define DEBOUNCE 0x0040
209 #define GPIO_CONFB 0x0020
210 #define CHI_CONFB 0x0010
211 #define IDMA_CONFB 0x0008 /*undoc */
212 #define MIDI_FIX 0x0004 /*undoc */
213 #define IRQ_TO_ISA 0x0001 /*undoc */
214
215 /* Values for Ring Bus Control B */
216 #define RINGB_2CODEC_ID_MASK 0x0003
217 #define RINGB_DIS_VALIDATION 0x0008
218 #define RINGB_EN_SPDIF 0x0010
219 #define RINGB_EN_2CODEC 0x0020
220 #define RINGB_SING_BIT_DUAL 0x0040
221
222 /* ****Port Adresses**** */
223
224 /* Write & Read */
225 #define ESM_INDEX 0x02
226 #define ESM_DATA 0x00
227
228 /* AC97 + RingBus */
229 #define ESM_AC97_INDEX 0x30
230 #define ESM_AC97_DATA 0x32
231 #define ESM_RING_BUS_DEST 0x34
232 #define ESM_RING_BUS_CONTR_A 0x36
233 #define ESM_RING_BUS_CONTR_B 0x38
234 #define ESM_RING_BUS_SDO 0x3A
235
236 /* WaveCache*/
237 #define WC_INDEX 0x10
238 #define WC_DATA 0x12
239 #define WC_CONTROL 0x14
240
241 /* ASSP*/
242 #define ASSP_INDEX 0x80
243 #define ASSP_MEMORY 0x82
244 #define ASSP_DATA 0x84
245 #define ASSP_CONTROL_A 0xA2
246 #define ASSP_CONTROL_B 0xA4
247 #define ASSP_CONTROL_C 0xA6
248 #define ASSP_HOSTW_INDEX 0xA8
249 #define ASSP_HOSTW_DATA 0xAA
250 #define ASSP_HOSTW_IRQ 0xAC
251 /* Midi */
252 #define ESM_MPU401_PORT 0x98
253 /* Others */
254 #define ESM_PORT_HOST_IRQ 0x18
255
256 #define IDR0_DATA_PORT 0x00
257 #define IDR1_CRAM_POINTER 0x01
258 #define IDR2_CRAM_DATA 0x02
259 #define IDR3_WAVE_DATA 0x03
260 #define IDR4_WAVE_PTR_LOW 0x04
261 #define IDR5_WAVE_PTR_HI 0x05
262 #define IDR6_TIMER_CTRL 0x06
263 #define IDR7_WAVE_ROMRAM 0x07
264
265 #define WRITEABLE_MAP 0xEFFFFF
266 #define READABLE_MAP 0x64003F
267
268 /* PCI Register */
269
270 #define ESM_LEGACY_AUDIO_CONTROL 0x40
271 #define ESM_ACPI_COMMAND 0x54
272 #define ESM_CONFIG_A 0x50
273 #define ESM_CONFIG_B 0x52
274 #define ESM_DDMA 0x60
275
276 /* Bob Bits */
277 #define ESM_BOB_ENABLE 0x0001
278 #define ESM_BOB_START 0x0001
279
280 /* Host IRQ Control Bits */
281 #define ESM_RESET_MAESTRO 0x8000
282 #define ESM_RESET_DIRECTSOUND 0x4000
283 #define ESM_HIRQ_ClkRun 0x0100
284 #define ESM_HIRQ_HW_VOLUME 0x0040
285 #define ESM_HIRQ_HARPO 0x0030 /* What's that? */
286 #define ESM_HIRQ_ASSP 0x0010
287 #define ESM_HIRQ_DSIE 0x0004
288 #define ESM_HIRQ_MPU401 0x0002
289 #define ESM_HIRQ_SB 0x0001
290
291 /* Host IRQ Status Bits */
292 #define ESM_MPU401_IRQ 0x02
293 #define ESM_SB_IRQ 0x01
294 #define ESM_SOUND_IRQ 0x04
295 #define ESM_ASSP_IRQ 0x10
296 #define ESM_HWVOL_IRQ 0x40
297
298 #define ESS_SYSCLK 50000000
299 #define ESM_BOB_FREQ 200
300 #define ESM_BOB_FREQ_MAX 800
301
302 #define ESM_FREQ_ESM1 (49152000L / 1024L) /* default rate 48000 */
303 #define ESM_FREQ_ESM2 (50000000L / 1024L)
304
305 /* APU Modes: reg 0x00, bit 4-7 */
306 #define ESM_APU_MODE_SHIFT 4
307 #define ESM_APU_MODE_MASK (0xf << 4)
308 #define ESM_APU_OFF 0x00
309 #define ESM_APU_16BITLINEAR 0x01 /* 16-Bit Linear Sample Player */
310 #define ESM_APU_16BITSTEREO 0x02 /* 16-Bit Stereo Sample Player */
311 #define ESM_APU_8BITLINEAR 0x03 /* 8-Bit Linear Sample Player */
312 #define ESM_APU_8BITSTEREO 0x04 /* 8-Bit Stereo Sample Player */
313 #define ESM_APU_8BITDIFF 0x05 /* 8-Bit Differential Sample Playrer */
314 #define ESM_APU_DIGITALDELAY 0x06 /* Digital Delay Line */
315 #define ESM_APU_DUALTAP 0x07 /* Dual Tap Reader */
316 #define ESM_APU_CORRELATOR 0x08 /* Correlator */
317 #define ESM_APU_INPUTMIXER 0x09 /* Input Mixer */
318 #define ESM_APU_WAVETABLE 0x0A /* Wave Table Mode */
319 #define ESM_APU_SRCONVERTOR 0x0B /* Sample Rate Convertor */
320 #define ESM_APU_16BITPINGPONG 0x0C /* 16-Bit Ping-Pong Sample Player */
321 #define ESM_APU_RESERVED1 0x0D /* Reserved 1 */
322 #define ESM_APU_RESERVED2 0x0E /* Reserved 2 */
323 #define ESM_APU_RESERVED3 0x0F /* Reserved 3 */
324
325 /* reg 0x00 */
326 #define ESM_APU_FILTER_Q_SHIFT 0
327 #define ESM_APU_FILTER_Q_MASK (3 << 0)
328 /* APU Filtey Q Control */
329 #define ESM_APU_FILTER_LESSQ 0x00
330 #define ESM_APU_FILTER_MOREQ 0x03
331
332 #define ESM_APU_FILTER_TYPE_SHIFT 2
333 #define ESM_APU_FILTER_TYPE_MASK (3 << 2)
334 #define ESM_APU_ENV_TYPE_SHIFT 8
335 #define ESM_APU_ENV_TYPE_MASK (3 << 8)
336 #define ESM_APU_ENV_STATE_SHIFT 10
337 #define ESM_APU_ENV_STATE_MASK (3 << 10)
338 #define ESM_APU_END_CURVE (1 << 12)
339 #define ESM_APU_INT_ON_LOOP (1 << 13)
340 #define ESM_APU_DMA_ENABLE (1 << 14)
341
342 /* reg 0x02 */
343 #define ESM_APU_SUBMIX_GROUP_SHIRT 0
344 #define ESM_APU_SUBMIX_GROUP_MASK (7 << 0)
345 #define ESM_APU_SUBMIX_MODE (1 << 3)
346 #define ESM_APU_6dB (1 << 4)
347 #define ESM_APU_DUAL_EFFECT (1 << 5)
348 #define ESM_APU_EFFECT_CHANNELS_SHIFT 6
349 #define ESM_APU_EFFECT_CHANNELS_MASK (3 << 6)
350
351 /* reg 0x03 */
352 #define ESM_APU_STEP_SIZE_MASK 0x0fff
353
354 /* reg 0x04 */
355 #define ESM_APU_PHASE_SHIFT 0
356 #define ESM_APU_PHASE_MASK (0xff << 0)
357 #define ESM_APU_WAVE64K_PAGE_SHIFT 8 /* most 8bit of wave start offset */
358 #define ESM_APU_WAVE64K_PAGE_MASK (0xff << 8)
359
360 /* reg 0x05 - wave start offset */
361 /* reg 0x06 - wave end offset */
362 /* reg 0x07 - wave loop length */
363
364 /* reg 0x08 */
365 #define ESM_APU_EFFECT_GAIN_SHIFT 0
366 #define ESM_APU_EFFECT_GAIN_MASK (0xff << 0)
367 #define ESM_APU_TREMOLO_DEPTH_SHIFT 8
368 #define ESM_APU_TREMOLO_DEPTH_MASK (0xf << 8)
369 #define ESM_APU_TREMOLO_RATE_SHIFT 12
370 #define ESM_APU_TREMOLO_RATE_MASK (0xf << 12)
371
372 /* reg 0x09 */
373 /* bit 0-7 amplitude dest? */
374 #define ESM_APU_AMPLITUDE_NOW_SHIFT 8
375 #define ESM_APU_AMPLITUDE_NOW_MASK (0xff << 8)
376
377 /* reg 0x0a */
378 #define ESM_APU_POLAR_PAN_SHIFT 0
379 #define ESM_APU_POLAR_PAN_MASK (0x3f << 0)
380 /* Polar Pan Control */
381 #define ESM_APU_PAN_CENTER_CIRCLE 0x00
382 #define ESM_APU_PAN_MIDDLE_RADIUS 0x01
383 #define ESM_APU_PAN_OUTSIDE_RADIUS 0x02
384
385 #define ESM_APU_FILTER_TUNING_SHIFT 8
386 #define ESM_APU_FILTER_TUNING_MASK (0xff << 8)
387
388 /* reg 0x0b */
389 #define ESM_APU_DATA_SRC_A_SHIFT 0
390 #define ESM_APU_DATA_SRC_A_MASK (0x7f << 0)
391 #define ESM_APU_INV_POL_A (1 << 7)
392 #define ESM_APU_DATA_SRC_B_SHIFT 8
393 #define ESM_APU_DATA_SRC_B_MASK (0x7f << 8)
394 #define ESM_APU_INV_POL_B (1 << 15)
395
396 #define ESM_APU_VIBRATO_RATE_SHIFT 0
397 #define ESM_APU_VIBRATO_RATE_MASK (0xf << 0)
398 #define ESM_APU_VIBRATO_DEPTH_SHIFT 4
399 #define ESM_APU_VIBRATO_DEPTH_MASK (0xf << 4)
400 #define ESM_APU_VIBRATO_PHASE_SHIFT 8
401 #define ESM_APU_VIBRATO_PHASE_MASK (0xff << 8)
402
403 /* reg 0x0c */
404 #define ESM_APU_RADIUS_SELECT (1 << 6)
405
406 /* APU Filter Control */
407 #define ESM_APU_FILTER_2POLE_LOPASS 0x00
408 #define ESM_APU_FILTER_2POLE_BANDPASS 0x01
409 #define ESM_APU_FILTER_2POLE_HIPASS 0x02
410 #define ESM_APU_FILTER_1POLE_LOPASS 0x03
411 #define ESM_APU_FILTER_1POLE_HIPASS 0x04
412 #define ESM_APU_FILTER_OFF 0x05
413
414 /* APU ATFP Type */
415 #define ESM_APU_ATFP_AMPLITUDE 0x00
416 #define ESM_APU_ATFP_TREMELO 0x01
417 #define ESM_APU_ATFP_FILTER 0x02
418 #define ESM_APU_ATFP_PAN 0x03
419
420 /* APU ATFP Flags */
421 #define ESM_APU_ATFP_FLG_OFF 0x00
422 #define ESM_APU_ATFP_FLG_WAIT 0x01
423 #define ESM_APU_ATFP_FLG_DONE 0x02
424 #define ESM_APU_ATFP_FLG_INPROCESS 0x03
425
426
427 /* capture mixing buffer size */
428 #define ESM_MEM_ALIGN 0x1000
429 #define ESM_MIXBUF_SIZE 0x400
430
431 #define ESM_MODE_PLAY 0
432 #define ESM_MODE_CAPTURE 1
433
434
435 /* APU use in the driver */
436 enum snd_enum_apu_type {
437 ESM_APU_PCM_PLAY,
438 ESM_APU_PCM_CAPTURE,
439 ESM_APU_PCM_RATECONV,
440 ESM_APU_FREE
441 };
442
443 /* chip type */
444 enum {
445 TYPE_MAESTRO, TYPE_MAESTRO2, TYPE_MAESTRO2E
446 };
447
448 /* DMA Hack! */
449 struct esm_memory {
450 struct snd_dma_buffer buf;
451 int empty; /* status */
452 struct list_head list;
453 };
454
455 /* Playback Channel */
456 struct esschan {
457 int running;
458
459 u8 apu[4];
460 u8 apu_mode[4];
461
462 /* playback/capture pcm buffer */
463 struct esm_memory *memory;
464 /* capture mixer buffer */
465 struct esm_memory *mixbuf;
466
467 unsigned int hwptr; /* current hw pointer in bytes */
468 unsigned int count; /* sample counter in bytes */
469 unsigned int dma_size; /* total buffer size in bytes */
470 unsigned int frag_size; /* period size in bytes */
471 unsigned int wav_shift;
472 u16 base[4]; /* offset for ptr */
473
474 /* stereo/16bit flag */
475 unsigned char fmt;
476 int mode; /* playback / capture */
477
478 int bob_freq; /* required timer frequency */
479
480 struct snd_pcm_substream *substream;
481
482 /* linked list */
483 struct list_head list;
484
485 #ifdef CONFIG_PM
486 u16 wc_map[4];
487 #endif
488 };
489
490 struct es1968 {
491 /* Module Config */
492 int total_bufsize; /* in bytes */
493
494 int playback_streams, capture_streams;
495
496 unsigned int clock; /* clock */
497 /* for clock measurement */
498 unsigned int in_measurement: 1;
499 unsigned int measure_apu;
500 unsigned int measure_lastpos;
501 unsigned int measure_count;
502
503 /* buffer */
504 struct snd_dma_buffer dma;
505
506 /* Resources... */
507 int irq;
508 unsigned long io_port;
509 int type;
510 struct pci_dev *pci;
511 struct snd_card *card;
512 struct snd_pcm *pcm;
513 int do_pm; /* power-management enabled */
514
515 /* DMA memory block */
516 struct list_head buf_list;
517
518 /* ALSA Stuff */
519 struct snd_ac97 *ac97;
520 struct snd_kcontrol *master_switch; /* for h/w volume control */
521 struct snd_kcontrol *master_volume;
522
523 struct snd_rawmidi *rmidi;
524
525 spinlock_t reg_lock;
526 spinlock_t ac97_lock;
527 struct tasklet_struct hwvol_tq;
528 unsigned int in_suspend;
529
530 /* Maestro Stuff */
531 u16 maestro_map[32];
532 int bobclient; /* active timer instancs */
533 int bob_freq; /* timer frequency */
534 struct mutex memory_mutex; /* memory lock */
535
536 /* APU states */
537 unsigned char apu[NR_APUS];
538
539 /* active substreams */
540 struct list_head substream_list;
541 spinlock_t substream_lock;
542
543 #ifdef CONFIG_PM
544 u16 apu_map[NR_APUS][NR_APU_REGS];
545 #endif
546
547 #ifdef SUPPORT_JOYSTICK
548 struct gameport *gameport;
549 #endif
550 };
551
552 static irqreturn_t snd_es1968_interrupt(int irq, void *dev_id);
553
554 static struct pci_device_id snd_es1968_ids[] = {
555 /* Maestro 1 */
556 { 0x1285, 0x0100, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO },
557 /* Maestro 2 */
558 { 0x125d, 0x1968, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO2 },
559 /* Maestro 2E */
560 { 0x125d, 0x1978, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO2E },
561 { 0, }
562 };
563
564 MODULE_DEVICE_TABLE(pci, snd_es1968_ids);
565
566 /* *********************
567 * Low Level Funcs! *
568 *********************/
569
570 /* no spinlock */
571 static void __maestro_write(struct es1968 *chip, u16 reg, u16 data)
572 {
573 outw(reg, chip->io_port + ESM_INDEX);
574 outw(data, chip->io_port + ESM_DATA);
575 chip->maestro_map[reg] = data;
576 }
577
578 static inline void maestro_write(struct es1968 *chip, u16 reg, u16 data)
579 {
580 unsigned long flags;
581 spin_lock_irqsave(&chip->reg_lock, flags);
582 __maestro_write(chip, reg, data);
583 spin_unlock_irqrestore(&chip->reg_lock, flags);
584 }
585
586 /* no spinlock */
587 static u16 __maestro_read(struct es1968 *chip, u16 reg)
588 {
589 if (READABLE_MAP & (1 << reg)) {
590 outw(reg, chip->io_port + ESM_INDEX);
591 chip->maestro_map[reg] = inw(chip->io_port + ESM_DATA);
592 }
593 return chip->maestro_map[reg];
594 }
595
596 static inline u16 maestro_read(struct es1968 *chip, u16 reg)
597 {
598 unsigned long flags;
599 u16 result;
600 spin_lock_irqsave(&chip->reg_lock, flags);
601 result = __maestro_read(chip, reg);
602 spin_unlock_irqrestore(&chip->reg_lock, flags);
603 return result;
604 }
605
606 /* Wait for the codec bus to be free */
607 static int snd_es1968_ac97_wait(struct es1968 *chip)
608 {
609 int timeout = 100000;
610
611 while (timeout-- > 0) {
612 if (!(inb(chip->io_port + ESM_AC97_INDEX) & 1))
613 return 0;
614 cond_resched();
615 }
616 snd_printd("es1968: ac97 timeout\n");
617 return 1; /* timeout */
618 }
619
620 static void snd_es1968_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
621 {
622 struct es1968 *chip = ac97->private_data;
623 unsigned long flags;
624
625 snd_es1968_ac97_wait(chip);
626
627 /* Write the bus */
628 spin_lock_irqsave(&chip->ac97_lock, flags);
629 outw(val, chip->io_port + ESM_AC97_DATA);
630 /*msleep(1);*/
631 outb(reg, chip->io_port + ESM_AC97_INDEX);
632 /*msleep(1);*/
633 spin_unlock_irqrestore(&chip->ac97_lock, flags);
634 }
635
636 static unsigned short snd_es1968_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
637 {
638 u16 data = 0;
639 struct es1968 *chip = ac97->private_data;
640 unsigned long flags;
641
642 snd_es1968_ac97_wait(chip);
643
644 spin_lock_irqsave(&chip->ac97_lock, flags);
645 outb(reg | 0x80, chip->io_port + ESM_AC97_INDEX);
646 /*msleep(1);*/
647
648 if (! snd_es1968_ac97_wait(chip)) {
649 data = inw(chip->io_port + ESM_AC97_DATA);
650 /*msleep(1);*/
651 }
652 spin_unlock_irqrestore(&chip->ac97_lock, flags);
653
654 return data;
655 }
656
657 /* no spinlock */
658 static void apu_index_set(struct es1968 *chip, u16 index)
659 {
660 int i;
661 __maestro_write(chip, IDR1_CRAM_POINTER, index);
662 for (i = 0; i < 1000; i++)
663 if (__maestro_read(chip, IDR1_CRAM_POINTER) == index)
664 return;
665 snd_printd("es1968: APU register select failed. (Timeout)\n");
666 }
667
668 /* no spinlock */
669 static void apu_data_set(struct es1968 *chip, u16 data)
670 {
671 int i;
672 for (i = 0; i < 1000; i++) {
673 if (__maestro_read(chip, IDR0_DATA_PORT) == data)
674 return;
675 __maestro_write(chip, IDR0_DATA_PORT, data);
676 }
677 snd_printd("es1968: APU register set probably failed (Timeout)!\n");
678 }
679
680 /* no spinlock */
681 static void __apu_set_register(struct es1968 *chip, u16 channel, u8 reg, u16 data)
682 {
683 snd_assert(channel < NR_APUS, return);
684 #ifdef CONFIG_PM
685 chip->apu_map[channel][reg] = data;
686 #endif
687 reg |= (channel << 4);
688 apu_index_set(chip, reg);
689 apu_data_set(chip, data);
690 }
691
692 static void apu_set_register(struct es1968 *chip, u16 channel, u8 reg, u16 data)
693 {
694 unsigned long flags;
695 spin_lock_irqsave(&chip->reg_lock, flags);
696 __apu_set_register(chip, channel, reg, data);
697 spin_unlock_irqrestore(&chip->reg_lock, flags);
698 }
699
700 static u16 __apu_get_register(struct es1968 *chip, u16 channel, u8 reg)
701 {
702 snd_assert(channel < NR_APUS, return 0);
703 reg |= (channel << 4);
704 apu_index_set(chip, reg);
705 return __maestro_read(chip, IDR0_DATA_PORT);
706 }
707
708 static u16 apu_get_register(struct es1968 *chip, u16 channel, u8 reg)
709 {
710 unsigned long flags;
711 u16 v;
712 spin_lock_irqsave(&chip->reg_lock, flags);
713 v = __apu_get_register(chip, channel, reg);
714 spin_unlock_irqrestore(&chip->reg_lock, flags);
715 return v;
716 }
717
718 #if 0 /* ASSP is not supported */
719
720 static void assp_set_register(struct es1968 *chip, u32 reg, u32 value)
721 {
722 unsigned long flags;
723
724 spin_lock_irqsave(&chip->reg_lock, flags);
725 outl(reg, chip->io_port + ASSP_INDEX);
726 outl(value, chip->io_port + ASSP_DATA);
727 spin_unlock_irqrestore(&chip->reg_lock, flags);
728 }
729
730 static u32 assp_get_register(struct es1968 *chip, u32 reg)
731 {
732 unsigned long flags;
733 u32 value;
734
735 spin_lock_irqsave(&chip->reg_lock, flags);
736 outl(reg, chip->io_port + ASSP_INDEX);
737 value = inl(chip->io_port + ASSP_DATA);
738 spin_unlock_irqrestore(&chip->reg_lock, flags);
739
740 return value;
741 }
742
743 #endif
744
745 static void wave_set_register(struct es1968 *chip, u16 reg, u16 value)
746 {
747 unsigned long flags;
748
749 spin_lock_irqsave(&chip->reg_lock, flags);
750 outw(reg, chip->io_port + WC_INDEX);
751 outw(value, chip->io_port + WC_DATA);
752 spin_unlock_irqrestore(&chip->reg_lock, flags);
753 }
754
755 static u16 wave_get_register(struct es1968 *chip, u16 reg)
756 {
757 unsigned long flags;
758 u16 value;
759
760 spin_lock_irqsave(&chip->reg_lock, flags);
761 outw(reg, chip->io_port + WC_INDEX);
762 value = inw(chip->io_port + WC_DATA);
763 spin_unlock_irqrestore(&chip->reg_lock, flags);
764
765 return value;
766 }
767
768 /* *******************
769 * Bob the Timer! *
770 *******************/
771
772 static void snd_es1968_bob_stop(struct es1968 *chip)
773 {
774 u16 reg;
775
776 reg = __maestro_read(chip, 0x11);
777 reg &= ~ESM_BOB_ENABLE;
778 __maestro_write(chip, 0x11, reg);
779 reg = __maestro_read(chip, 0x17);
780 reg &= ~ESM_BOB_START;
781 __maestro_write(chip, 0x17, reg);
782 }
783
784 static void snd_es1968_bob_start(struct es1968 *chip)
785 {
786 int prescale;
787 int divide;
788
789 /* compute ideal interrupt frequency for buffer size & play rate */
790 /* first, find best prescaler value to match freq */
791 for (prescale = 5; prescale < 12; prescale++)
792 if (chip->bob_freq > (ESS_SYSCLK >> (prescale + 9)))
793 break;
794
795 /* next, back off prescaler whilst getting divider into optimum range */
796 divide = 1;
797 while ((prescale > 5) && (divide < 32)) {
798 prescale--;
799 divide <<= 1;
800 }
801 divide >>= 1;
802
803 /* now fine-tune the divider for best match */
804 for (; divide < 31; divide++)
805 if (chip->bob_freq >
806 ((ESS_SYSCLK >> (prescale + 9)) / (divide + 1))) break;
807
808 /* divide = 0 is illegal, but don't let prescale = 4! */
809 if (divide == 0) {
810 divide++;
811 if (prescale > 5)
812 prescale--;
813 } else if (divide > 1)
814 divide--;
815
816 __maestro_write(chip, 6, 0x9000 | (prescale << 5) | divide); /* set reg */
817
818 /* Now set IDR 11/17 */
819 __maestro_write(chip, 0x11, __maestro_read(chip, 0x11) | 1);
820 __maestro_write(chip, 0x17, __maestro_read(chip, 0x17) | 1);
821 }
822
823 /* call with substream spinlock */
824 static void snd_es1968_bob_inc(struct es1968 *chip, int freq)
825 {
826 chip->bobclient++;
827 if (chip->bobclient == 1) {
828 chip->bob_freq = freq;
829 snd_es1968_bob_start(chip);
830 } else if (chip->bob_freq < freq) {
831 snd_es1968_bob_stop(chip);
832 chip->bob_freq = freq;
833 snd_es1968_bob_start(chip);
834 }
835 }
836
837 /* call with substream spinlock */
838 static void snd_es1968_bob_dec(struct es1968 *chip)
839 {
840 chip->bobclient--;
841 if (chip->bobclient <= 0)
842 snd_es1968_bob_stop(chip);
843 else if (chip->bob_freq > ESM_BOB_FREQ) {
844 /* check reduction of timer frequency */
845 int max_freq = ESM_BOB_FREQ;
846 struct esschan *es;
847 list_for_each_entry(es, &chip->substream_list, list) {
848 if (max_freq < es->bob_freq)
849 max_freq = es->bob_freq;
850 }
851 if (max_freq != chip->bob_freq) {
852 snd_es1968_bob_stop(chip);
853 chip->bob_freq = max_freq;
854 snd_es1968_bob_start(chip);
855 }
856 }
857 }
858
859 static int
860 snd_es1968_calc_bob_rate(struct es1968 *chip, struct esschan *es,
861 struct snd_pcm_runtime *runtime)
862 {
863 /* we acquire 4 interrupts per period for precise control.. */
864 int freq = runtime->rate * 4;
865 if (es->fmt & ESS_FMT_STEREO)
866 freq <<= 1;
867 if (es->fmt & ESS_FMT_16BIT)
868 freq <<= 1;
869 freq /= es->frag_size;
870 if (freq < ESM_BOB_FREQ)
871 freq = ESM_BOB_FREQ;
872 else if (freq > ESM_BOB_FREQ_MAX)
873 freq = ESM_BOB_FREQ_MAX;
874 return freq;
875 }
876
877
878 /*************
879 * PCM Part *
880 *************/
881
882 static u32 snd_es1968_compute_rate(struct es1968 *chip, u32 freq)
883 {
884 u32 rate = (freq << 16) / chip->clock;
885 #if 0 /* XXX: do we need this? */
886 if (rate > 0x10000)
887 rate = 0x10000;
888 #endif
889 return rate;
890 }
891
892 /* get current pointer */
893 static inline unsigned int
894 snd_es1968_get_dma_ptr(struct es1968 *chip, struct esschan *es)
895 {
896 unsigned int offset;
897
898 offset = apu_get_register(chip, es->apu[0], 5);
899
900 offset -= es->base[0];
901
902 return (offset & 0xFFFE); /* hardware is in words */
903 }
904
905 static void snd_es1968_apu_set_freq(struct es1968 *chip, int apu, int freq)
906 {
907 apu_set_register(chip, apu, 2,
908 (apu_get_register(chip, apu, 2) & 0x00FF) |
909 ((freq & 0xff) << 8) | 0x10);
910 apu_set_register(chip, apu, 3, freq >> 8);
911 }
912
913 /* spin lock held */
914 static inline void snd_es1968_trigger_apu(struct es1968 *esm, int apu, int mode)
915 {
916 /* set the APU mode */
917 __apu_set_register(esm, apu, 0,
918 (__apu_get_register(esm, apu, 0) & 0xff0f) |
919 (mode << 4));
920 }
921
922 static void snd_es1968_pcm_start(struct es1968 *chip, struct esschan *es)
923 {
924 spin_lock(&chip->reg_lock);
925 __apu_set_register(chip, es->apu[0], 5, es->base[0]);
926 snd_es1968_trigger_apu(chip, es->apu[0], es->apu_mode[0]);
927 if (es->mode == ESM_MODE_CAPTURE) {
928 __apu_set_register(chip, es->apu[2], 5, es->base[2]);
929 snd_es1968_trigger_apu(chip, es->apu[2], es->apu_mode[2]);
930 }
931 if (es->fmt & ESS_FMT_STEREO) {
932 __apu_set_register(chip, es->apu[1], 5, es->base[1]);
933 snd_es1968_trigger_apu(chip, es->apu[1], es->apu_mode[1]);
934 if (es->mode == ESM_MODE_CAPTURE) {
935 __apu_set_register(chip, es->apu[3], 5, es->base[3]);
936 snd_es1968_trigger_apu(chip, es->apu[3], es->apu_mode[3]);
937 }
938 }
939 spin_unlock(&chip->reg_lock);
940 }
941
942 static void snd_es1968_pcm_stop(struct es1968 *chip, struct esschan *es)
943 {
944 spin_lock(&chip->reg_lock);
945 snd_es1968_trigger_apu(chip, es->apu[0], 0);
946 snd_es1968_trigger_apu(chip, es->apu[1], 0);
947 if (es->mode == ESM_MODE_CAPTURE) {
948 snd_es1968_trigger_apu(chip, es->apu[2], 0);
949 snd_es1968_trigger_apu(chip, es->apu[3], 0);
950 }
951 spin_unlock(&chip->reg_lock);
952 }
953
954 /* set the wavecache control reg */
955 static void snd_es1968_program_wavecache(struct es1968 *chip, struct esschan *es,
956 int channel, u32 addr, int capture)
957 {
958 u32 tmpval = (addr - 0x10) & 0xFFF8;
959
960 if (! capture) {
961 if (!(es->fmt & ESS_FMT_16BIT))
962 tmpval |= 4; /* 8bit */
963 if (es->fmt & ESS_FMT_STEREO)
964 tmpval |= 2; /* stereo */
965 }
966
967 /* set the wavecache control reg */
968 wave_set_register(chip, es->apu[channel] << 3, tmpval);
969
970 #ifdef CONFIG_PM
971 es->wc_map[channel] = tmpval;
972 #endif
973 }
974
975
976 static void snd_es1968_playback_setup(struct es1968 *chip, struct esschan *es,
977 struct snd_pcm_runtime *runtime)
978 {
979 u32 pa;
980 int high_apu = 0;
981 int channel, apu;
982 int i, size;
983 unsigned long flags;
984 u32 freq;
985
986 size = es->dma_size >> es->wav_shift;
987
988 if (es->fmt & ESS_FMT_STEREO)
989 high_apu++;
990
991 for (channel = 0; channel <= high_apu; channel++) {
992 apu = es->apu[channel];
993
994 snd_es1968_program_wavecache(chip, es, channel, es->memory->buf.addr, 0);
995
996 /* Offset to PCMBAR */
997 pa = es->memory->buf.addr;
998 pa -= chip->dma.addr;
999 pa >>= 1; /* words */
1000
1001 pa |= 0x00400000; /* System RAM (Bit 22) */
1002
1003 if (es->fmt & ESS_FMT_STEREO) {
1004 /* Enable stereo */
1005 if (channel)
1006 pa |= 0x00800000; /* (Bit 23) */
1007 if (es->fmt & ESS_FMT_16BIT)
1008 pa >>= 1;
1009 }
1010
1011 /* base offset of dma calcs when reading the pointer
1012 on this left one */
1013 es->base[channel] = pa & 0xFFFF;
1014
1015 for (i = 0; i < 16; i++)
1016 apu_set_register(chip, apu, i, 0x0000);
1017
1018 /* Load the buffer into the wave engine */
1019 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xFF) << 8);
1020 apu_set_register(chip, apu, 5, pa & 0xFFFF);
1021 apu_set_register(chip, apu, 6, (pa + size) & 0xFFFF);
1022 /* setting loop == sample len */
1023 apu_set_register(chip, apu, 7, size);
1024
1025 /* clear effects/env.. */
1026 apu_set_register(chip, apu, 8, 0x0000);
1027 /* set amp now to 0xd0 (?), low byte is 'amplitude dest'? */
1028 apu_set_register(chip, apu, 9, 0xD000);
1029
1030 /* clear routing stuff */
1031 apu_set_register(chip, apu, 11, 0x0000);
1032 /* dma on, no envelopes, filter to all 1s) */
1033 apu_set_register(chip, apu, 0, 0x400F);
1034
1035 if (es->fmt & ESS_FMT_16BIT)
1036 es->apu_mode[channel] = ESM_APU_16BITLINEAR;
1037 else
1038 es->apu_mode[channel] = ESM_APU_8BITLINEAR;
1039
1040 if (es->fmt & ESS_FMT_STEREO) {
1041 /* set panning: left or right */
1042 /* Check: different panning. On my Canyon 3D Chipset the
1043 Channels are swapped. I don't know, about the output
1044 to the SPDif Link. Perhaps you have to change this
1045 and not the APU Regs 4-5. */
1046 apu_set_register(chip, apu, 10,
1047 0x8F00 | (channel ? 0 : 0x10));
1048 es->apu_mode[channel] += 1; /* stereo */
1049 } else
1050 apu_set_register(chip, apu, 10, 0x8F08);
1051 }
1052
1053 spin_lock_irqsave(&chip->reg_lock, flags);
1054 /* clear WP interrupts */
1055 outw(1, chip->io_port + 0x04);
1056 /* enable WP ints */
1057 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ);
1058 spin_unlock_irqrestore(&chip->reg_lock, flags);
1059
1060 freq = runtime->rate;
1061 /* set frequency */
1062 if (freq > 48000)
1063 freq = 48000;
1064 if (freq < 4000)
1065 freq = 4000;
1066
1067 /* hmmm.. */
1068 if (!(es->fmt & ESS_FMT_16BIT) && !(es->fmt & ESS_FMT_STEREO))
1069 freq >>= 1;
1070
1071 freq = snd_es1968_compute_rate(chip, freq);
1072
1073 /* Load the frequency, turn on 6dB */
1074 snd_es1968_apu_set_freq(chip, es->apu[0], freq);
1075 snd_es1968_apu_set_freq(chip, es->apu[1], freq);
1076 }
1077
1078
1079 static void init_capture_apu(struct es1968 *chip, struct esschan *es, int channel,
1080 unsigned int pa, unsigned int bsize,
1081 int mode, int route)
1082 {
1083 int i, apu = es->apu[channel];
1084
1085 es->apu_mode[channel] = mode;
1086
1087 /* set the wavecache control reg */
1088 snd_es1968_program_wavecache(chip, es, channel, pa, 1);
1089
1090 /* Offset to PCMBAR */
1091 pa -= chip->dma.addr;
1092 pa >>= 1; /* words */
1093
1094 /* base offset of dma calcs when reading the pointer
1095 on this left one */
1096 es->base[channel] = pa & 0xFFFF;
1097 pa |= 0x00400000; /* bit 22 -> System RAM */
1098
1099 /* Begin loading the APU */
1100 for (i = 0; i < 16; i++)
1101 apu_set_register(chip, apu, i, 0x0000);
1102
1103 /* need to enable subgroups.. and we should probably
1104 have different groups for different /dev/dsps.. */
1105 apu_set_register(chip, apu, 2, 0x8);
1106
1107 /* Load the buffer into the wave engine */
1108 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xFF) << 8);
1109 apu_set_register(chip, apu, 5, pa & 0xFFFF);
1110 apu_set_register(chip, apu, 6, (pa + bsize) & 0xFFFF);
1111 apu_set_register(chip, apu, 7, bsize);
1112 /* clear effects/env.. */
1113 apu_set_register(chip, apu, 8, 0x00F0);
1114 /* amplitude now? sure. why not. */
1115 apu_set_register(chip, apu, 9, 0x0000);
1116 /* set filter tune, radius, polar pan */
1117 apu_set_register(chip, apu, 10, 0x8F08);
1118 /* route input */
1119 apu_set_register(chip, apu, 11, route);
1120 /* dma on, no envelopes, filter to all 1s) */
1121 apu_set_register(chip, apu, 0, 0x400F);
1122 }
1123
1124 static void snd_es1968_capture_setup(struct es1968 *chip, struct esschan *es,
1125 struct snd_pcm_runtime *runtime)
1126 {
1127 int size;
1128 u32 freq;
1129 unsigned long flags;
1130
1131 size = es->dma_size >> es->wav_shift;
1132
1133 /* APU assignments:
1134 0 = mono/left SRC
1135 1 = right SRC
1136 2 = mono/left Input Mixer
1137 3 = right Input Mixer
1138 */
1139 /* data seems to flow from the codec, through an apu into
1140 the 'mixbuf' bit of page, then through the SRC apu
1141 and out to the real 'buffer'. ok. sure. */
1142
1143 /* input mixer (left/mono) */
1144 /* parallel in crap, see maestro reg 0xC [8-11] */
1145 init_capture_apu(chip, es, 2,
1146 es->mixbuf->buf.addr, ESM_MIXBUF_SIZE/4, /* in words */
1147 ESM_APU_INPUTMIXER, 0x14);
1148 /* SRC (left/mono); get input from inputing apu */
1149 init_capture_apu(chip, es, 0, es->memory->buf.addr, size,
1150 ESM_APU_SRCONVERTOR, es->apu[2]);
1151 if (es->fmt & ESS_FMT_STEREO) {
1152 /* input mixer (right) */
1153 init_capture_apu(chip, es, 3,
1154 es->mixbuf->buf.addr + ESM_MIXBUF_SIZE/2,
1155 ESM_MIXBUF_SIZE/4, /* in words */
1156 ESM_APU_INPUTMIXER, 0x15);
1157 /* SRC (right) */
1158 init_capture_apu(chip, es, 1,
1159 es->memory->buf.addr + size*2, size,
1160 ESM_APU_SRCONVERTOR, es->apu[3]);
1161 }
1162
1163 freq = runtime->rate;
1164 /* Sample Rate conversion APUs don't like 0x10000 for their rate */
1165 if (freq > 47999)
1166 freq = 47999;
1167 if (freq < 4000)
1168 freq = 4000;
1169
1170 freq = snd_es1968_compute_rate(chip, freq);
1171
1172 /* Load the frequency, turn on 6dB */
1173 snd_es1968_apu_set_freq(chip, es->apu[0], freq);
1174 snd_es1968_apu_set_freq(chip, es->apu[1], freq);
1175
1176 /* fix mixer rate at 48khz. and its _must_ be 0x10000. */
1177 freq = 0x10000;
1178 snd_es1968_apu_set_freq(chip, es->apu[2], freq);
1179 snd_es1968_apu_set_freq(chip, es->apu[3], freq);
1180
1181 spin_lock_irqsave(&chip->reg_lock, flags);
1182 /* clear WP interrupts */
1183 outw(1, chip->io_port + 0x04);
1184 /* enable WP ints */
1185 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ);
1186 spin_unlock_irqrestore(&chip->reg_lock, flags);
1187 }
1188
1189 /*******************
1190 * ALSA Interface *
1191 *******************/
1192
1193 static int snd_es1968_pcm_prepare(struct snd_pcm_substream *substream)
1194 {
1195 struct es1968 *chip = snd_pcm_substream_chip(substream);
1196 struct snd_pcm_runtime *runtime = substream->runtime;
1197 struct esschan *es = runtime->private_data;
1198
1199 es->dma_size = snd_pcm_lib_buffer_bytes(substream);
1200 es->frag_size = snd_pcm_lib_period_bytes(substream);
1201
1202 es->wav_shift = 1; /* maestro handles always 16bit */
1203 es->fmt = 0;
1204 if (snd_pcm_format_width(runtime->format) == 16)
1205 es->fmt |= ESS_FMT_16BIT;
1206 if (runtime->channels > 1) {
1207 es->fmt |= ESS_FMT_STEREO;
1208 if (es->fmt & ESS_FMT_16BIT) /* 8bit is already word shifted */
1209 es->wav_shift++;
1210 }
1211 es->bob_freq = snd_es1968_calc_bob_rate(chip, es, runtime);
1212
1213 switch (es->mode) {
1214 case ESM_MODE_PLAY:
1215 snd_es1968_playback_setup(chip, es, runtime);
1216 break;
1217 case ESM_MODE_CAPTURE:
1218 snd_es1968_capture_setup(chip, es, runtime);
1219 break;
1220 }
1221
1222 return 0;
1223 }
1224
1225 static int snd_es1968_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1226 {
1227 struct es1968 *chip = snd_pcm_substream_chip(substream);
1228 struct esschan *es = substream->runtime->private_data;
1229
1230 spin_lock(&chip->substream_lock);
1231 switch (cmd) {
1232 case SNDRV_PCM_TRIGGER_START:
1233 case SNDRV_PCM_TRIGGER_RESUME:
1234 if (es->running)
1235 break;
1236 snd_es1968_bob_inc(chip, es->bob_freq);
1237 es->count = 0;
1238 es->hwptr = 0;
1239 snd_es1968_pcm_start(chip, es);
1240 es->running = 1;
1241 break;
1242 case SNDRV_PCM_TRIGGER_STOP:
1243 case SNDRV_PCM_TRIGGER_SUSPEND:
1244 if (! es->running)
1245 break;
1246 snd_es1968_pcm_stop(chip, es);
1247 es->running = 0;
1248 snd_es1968_bob_dec(chip);
1249 break;
1250 }
1251 spin_unlock(&chip->substream_lock);
1252 return 0;
1253 }
1254
1255 static snd_pcm_uframes_t snd_es1968_pcm_pointer(struct snd_pcm_substream *substream)
1256 {
1257 struct es1968 *chip = snd_pcm_substream_chip(substream);
1258 struct esschan *es = substream->runtime->private_data;
1259 unsigned int ptr;
1260
1261 ptr = snd_es1968_get_dma_ptr(chip, es) << es->wav_shift;
1262
1263 return bytes_to_frames(substream->runtime, ptr % es->dma_size);
1264 }
1265
1266 static struct snd_pcm_hardware snd_es1968_playback = {
1267 .info = (SNDRV_PCM_INFO_MMAP |
1268 SNDRV_PCM_INFO_MMAP_VALID |
1269 SNDRV_PCM_INFO_INTERLEAVED |
1270 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1271 /*SNDRV_PCM_INFO_PAUSE |*/
1272 SNDRV_PCM_INFO_RESUME),
1273 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1274 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1275 .rate_min = 4000,
1276 .rate_max = 48000,
1277 .channels_min = 1,
1278 .channels_max = 2,
1279 .buffer_bytes_max = 65536,
1280 .period_bytes_min = 256,
1281 .period_bytes_max = 65536,
1282 .periods_min = 1,
1283 .periods_max = 1024,
1284 .fifo_size = 0,
1285 };
1286
1287 static struct snd_pcm_hardware snd_es1968_capture = {
1288 .info = (SNDRV_PCM_INFO_NONINTERLEAVED |
1289 SNDRV_PCM_INFO_MMAP |
1290 SNDRV_PCM_INFO_MMAP_VALID |
1291 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1292 /*SNDRV_PCM_INFO_PAUSE |*/
1293 SNDRV_PCM_INFO_RESUME),
1294 .formats = /*SNDRV_PCM_FMTBIT_U8 |*/ SNDRV_PCM_FMTBIT_S16_LE,
1295 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1296 .rate_min = 4000,
1297 .rate_max = 48000,
1298 .channels_min = 1,
1299 .channels_max = 2,
1300 .buffer_bytes_max = 65536,
1301 .period_bytes_min = 256,
1302 .period_bytes_max = 65536,
1303 .periods_min = 1,
1304 .periods_max = 1024,
1305 .fifo_size = 0,
1306 };
1307
1308 /* *************************
1309 * DMA memory management *
1310 *************************/
1311
1312 /* Because the Maestro can only take addresses relative to the PCM base address
1313 register :( */
1314
1315 static int calc_available_memory_size(struct es1968 *chip)
1316 {
1317 int max_size = 0;
1318 struct esm_memory *buf;
1319
1320 mutex_lock(&chip->memory_mutex);
1321 list_for_each_entry(buf, &chip->buf_list, list) {
1322 if (buf->empty && buf->buf.bytes > max_size)
1323 max_size = buf->buf.bytes;
1324 }
1325 mutex_unlock(&chip->memory_mutex);
1326 if (max_size >= 128*1024)
1327 max_size = 127*1024;
1328 return max_size;
1329 }
1330
1331 /* allocate a new memory chunk with the specified size */
1332 static struct esm_memory *snd_es1968_new_memory(struct es1968 *chip, int size)
1333 {
1334 struct esm_memory *buf;
1335
1336 size = ALIGN(size, ESM_MEM_ALIGN);
1337 mutex_lock(&chip->memory_mutex);
1338 list_for_each_entry(buf, &chip->buf_list, list) {
1339 if (buf->empty && buf->buf.bytes >= size)
1340 goto __found;
1341 }
1342 mutex_unlock(&chip->memory_mutex);
1343 return NULL;
1344
1345 __found:
1346 if (buf->buf.bytes > size) {
1347 struct esm_memory *chunk = kmalloc(sizeof(*chunk), GFP_KERNEL);
1348 if (chunk == NULL) {
1349 mutex_unlock(&chip->memory_mutex);
1350 return NULL;
1351 }
1352 chunk->buf = buf->buf;
1353 chunk->buf.bytes -= size;
1354 chunk->buf.area += size;
1355 chunk->buf.addr += size;
1356 chunk->empty = 1;
1357 buf->buf.bytes = size;
1358 list_add(&chunk->list, &buf->list);
1359 }
1360 buf->empty = 0;
1361 mutex_unlock(&chip->memory_mutex);
1362 return buf;
1363 }
1364
1365 /* free a memory chunk */
1366 static void snd_es1968_free_memory(struct es1968 *chip, struct esm_memory *buf)
1367 {
1368 struct esm_memory *chunk;
1369
1370 mutex_lock(&chip->memory_mutex);
1371 buf->empty = 1;
1372 if (buf->list.prev != &chip->buf_list) {
1373 chunk = list_entry(buf->list.prev, struct esm_memory, list);
1374 if (chunk->empty) {
1375 chunk->buf.bytes += buf->buf.bytes;
1376 list_del(&buf->list);
1377 kfree(buf);
1378 buf = chunk;
1379 }
1380 }
1381 if (buf->list.next != &chip->buf_list) {
1382 chunk = list_entry(buf->list.next, struct esm_memory, list);
1383 if (chunk->empty) {
1384 buf->buf.bytes += chunk->buf.bytes;
1385 list_del(&chunk->list);
1386 kfree(chunk);
1387 }
1388 }
1389 mutex_unlock(&chip->memory_mutex);
1390 }
1391
1392 static void snd_es1968_free_dmabuf(struct es1968 *chip)
1393 {
1394 struct list_head *p;
1395
1396 if (! chip->dma.area)
1397 return;
1398 snd_dma_reserve_buf(&chip->dma, snd_dma_pci_buf_id(chip->pci));
1399 while ((p = chip->buf_list.next) != &chip->buf_list) {
1400 struct esm_memory *chunk = list_entry(p, struct esm_memory, list);
1401 list_del(p);
1402 kfree(chunk);
1403 }
1404 }
1405
1406 static int __devinit
1407 snd_es1968_init_dmabuf(struct es1968 *chip)
1408 {
1409 int err;
1410 struct esm_memory *chunk;
1411
1412 chip->dma.dev.type = SNDRV_DMA_TYPE_DEV;
1413 chip->dma.dev.dev = snd_dma_pci_data(chip->pci);
1414 if (! snd_dma_get_reserved_buf(&chip->dma, snd_dma_pci_buf_id(chip->pci))) {
1415 err = snd_dma_alloc_pages_fallback(SNDRV_DMA_TYPE_DEV,
1416 snd_dma_pci_data(chip->pci),
1417 chip->total_bufsize, &chip->dma);
1418 if (err < 0 || ! chip->dma.area) {
1419 snd_printk(KERN_ERR "es1968: can't allocate dma pages for size %d\n",
1420 chip->total_bufsize);
1421 return -ENOMEM;
1422 }
1423 if ((chip->dma.addr + chip->dma.bytes - 1) & ~((1 << 28) - 1)) {
1424 snd_dma_free_pages(&chip->dma);
1425 snd_printk(KERN_ERR "es1968: DMA buffer beyond 256MB.\n");
1426 return -ENOMEM;
1427 }
1428 }
1429
1430 INIT_LIST_HEAD(&chip->buf_list);
1431 /* allocate an empty chunk */
1432 chunk = kmalloc(sizeof(*chunk), GFP_KERNEL);
1433 if (chunk == NULL) {
1434 snd_es1968_free_dmabuf(chip);
1435 return -ENOMEM;
1436 }
1437 memset(chip->dma.area, 0, ESM_MEM_ALIGN);
1438 chunk->buf = chip->dma;
1439 chunk->buf.area += ESM_MEM_ALIGN;
1440 chunk->buf.addr += ESM_MEM_ALIGN;
1441 chunk->buf.bytes -= ESM_MEM_ALIGN;
1442 chunk->empty = 1;
1443 list_add(&chunk->list, &chip->buf_list);
1444
1445 return 0;
1446 }
1447
1448 /* setup the dma_areas */
1449 /* buffer is extracted from the pre-allocated memory chunk */
1450 static int snd_es1968_hw_params(struct snd_pcm_substream *substream,
1451 struct snd_pcm_hw_params *hw_params)
1452 {
1453 struct es1968 *chip = snd_pcm_substream_chip(substream);
1454 struct snd_pcm_runtime *runtime = substream->runtime;
1455 struct esschan *chan = runtime->private_data;
1456 int size = params_buffer_bytes(hw_params);
1457
1458 if (chan->memory) {
1459 if (chan->memory->buf.bytes >= size) {
1460 runtime->dma_bytes = size;
1461 return 0;
1462 }
1463 snd_es1968_free_memory(chip, chan->memory);
1464 }
1465 chan->memory = snd_es1968_new_memory(chip, size);
1466 if (chan->memory == NULL) {
1467 // snd_printd("cannot allocate dma buffer: size = %d\n", size);
1468 return -ENOMEM;
1469 }
1470 snd_pcm_set_runtime_buffer(substream, &chan->memory->buf);
1471 return 1; /* area was changed */
1472 }
1473
1474 /* remove dma areas if allocated */
1475 static int snd_es1968_hw_free(struct snd_pcm_substream *substream)
1476 {
1477 struct es1968 *chip = snd_pcm_substream_chip(substream);
1478 struct snd_pcm_runtime *runtime = substream->runtime;
1479 struct esschan *chan;
1480
1481 if (runtime->private_data == NULL)
1482 return 0;
1483 chan = runtime->private_data;
1484 if (chan->memory) {
1485 snd_es1968_free_memory(chip, chan->memory);
1486 chan->memory = NULL;
1487 }
1488 return 0;
1489 }
1490
1491
1492 /*
1493 * allocate APU pair
1494 */
1495 static int snd_es1968_alloc_apu_pair(struct es1968 *chip, int type)
1496 {
1497 int apu;
1498
1499 for (apu = 0; apu < NR_APUS; apu += 2) {
1500 if (chip->apu[apu] == ESM_APU_FREE &&
1501 chip->apu[apu + 1] == ESM_APU_FREE) {
1502 chip->apu[apu] = chip->apu[apu + 1] = type;
1503 return apu;
1504 }
1505 }
1506 return -EBUSY;
1507 }
1508
1509 /*
1510 * release APU pair
1511 */
1512 static void snd_es1968_free_apu_pair(struct es1968 *chip, int apu)
1513 {
1514 chip->apu[apu] = chip->apu[apu + 1] = ESM_APU_FREE;
1515 }
1516
1517
1518 /******************
1519 * PCM open/close *
1520 ******************/
1521
1522 static int snd_es1968_playback_open(struct snd_pcm_substream *substream)
1523 {
1524 struct es1968 *chip = snd_pcm_substream_chip(substream);
1525 struct snd_pcm_runtime *runtime = substream->runtime;
1526 struct esschan *es;
1527 int apu1;
1528
1529 /* search 2 APUs */
1530 apu1 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_PLAY);
1531 if (apu1 < 0)
1532 return apu1;
1533
1534 es = kzalloc(sizeof(*es), GFP_KERNEL);
1535 if (!es) {
1536 snd_es1968_free_apu_pair(chip, apu1);
1537 return -ENOMEM;
1538 }
1539
1540 es->apu[0] = apu1;
1541 es->apu[1] = apu1 + 1;
1542 es->apu_mode[0] = 0;
1543 es->apu_mode[1] = 0;
1544 es->running = 0;
1545 es->substream = substream;
1546 es->mode = ESM_MODE_PLAY;
1547
1548 runtime->private_data = es;
1549 runtime->hw = snd_es1968_playback;
1550 runtime->hw.buffer_bytes_max = runtime->hw.period_bytes_max =
1551 calc_available_memory_size(chip);
1552
1553 spin_lock_irq(&chip->substream_lock);
1554 list_add(&es->list, &chip->substream_list);
1555 spin_unlock_irq(&chip->substream_lock);
1556
1557 return 0;
1558 }
1559
1560 static int snd_es1968_capture_open(struct snd_pcm_substream *substream)
1561 {
1562 struct snd_pcm_runtime *runtime = substream->runtime;
1563 struct es1968 *chip = snd_pcm_substream_chip(substream);
1564 struct esschan *es;
1565 int apu1, apu2;
1566
1567 apu1 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_CAPTURE);
1568 if (apu1 < 0)
1569 return apu1;
1570 apu2 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_RATECONV);
1571 if (apu2 < 0) {
1572 snd_es1968_free_apu_pair(chip, apu1);
1573 return apu2;
1574 }
1575
1576 es = kzalloc(sizeof(*es), GFP_KERNEL);
1577 if (!es) {
1578 snd_es1968_free_apu_pair(chip, apu1);
1579 snd_es1968_free_apu_pair(chip, apu2);
1580 return -ENOMEM;
1581 }
1582
1583 es->apu[0] = apu1;
1584 es->apu[1] = apu1 + 1;
1585 es->apu[2] = apu2;
1586 es->apu[3] = apu2 + 1;
1587 es->apu_mode[0] = 0;
1588 es->apu_mode[1] = 0;
1589 es->apu_mode[2] = 0;
1590 es->apu_mode[3] = 0;
1591 es->running = 0;
1592 es->substream = substream;
1593 es->mode = ESM_MODE_CAPTURE;
1594
1595 /* get mixbuffer */
1596 if ((es->mixbuf = snd_es1968_new_memory(chip, ESM_MIXBUF_SIZE)) == NULL) {
1597 snd_es1968_free_apu_pair(chip, apu1);
1598 snd_es1968_free_apu_pair(chip, apu2);
1599 kfree(es);
1600 return -ENOMEM;
1601 }
1602 memset(es->mixbuf->buf.area, 0, ESM_MIXBUF_SIZE);
1603
1604 runtime->private_data = es;
1605 runtime->hw = snd_es1968_capture;
1606 runtime->hw.buffer_bytes_max = runtime->hw.period_bytes_max =
1607 calc_available_memory_size(chip) - 1024; /* keep MIXBUF size */
1608 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES);
1609
1610 spin_lock_irq(&chip->substream_lock);
1611 list_add(&es->list, &chip->substream_list);
1612 spin_unlock_irq(&chip->substream_lock);
1613
1614 return 0;
1615 }
1616
1617 static int snd_es1968_playback_close(struct snd_pcm_substream *substream)
1618 {
1619 struct es1968 *chip = snd_pcm_substream_chip(substream);
1620 struct esschan *es;
1621
1622 if (substream->runtime->private_data == NULL)
1623 return 0;
1624 es = substream->runtime->private_data;
1625 spin_lock_irq(&chip->substream_lock);
1626 list_del(&es->list);
1627 spin_unlock_irq(&chip->substream_lock);
1628 snd_es1968_free_apu_pair(chip, es->apu[0]);
1629 kfree(es);
1630
1631 return 0;
1632 }
1633
1634 static int snd_es1968_capture_close(struct snd_pcm_substream *substream)
1635 {
1636 struct es1968 *chip = snd_pcm_substream_chip(substream);
1637 struct esschan *es;
1638
1639 if (substream->runtime->private_data == NULL)
1640 return 0;
1641 es = substream->runtime->private_data;
1642 spin_lock_irq(&chip->substream_lock);
1643 list_del(&es->list);
1644 spin_unlock_irq(&chip->substream_lock);
1645 snd_es1968_free_memory(chip, es->mixbuf);
1646 snd_es1968_free_apu_pair(chip, es->apu[0]);
1647 snd_es1968_free_apu_pair(chip, es->apu[2]);
1648 kfree(es);
1649
1650 return 0;
1651 }
1652
1653 static struct snd_pcm_ops snd_es1968_playback_ops = {
1654 .open = snd_es1968_playback_open,
1655 .close = snd_es1968_playback_close,
1656 .ioctl = snd_pcm_lib_ioctl,
1657 .hw_params = snd_es1968_hw_params,
1658 .hw_free = snd_es1968_hw_free,
1659 .prepare = snd_es1968_pcm_prepare,
1660 .trigger = snd_es1968_pcm_trigger,
1661 .pointer = snd_es1968_pcm_pointer,
1662 };
1663
1664 static struct snd_pcm_ops snd_es1968_capture_ops = {
1665 .open = snd_es1968_capture_open,
1666 .close = snd_es1968_capture_close,
1667 .ioctl = snd_pcm_lib_ioctl,
1668 .hw_params = snd_es1968_hw_params,
1669 .hw_free = snd_es1968_hw_free,
1670 .prepare = snd_es1968_pcm_prepare,
1671 .trigger = snd_es1968_pcm_trigger,
1672 .pointer = snd_es1968_pcm_pointer,
1673 };
1674
1675
1676 /*
1677 * measure clock
1678 */
1679 #define CLOCK_MEASURE_BUFSIZE 16768 /* enough large for a single shot */
1680
1681 static void __devinit es1968_measure_clock(struct es1968 *chip)
1682 {
1683 int i, apu;
1684 unsigned int pa, offset, t;
1685 struct esm_memory *memory;
1686 struct timeval start_time, stop_time;
1687
1688 if (chip->clock == 0)
1689 chip->clock = 48000; /* default clock value */
1690
1691 /* search 2 APUs (although one apu is enough) */
1692 if ((apu = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_PLAY)) < 0) {
1693 snd_printk(KERN_ERR "Hmm, cannot find empty APU pair!?\n");
1694 return;
1695 }
1696 if ((memory = snd_es1968_new_memory(chip, CLOCK_MEASURE_BUFSIZE)) == NULL) {
1697 snd_printk(KERN_ERR "cannot allocate dma buffer - using default clock %d\n", chip->clock);
1698 snd_es1968_free_apu_pair(chip, apu);
1699 return;
1700 }
1701
1702 memset(memory->buf.area, 0, CLOCK_MEASURE_BUFSIZE);
1703
1704 wave_set_register(chip, apu << 3, (memory->buf.addr - 0x10) & 0xfff8);
1705
1706 pa = (unsigned int)((memory->buf.addr - chip->dma.addr) >> 1);
1707 pa |= 0x00400000; /* System RAM (Bit 22) */
1708
1709 /* initialize apu */
1710 for (i = 0; i < 16; i++)
1711 apu_set_register(chip, apu, i, 0x0000);
1712
1713 apu_set_register(chip, apu, 0, 0x400f);
1714 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xff) << 8);
1715 apu_set_register(chip, apu, 5, pa & 0xffff);
1716 apu_set_register(chip, apu, 6, (pa + CLOCK_MEASURE_BUFSIZE/2) & 0xffff);
1717 apu_set_register(chip, apu, 7, CLOCK_MEASURE_BUFSIZE/2);
1718 apu_set_register(chip, apu, 8, 0x0000);
1719 apu_set_register(chip, apu, 9, 0xD000);
1720 apu_set_register(chip, apu, 10, 0x8F08);
1721 apu_set_register(chip, apu, 11, 0x0000);
1722 spin_lock_irq(&chip->reg_lock);
1723 outw(1, chip->io_port + 0x04); /* clear WP interrupts */
1724 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ); /* enable WP ints */
1725 spin_unlock_irq(&chip->reg_lock);
1726
1727 snd_es1968_apu_set_freq(chip, apu, ((unsigned int)48000 << 16) / chip->clock); /* 48000 Hz */
1728
1729 chip->in_measurement = 1;
1730 chip->measure_apu = apu;
1731 spin_lock_irq(&chip->reg_lock);
1732 snd_es1968_bob_inc(chip, ESM_BOB_FREQ);
1733 __apu_set_register(chip, apu, 5, pa & 0xffff);
1734 snd_es1968_trigger_apu(chip, apu, ESM_APU_16BITLINEAR);
1735 do_gettimeofday(&start_time);
1736 spin_unlock_irq(&chip->reg_lock);
1737 msleep(50);
1738 spin_lock_irq(&chip->reg_lock);
1739 offset = __apu_get_register(chip, apu, 5);
1740 do_gettimeofday(&stop_time);
1741 snd_es1968_trigger_apu(chip, apu, 0); /* stop */
1742 snd_es1968_bob_dec(chip);
1743 chip->in_measurement = 0;
1744 spin_unlock_irq(&chip->reg_lock);
1745
1746 /* check the current position */
1747 offset -= (pa & 0xffff);
1748 offset &= 0xfffe;
1749 offset += chip->measure_count * (CLOCK_MEASURE_BUFSIZE/2);
1750
1751 t = stop_time.tv_sec - start_time.tv_sec;
1752 t *= 1000000;
1753 if (stop_time.tv_usec < start_time.tv_usec)
1754 t -= start_time.tv_usec - stop_time.tv_usec;
1755 else
1756 t += stop_time.tv_usec - start_time.tv_usec;
1757 if (t == 0) {
1758 snd_printk(KERN_ERR "?? calculation error..\n");
1759 } else {
1760 offset *= 1000;
1761 offset = (offset / t) * 1000 + ((offset % t) * 1000) / t;
1762 if (offset < 47500 || offset > 48500) {
1763 if (offset >= 40000 && offset <= 50000)
1764 chip->clock = (chip->clock * offset) / 48000;
1765 }
1766 printk(KERN_INFO "es1968: clocking to %d\n", chip->clock);
1767 }
1768 snd_es1968_free_memory(chip, memory);
1769 snd_es1968_free_apu_pair(chip, apu);
1770 }
1771
1772
1773 /*
1774 */
1775
1776 static void snd_es1968_pcm_free(struct snd_pcm *pcm)
1777 {
1778 struct es1968 *esm = pcm->private_data;
1779 snd_es1968_free_dmabuf(esm);
1780 esm->pcm = NULL;
1781 }
1782
1783 static int __devinit
1784 snd_es1968_pcm(struct es1968 *chip, int device)
1785 {
1786 struct snd_pcm *pcm;
1787 int err;
1788
1789 /* get DMA buffer */
1790 if ((err = snd_es1968_init_dmabuf(chip)) < 0)
1791 return err;
1792
1793 /* set PCMBAR */
1794 wave_set_register(chip, 0x01FC, chip->dma.addr >> 12);
1795 wave_set_register(chip, 0x01FD, chip->dma.addr >> 12);
1796 wave_set_register(chip, 0x01FE, chip->dma.addr >> 12);
1797 wave_set_register(chip, 0x01FF, chip->dma.addr >> 12);
1798
1799 if ((err = snd_pcm_new(chip->card, "ESS Maestro", device,
1800 chip->playback_streams,
1801 chip->capture_streams, &pcm)) < 0)
1802 return err;
1803
1804 pcm->private_data = chip;
1805 pcm->private_free = snd_es1968_pcm_free;
1806
1807 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_es1968_playback_ops);
1808 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_es1968_capture_ops);
1809
1810 pcm->info_flags = 0;
1811
1812 strcpy(pcm->name, "ESS Maestro");
1813
1814 chip->pcm = pcm;
1815
1816 return 0;
1817 }
1818
1819 /*
1820 * update pointer
1821 */
1822 static void snd_es1968_update_pcm(struct es1968 *chip, struct esschan *es)
1823 {
1824 unsigned int hwptr;
1825 unsigned int diff;
1826 struct snd_pcm_substream *subs = es->substream;
1827
1828 if (subs == NULL || !es->running)
1829 return;
1830
1831 hwptr = snd_es1968_get_dma_ptr(chip, es) << es->wav_shift;
1832 hwptr %= es->dma_size;
1833
1834 diff = (es->dma_size + hwptr - es->hwptr) % es->dma_size;
1835
1836 es->hwptr = hwptr;
1837 es->count += diff;
1838
1839 if (es->count > es->frag_size) {
1840 spin_unlock(&chip->substream_lock);
1841 snd_pcm_period_elapsed(subs);
1842 spin_lock(&chip->substream_lock);
1843 es->count %= es->frag_size;
1844 }
1845 }
1846
1847 /*
1848 */
1849 static void es1968_update_hw_volume(unsigned long private_data)
1850 {
1851 struct es1968 *chip = (struct es1968 *) private_data;
1852 int x, val;
1853 unsigned long flags;
1854
1855 /* Figure out which volume control button was pushed,
1856 based on differences from the default register
1857 values. */
1858 x = inb(chip->io_port + 0x1c) & 0xee;
1859 /* Reset the volume control registers. */
1860 outb(0x88, chip->io_port + 0x1c);
1861 outb(0x88, chip->io_port + 0x1d);
1862 outb(0x88, chip->io_port + 0x1e);
1863 outb(0x88, chip->io_port + 0x1f);
1864
1865 if (chip->in_suspend)
1866 return;
1867
1868 if (! chip->master_switch || ! chip->master_volume)
1869 return;
1870
1871 /* FIXME: we can't call snd_ac97_* functions since here is in tasklet. */
1872 spin_lock_irqsave(&chip->ac97_lock, flags);
1873 val = chip->ac97->regs[AC97_MASTER];
1874 switch (x) {
1875 case 0x88:
1876 /* mute */
1877 val ^= 0x8000;
1878 chip->ac97->regs[AC97_MASTER] = val;
1879 outw(val, chip->io_port + ESM_AC97_DATA);
1880 outb(AC97_MASTER, chip->io_port + ESM_AC97_INDEX);
1881 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1882 &chip->master_switch->id);
1883 break;
1884 case 0xaa:
1885 /* volume up */
1886 if ((val & 0x7f) > 0)
1887 val--;
1888 if ((val & 0x7f00) > 0)
1889 val -= 0x0100;
1890 chip->ac97->regs[AC97_MASTER] = val;
1891 outw(val, chip->io_port + ESM_AC97_DATA);
1892 outb(AC97_MASTER, chip->io_port + ESM_AC97_INDEX);
1893 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1894 &chip->master_volume->id);
1895 break;
1896 case 0x66:
1897 /* volume down */
1898 if ((val & 0x7f) < 0x1f)
1899 val++;
1900 if ((val & 0x7f00) < 0x1f00)
1901 val += 0x0100;
1902 chip->ac97->regs[AC97_MASTER] = val;
1903 outw(val, chip->io_port + ESM_AC97_DATA);
1904 outb(AC97_MASTER, chip->io_port + ESM_AC97_INDEX);
1905 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1906 &chip->master_volume->id);
1907 break;
1908 }
1909 spin_unlock_irqrestore(&chip->ac97_lock, flags);
1910 }
1911
1912 /*
1913 * interrupt handler
1914 */
1915 static irqreturn_t snd_es1968_interrupt(int irq, void *dev_id)
1916 {
1917 struct es1968 *chip = dev_id;
1918 u32 event;
1919
1920 if (!(event = inb(chip->io_port + 0x1A)))
1921 return IRQ_NONE;
1922
1923 outw(inw(chip->io_port + 4) & 1, chip->io_port + 4);
1924
1925 if (event & ESM_HWVOL_IRQ)
1926 tasklet_hi_schedule(&chip->hwvol_tq); /* we'll do this later */
1927
1928 /* else ack 'em all, i imagine */
1929 outb(0xFF, chip->io_port + 0x1A);
1930
1931 if ((event & ESM_MPU401_IRQ) && chip->rmidi) {
1932 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data);
1933 }
1934
1935 if (event & ESM_SOUND_IRQ) {
1936 struct esschan *es;
1937 spin_lock(&chip->substream_lock);
1938 list_for_each_entry(es, &chip->substream_list, list) {
1939 if (es->running)
1940 snd_es1968_update_pcm(chip, es);
1941 }
1942 spin_unlock(&chip->substream_lock);
1943 if (chip->in_measurement) {
1944 unsigned int curp = __apu_get_register(chip, chip->measure_apu, 5);
1945 if (curp < chip->measure_lastpos)
1946 chip->measure_count++;
1947 chip->measure_lastpos = curp;
1948 }
1949 }
1950
1951 return IRQ_HANDLED;
1952 }
1953
1954 /*
1955 * Mixer stuff
1956 */
1957
1958 static int __devinit
1959 snd_es1968_mixer(struct es1968 *chip)
1960 {
1961 struct snd_ac97_bus *pbus;
1962 struct snd_ac97_template ac97;
1963 struct snd_ctl_elem_id id;
1964 int err;
1965 static struct snd_ac97_bus_ops ops = {
1966 .write = snd_es1968_ac97_write,
1967 .read = snd_es1968_ac97_read,
1968 };
1969
1970 if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
1971 return err;
1972 pbus->no_vra = 1; /* ES1968 doesn't need VRA */
1973
1974 memset(&ac97, 0, sizeof(ac97));
1975 ac97.private_data = chip;
1976 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
1977 return err;
1978
1979 /* attach master switch / volumes for h/w volume control */
1980 memset(&id, 0, sizeof(id));
1981 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1982 strcpy(id.name, "Master Playback Switch");
1983 chip->master_switch = snd_ctl_find_id(chip->card, &id);
1984 memset(&id, 0, sizeof(id));
1985 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1986 strcpy(id.name, "Master Playback Volume");
1987 chip->master_volume = snd_ctl_find_id(chip->card, &id);
1988
1989 return 0;
1990 }
1991
1992 /*
1993 * reset ac97 codec
1994 */
1995
1996 static void snd_es1968_ac97_reset(struct es1968 *chip)
1997 {
1998 unsigned long ioaddr = chip->io_port;
1999
2000 unsigned short save_ringbus_a;
2001 unsigned short save_68;
2002 unsigned short w;
2003 unsigned int vend;
2004
2005 /* save configuration */
2006 save_ringbus_a = inw(ioaddr + 0x36);
2007
2008 //outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38); /* clear second codec id? */
2009 /* set command/status address i/o to 1st codec */
2010 outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a);
2011 outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c);
2012
2013 /* disable ac link */
2014 outw(0x0000, ioaddr + 0x36);
2015 save_68 = inw(ioaddr + 0x68);
2016 pci_read_config_word(chip->pci, 0x58, &w); /* something magical with gpio and bus arb. */
2017 pci_read_config_dword(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
2018 if (w & 1)
2019 save_68 |= 0x10;
2020 outw(0xfffe, ioaddr + 0x64); /* unmask gpio 0 */
2021 outw(0x0001, ioaddr + 0x68); /* gpio write */
2022 outw(0x0000, ioaddr + 0x60); /* write 0 to gpio 0 */
2023 udelay(20);
2024 outw(0x0001, ioaddr + 0x60); /* write 1 to gpio 1 */
2025 msleep(20);
2026
2027 outw(save_68 | 0x1, ioaddr + 0x68); /* now restore .. */
2028 outw((inw(ioaddr + 0x38) & 0xfffc) | 0x1, ioaddr + 0x38);
2029 outw((inw(ioaddr + 0x3a) & 0xfffc) | 0x1, ioaddr + 0x3a);
2030 outw((inw(ioaddr + 0x3c) & 0xfffc) | 0x1, ioaddr + 0x3c);
2031
2032 /* now the second codec */
2033 /* disable ac link */
2034 outw(0x0000, ioaddr + 0x36);
2035 outw(0xfff7, ioaddr + 0x64); /* unmask gpio 3 */
2036 save_68 = inw(ioaddr + 0x68);
2037 outw(0x0009, ioaddr + 0x68); /* gpio write 0 & 3 ?? */
2038 outw(0x0001, ioaddr + 0x60); /* write 1 to gpio */
2039 udelay(20);
2040 outw(0x0009, ioaddr + 0x60); /* write 9 to gpio */
2041 msleep(500);
2042 //outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38);
2043 outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a);
2044 outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c);
2045
2046 #if 0 /* the loop here needs to be much better if we want it.. */
2047 snd_printk(KERN_INFO "trying software reset\n");
2048 /* try and do a software reset */
2049 outb(0x80 | 0x7c, ioaddr + 0x30);
2050 for (w = 0;; w++) {
2051 if ((inw(ioaddr + 0x30) & 1) == 0) {
2052 if (inb(ioaddr + 0x32) != 0)
2053 break;
2054
2055 outb(0x80 | 0x7d, ioaddr + 0x30);
2056 if (((inw(ioaddr + 0x30) & 1) == 0)
2057 && (inb(ioaddr + 0x32) != 0))
2058 break;
2059 outb(0x80 | 0x7f, ioaddr + 0x30);
2060 if (((inw(ioaddr + 0x30) & 1) == 0)
2061 && (inb(ioaddr + 0x32) != 0))
2062 break;
2063 }
2064
2065 if (w > 10000) {
2066 outb(inb(ioaddr + 0x37) | 0x08, ioaddr + 0x37); /* do a software reset */
2067 msleep(500); /* oh my.. */
2068 outb(inb(ioaddr + 0x37) & ~0x08,
2069 ioaddr + 0x37);
2070 udelay(1);
2071 outw(0x80, ioaddr + 0x30);
2072 for (w = 0; w < 10000; w++) {
2073 if ((inw(ioaddr + 0x30) & 1) == 0)
2074 break;
2075 }
2076 }
2077 }
2078 #endif
2079 if (vend == NEC_VERSA_SUBID1 || vend == NEC_VERSA_SUBID2) {
2080 /* turn on external amp? */
2081 outw(0xf9ff, ioaddr + 0x64);
2082 outw(inw(ioaddr + 0x68) | 0x600, ioaddr + 0x68);
2083 outw(0x0209, ioaddr + 0x60);
2084 }
2085
2086 /* restore.. */
2087 outw(save_ringbus_a, ioaddr + 0x36);
2088
2089 /* Turn on the 978 docking chip.
2090 First frob the "master output enable" bit,
2091 then set most of the playback volume control registers to max. */
2092 outb(inb(ioaddr+0xc0)|(1<<5), ioaddr+0xc0);
2093 outb(0xff, ioaddr+0xc3);
2094 outb(0xff, ioaddr+0xc4);
2095 outb(0xff, ioaddr+0xc6);
2096 outb(0xff, ioaddr+0xc8);
2097 outb(0x3f, ioaddr+0xcf);
2098 outb(0x3f, ioaddr+0xd0);
2099 }
2100
2101 static void snd_es1968_reset(struct es1968 *chip)
2102 {
2103 /* Reset */
2104 outw(ESM_RESET_MAESTRO | ESM_RESET_DIRECTSOUND,
2105 chip->io_port + ESM_PORT_HOST_IRQ);
2106 udelay(10);
2107 outw(0x0000, chip->io_port + ESM_PORT_HOST_IRQ);
2108 udelay(10);
2109 }
2110
2111 /*
2112 * initialize maestro chip
2113 */
2114 static void snd_es1968_chip_init(struct es1968 *chip)
2115 {
2116 struct pci_dev *pci = chip->pci;
2117 int i;
2118 unsigned long iobase = chip->io_port;
2119 u16 w;
2120 u32 n;
2121
2122 /* We used to muck around with pci config space that
2123 * we had no business messing with. We don't know enough
2124 * about the machine to know which DMA mode is appropriate,
2125 * etc. We were guessing wrong on some machines and making
2126 * them unhappy. We now trust in the BIOS to do things right,
2127 * which almost certainly means a new host of problems will
2128 * arise with broken BIOS implementations. screw 'em.
2129 * We're already intolerant of machines that don't assign
2130 * IRQs.
2131 */
2132
2133 /* Config Reg A */
2134 pci_read_config_word(pci, ESM_CONFIG_A, &w);
2135
2136 w &= ~DMA_CLEAR; /* Clear DMA bits */
2137 w &= ~(PIC_SNOOP1 | PIC_SNOOP2); /* Clear Pic Snoop Mode Bits */
2138 w &= ~SAFEGUARD; /* Safeguard off */
2139 w |= POST_WRITE; /* Posted write */
2140 w |= PCI_TIMING; /* PCI timing on */
2141 /* XXX huh? claims to be reserved.. */
2142 w &= ~SWAP_LR; /* swap left/right
2143 seems to only have effect on SB
2144 Emulation */
2145 w &= ~SUBTR_DECODE; /* Subtractive decode off */
2146
2147 pci_write_config_word(pci, ESM_CONFIG_A, w);
2148
2149 /* Config Reg B */
2150
2151 pci_read_config_word(pci, ESM_CONFIG_B, &w);
2152
2153 w &= ~(1 << 15); /* Turn off internal clock multiplier */
2154 /* XXX how do we know which to use? */
2155 w &= ~(1 << 14); /* External clock */
2156
2157 w &= ~SPDIF_CONFB; /* disable S/PDIF output */
2158 w |= HWV_CONFB; /* HWV on */
2159 w |= DEBOUNCE; /* Debounce off: easier to push the HW buttons */
2160 w &= ~GPIO_CONFB; /* GPIO 4:5 */
2161 w |= CHI_CONFB; /* Disconnect from the CHI. Enabling this made a dell 7500 work. */
2162 w &= ~IDMA_CONFB; /* IDMA off (undocumented) */
2163 w &= ~MIDI_FIX; /* MIDI fix off (undoc) */
2164 w &= ~(1 << 1); /* reserved, always write 0 */
2165 w &= ~IRQ_TO_ISA; /* IRQ to ISA off (undoc) */
2166
2167 pci_write_config_word(pci, ESM_CONFIG_B, w);
2168
2169 /* DDMA off */
2170
2171 pci_read_config_word(pci, ESM_DDMA, &w);
2172 w &= ~(1 << 0);
2173 pci_write_config_word(pci, ESM_DDMA, w);
2174
2175 /*
2176 * Legacy mode
2177 */
2178
2179 pci_read_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, &w);
2180
2181 w |= ESS_DISABLE_AUDIO; /* Disable Legacy Audio */
2182 w &= ~ESS_ENABLE_SERIAL_IRQ; /* Disable SIRQ */
2183 w &= ~(0x1f); /* disable mpu irq/io, game port, fm, SB */
2184
2185 pci_write_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, w);
2186
2187 /* Set up 978 docking control chip. */
2188 pci_read_config_word(pci, 0x58, &w);
2189 w|=1<<2; /* Enable 978. */
2190 w|=1<<3; /* Turn on 978 hardware volume control. */
2191 w&=~(1<<11); /* Turn on 978 mixer volume control. */
2192 pci_write_config_word(pci, 0x58, w);
2193
2194 /* Sound Reset */
2195
2196 snd_es1968_reset(chip);
2197
2198 /*
2199 * Ring Bus Setup
2200 */
2201
2202 /* setup usual 0x34 stuff.. 0x36 may be chip specific */
2203 outw(0xC090, iobase + ESM_RING_BUS_DEST); /* direct sound, stereo */
2204 udelay(20);
2205 outw(0x3000, iobase + ESM_RING_BUS_CONTR_A); /* enable ringbus/serial */
2206 udelay(20);
2207
2208 /*
2209 * Reset the CODEC
2210 */
2211
2212 snd_es1968_ac97_reset(chip);
2213
2214 /* Ring Bus Control B */
2215
2216 n = inl(iobase + ESM_RING_BUS_CONTR_B);
2217 n &= ~RINGB_EN_SPDIF; /* SPDIF off */
2218 //w |= RINGB_EN_2CODEC; /* enable 2nd codec */
2219 outl(n, iobase + ESM_RING_BUS_CONTR_B);
2220
2221 /* Set hardware volume control registers to midpoints.
2222 We can tell which button was pushed based on how they change. */
2223 outb(0x88, iobase+0x1c);
2224 outb(0x88, iobase+0x1d);
2225 outb(0x88, iobase+0x1e);
2226 outb(0x88, iobase+0x1f);
2227
2228 /* it appears some maestros (dell 7500) only work if these are set,
2229 regardless of wether we use the assp or not. */
2230
2231 outb(0, iobase + ASSP_CONTROL_B);
2232 outb(3, iobase + ASSP_CONTROL_A); /* M: Reserved bits... */
2233 outb(0, iobase + ASSP_CONTROL_C); /* M: Disable ASSP, ASSP IRQ's and FM Port */
2234
2235 /*
2236 * set up wavecache
2237 */
2238 for (i = 0; i < 16; i++) {
2239 /* Write 0 into the buffer area 0x1E0->1EF */
2240 outw(0x01E0 + i, iobase + WC_INDEX);
2241 outw(0x0000, iobase + WC_DATA);
2242
2243 /* The 1.10 test program seem to write 0 into the buffer area
2244 * 0x1D0-0x1DF too.*/
2245 outw(0x01D0 + i, iobase + WC_INDEX);
2246 outw(0x0000, iobase + WC_DATA);
2247 }
2248 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2249 (wave_get_register(chip, IDR7_WAVE_ROMRAM) & 0xFF00));
2250 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2251 wave_get_register(chip, IDR7_WAVE_ROMRAM) | 0x100);
2252 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2253 wave_get_register(chip, IDR7_WAVE_ROMRAM) & ~0x200);
2254 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2255 wave_get_register(chip, IDR7_WAVE_ROMRAM) | ~0x400);
2256
2257
2258 maestro_write(chip, IDR2_CRAM_DATA, 0x0000);
2259 /* Now back to the DirectSound stuff */
2260 /* audio serial configuration.. ? */
2261 maestro_write(chip, 0x08, 0xB004);
2262 maestro_write(chip, 0x09, 0x001B);
2263 maestro_write(chip, 0x0A, 0x8000);
2264 maestro_write(chip, 0x0B, 0x3F37);
2265 maestro_write(chip, 0x0C, 0x0098);
2266
2267 /* parallel in, has something to do with recording :) */
2268 maestro_write(chip, 0x0C,
2269 (maestro_read(chip, 0x0C) & ~0xF000) | 0x8000);
2270 /* parallel out */
2271 maestro_write(chip, 0x0C,
2272 (maestro_read(chip, 0x0C) & ~0x0F00) | 0x0500);
2273
2274 maestro_write(chip, 0x0D, 0x7632);
2275
2276 /* Wave cache control on - test off, sg off,
2277 enable, enable extra chans 1Mb */
2278
2279 w = inw(iobase + WC_CONTROL);
2280
2281 w &= ~0xFA00; /* Seems to be reserved? I don't know */
2282 w |= 0xA000; /* reserved... I don't know */
2283 w &= ~0x0200; /* Channels 56,57,58,59 as Extra Play,Rec Channel enable
2284 Seems to crash the Computer if enabled... */
2285 w |= 0x0100; /* Wave Cache Operation Enabled */
2286 w |= 0x0080; /* Channels 60/61 as Placback/Record enabled */
2287 w &= ~0x0060; /* Clear Wavtable Size */
2288 w |= 0x0020; /* Wavetable Size : 1MB */
2289 /* Bit 4 is reserved */
2290 w &= ~0x000C; /* DMA Stuff? I don't understand what the datasheet means */
2291 /* Bit 1 is reserved */
2292 w &= ~0x0001; /* Test Mode off */
2293
2294 outw(w, iobase + WC_CONTROL);
2295
2296 /* Now clear the APU control ram */
2297 for (i = 0; i < NR_APUS; i++) {
2298 for (w = 0; w < NR_APU_REGS; w++)
2299 apu_set_register(chip, i, w, 0);
2300
2301 }
2302 }
2303
2304 /* Enable IRQ's */
2305 static void snd_es1968_start_irq(struct es1968 *chip)
2306 {
2307 unsigned short w;
2308 w = ESM_HIRQ_DSIE | ESM_HIRQ_HW_VOLUME;
2309 if (chip->rmidi)
2310 w |= ESM_HIRQ_MPU401;
2311 outw(w, chip->io_port + ESM_PORT_HOST_IRQ);
2312 }
2313
2314 #ifdef CONFIG_PM
2315 /*
2316 * PM support
2317 */
2318 static int es1968_suspend(struct pci_dev *pci, pm_message_t state)
2319 {
2320 struct snd_card *card = pci_get_drvdata(pci);
2321 struct es1968 *chip = card->private_data;
2322
2323 if (! chip->do_pm)
2324 return 0;
2325
2326 chip->in_suspend = 1;
2327 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2328 snd_pcm_suspend_all(chip->pcm);
2329 snd_ac97_suspend(chip->ac97);
2330 snd_es1968_bob_stop(chip);
2331
2332 pci_disable_device(pci);
2333 pci_save_state(pci);
2334 pci_set_power_state(pci, pci_choose_state(pci, state));
2335 return 0;
2336 }
2337
2338 static int es1968_resume(struct pci_dev *pci)
2339 {
2340 struct snd_card *card = pci_get_drvdata(pci);
2341 struct es1968 *chip = card->private_data;
2342 struct esschan *es;
2343
2344 if (! chip->do_pm)
2345 return 0;
2346
2347 /* restore all our config */
2348 pci_set_power_state(pci, PCI_D0);
2349 pci_restore_state(pci);
2350 if (pci_enable_device(pci) < 0) {
2351 printk(KERN_ERR "es1968: pci_enable_device failed, "
2352 "disabling device\n");
2353 snd_card_disconnect(card);
2354 return -EIO;
2355 }
2356 pci_set_master(pci);
2357
2358 snd_es1968_chip_init(chip);
2359
2360 /* need to restore the base pointers.. */
2361 if (chip->dma.addr) {
2362 /* set PCMBAR */
2363 wave_set_register(chip, 0x01FC, chip->dma.addr >> 12);
2364 }
2365
2366 snd_es1968_start_irq(chip);
2367
2368 /* restore ac97 state */
2369 snd_ac97_resume(chip->ac97);
2370
2371 list_for_each_entry(es, &chip->substream_list, list) {
2372 switch (es->mode) {
2373 case ESM_MODE_PLAY:
2374 snd_es1968_playback_setup(chip, es, es->substream->runtime);
2375 break;
2376 case ESM_MODE_CAPTURE:
2377 snd_es1968_capture_setup(chip, es, es->substream->runtime);
2378 break;
2379 }
2380 }
2381
2382 /* start timer again */
2383 if (chip->bobclient)
2384 snd_es1968_bob_start(chip);
2385
2386 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2387 chip->in_suspend = 0;
2388 return 0;
2389 }
2390 #endif /* CONFIG_PM */
2391
2392 #ifdef SUPPORT_JOYSTICK
2393 #define JOYSTICK_ADDR 0x200
2394 static int __devinit snd_es1968_create_gameport(struct es1968 *chip, int dev)
2395 {
2396 struct gameport *gp;
2397 struct resource *r;
2398 u16 val;
2399
2400 if (!joystick[dev])
2401 return -ENODEV;
2402
2403 r = request_region(JOYSTICK_ADDR, 8, "ES1968 gameport");
2404 if (!r)
2405 return -EBUSY;
2406
2407 chip->gameport = gp = gameport_allocate_port();
2408 if (!gp) {
2409 printk(KERN_ERR "es1968: cannot allocate memory for gameport\n");
2410 release_and_free_resource(r);
2411 return -ENOMEM;
2412 }
2413
2414 pci_read_config_word(chip->pci, ESM_LEGACY_AUDIO_CONTROL, &val);
2415 pci_write_config_word(chip->pci, ESM_LEGACY_AUDIO_CONTROL, val | 0x04);
2416
2417 gameport_set_name(gp, "ES1968 Gameport");
2418 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
2419 gameport_set_dev_parent(gp, &chip->pci->dev);
2420 gp->io = JOYSTICK_ADDR;
2421 gameport_set_port_data(gp, r);
2422
2423 gameport_register_port(gp);
2424
2425 return 0;
2426 }
2427
2428 static void snd_es1968_free_gameport(struct es1968 *chip)
2429 {
2430 if (chip->gameport) {
2431 struct resource *r = gameport_get_port_data(chip->gameport);
2432
2433 gameport_unregister_port(chip->gameport);
2434 chip->gameport = NULL;
2435
2436 release_and_free_resource(r);
2437 }
2438 }
2439 #else
2440 static inline int snd_es1968_create_gameport(struct es1968 *chip, int dev) { return -ENOSYS; }
2441 static inline void snd_es1968_free_gameport(struct es1968 *chip) { }
2442 #endif
2443
2444 static int snd_es1968_free(struct es1968 *chip)
2445 {
2446 if (chip->io_port) {
2447 synchronize_irq(chip->irq);
2448 outw(1, chip->io_port + 0x04); /* clear WP interrupts */
2449 outw(0, chip->io_port + ESM_PORT_HOST_IRQ); /* disable IRQ */
2450 }
2451
2452 if (chip->irq >= 0)
2453 free_irq(chip->irq, chip);
2454 snd_es1968_free_gameport(chip);
2455 chip->master_switch = NULL;
2456 chip->master_volume = NULL;
2457 pci_release_regions(chip->pci);
2458 pci_disable_device(chip->pci);
2459 kfree(chip);
2460 return 0;
2461 }
2462
2463 static int snd_es1968_dev_free(struct snd_device *device)
2464 {
2465 struct es1968 *chip = device->device_data;
2466 return snd_es1968_free(chip);
2467 }
2468
2469 struct ess_device_list {
2470 unsigned short type; /* chip type */
2471 unsigned short vendor; /* subsystem vendor id */
2472 };
2473
2474 static struct ess_device_list pm_whitelist[] __devinitdata = {
2475 { TYPE_MAESTRO2E, 0x0e11 }, /* Compaq Armada */
2476 { TYPE_MAESTRO2E, 0x1028 },
2477 { TYPE_MAESTRO2E, 0x103c },
2478 { TYPE_MAESTRO2E, 0x1179 },
2479 { TYPE_MAESTRO2E, 0x14c0 }, /* HP omnibook 4150 */
2480 { TYPE_MAESTRO2E, 0x1558 },
2481 };
2482
2483 static struct ess_device_list mpu_blacklist[] __devinitdata = {
2484 { TYPE_MAESTRO2, 0x125d },
2485 };
2486
2487 static int __devinit snd_es1968_create(struct snd_card *card,
2488 struct pci_dev *pci,
2489 int total_bufsize,
2490 int play_streams,
2491 int capt_streams,
2492 int chip_type,
2493 int do_pm,
2494 struct es1968 **chip_ret)
2495 {
2496 static struct snd_device_ops ops = {
2497 .dev_free = snd_es1968_dev_free,
2498 };
2499 struct es1968 *chip;
2500 int i, err;
2501
2502 *chip_ret = NULL;
2503
2504 /* enable PCI device */
2505 if ((err = pci_enable_device(pci)) < 0)
2506 return err;
2507 /* check, if we can restrict PCI DMA transfers to 28 bits */
2508 if (pci_set_dma_mask(pci, DMA_28BIT_MASK) < 0 ||
2509 pci_set_consistent_dma_mask(pci, DMA_28BIT_MASK) < 0) {
2510 snd_printk(KERN_ERR "architecture does not support 28bit PCI busmaster DMA\n");
2511 pci_disable_device(pci);
2512 return -ENXIO;
2513 }
2514
2515 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2516 if (! chip) {
2517 pci_disable_device(pci);
2518 return -ENOMEM;
2519 }
2520
2521 /* Set Vars */
2522 chip->type = chip_type;
2523 spin_lock_init(&chip->reg_lock);
2524 spin_lock_init(&chip->substream_lock);
2525 INIT_LIST_HEAD(&chip->buf_list);
2526 INIT_LIST_HEAD(&chip->substream_list);
2527 spin_lock_init(&chip->ac97_lock);
2528 mutex_init(&chip->memory_mutex);
2529 tasklet_init(&chip->hwvol_tq, es1968_update_hw_volume, (unsigned long)chip);
2530 chip->card = card;
2531 chip->pci = pci;
2532 chip->irq = -1;
2533 chip->total_bufsize = total_bufsize; /* in bytes */
2534 chip->playback_streams = play_streams;
2535 chip->capture_streams = capt_streams;
2536
2537 if ((err = pci_request_regions(pci, "ESS Maestro")) < 0) {
2538 kfree(chip);
2539 pci_disable_device(pci);
2540 return err;
2541 }
2542 chip->io_port = pci_resource_start(pci, 0);
2543 if (request_irq(pci->irq, snd_es1968_interrupt, IRQF_SHARED,
2544 "ESS Maestro", chip)) {
2545 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2546 snd_es1968_free(chip);
2547 return -EBUSY;
2548 }
2549 chip->irq = pci->irq;
2550
2551 /* Clear Maestro_map */
2552 for (i = 0; i < 32; i++)
2553 chip->maestro_map[i] = 0;
2554
2555 /* Clear Apu Map */
2556 for (i = 0; i < NR_APUS; i++)
2557 chip->apu[i] = ESM_APU_FREE;
2558
2559 /* just to be sure */
2560 pci_set_master(pci);
2561
2562 if (do_pm > 1) {
2563 /* disable power-management if not on the whitelist */
2564 unsigned short vend;
2565 pci_read_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
2566 for (i = 0; i < (int)ARRAY_SIZE(pm_whitelist); i++) {
2567 if (chip->type == pm_whitelist[i].type &&
2568 vend == pm_whitelist[i].vendor) {
2569 do_pm = 1;
2570 break;
2571 }
2572 }
2573 if (do_pm > 1) {
2574 /* not matched; disabling pm */
2575 printk(KERN_INFO "es1968: not attempting power management.\n");
2576 do_pm = 0;
2577 }
2578 }
2579 chip->do_pm = do_pm;
2580
2581 snd_es1968_chip_init(chip);
2582
2583 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2584 snd_es1968_free(chip);
2585 return err;
2586 }
2587
2588 snd_card_set_dev(card, &pci->dev);
2589
2590 *chip_ret = chip;
2591
2592 return 0;
2593 }
2594
2595
2596 /*
2597 */
2598 static int __devinit snd_es1968_probe(struct pci_dev *pci,
2599 const struct pci_device_id *pci_id)
2600 {
2601 static int dev;
2602 struct snd_card *card;
2603 struct es1968 *chip;
2604 unsigned int i;
2605 int err;
2606
2607 if (dev >= SNDRV_CARDS)
2608 return -ENODEV;
2609 if (!enable[dev]) {
2610 dev++;
2611 return -ENOENT;
2612 }
2613
2614 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2615 if (!card)
2616 return -ENOMEM;
2617
2618 if (total_bufsize[dev] < 128)
2619 total_bufsize[dev] = 128;
2620 if (total_bufsize[dev] > 4096)
2621 total_bufsize[dev] = 4096;
2622 if ((err = snd_es1968_create(card, pci,
2623 total_bufsize[dev] * 1024, /* in bytes */
2624 pcm_substreams_p[dev],
2625 pcm_substreams_c[dev],
2626 pci_id->driver_data,
2627 use_pm[dev],
2628 &chip)) < 0) {
2629 snd_card_free(card);
2630 return err;
2631 }
2632 card->private_data = chip;
2633
2634 switch (chip->type) {
2635 case TYPE_MAESTRO2E:
2636 strcpy(card->driver, "ES1978");
2637 strcpy(card->shortname, "ESS ES1978 (Maestro 2E)");
2638 break;
2639 case TYPE_MAESTRO2:
2640 strcpy(card->driver, "ES1968");
2641 strcpy(card->shortname, "ESS ES1968 (Maestro 2)");
2642 break;
2643 case TYPE_MAESTRO:
2644 strcpy(card->driver, "ESM1");
2645 strcpy(card->shortname, "ESS Maestro 1");
2646 break;
2647 }
2648
2649 if ((err = snd_es1968_pcm(chip, 0)) < 0) {
2650 snd_card_free(card);
2651 return err;
2652 }
2653
2654 if ((err = snd_es1968_mixer(chip)) < 0) {
2655 snd_card_free(card);
2656 return err;
2657 }
2658
2659 if (enable_mpu[dev] == 2) {
2660 /* check the black list */
2661 unsigned short vend;
2662 pci_read_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
2663 for (i = 0; i < ARRAY_SIZE(mpu_blacklist); i++) {
2664 if (chip->type == mpu_blacklist[i].type &&
2665 vend == mpu_blacklist[i].vendor) {
2666 enable_mpu[dev] = 0;
2667 break;
2668 }
2669 }
2670 }
2671 if (enable_mpu[dev]) {
2672 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_MPU401,
2673 chip->io_port + ESM_MPU401_PORT,
2674 MPU401_INFO_INTEGRATED,
2675 chip->irq, 0, &chip->rmidi)) < 0) {
2676 printk(KERN_WARNING "es1968: skipping MPU-401 MIDI support..\n");
2677 }
2678 }
2679
2680 snd_es1968_create_gameport(chip, dev);
2681
2682 snd_es1968_start_irq(chip);
2683
2684 chip->clock = clock[dev];
2685 if (! chip->clock)
2686 es1968_measure_clock(chip);
2687
2688 sprintf(card->longname, "%s at 0x%lx, irq %i",
2689 card->shortname, chip->io_port, chip->irq);
2690
2691 if ((err = snd_card_register(card)) < 0) {
2692 snd_card_free(card);
2693 return err;
2694 }
2695 pci_set_drvdata(pci, card);
2696 dev++;
2697 return 0;
2698 }
2699
2700 static void __devexit snd_es1968_remove(struct pci_dev *pci)
2701 {
2702 snd_card_free(pci_get_drvdata(pci));
2703 pci_set_drvdata(pci, NULL);
2704 }
2705
2706 static struct pci_driver driver = {
2707 .name = "ES1968 (ESS Maestro)",
2708 .id_table = snd_es1968_ids,
2709 .probe = snd_es1968_probe,
2710 .remove = __devexit_p(snd_es1968_remove),
2711 #ifdef CONFIG_PM
2712 .suspend = es1968_suspend,
2713 .resume = es1968_resume,
2714 #endif
2715 };
2716
2717 static int __init alsa_card_es1968_init(void)
2718 {
2719 return pci_register_driver(&driver);
2720 }
2721
2722 static void __exit alsa_card_es1968_exit(void)
2723 {
2724 pci_unregister_driver(&driver);
2725 }
2726
2727 module_init(alsa_card_es1968_init)
2728 module_exit(alsa_card_es1968_exit)
WRT350N Kernel Patches