?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge git://git.kernel.org/pub/scm/linux/kernel/git/mingo/linux-2.6-sched
[wrt350n-kernel.git] / sound / pci / ice1712 / pontis.c
blob4945c81e8a96094d2c3bb73f9555a9d5ee6cd8b5
1 /*
2 * ALSA driver for ICEnsemble VT1724 (Envy24HT)
3 *
4 * Lowlevel functions for Pontis MS300
5 *
6 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24 #include <asm/io.h>
25 #include <linux/delay.h>
26 #include <linux/interrupt.h>
27 #include <linux/init.h>
28 #include <linux/slab.h>
29 #include <linux/mutex.h>
30
31 #include <sound/core.h>
32 #include <sound/info.h>
33 #include <sound/tlv.h>
34
35 #include "ice1712.h"
36 #include "envy24ht.h"
37 #include "pontis.h"
38
39 /* I2C addresses */
40 #define WM_DEV 0x34
41 #define CS_DEV 0x20
42
43 /* WM8776 registers */
44 #define WM_HP_ATTEN_L 0x00 /* headphone left attenuation */
45 #define WM_HP_ATTEN_R 0x01 /* headphone left attenuation */
46 #define WM_HP_MASTER 0x02 /* headphone master (both channels), override LLR */
47 #define WM_DAC_ATTEN_L 0x03 /* digital left attenuation */
48 #define WM_DAC_ATTEN_R 0x04
49 #define WM_DAC_MASTER 0x05
50 #define WM_PHASE_SWAP 0x06 /* DAC phase swap */
51 #define WM_DAC_CTRL1 0x07
52 #define WM_DAC_MUTE 0x08
53 #define WM_DAC_CTRL2 0x09
54 #define WM_DAC_INT 0x0a
55 #define WM_ADC_INT 0x0b
56 #define WM_MASTER_CTRL 0x0c
57 #define WM_POWERDOWN 0x0d
58 #define WM_ADC_ATTEN_L 0x0e
59 #define WM_ADC_ATTEN_R 0x0f
60 #define WM_ALC_CTRL1 0x10
61 #define WM_ALC_CTRL2 0x11
62 #define WM_ALC_CTRL3 0x12
63 #define WM_NOISE_GATE 0x13
64 #define WM_LIMITER 0x14
65 #define WM_ADC_MUX 0x15
66 #define WM_OUT_MUX 0x16
67 #define WM_RESET 0x17
68
69 /*
70 * GPIO
71 */
72 #define PONTIS_CS_CS (1<<4) /* CS */
73 #define PONTIS_CS_CLK (1<<5) /* CLK */
74 #define PONTIS_CS_RDATA (1<<6) /* CS8416 -> VT1720 */
75 #define PONTIS_CS_WDATA (1<<7) /* VT1720 -> CS8416 */
76
77
78 /*
79 * get the current register value of WM codec
80 */
81 static unsigned short wm_get(struct snd_ice1712 *ice, int reg)
82 {
83 reg <<= 1;
84 return ((unsigned short)ice->akm[0].images[reg] << 8) |
85 ice->akm[0].images[reg + 1];
86 }
87
88 /*
89 * set the register value of WM codec and remember it
90 */
91 static void wm_put_nocache(struct snd_ice1712 *ice, int reg, unsigned short val)
92 {
93 unsigned short cval;
94 cval = (reg << 9) | val;
95 snd_vt1724_write_i2c(ice, WM_DEV, cval >> 8, cval & 0xff);
96 }
97
98 static void wm_put(struct snd_ice1712 *ice, int reg, unsigned short val)
99 {
100 wm_put_nocache(ice, reg, val);
101 reg <<= 1;
102 ice->akm[0].images[reg] = val >> 8;
103 ice->akm[0].images[reg + 1] = val;
104 }
105
106 /*
107 * DAC volume attenuation mixer control (-64dB to 0dB)
108 */
109
110 #define DAC_0dB 0xff
111 #define DAC_RES 128
112 #define DAC_MIN (DAC_0dB - DAC_RES)
113
114 static int wm_dac_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
115 {
116 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
117 uinfo->count = 2;
118 uinfo->value.integer.min = 0; /* mute */
119 uinfo->value.integer.max = DAC_RES; /* 0dB, 0.5dB step */
120 return 0;
121 }
122
123 static int wm_dac_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
124 {
125 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
126 unsigned short val;
127 int i;
128
129 mutex_lock(&ice->gpio_mutex);
130 for (i = 0; i < 2; i++) {
131 val = wm_get(ice, WM_DAC_ATTEN_L + i) & 0xff;
132 val = val > DAC_MIN ? (val - DAC_MIN) : 0;
133 ucontrol->value.integer.value[i] = val;
134 }
135 mutex_unlock(&ice->gpio_mutex);
136 return 0;
137 }
138
139 static int wm_dac_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
140 {
141 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
142 unsigned short oval, nval;
143 int i, idx, change = 0;
144
145 mutex_lock(&ice->gpio_mutex);
146 for (i = 0; i < 2; i++) {
147 nval = ucontrol->value.integer.value[i];
148 nval = (nval ? (nval + DAC_MIN) : 0) & 0xff;
149 idx = WM_DAC_ATTEN_L + i;
150 oval = wm_get(ice, idx) & 0xff;
151 if (oval != nval) {
152 wm_put(ice, idx, nval);
153 wm_put_nocache(ice, idx, nval | 0x100);
154 change = 1;
155 }
156 }
157 mutex_unlock(&ice->gpio_mutex);
158 return change;
159 }
160
161 /*
162 * ADC gain mixer control (-64dB to 0dB)
163 */
164
165 #define ADC_0dB 0xcf
166 #define ADC_RES 128
167 #define ADC_MIN (ADC_0dB - ADC_RES)
168
169 static int wm_adc_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
170 {
171 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
172 uinfo->count = 2;
173 uinfo->value.integer.min = 0; /* mute (-64dB) */
174 uinfo->value.integer.max = ADC_RES; /* 0dB, 0.5dB step */
175 return 0;
176 }
177
178 static int wm_adc_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
179 {
180 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
181 unsigned short val;
182 int i;
183
184 mutex_lock(&ice->gpio_mutex);
185 for (i = 0; i < 2; i++) {
186 val = wm_get(ice, WM_ADC_ATTEN_L + i) & 0xff;
187 val = val > ADC_MIN ? (val - ADC_MIN) : 0;
188 ucontrol->value.integer.value[i] = val;
189 }
190 mutex_unlock(&ice->gpio_mutex);
191 return 0;
192 }
193
194 static int wm_adc_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
195 {
196 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
197 unsigned short ovol, nvol;
198 int i, idx, change = 0;
199
200 mutex_lock(&ice->gpio_mutex);
201 for (i = 0; i < 2; i++) {
202 nvol = ucontrol->value.integer.value[i];
203 nvol = nvol ? (nvol + ADC_MIN) : 0;
204 idx = WM_ADC_ATTEN_L + i;
205 ovol = wm_get(ice, idx) & 0xff;
206 if (ovol != nvol) {
207 wm_put(ice, idx, nvol);
208 change = 1;
209 }
210 }
211 mutex_unlock(&ice->gpio_mutex);
212 return change;
213 }
214
215 /*
216 * ADC input mux mixer control
217 */
218 #define wm_adc_mux_info snd_ctl_boolean_mono_info
219
220 static int wm_adc_mux_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
221 {
222 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
223 int bit = kcontrol->private_value;
224
225 mutex_lock(&ice->gpio_mutex);
226 ucontrol->value.integer.value[0] = (wm_get(ice, WM_ADC_MUX) & (1 << bit)) ? 1 : 0;
227 mutex_unlock(&ice->gpio_mutex);
228 return 0;
229 }
230
231 static int wm_adc_mux_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
232 {
233 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
234 int bit = kcontrol->private_value;
235 unsigned short oval, nval;
236 int change;
237
238 mutex_lock(&ice->gpio_mutex);
239 nval = oval = wm_get(ice, WM_ADC_MUX);
240 if (ucontrol->value.integer.value[0])
241 nval |= (1 << bit);
242 else
243 nval &= ~(1 << bit);
244 change = nval != oval;
245 if (change) {
246 wm_put(ice, WM_ADC_MUX, nval);
247 }
248 mutex_unlock(&ice->gpio_mutex);
249 return 0;
250 }
251
252 /*
253 * Analog bypass (In -> Out)
254 */
255 #define wm_bypass_info snd_ctl_boolean_mono_info
256
257 static int wm_bypass_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
258 {
259 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
260
261 mutex_lock(&ice->gpio_mutex);
262 ucontrol->value.integer.value[0] = (wm_get(ice, WM_OUT_MUX) & 0x04) ? 1 : 0;
263 mutex_unlock(&ice->gpio_mutex);
264 return 0;
265 }
266
267 static int wm_bypass_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
268 {
269 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
270 unsigned short val, oval;
271 int change = 0;
272
273 mutex_lock(&ice->gpio_mutex);
274 val = oval = wm_get(ice, WM_OUT_MUX);
275 if (ucontrol->value.integer.value[0])
276 val |= 0x04;
277 else
278 val &= ~0x04;
279 if (val != oval) {
280 wm_put(ice, WM_OUT_MUX, val);
281 change = 1;
282 }
283 mutex_unlock(&ice->gpio_mutex);
284 return change;
285 }
286
287 /*
288 * Left/Right swap
289 */
290 #define wm_chswap_info snd_ctl_boolean_mono_info
291
292 static int wm_chswap_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
293 {
294 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
295
296 mutex_lock(&ice->gpio_mutex);
297 ucontrol->value.integer.value[0] = (wm_get(ice, WM_DAC_CTRL1) & 0xf0) != 0x90;
298 mutex_unlock(&ice->gpio_mutex);
299 return 0;
300 }
301
302 static int wm_chswap_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
303 {
304 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
305 unsigned short val, oval;
306 int change = 0;
307
308 mutex_lock(&ice->gpio_mutex);
309 oval = wm_get(ice, WM_DAC_CTRL1);
310 val = oval & 0x0f;
311 if (ucontrol->value.integer.value[0])
312 val |= 0x60;
313 else
314 val |= 0x90;
315 if (val != oval) {
316 wm_put(ice, WM_DAC_CTRL1, val);
317 wm_put_nocache(ice, WM_DAC_CTRL1, val);
318 change = 1;
319 }
320 mutex_unlock(&ice->gpio_mutex);
321 return change;
322 }
323
324 /*
325 * write data in the SPI mode
326 */
327 static void set_gpio_bit(struct snd_ice1712 *ice, unsigned int bit, int val)
328 {
329 unsigned int tmp = snd_ice1712_gpio_read(ice);
330 if (val)
331 tmp |= bit;
332 else
333 tmp &= ~bit;
334 snd_ice1712_gpio_write(ice, tmp);
335 }
336
337 static void spi_send_byte(struct snd_ice1712 *ice, unsigned char data)
338 {
339 int i;
340 for (i = 0; i < 8; i++) {
341 set_gpio_bit(ice, PONTIS_CS_CLK, 0);
342 udelay(1);
343 set_gpio_bit(ice, PONTIS_CS_WDATA, data & 0x80);
344 udelay(1);
345 set_gpio_bit(ice, PONTIS_CS_CLK, 1);
346 udelay(1);
347 data <<= 1;
348 }
349 }
350
351 static unsigned int spi_read_byte(struct snd_ice1712 *ice)
352 {
353 int i;
354 unsigned int val = 0;
355
356 for (i = 0; i < 8; i++) {
357 val <<= 1;
358 set_gpio_bit(ice, PONTIS_CS_CLK, 0);
359 udelay(1);
360 if (snd_ice1712_gpio_read(ice) & PONTIS_CS_RDATA)
361 val |= 1;
362 udelay(1);
363 set_gpio_bit(ice, PONTIS_CS_CLK, 1);
364 udelay(1);
365 }
366 return val;
367 }
368
369
370 static void spi_write(struct snd_ice1712 *ice, unsigned int dev, unsigned int reg, unsigned int data)
371 {
372 snd_ice1712_gpio_set_dir(ice, PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK);
373 snd_ice1712_gpio_set_mask(ice, ~(PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK));
374 set_gpio_bit(ice, PONTIS_CS_CS, 0);
375 spi_send_byte(ice, dev & ~1); /* WRITE */
376 spi_send_byte(ice, reg); /* MAP */
377 spi_send_byte(ice, data); /* DATA */
378 /* trigger */
379 set_gpio_bit(ice, PONTIS_CS_CS, 1);
380 udelay(1);
381 /* restore */
382 snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
383 snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
384 }
385
386 static unsigned int spi_read(struct snd_ice1712 *ice, unsigned int dev, unsigned int reg)
387 {
388 unsigned int val;
389 snd_ice1712_gpio_set_dir(ice, PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK);
390 snd_ice1712_gpio_set_mask(ice, ~(PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK));
391 set_gpio_bit(ice, PONTIS_CS_CS, 0);
392 spi_send_byte(ice, dev & ~1); /* WRITE */
393 spi_send_byte(ice, reg); /* MAP */
394 /* trigger */
395 set_gpio_bit(ice, PONTIS_CS_CS, 1);
396 udelay(1);
397 set_gpio_bit(ice, PONTIS_CS_CS, 0);
398 spi_send_byte(ice, dev | 1); /* READ */
399 val = spi_read_byte(ice);
400 /* trigger */
401 set_gpio_bit(ice, PONTIS_CS_CS, 1);
402 udelay(1);
403 /* restore */
404 snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
405 snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
406 return val;
407 }
408
409
410 /*
411 * SPDIF input source
412 */
413 static int cs_source_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
414 {
415 static const char * const texts[] = {
416 "Coax", /* RXP0 */
417 "Optical", /* RXP1 */
418 "CD", /* RXP2 */
419 };
420 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
421 uinfo->count = 1;
422 uinfo->value.enumerated.items = 3;
423 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
424 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
425 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
426 return 0;
427 }
428
429 static int cs_source_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
430 {
431 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
432
433 mutex_lock(&ice->gpio_mutex);
434 ucontrol->value.enumerated.item[0] = ice->gpio.saved[0];
435 mutex_unlock(&ice->gpio_mutex);
436 return 0;
437 }
438
439 static int cs_source_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
440 {
441 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
442 unsigned char val;
443 int change = 0;
444
445 mutex_lock(&ice->gpio_mutex);
446 if (ucontrol->value.enumerated.item[0] != ice->gpio.saved[0]) {
447 ice->gpio.saved[0] = ucontrol->value.enumerated.item[0] & 3;
448 val = 0x80 | (ice->gpio.saved[0] << 3);
449 spi_write(ice, CS_DEV, 0x04, val);
450 change = 1;
451 }
452 mutex_unlock(&ice->gpio_mutex);
453 return 0;
454 }
455
456
457 /*
458 * GPIO controls
459 */
460 static int pontis_gpio_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
461 {
462 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
463 uinfo->count = 1;
464 uinfo->value.integer.min = 0;
465 uinfo->value.integer.max = 0xffff; /* 16bit */
466 return 0;
467 }
468
469 static int pontis_gpio_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
470 {
471 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
472 mutex_lock(&ice->gpio_mutex);
473 /* 4-7 reserved */
474 ucontrol->value.integer.value[0] = (~ice->gpio.write_mask & 0xffff) | 0x00f0;
475 mutex_unlock(&ice->gpio_mutex);
476 return 0;
477 }
478
479 static int pontis_gpio_mask_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
480 {
481 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
482 unsigned int val;
483 int changed;
484 mutex_lock(&ice->gpio_mutex);
485 /* 4-7 reserved */
486 val = (~ucontrol->value.integer.value[0] & 0xffff) | 0x00f0;
487 changed = val != ice->gpio.write_mask;
488 ice->gpio.write_mask = val;
489 mutex_unlock(&ice->gpio_mutex);
490 return changed;
491 }
492
493 static int pontis_gpio_dir_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
494 {
495 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
496 mutex_lock(&ice->gpio_mutex);
497 /* 4-7 reserved */
498 ucontrol->value.integer.value[0] = ice->gpio.direction & 0xff0f;
499 mutex_unlock(&ice->gpio_mutex);
500 return 0;
501 }
502
503 static int pontis_gpio_dir_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
504 {
505 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
506 unsigned int val;
507 int changed;
508 mutex_lock(&ice->gpio_mutex);
509 /* 4-7 reserved */
510 val = ucontrol->value.integer.value[0] & 0xff0f;
511 changed = (val != ice->gpio.direction);
512 ice->gpio.direction = val;
513 mutex_unlock(&ice->gpio_mutex);
514 return changed;
515 }
516
517 static int pontis_gpio_data_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
518 {
519 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
520 mutex_lock(&ice->gpio_mutex);
521 snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
522 snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
523 ucontrol->value.integer.value[0] = snd_ice1712_gpio_read(ice) & 0xffff;
524 mutex_unlock(&ice->gpio_mutex);
525 return 0;
526 }
527
528 static int pontis_gpio_data_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
529 {
530 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
531 unsigned int val, nval;
532 int changed = 0;
533 mutex_lock(&ice->gpio_mutex);
534 snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
535 snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
536 val = snd_ice1712_gpio_read(ice) & 0xffff;
537 nval = ucontrol->value.integer.value[0] & 0xffff;
538 if (val != nval) {
539 snd_ice1712_gpio_write(ice, nval);
540 changed = 1;
541 }
542 mutex_unlock(&ice->gpio_mutex);
543 return changed;
544 }
545
546 static const DECLARE_TLV_DB_SCALE(db_scale_volume, -6400, 50, 1);
547
548 /*
549 * mixers
550 */
551
552 static struct snd_kcontrol_new pontis_controls[] __devinitdata = {
553 {
554 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
555 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
556 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
557 .name = "PCM Playback Volume",
558 .info = wm_dac_vol_info,
559 .get = wm_dac_vol_get,
560 .put = wm_dac_vol_put,
561 .tlv = { .p = db_scale_volume },
562 },
563 {
564 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
565 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
566 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
567 .name = "Capture Volume",
568 .info = wm_adc_vol_info,
569 .get = wm_adc_vol_get,
570 .put = wm_adc_vol_put,
571 .tlv = { .p = db_scale_volume },
572 },
573 {
574 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
575 .name = "CD Capture Switch",
576 .info = wm_adc_mux_info,
577 .get = wm_adc_mux_get,
578 .put = wm_adc_mux_put,
579 .private_value = 0,
580 },
581 {
582 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
583 .name = "Line Capture Switch",
584 .info = wm_adc_mux_info,
585 .get = wm_adc_mux_get,
586 .put = wm_adc_mux_put,
587 .private_value = 1,
588 },
589 {
590 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
591 .name = "Analog Bypass Switch",
592 .info = wm_bypass_info,
593 .get = wm_bypass_get,
594 .put = wm_bypass_put,
595 },
596 {
597 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
598 .name = "Swap Output Channels",
599 .info = wm_chswap_info,
600 .get = wm_chswap_get,
601 .put = wm_chswap_put,
602 },
603 {
604 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
605 .name = "IEC958 Input Source",
606 .info = cs_source_info,
607 .get = cs_source_get,
608 .put = cs_source_put,
609 },
610 /* FIXME: which interface? */
611 {
612 .iface = SNDRV_CTL_ELEM_IFACE_CARD,
613 .name = "GPIO Mask",
614 .info = pontis_gpio_mask_info,
615 .get = pontis_gpio_mask_get,
616 .put = pontis_gpio_mask_put,
617 },
618 {
619 .iface = SNDRV_CTL_ELEM_IFACE_CARD,
620 .name = "GPIO Direction",
621 .info = pontis_gpio_mask_info,
622 .get = pontis_gpio_dir_get,
623 .put = pontis_gpio_dir_put,
624 },
625 {
626 .iface = SNDRV_CTL_ELEM_IFACE_CARD,
627 .name = "GPIO Data",
628 .info = pontis_gpio_mask_info,
629 .get = pontis_gpio_data_get,
630 .put = pontis_gpio_data_put,
631 },
632 };
633
634
635 /*
636 * WM codec registers
637 */
638 static void wm_proc_regs_write(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
639 {
640 struct snd_ice1712 *ice = (struct snd_ice1712 *)entry->private_data;
641 char line[64];
642 unsigned int reg, val;
643 mutex_lock(&ice->gpio_mutex);
644 while (!snd_info_get_line(buffer, line, sizeof(line))) {
645 if (sscanf(line, "%x %x", &reg, &val) != 2)
646 continue;
647 if (reg <= 0x17 && val <= 0xffff)
648 wm_put(ice, reg, val);
649 }
650 mutex_unlock(&ice->gpio_mutex);
651 }
652
653 static void wm_proc_regs_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
654 {
655 struct snd_ice1712 *ice = (struct snd_ice1712 *)entry->private_data;
656 int reg, val;
657
658 mutex_lock(&ice->gpio_mutex);
659 for (reg = 0; reg <= 0x17; reg++) {
660 val = wm_get(ice, reg);
661 snd_iprintf(buffer, "%02x = %04x\n", reg, val);
662 }
663 mutex_unlock(&ice->gpio_mutex);
664 }
665
666 static void wm_proc_init(struct snd_ice1712 *ice)
667 {
668 struct snd_info_entry *entry;
669 if (! snd_card_proc_new(ice->card, "wm_codec", &entry)) {
670 snd_info_set_text_ops(entry, ice, wm_proc_regs_read);
671 entry->mode |= S_IWUSR;
672 entry->c.text.write = wm_proc_regs_write;
673 }
674 }
675
676 static void cs_proc_regs_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
677 {
678 struct snd_ice1712 *ice = (struct snd_ice1712 *)entry->private_data;
679 int reg, val;
680
681 mutex_lock(&ice->gpio_mutex);
682 for (reg = 0; reg <= 0x26; reg++) {
683 val = spi_read(ice, CS_DEV, reg);
684 snd_iprintf(buffer, "%02x = %02x\n", reg, val);
685 }
686 val = spi_read(ice, CS_DEV, 0x7f);
687 snd_iprintf(buffer, "%02x = %02x\n", 0x7f, val);
688 mutex_unlock(&ice->gpio_mutex);
689 }
690
691 static void cs_proc_init(struct snd_ice1712 *ice)
692 {
693 struct snd_info_entry *entry;
694 if (! snd_card_proc_new(ice->card, "cs_codec", &entry))
695 snd_info_set_text_ops(entry, ice, cs_proc_regs_read);
696 }
697
698
699 static int __devinit pontis_add_controls(struct snd_ice1712 *ice)
700 {
701 unsigned int i;
702 int err;
703
704 for (i = 0; i < ARRAY_SIZE(pontis_controls); i++) {
705 err = snd_ctl_add(ice->card, snd_ctl_new1(&pontis_controls[i], ice));
706 if (err < 0)
707 return err;
708 }
709
710 wm_proc_init(ice);
711 cs_proc_init(ice);
712
713 return 0;
714 }
715
716
717 /*
718 * initialize the chip
719 */
720 static int __devinit pontis_init(struct snd_ice1712 *ice)
721 {
722 static const unsigned short wm_inits[] = {
723 /* These come first to reduce init pop noise */
724 WM_ADC_MUX, 0x00c0, /* ADC mute */
725 WM_DAC_MUTE, 0x0001, /* DAC softmute */
726 WM_DAC_CTRL1, 0x0000, /* DAC mute */
727
728 WM_POWERDOWN, 0x0008, /* All power-up except HP */
729 WM_RESET, 0x0000, /* reset */
730 };
731 static const unsigned short wm_inits2[] = {
732 WM_MASTER_CTRL, 0x0022, /* 256fs, slave mode */
733 WM_DAC_INT, 0x0022, /* I2S, normal polarity, 24bit */
734 WM_ADC_INT, 0x0022, /* I2S, normal polarity, 24bit */
735 WM_DAC_CTRL1, 0x0090, /* DAC L/R */
736 WM_OUT_MUX, 0x0001, /* OUT DAC */
737 WM_HP_ATTEN_L, 0x0179, /* HP 0dB */
738 WM_HP_ATTEN_R, 0x0179, /* HP 0dB */
739 WM_DAC_ATTEN_L, 0x0000, /* DAC 0dB */
740 WM_DAC_ATTEN_L, 0x0100, /* DAC 0dB */
741 WM_DAC_ATTEN_R, 0x0000, /* DAC 0dB */
742 WM_DAC_ATTEN_R, 0x0100, /* DAC 0dB */
743 // WM_DAC_MASTER, 0x0100, /* DAC master muted */
744 WM_PHASE_SWAP, 0x0000, /* phase normal */
745 WM_DAC_CTRL2, 0x0000, /* no deemphasis, no ZFLG */
746 WM_ADC_ATTEN_L, 0x0000, /* ADC muted */
747 WM_ADC_ATTEN_R, 0x0000, /* ADC muted */
748 #if 0
749 WM_ALC_CTRL1, 0x007b, /* */
750 WM_ALC_CTRL2, 0x0000, /* */
751 WM_ALC_CTRL3, 0x0000, /* */
752 WM_NOISE_GATE, 0x0000, /* */
753 #endif
754 WM_DAC_MUTE, 0x0000, /* DAC unmute */
755 WM_ADC_MUX, 0x0003, /* ADC unmute, both CD/Line On */
756 };
757 static const unsigned char cs_inits[] = {
758 0x04, 0x80, /* RUN, RXP0 */
759 0x05, 0x05, /* slave, 24bit */
760 0x01, 0x00,
761 0x02, 0x00,
762 0x03, 0x00,
763 };
764 unsigned int i;
765
766 ice->vt1720 = 1;
767 ice->num_total_dacs = 2;
768 ice->num_total_adcs = 2;
769
770 /* to remeber the register values */
771 ice->akm = kzalloc(sizeof(struct snd_akm4xxx), GFP_KERNEL);
772 if (! ice->akm)
773 return -ENOMEM;
774 ice->akm_codecs = 1;
775
776 /* HACK - use this as the SPDIF source.
777 * don't call snd_ice1712_gpio_get/put(), otherwise it's overwritten
778 */
779 ice->gpio.saved[0] = 0;
780
781 /* initialize WM8776 codec */
782 for (i = 0; i < ARRAY_SIZE(wm_inits); i += 2)
783 wm_put(ice, wm_inits[i], wm_inits[i+1]);
784 schedule_timeout_uninterruptible(1);
785 for (i = 0; i < ARRAY_SIZE(wm_inits2); i += 2)
786 wm_put(ice, wm_inits2[i], wm_inits2[i+1]);
787
788 /* initialize CS8416 codec */
789 /* assert PRST#; MT05 bit 7 */
790 outb(inb(ICEMT1724(ice, AC97_CMD)) | 0x80, ICEMT1724(ice, AC97_CMD));
791 mdelay(5);
792 /* deassert PRST# */
793 outb(inb(ICEMT1724(ice, AC97_CMD)) & ~0x80, ICEMT1724(ice, AC97_CMD));
794
795 for (i = 0; i < ARRAY_SIZE(cs_inits); i += 2)
796 spi_write(ice, CS_DEV, cs_inits[i], cs_inits[i+1]);
797
798 return 0;
799 }
800
801
802 /*
803 * Pontis boards don't provide the EEPROM data at all.
804 * hence the driver needs to sets up it properly.
805 */
806
807 static unsigned char pontis_eeprom[] __devinitdata = {
808 [ICE_EEP2_SYSCONF] = 0x08, /* clock 256, mpu401, spdif-in/ADC, 1DAC */
809 [ICE_EEP2_ACLINK] = 0x80, /* I2S */
810 [ICE_EEP2_I2S] = 0xf8, /* vol, 96k, 24bit, 192k */
811 [ICE_EEP2_SPDIF] = 0xc3, /* out-en, out-int, spdif-in */
812 [ICE_EEP2_GPIO_DIR] = 0x07,
813 [ICE_EEP2_GPIO_DIR1] = 0x00,
814 [ICE_EEP2_GPIO_DIR2] = 0x00, /* ignored */
815 [ICE_EEP2_GPIO_MASK] = 0x0f, /* 4-7 reserved for CS8416 */
816 [ICE_EEP2_GPIO_MASK1] = 0xff,
817 [ICE_EEP2_GPIO_MASK2] = 0x00, /* ignored */
818 [ICE_EEP2_GPIO_STATE] = 0x06, /* 0-low, 1-high, 2-high */
819 [ICE_EEP2_GPIO_STATE1] = 0x00,
820 [ICE_EEP2_GPIO_STATE2] = 0x00, /* ignored */
821 };
822
823 /* entry point */
824 struct snd_ice1712_card_info snd_vt1720_pontis_cards[] __devinitdata = {
825 {
826 .subvendor = VT1720_SUBDEVICE_PONTIS_MS300,
827 .name = "Pontis MS300",
828 .model = "ms300",
829 .chip_init = pontis_init,
830 .build_controls = pontis_add_controls,
831 .eeprom_size = sizeof(pontis_eeprom),
832 .eeprom_data = pontis_eeprom,
833 },
834 { } /* terminator */
835 };
WRT350N Kernel Patches