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[POWERPC] Use menuconfig objects II - Macintosh
[wrt350n-kernel.git] / drivers / ata / pata_cmd64x.c
blob3989cc577fcd503b6e073a001f89eb72d935b6f0
1 /*
2 * pata_cmd64x.c - CMD64x PATA for new ATA layer
3 * (C) 2005 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * Based upon
7 * linux/drivers/ide/pci/cmd64x.c Version 1.30 Sept 10, 2002
8 *
9 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
10 * Note, this driver is not used at all on other systems because
11 * there the "BIOS" has done all of the following already.
12 * Due to massive hardware bugs, UltraDMA is only supported
13 * on the 646U2 and not on the 646U.
14 *
15 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
16 * Copyright (C) 1998 David S. Miller (davem@redhat.com)
17 *
18 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
19 *
20 * TODO
21 * Testing work
22 */
23
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <linux/init.h>
28 #include <linux/blkdev.h>
29 #include <linux/delay.h>
30 #include <scsi/scsi_host.h>
31 #include <linux/libata.h>
32
33 #define DRV_NAME "pata_cmd64x"
34 #define DRV_VERSION "0.2.2"
35
36 /*
37 * CMD64x specific registers definition.
38 */
39
40 enum {
41 CFR = 0x50,
42 CFR_INTR_CH0 = 0x02,
43 CNTRL = 0x51,
44 CNTRL_DIS_RA0 = 0x40,
45 CNTRL_DIS_RA1 = 0x80,
46 CNTRL_ENA_2ND = 0x08,
47 CMDTIM = 0x52,
48 ARTTIM0 = 0x53,
49 DRWTIM0 = 0x54,
50 ARTTIM1 = 0x55,
51 DRWTIM1 = 0x56,
52 ARTTIM23 = 0x57,
53 ARTTIM23_DIS_RA2 = 0x04,
54 ARTTIM23_DIS_RA3 = 0x08,
55 ARTTIM23_INTR_CH1 = 0x10,
56 ARTTIM2 = 0x57,
57 ARTTIM3 = 0x57,
58 DRWTIM23 = 0x58,
59 DRWTIM2 = 0x58,
60 BRST = 0x59,
61 DRWTIM3 = 0x5b,
62 BMIDECR0 = 0x70,
63 MRDMODE = 0x71,
64 MRDMODE_INTR_CH0 = 0x04,
65 MRDMODE_INTR_CH1 = 0x08,
66 MRDMODE_BLK_CH0 = 0x10,
67 MRDMODE_BLK_CH1 = 0x20,
68 BMIDESR0 = 0x72,
69 UDIDETCR0 = 0x73,
70 DTPR0 = 0x74,
71 BMIDECR1 = 0x78,
72 BMIDECSR = 0x79,
73 BMIDESR1 = 0x7A,
74 UDIDETCR1 = 0x7B,
75 DTPR1 = 0x7C
76 };
77
78 static int cmd648_cable_detect(struct ata_port *ap)
79 {
80 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
81 u8 r;
82
83 /* Check cable detect bits */
84 pci_read_config_byte(pdev, BMIDECSR, &r);
85 if (r & (1 << ap->port_no))
86 return ATA_CBL_PATA80;
87 return ATA_CBL_PATA40;
88 }
89
90 /**
91 * cmd64x_set_piomode - set initial PIO mode data
92 * @ap: ATA interface
93 * @adev: ATA device
94 *
95 * Called to do the PIO mode setup.
96 */
97
98 static void cmd64x_set_piomode(struct ata_port *ap, struct ata_device *adev)
99 {
100 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
101 struct ata_timing t;
102 const unsigned long T = 1000000 / 33;
103 const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 };
104
105 u8 reg;
106
107 /* Port layout is not logical so use a table */
108 const u8 arttim_port[2][2] = {
109 { ARTTIM0, ARTTIM1 },
110 { ARTTIM23, ARTTIM23 }
111 };
112 const u8 drwtim_port[2][2] = {
113 { DRWTIM0, DRWTIM1 },
114 { DRWTIM2, DRWTIM3 }
115 };
116
117 int arttim = arttim_port[ap->port_no][adev->devno];
118 int drwtim = drwtim_port[ap->port_no][adev->devno];
119
120
121 if (ata_timing_compute(adev, adev->pio_mode, &t, T, 0) < 0) {
122 printk(KERN_ERR DRV_NAME ": mode computation failed.\n");
123 return;
124 }
125 if (ap->port_no) {
126 /* Slave has shared address setup */
127 struct ata_device *pair = ata_dev_pair(adev);
128
129 if (pair) {
130 struct ata_timing tp;
131 ata_timing_compute(pair, pair->pio_mode, &tp, T, 0);
132 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
133 }
134 }
135
136 printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n",
137 t.active, t.recover, t.setup);
138 if (t.recover > 16) {
139 t.active += t.recover - 16;
140 t.recover = 16;
141 }
142 if (t.active > 16)
143 t.active = 16;
144
145 /* Now convert the clocks into values we can actually stuff into
146 the chip */
147
148 if (t.recover > 1)
149 t.recover--;
150 else
151 t.recover = 15;
152
153 if (t.setup > 4)
154 t.setup = 0xC0;
155 else
156 t.setup = setup_data[t.setup];
157
158 t.active &= 0x0F; /* 0 = 16 */
159
160 /* Load setup timing */
161 pci_read_config_byte(pdev, arttim, &reg);
162 reg &= 0x3F;
163 reg |= t.setup;
164 pci_write_config_byte(pdev, arttim, reg);
165
166 /* Load active/recovery */
167 pci_write_config_byte(pdev, drwtim, (t.active << 4) | t.recover);
168 }
169
170 /**
171 * cmd64x_set_dmamode - set initial DMA mode data
172 * @ap: ATA interface
173 * @adev: ATA device
174 *
175 * Called to do the DMA mode setup.
176 */
177
178 static void cmd64x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
179 {
180 static const u8 udma_data[] = {
181 0x30, 0x20, 0x10, 0x20, 0x10, 0x00
182 };
183 static const u8 mwdma_data[] = {
184 0x30, 0x20, 0x10
185 };
186
187 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
188 u8 regU, regD;
189
190 int pciU = UDIDETCR0 + 8 * ap->port_no;
191 int pciD = BMIDESR0 + 8 * ap->port_no;
192 int shift = 2 * adev->devno;
193
194 pci_read_config_byte(pdev, pciD, &regD);
195 pci_read_config_byte(pdev, pciU, &regU);
196
197 /* DMA bits off */
198 regD &= ~(0x20 << adev->devno);
199 /* DMA control bits */
200 regU &= ~(0x30 << shift);
201 /* DMA timing bits */
202 regU &= ~(0x05 << adev->devno);
203
204 if (adev->dma_mode >= XFER_UDMA_0) {
205 /* Merge thge timing value */
206 regU |= udma_data[adev->dma_mode - XFER_UDMA_0] << shift;
207 /* Merge the control bits */
208 regU |= 1 << adev->devno; /* UDMA on */
209 if (adev->dma_mode > 2) /* 15nS timing */
210 regU |= 4 << adev->devno;
211 } else
212 regD |= mwdma_data[adev->dma_mode - XFER_MW_DMA_0] << shift;
213
214 regD |= 0x20 << adev->devno;
215
216 pci_write_config_byte(pdev, pciU, regU);
217 pci_write_config_byte(pdev, pciD, regD);
218 }
219
220 /**
221 * cmd648_dma_stop - DMA stop callback
222 * @qc: Command in progress
223 *
224 * DMA has completed.
225 */
226
227 static void cmd648_bmdma_stop(struct ata_queued_cmd *qc)
228 {
229 struct ata_port *ap = qc->ap;
230 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
231 u8 dma_intr;
232 int dma_mask = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0;
233 int dma_reg = ap->port_no ? ARTTIM2 : CFR;
234
235 ata_bmdma_stop(qc);
236
237 pci_read_config_byte(pdev, dma_reg, &dma_intr);
238 pci_write_config_byte(pdev, dma_reg, dma_intr | dma_mask);
239 }
240
241 /**
242 * cmd646r1_dma_stop - DMA stop callback
243 * @qc: Command in progress
244 *
245 * Stub for now while investigating the r1 quirk in the old driver.
246 */
247
248 static void cmd646r1_bmdma_stop(struct ata_queued_cmd *qc)
249 {
250 ata_bmdma_stop(qc);
251 }
252
253 static struct scsi_host_template cmd64x_sht = {
254 .module = THIS_MODULE,
255 .name = DRV_NAME,
256 .ioctl = ata_scsi_ioctl,
257 .queuecommand = ata_scsi_queuecmd,
258 .can_queue = ATA_DEF_QUEUE,
259 .this_id = ATA_SHT_THIS_ID,
260 .sg_tablesize = LIBATA_MAX_PRD,
261 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
262 .emulated = ATA_SHT_EMULATED,
263 .use_clustering = ATA_SHT_USE_CLUSTERING,
264 .proc_name = DRV_NAME,
265 .dma_boundary = ATA_DMA_BOUNDARY,
266 .slave_configure = ata_scsi_slave_config,
267 .slave_destroy = ata_scsi_slave_destroy,
268 .bios_param = ata_std_bios_param,
269 #ifdef CONFIG_PM
270 .resume = ata_scsi_device_resume,
271 .suspend = ata_scsi_device_suspend,
272 #endif
273 };
274
275 static struct ata_port_operations cmd64x_port_ops = {
276 .port_disable = ata_port_disable,
277 .set_piomode = cmd64x_set_piomode,
278 .set_dmamode = cmd64x_set_dmamode,
279 .mode_filter = ata_pci_default_filter,
280 .tf_load = ata_tf_load,
281 .tf_read = ata_tf_read,
282 .check_status = ata_check_status,
283 .exec_command = ata_exec_command,
284 .dev_select = ata_std_dev_select,
285
286 .freeze = ata_bmdma_freeze,
287 .thaw = ata_bmdma_thaw,
288 .error_handler = ata_bmdma_error_handler,
289 .post_internal_cmd = ata_bmdma_post_internal_cmd,
290 .cable_detect = ata_cable_40wire,
291
292 .bmdma_setup = ata_bmdma_setup,
293 .bmdma_start = ata_bmdma_start,
294 .bmdma_stop = ata_bmdma_stop,
295 .bmdma_status = ata_bmdma_status,
296
297 .qc_prep = ata_qc_prep,
298 .qc_issue = ata_qc_issue_prot,
299
300 .data_xfer = ata_data_xfer,
301
302 .irq_handler = ata_interrupt,
303 .irq_clear = ata_bmdma_irq_clear,
304 .irq_on = ata_irq_on,
305 .irq_ack = ata_irq_ack,
306
307 .port_start = ata_port_start,
308 };
309
310 static struct ata_port_operations cmd646r1_port_ops = {
311 .port_disable = ata_port_disable,
312 .set_piomode = cmd64x_set_piomode,
313 .set_dmamode = cmd64x_set_dmamode,
314 .mode_filter = ata_pci_default_filter,
315 .tf_load = ata_tf_load,
316 .tf_read = ata_tf_read,
317 .check_status = ata_check_status,
318 .exec_command = ata_exec_command,
319 .dev_select = ata_std_dev_select,
320
321 .freeze = ata_bmdma_freeze,
322 .thaw = ata_bmdma_thaw,
323 .error_handler = ata_bmdma_error_handler,
324 .post_internal_cmd = ata_bmdma_post_internal_cmd,
325 .cable_detect = ata_cable_40wire,
326
327 .bmdma_setup = ata_bmdma_setup,
328 .bmdma_start = ata_bmdma_start,
329 .bmdma_stop = cmd646r1_bmdma_stop,
330 .bmdma_status = ata_bmdma_status,
331
332 .qc_prep = ata_qc_prep,
333 .qc_issue = ata_qc_issue_prot,
334
335 .data_xfer = ata_data_xfer,
336
337 .irq_handler = ata_interrupt,
338 .irq_clear = ata_bmdma_irq_clear,
339 .irq_on = ata_irq_on,
340 .irq_ack = ata_irq_ack,
341
342 .port_start = ata_port_start,
343 };
344
345 static struct ata_port_operations cmd648_port_ops = {
346 .port_disable = ata_port_disable,
347 .set_piomode = cmd64x_set_piomode,
348 .set_dmamode = cmd64x_set_dmamode,
349 .mode_filter = ata_pci_default_filter,
350 .tf_load = ata_tf_load,
351 .tf_read = ata_tf_read,
352 .check_status = ata_check_status,
353 .exec_command = ata_exec_command,
354 .dev_select = ata_std_dev_select,
355
356 .freeze = ata_bmdma_freeze,
357 .thaw = ata_bmdma_thaw,
358 .error_handler = ata_bmdma_error_handler,
359 .post_internal_cmd = ata_bmdma_post_internal_cmd,
360 .cable_detect = cmd648_cable_detect,
361
362 .bmdma_setup = ata_bmdma_setup,
363 .bmdma_start = ata_bmdma_start,
364 .bmdma_stop = cmd648_bmdma_stop,
365 .bmdma_status = ata_bmdma_status,
366
367 .qc_prep = ata_qc_prep,
368 .qc_issue = ata_qc_issue_prot,
369
370 .data_xfer = ata_data_xfer,
371
372 .irq_handler = ata_interrupt,
373 .irq_clear = ata_bmdma_irq_clear,
374 .irq_on = ata_irq_on,
375 .irq_ack = ata_irq_ack,
376
377 .port_start = ata_port_start,
378 };
379
380 static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
381 {
382 u32 class_rev;
383
384 static struct ata_port_info cmd_info[6] = {
385 { /* CMD 643 - no UDMA */
386 .sht = &cmd64x_sht,
387 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
388 .pio_mask = 0x1f,
389 .mwdma_mask = 0x07,
390 .port_ops = &cmd64x_port_ops
391 },
392 { /* CMD 646 with broken UDMA */
393 .sht = &cmd64x_sht,
394 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
395 .pio_mask = 0x1f,
396 .mwdma_mask = 0x07,
397 .port_ops = &cmd64x_port_ops
398 },
399 { /* CMD 646 with working UDMA */
400 .sht = &cmd64x_sht,
401 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
402 .pio_mask = 0x1f,
403 .mwdma_mask = 0x07,
404 .udma_mask = ATA_UDMA1,
405 .port_ops = &cmd64x_port_ops
406 },
407 { /* CMD 646 rev 1 */
408 .sht = &cmd64x_sht,
409 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
410 .pio_mask = 0x1f,
411 .mwdma_mask = 0x07,
412 .port_ops = &cmd646r1_port_ops
413 },
414 { /* CMD 648 */
415 .sht = &cmd64x_sht,
416 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
417 .pio_mask = 0x1f,
418 .mwdma_mask = 0x07,
419 .udma_mask = ATA_UDMA2,
420 .port_ops = &cmd648_port_ops
421 },
422 { /* CMD 649 */
423 .sht = &cmd64x_sht,
424 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
425 .pio_mask = 0x1f,
426 .mwdma_mask = 0x07,
427 .udma_mask = ATA_UDMA3,
428 .port_ops = &cmd648_port_ops
429 }
430 };
431 static struct ata_port_info *port_info[2], *info;
432 u8 mrdmode;
433
434 info = &cmd_info[id->driver_data];
435
436 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
437 class_rev &= 0xFF;
438
439 if (id->driver_data == 0) /* 643 */
440 ata_pci_clear_simplex(pdev);
441
442 if (pdev->device == PCI_DEVICE_ID_CMD_646) {
443 /* Does UDMA work ? */
444 if (class_rev > 4)
445 info = &cmd_info[2];
446 /* Early rev with other problems ? */
447 else if (class_rev == 1)
448 info = &cmd_info[3];
449 }
450
451 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
452 pci_read_config_byte(pdev, MRDMODE, &mrdmode);
453 mrdmode &= ~ 0x30; /* IRQ set up */
454 mrdmode |= 0x02; /* Memory read line enable */
455 pci_write_config_byte(pdev, MRDMODE, mrdmode);
456
457 /* Force PIO 0 here.. */
458
459 /* PPC specific fixup copied from old driver */
460 #ifdef CONFIG_PPC
461 pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
462 #endif
463
464 port_info[0] = port_info[1] = info;
465 return ata_pci_init_one(pdev, port_info, 2);
466 }
467
468 #ifdef CONFIG_PM
469 static int cmd64x_reinit_one(struct pci_dev *pdev)
470 {
471 u8 mrdmode;
472 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
473 pci_read_config_byte(pdev, MRDMODE, &mrdmode);
474 mrdmode &= ~ 0x30; /* IRQ set up */
475 mrdmode |= 0x02; /* Memory read line enable */
476 pci_write_config_byte(pdev, MRDMODE, mrdmode);
477 #ifdef CONFIG_PPC
478 pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
479 #endif
480 return ata_pci_device_resume(pdev);
481 }
482 #endif
483
484 static const struct pci_device_id cmd64x[] = {
485 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
486 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
487 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 4 },
488 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 5 },
489
490 { },
491 };
492
493 static struct pci_driver cmd64x_pci_driver = {
494 .name = DRV_NAME,
495 .id_table = cmd64x,
496 .probe = cmd64x_init_one,
497 .remove = ata_pci_remove_one,
498 #ifdef CONFIG_PM
499 .suspend = ata_pci_device_suspend,
500 .resume = cmd64x_reinit_one,
501 #endif
502 };
503
504 static int __init cmd64x_init(void)
505 {
506 return pci_register_driver(&cmd64x_pci_driver);
507 }
508
509 static void __exit cmd64x_exit(void)
510 {
511 pci_unregister_driver(&cmd64x_pci_driver);
512 }
513
514 MODULE_AUTHOR("Alan Cox");
515 MODULE_DESCRIPTION("low-level driver for CMD64x series PATA controllers");
516 MODULE_LICENSE("GPL");
517 MODULE_DEVICE_TABLE(pci, cmd64x);
518 MODULE_VERSION(DRV_VERSION);
519
520 module_init(cmd64x_init);
521 module_exit(cmd64x_exit);
WRT350N Kernel Patches