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[POWERPC] Use menuconfig objects II - Macintosh
[wrt350n-kernel.git] / drivers / ata / pata_sis.c
bloba3fbcee6fb330185ebf97ba10ecf9cb711862530
1 /*
2 * pata_sis.c - SiS ATA driver
3 *
4 * (C) 2005 Red Hat <alan@redhat.com>
5 *
6 * Based upon linux/drivers/ide/pci/sis5513.c
7 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
8 * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
9 * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz>
10 * SiS Taiwan : for direct support and hardware.
11 * Daniela Engert : for initial ATA100 advices and numerous others.
12 * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt :
13 * for checking code correctness, providing patches.
14 * Original tests and design on the SiS620 chipset.
15 * ATA100 tests and design on the SiS735 chipset.
16 * ATA16/33 support from specs
17 * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw>
18 *
19 *
20 * TODO
21 * Check MWDMA on drives that don't support MWDMA speed pio cycles ?
22 * More Testing
23 */
24
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/init.h>
29 #include <linux/blkdev.h>
30 #include <linux/delay.h>
31 #include <linux/device.h>
32 #include <scsi/scsi_host.h>
33 #include <linux/libata.h>
34 #include <linux/ata.h>
35 #include "sis.h"
36
37 #define DRV_NAME "pata_sis"
38 #define DRV_VERSION "0.5.1"
39
40 struct sis_chipset {
41 u16 device; /* PCI host ID */
42 struct ata_port_info *info; /* Info block */
43 /* Probably add family, cable detect type etc here to clean
44 up code later */
45 };
46
47 struct sis_laptop {
48 u16 device;
49 u16 subvendor;
50 u16 subdevice;
51 };
52
53 static const struct sis_laptop sis_laptop[] = {
54 /* devid, subvendor, subdev */
55 { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */
56 /* end marker */
57 { 0, }
58 };
59
60 static int sis_short_ata40(struct pci_dev *dev)
61 {
62 const struct sis_laptop *lap = &sis_laptop[0];
63
64 while (lap->device) {
65 if (lap->device == dev->device &&
66 lap->subvendor == dev->subsystem_vendor &&
67 lap->subdevice == dev->subsystem_device)
68 return 1;
69 lap++;
70 }
71
72 return 0;
73 }
74
75 /**
76 * sis_port_base - return PCI configuration base for dev
77 * @adev: device
78 *
79 * Returns the base of the PCI configuration registers for this port
80 * number.
81 */
82
83 static int sis_port_base(struct ata_device *adev)
84 {
85 return 0x40 + (4 * adev->ap->port_no) + (2 * adev->devno);
86 }
87
88 /**
89 * sis_133_cable_detect - check for 40/80 pin
90 * @ap: Port
91 *
92 * Perform cable detection for the later UDMA133 capable
93 * SiS chipset.
94 */
95
96 static int sis_133_cable_detect(struct ata_port *ap)
97 {
98 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
99 u16 tmp;
100
101 /* The top bit of this register is the cable detect bit */
102 pci_read_config_word(pdev, 0x50 + 2 * ap->port_no, &tmp);
103 if ((tmp & 0x8000) && !sis_short_ata40(pdev))
104 return ATA_CBL_PATA40;
105 return ATA_CBL_PATA80;
106 }
107
108 /**
109 * sis_66_cable_detect - check for 40/80 pin
110 * @ap: Port
111 *
112 * Perform cable detection on the UDMA66, UDMA100 and early UDMA133
113 * SiS IDE controllers.
114 */
115
116 static int sis_66_cable_detect(struct ata_port *ap)
117 {
118 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
119 u8 tmp;
120
121 /* Older chips keep cable detect in bits 4/5 of reg 0x48 */
122 pci_read_config_byte(pdev, 0x48, &tmp);
123 tmp >>= ap->port_no;
124 if ((tmp & 0x10) && !sis_short_ata40(pdev))
125 return ATA_CBL_PATA40;
126 return ATA_CBL_PATA80;
127 }
128
129
130 /**
131 * sis_pre_reset - probe begin
132 * @ap: ATA port
133 *
134 * Set up cable type and use generic probe init
135 */
136
137 static int sis_pre_reset(struct ata_port *ap)
138 {
139 static const struct pci_bits sis_enable_bits[] = {
140 { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */
141 { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */
142 };
143
144 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
145
146 if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no]))
147 return -ENOENT;
148 return ata_std_prereset(ap);
149 }
150
151
152 /**
153 * sis_error_handler - Probe specified port on PATA host controller
154 * @ap: Port to probe
155 *
156 * LOCKING:
157 * None (inherited from caller).
158 */
159
160 static void sis_error_handler(struct ata_port *ap)
161 {
162 ata_bmdma_drive_eh(ap, sis_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
163 }
164
165 /**
166 * sis_set_fifo - Set RWP fifo bits for this device
167 * @ap: Port
168 * @adev: Device
169 *
170 * SIS chipsets implement prefetch/postwrite bits for each device
171 * on both channels. This functionality is not ATAPI compatible and
172 * must be configured according to the class of device present
173 */
174
175 static void sis_set_fifo(struct ata_port *ap, struct ata_device *adev)
176 {
177 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
178 u8 fifoctrl;
179 u8 mask = 0x11;
180
181 mask <<= (2 * ap->port_no);
182 mask <<= adev->devno;
183
184 /* This holds various bits including the FIFO control */
185 pci_read_config_byte(pdev, 0x4B, &fifoctrl);
186 fifoctrl &= ~mask;
187
188 /* Enable for ATA (disk) only */
189 if (adev->class == ATA_DEV_ATA)
190 fifoctrl |= mask;
191 pci_write_config_byte(pdev, 0x4B, fifoctrl);
192 }
193
194 /**
195 * sis_old_set_piomode - Initialize host controller PATA PIO timings
196 * @ap: Port whose timings we are configuring
197 * @adev: Device we are configuring for.
198 *
199 * Set PIO mode for device, in host controller PCI config space. This
200 * function handles PIO set up for all chips that are pre ATA100 and
201 * also early ATA100 devices.
202 *
203 * LOCKING:
204 * None (inherited from caller).
205 */
206
207 static void sis_old_set_piomode (struct ata_port *ap, struct ata_device *adev)
208 {
209 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
210 int port = sis_port_base(adev);
211 u8 t1, t2;
212 int speed = adev->pio_mode - XFER_PIO_0;
213
214 const u8 active[] = { 0x00, 0x07, 0x04, 0x03, 0x01 };
215 const u8 recovery[] = { 0x00, 0x06, 0x04, 0x03, 0x03 };
216
217 sis_set_fifo(ap, adev);
218
219 pci_read_config_byte(pdev, port, &t1);
220 pci_read_config_byte(pdev, port + 1, &t2);
221
222 t1 &= ~0x0F; /* Clear active/recovery timings */
223 t2 &= ~0x07;
224
225 t1 |= active[speed];
226 t2 |= recovery[speed];
227
228 pci_write_config_byte(pdev, port, t1);
229 pci_write_config_byte(pdev, port + 1, t2);
230 }
231
232 /**
233 * sis_100_set_pioode - Initialize host controller PATA PIO timings
234 * @ap: Port whose timings we are configuring
235 * @adev: Device we are configuring for.
236 *
237 * Set PIO mode for device, in host controller PCI config space. This
238 * function handles PIO set up for ATA100 devices and early ATA133.
239 *
240 * LOCKING:
241 * None (inherited from caller).
242 */
243
244 static void sis_100_set_piomode (struct ata_port *ap, struct ata_device *adev)
245 {
246 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
247 int port = sis_port_base(adev);
248 int speed = adev->pio_mode - XFER_PIO_0;
249
250 const u8 actrec[] = { 0x00, 0x67, 0x44, 0x33, 0x31 };
251
252 sis_set_fifo(ap, adev);
253
254 pci_write_config_byte(pdev, port, actrec[speed]);
255 }
256
257 /**
258 * sis_133_set_pioode - Initialize host controller PATA PIO timings
259 * @ap: Port whose timings we are configuring
260 * @adev: Device we are configuring for.
261 *
262 * Set PIO mode for device, in host controller PCI config space. This
263 * function handles PIO set up for the later ATA133 devices.
264 *
265 * LOCKING:
266 * None (inherited from caller).
267 */
268
269 static void sis_133_set_piomode (struct ata_port *ap, struct ata_device *adev)
270 {
271 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
272 int port = 0x40;
273 u32 t1;
274 u32 reg54;
275 int speed = adev->pio_mode - XFER_PIO_0;
276
277 const u32 timing133[] = {
278 0x28269000, /* Recovery << 24 | Act << 16 | Ini << 12 */
279 0x0C266000,
280 0x04263000,
281 0x0C0A3000,
282 0x05093000
283 };
284 const u32 timing100[] = {
285 0x1E1C6000, /* Recovery << 24 | Act << 16 | Ini << 12 */
286 0x091C4000,
287 0x031C2000,
288 0x09072000,
289 0x04062000
290 };
291
292 sis_set_fifo(ap, adev);
293
294 /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */
295 pci_read_config_dword(pdev, 0x54, &reg54);
296 if (reg54 & 0x40000000)
297 port = 0x70;
298 port += 8 * ap->port_no + 4 * adev->devno;
299
300 pci_read_config_dword(pdev, port, &t1);
301 t1 &= 0xC0C00FFF; /* Mask out timing */
302
303 if (t1 & 0x08) /* 100 or 133 ? */
304 t1 |= timing133[speed];
305 else
306 t1 |= timing100[speed];
307 pci_write_config_byte(pdev, port, t1);
308 }
309
310 /**
311 * sis_old_set_dmamode - Initialize host controller PATA DMA timings
312 * @ap: Port whose timings we are configuring
313 * @adev: Device to program
314 *
315 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
316 * Handles pre UDMA and UDMA33 devices. Supports MWDMA as well unlike
317 * the old ide/pci driver.
318 *
319 * LOCKING:
320 * None (inherited from caller).
321 */
322
323 static void sis_old_set_dmamode (struct ata_port *ap, struct ata_device *adev)
324 {
325 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
326 int speed = adev->dma_mode - XFER_MW_DMA_0;
327 int drive_pci = sis_port_base(adev);
328 u16 timing;
329
330 const u16 mwdma_bits[] = { 0x707, 0x202, 0x202 };
331 const u16 udma_bits[] = { 0xE000, 0xC000, 0xA000 };
332
333 pci_read_config_word(pdev, drive_pci, &timing);
334
335 if (adev->dma_mode < XFER_UDMA_0) {
336 /* bits 3-0 hold recovery timing bits 8-10 active timing and
337 the higer bits are dependant on the device */
338 timing &= ~ 0x870F;
339 timing |= mwdma_bits[speed];
340 pci_write_config_word(pdev, drive_pci, timing);
341 } else {
342 /* Bit 15 is UDMA on/off, bit 13-14 are cycle time */
343 speed = adev->dma_mode - XFER_UDMA_0;
344 timing &= ~0x6000;
345 timing |= udma_bits[speed];
346 }
347 }
348
349 /**
350 * sis_66_set_dmamode - Initialize host controller PATA DMA timings
351 * @ap: Port whose timings we are configuring
352 * @adev: Device to program
353 *
354 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
355 * Handles UDMA66 and early UDMA100 devices. Supports MWDMA as well unlike
356 * the old ide/pci driver.
357 *
358 * LOCKING:
359 * None (inherited from caller).
360 */
361
362 static void sis_66_set_dmamode (struct ata_port *ap, struct ata_device *adev)
363 {
364 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
365 int speed = adev->dma_mode - XFER_MW_DMA_0;
366 int drive_pci = sis_port_base(adev);
367 u16 timing;
368
369 const u16 mwdma_bits[] = { 0x707, 0x202, 0x202 };
370 const u16 udma_bits[] = { 0xF000, 0xD000, 0xB000, 0xA000, 0x9000};
371
372 pci_read_config_word(pdev, drive_pci, &timing);
373
374 if (adev->dma_mode < XFER_UDMA_0) {
375 /* bits 3-0 hold recovery timing bits 8-10 active timing and
376 the higer bits are dependant on the device, bit 15 udma */
377 timing &= ~ 0x870F;
378 timing |= mwdma_bits[speed];
379 } else {
380 /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */
381 speed = adev->dma_mode - XFER_UDMA_0;
382 timing &= ~0x6000;
383 timing |= udma_bits[speed];
384 }
385 pci_write_config_word(pdev, drive_pci, timing);
386 }
387
388 /**
389 * sis_100_set_dmamode - Initialize host controller PATA DMA timings
390 * @ap: Port whose timings we are configuring
391 * @adev: Device to program
392 *
393 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
394 * Handles UDMA66 and early UDMA100 devices.
395 *
396 * LOCKING:
397 * None (inherited from caller).
398 */
399
400 static void sis_100_set_dmamode (struct ata_port *ap, struct ata_device *adev)
401 {
402 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
403 int speed = adev->dma_mode - XFER_MW_DMA_0;
404 int drive_pci = sis_port_base(adev);
405 u16 timing;
406
407 const u16 udma_bits[] = { 0x8B00, 0x8700, 0x8500, 0x8300, 0x8200, 0x8100};
408
409 pci_read_config_word(pdev, drive_pci, &timing);
410
411 if (adev->dma_mode < XFER_UDMA_0) {
412 /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */
413 } else {
414 /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */
415 speed = adev->dma_mode - XFER_UDMA_0;
416 timing &= ~0x0F00;
417 timing |= udma_bits[speed];
418 }
419 pci_write_config_word(pdev, drive_pci, timing);
420 }
421
422 /**
423 * sis_133_early_set_dmamode - Initialize host controller PATA DMA timings
424 * @ap: Port whose timings we are configuring
425 * @adev: Device to program
426 *
427 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
428 * Handles early SiS 961 bridges. Supports MWDMA as well unlike
429 * the old ide/pci driver.
430 *
431 * LOCKING:
432 * None (inherited from caller).
433 */
434
435 static void sis_133_early_set_dmamode (struct ata_port *ap, struct ata_device *adev)
436 {
437 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
438 int speed = adev->dma_mode - XFER_MW_DMA_0;
439 int drive_pci = sis_port_base(adev);
440 u16 timing;
441
442 static const u16 udma_bits[] = { 0x8F00, 0x8A00, 0x8700, 0x8500, 0x8300, 0x8200, 0x8100};
443
444 pci_read_config_word(pdev, drive_pci, &timing);
445
446 if (adev->dma_mode < XFER_UDMA_0) {
447 /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */
448 } else {
449 /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */
450 speed = adev->dma_mode - XFER_UDMA_0;
451 timing &= ~0x0F00;
452 timing |= udma_bits[speed];
453 }
454 pci_write_config_word(pdev, drive_pci, timing);
455 }
456
457 /**
458 * sis_133_set_dmamode - Initialize host controller PATA DMA timings
459 * @ap: Port whose timings we are configuring
460 * @adev: Device to program
461 *
462 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
463 * Handles early SiS 961 bridges. Supports MWDMA as well unlike
464 * the old ide/pci driver.
465 *
466 * LOCKING:
467 * None (inherited from caller).
468 */
469
470 static void sis_133_set_dmamode (struct ata_port *ap, struct ata_device *adev)
471 {
472 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
473 int speed = adev->dma_mode - XFER_MW_DMA_0;
474 int port = 0x40;
475 u32 t1;
476 u32 reg54;
477
478 /* bits 4- cycle time 8 - cvs time */
479 static const u32 timing_u100[] = { 0x6B0, 0x470, 0x350, 0x140, 0x120, 0x110, 0x000 };
480 static const u32 timing_u133[] = { 0x9F0, 0x6A0, 0x470, 0x250, 0x230, 0x220, 0x210 };
481
482 /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */
483 pci_read_config_dword(pdev, 0x54, &reg54);
484 if (reg54 & 0x40000000)
485 port = 0x70;
486 port += (8 * ap->port_no) + (4 * adev->devno);
487
488 pci_read_config_dword(pdev, port, &t1);
489
490 if (adev->dma_mode < XFER_UDMA_0) {
491 t1 &= ~0x00000004;
492 /* FIXME: need data sheet to add MWDMA here. Also lacking on
493 ide/pci driver */
494 } else {
495 speed = adev->dma_mode - XFER_UDMA_0;
496 /* if & 8 no UDMA133 - need info for ... */
497 t1 &= ~0x00000FF0;
498 t1 |= 0x00000004;
499 if (t1 & 0x08)
500 t1 |= timing_u133[speed];
501 else
502 t1 |= timing_u100[speed];
503 }
504 pci_write_config_dword(pdev, port, t1);
505 }
506
507 static struct scsi_host_template sis_sht = {
508 .module = THIS_MODULE,
509 .name = DRV_NAME,
510 .ioctl = ata_scsi_ioctl,
511 .queuecommand = ata_scsi_queuecmd,
512 .can_queue = ATA_DEF_QUEUE,
513 .this_id = ATA_SHT_THIS_ID,
514 .sg_tablesize = LIBATA_MAX_PRD,
515 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
516 .emulated = ATA_SHT_EMULATED,
517 .use_clustering = ATA_SHT_USE_CLUSTERING,
518 .proc_name = DRV_NAME,
519 .dma_boundary = ATA_DMA_BOUNDARY,
520 .slave_configure = ata_scsi_slave_config,
521 .slave_destroy = ata_scsi_slave_destroy,
522 .bios_param = ata_std_bios_param,
523 #ifdef CONFIG_PM
524 .resume = ata_scsi_device_resume,
525 .suspend = ata_scsi_device_suspend,
526 #endif
527 };
528
529 static const struct ata_port_operations sis_133_ops = {
530 .port_disable = ata_port_disable,
531 .set_piomode = sis_133_set_piomode,
532 .set_dmamode = sis_133_set_dmamode,
533 .mode_filter = ata_pci_default_filter,
534
535 .tf_load = ata_tf_load,
536 .tf_read = ata_tf_read,
537 .check_status = ata_check_status,
538 .exec_command = ata_exec_command,
539 .dev_select = ata_std_dev_select,
540
541 .freeze = ata_bmdma_freeze,
542 .thaw = ata_bmdma_thaw,
543 .error_handler = sis_error_handler,
544 .post_internal_cmd = ata_bmdma_post_internal_cmd,
545 .cable_detect = sis_133_cable_detect,
546
547 .bmdma_setup = ata_bmdma_setup,
548 .bmdma_start = ata_bmdma_start,
549 .bmdma_stop = ata_bmdma_stop,
550 .bmdma_status = ata_bmdma_status,
551 .qc_prep = ata_qc_prep,
552 .qc_issue = ata_qc_issue_prot,
553 .data_xfer = ata_data_xfer,
554
555 .irq_handler = ata_interrupt,
556 .irq_clear = ata_bmdma_irq_clear,
557 .irq_on = ata_irq_on,
558 .irq_ack = ata_irq_ack,
559
560 .port_start = ata_port_start,
561 };
562
563 static const struct ata_port_operations sis_133_early_ops = {
564 .port_disable = ata_port_disable,
565 .set_piomode = sis_100_set_piomode,
566 .set_dmamode = sis_133_early_set_dmamode,
567 .mode_filter = ata_pci_default_filter,
568
569 .tf_load = ata_tf_load,
570 .tf_read = ata_tf_read,
571 .check_status = ata_check_status,
572 .exec_command = ata_exec_command,
573 .dev_select = ata_std_dev_select,
574
575 .freeze = ata_bmdma_freeze,
576 .thaw = ata_bmdma_thaw,
577 .error_handler = sis_error_handler,
578 .post_internal_cmd = ata_bmdma_post_internal_cmd,
579 .cable_detect = sis_66_cable_detect,
580
581 .bmdma_setup = ata_bmdma_setup,
582 .bmdma_start = ata_bmdma_start,
583 .bmdma_stop = ata_bmdma_stop,
584 .bmdma_status = ata_bmdma_status,
585 .qc_prep = ata_qc_prep,
586 .qc_issue = ata_qc_issue_prot,
587 .data_xfer = ata_data_xfer,
588
589 .irq_handler = ata_interrupt,
590 .irq_clear = ata_bmdma_irq_clear,
591 .irq_on = ata_irq_on,
592 .irq_ack = ata_irq_ack,
593
594 .port_start = ata_port_start,
595 };
596
597 static const struct ata_port_operations sis_100_ops = {
598 .port_disable = ata_port_disable,
599 .set_piomode = sis_100_set_piomode,
600 .set_dmamode = sis_100_set_dmamode,
601 .mode_filter = ata_pci_default_filter,
602
603 .tf_load = ata_tf_load,
604 .tf_read = ata_tf_read,
605 .check_status = ata_check_status,
606 .exec_command = ata_exec_command,
607 .dev_select = ata_std_dev_select,
608
609 .freeze = ata_bmdma_freeze,
610 .thaw = ata_bmdma_thaw,
611 .error_handler = sis_error_handler,
612 .post_internal_cmd = ata_bmdma_post_internal_cmd,
613 .cable_detect = sis_66_cable_detect,
614
615 .bmdma_setup = ata_bmdma_setup,
616 .bmdma_start = ata_bmdma_start,
617 .bmdma_stop = ata_bmdma_stop,
618 .bmdma_status = ata_bmdma_status,
619 .qc_prep = ata_qc_prep,
620 .qc_issue = ata_qc_issue_prot,
621 .data_xfer = ata_data_xfer,
622
623 .irq_handler = ata_interrupt,
624 .irq_clear = ata_bmdma_irq_clear,
625 .irq_on = ata_irq_on,
626 .irq_ack = ata_irq_ack,
627
628 .port_start = ata_port_start,
629 };
630
631 static const struct ata_port_operations sis_66_ops = {
632 .port_disable = ata_port_disable,
633 .set_piomode = sis_old_set_piomode,
634 .set_dmamode = sis_66_set_dmamode,
635 .mode_filter = ata_pci_default_filter,
636
637 .tf_load = ata_tf_load,
638 .tf_read = ata_tf_read,
639 .check_status = ata_check_status,
640 .exec_command = ata_exec_command,
641 .dev_select = ata_std_dev_select,
642 .cable_detect = sis_66_cable_detect,
643
644 .freeze = ata_bmdma_freeze,
645 .thaw = ata_bmdma_thaw,
646 .error_handler = sis_error_handler,
647 .post_internal_cmd = ata_bmdma_post_internal_cmd,
648
649 .bmdma_setup = ata_bmdma_setup,
650 .bmdma_start = ata_bmdma_start,
651 .bmdma_stop = ata_bmdma_stop,
652 .bmdma_status = ata_bmdma_status,
653 .qc_prep = ata_qc_prep,
654 .qc_issue = ata_qc_issue_prot,
655 .data_xfer = ata_data_xfer,
656
657 .irq_handler = ata_interrupt,
658 .irq_clear = ata_bmdma_irq_clear,
659 .irq_on = ata_irq_on,
660 .irq_ack = ata_irq_ack,
661
662 .port_start = ata_port_start,
663 };
664
665 static const struct ata_port_operations sis_old_ops = {
666 .port_disable = ata_port_disable,
667 .set_piomode = sis_old_set_piomode,
668 .set_dmamode = sis_old_set_dmamode,
669 .mode_filter = ata_pci_default_filter,
670
671 .tf_load = ata_tf_load,
672 .tf_read = ata_tf_read,
673 .check_status = ata_check_status,
674 .exec_command = ata_exec_command,
675 .dev_select = ata_std_dev_select,
676
677 .freeze = ata_bmdma_freeze,
678 .thaw = ata_bmdma_thaw,
679 .error_handler = sis_error_handler,
680 .post_internal_cmd = ata_bmdma_post_internal_cmd,
681 .cable_detect = ata_cable_40wire,
682
683 .bmdma_setup = ata_bmdma_setup,
684 .bmdma_start = ata_bmdma_start,
685 .bmdma_stop = ata_bmdma_stop,
686 .bmdma_status = ata_bmdma_status,
687 .qc_prep = ata_qc_prep,
688 .qc_issue = ata_qc_issue_prot,
689 .data_xfer = ata_data_xfer,
690
691 .irq_handler = ata_interrupt,
692 .irq_clear = ata_bmdma_irq_clear,
693 .irq_on = ata_irq_on,
694 .irq_ack = ata_irq_ack,
695
696 .port_start = ata_port_start,
697 };
698
699 static struct ata_port_info sis_info = {
700 .sht = &sis_sht,
701 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
702 .pio_mask = 0x1f, /* pio0-4 */
703 .mwdma_mask = 0x07,
704 .udma_mask = 0,
705 .port_ops = &sis_old_ops,
706 };
707 static struct ata_port_info sis_info33 = {
708 .sht = &sis_sht,
709 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
710 .pio_mask = 0x1f, /* pio0-4 */
711 .mwdma_mask = 0x07,
712 .udma_mask = ATA_UDMA2, /* UDMA 33 */
713 .port_ops = &sis_old_ops,
714 };
715 static struct ata_port_info sis_info66 = {
716 .sht = &sis_sht,
717 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
718 .pio_mask = 0x1f, /* pio0-4 */
719 .udma_mask = ATA_UDMA4, /* UDMA 66 */
720 .port_ops = &sis_66_ops,
721 };
722 static struct ata_port_info sis_info100 = {
723 .sht = &sis_sht,
724 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
725 .pio_mask = 0x1f, /* pio0-4 */
726 .udma_mask = ATA_UDMA5,
727 .port_ops = &sis_100_ops,
728 };
729 static struct ata_port_info sis_info100_early = {
730 .sht = &sis_sht,
731 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
732 .udma_mask = ATA_UDMA5,
733 .pio_mask = 0x1f, /* pio0-4 */
734 .port_ops = &sis_66_ops,
735 };
736 struct ata_port_info sis_info133 = {
737 .sht = &sis_sht,
738 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
739 .pio_mask = 0x1f, /* pio0-4 */
740 .udma_mask = ATA_UDMA6,
741 .port_ops = &sis_133_ops,
742 };
743 static struct ata_port_info sis_info133_early = {
744 .sht = &sis_sht,
745 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
746 .pio_mask = 0x1f, /* pio0-4 */
747 .udma_mask = ATA_UDMA6,
748 .port_ops = &sis_133_early_ops,
749 };
750
751 /* Privately shared with the SiS180 SATA driver, not for use elsewhere */
752 EXPORT_SYMBOL_GPL(sis_info133);
753
754 static void sis_fixup(struct pci_dev *pdev, struct sis_chipset *sis)
755 {
756 u16 regw;
757 u8 reg;
758
759 if (sis->info == &sis_info133) {
760 pci_read_config_word(pdev, 0x50, &regw);
761 if (regw & 0x08)
762 pci_write_config_word(pdev, 0x50, regw & ~0x08);
763 pci_read_config_word(pdev, 0x52, &regw);
764 if (regw & 0x08)
765 pci_write_config_word(pdev, 0x52, regw & ~0x08);
766 return;
767 }
768
769 if (sis->info == &sis_info133_early || sis->info == &sis_info100) {
770 /* Fix up latency */
771 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
772 /* Set compatibility bit */
773 pci_read_config_byte(pdev, 0x49, &reg);
774 if (!(reg & 0x01))
775 pci_write_config_byte(pdev, 0x49, reg | 0x01);
776 return;
777 }
778
779 if (sis->info == &sis_info66 || sis->info == &sis_info100_early) {
780 /* Fix up latency */
781 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
782 /* Set compatibility bit */
783 pci_read_config_byte(pdev, 0x52, &reg);
784 if (!(reg & 0x04))
785 pci_write_config_byte(pdev, 0x52, reg | 0x04);
786 return;
787 }
788
789 if (sis->info == &sis_info33) {
790 pci_read_config_byte(pdev, PCI_CLASS_PROG, &reg);
791 if (( reg & 0x0F ) != 0x00)
792 pci_write_config_byte(pdev, PCI_CLASS_PROG, reg & 0xF0);
793 /* Fall through to ATA16 fixup below */
794 }
795
796 if (sis->info == &sis_info || sis->info == &sis_info33) {
797 /* force per drive recovery and active timings
798 needed on ATA_33 and below chips */
799 pci_read_config_byte(pdev, 0x52, &reg);
800 if (!(reg & 0x08))
801 pci_write_config_byte(pdev, 0x52, reg|0x08);
802 return;
803 }
804
805 BUG();
806 }
807
808 /**
809 * sis_init_one - Register SiS ATA PCI device with kernel services
810 * @pdev: PCI device to register
811 * @ent: Entry in sis_pci_tbl matching with @pdev
812 *
813 * Called from kernel PCI layer. We probe for combined mode (sigh),
814 * and then hand over control to libata, for it to do the rest.
815 *
816 * LOCKING:
817 * Inherited from PCI layer (may sleep).
818 *
819 * RETURNS:
820 * Zero on success, or -ERRNO value.
821 */
822
823 static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
824 {
825 static int printed_version;
826 static struct ata_port_info *port_info[2];
827 struct ata_port_info *port;
828 struct pci_dev *host = NULL;
829 struct sis_chipset *chipset = NULL;
830 struct sis_chipset *sets;
831
832 static struct sis_chipset sis_chipsets[] = {
833
834 { 0x0968, &sis_info133 },
835 { 0x0966, &sis_info133 },
836 { 0x0965, &sis_info133 },
837 { 0x0745, &sis_info100 },
838 { 0x0735, &sis_info100 },
839 { 0x0733, &sis_info100 },
840 { 0x0635, &sis_info100 },
841 { 0x0633, &sis_info100 },
842
843 { 0x0730, &sis_info100_early }, /* 100 with ATA 66 layout */
844 { 0x0550, &sis_info100_early }, /* 100 with ATA 66 layout */
845
846 { 0x0640, &sis_info66 },
847 { 0x0630, &sis_info66 },
848 { 0x0620, &sis_info66 },
849 { 0x0540, &sis_info66 },
850 { 0x0530, &sis_info66 },
851
852 { 0x5600, &sis_info33 },
853 { 0x5598, &sis_info33 },
854 { 0x5597, &sis_info33 },
855 { 0x5591, &sis_info33 },
856 { 0x5582, &sis_info33 },
857 { 0x5581, &sis_info33 },
858
859 { 0x5596, &sis_info },
860 { 0x5571, &sis_info },
861 { 0x5517, &sis_info },
862 { 0x5511, &sis_info },
863
864 {0}
865 };
866 static struct sis_chipset sis133_early = {
867 0x0, &sis_info133_early
868 };
869 static struct sis_chipset sis133 = {
870 0x0, &sis_info133
871 };
872 static struct sis_chipset sis100_early = {
873 0x0, &sis_info100_early
874 };
875 static struct sis_chipset sis100 = {
876 0x0, &sis_info100
877 };
878
879 if (!printed_version++)
880 dev_printk(KERN_DEBUG, &pdev->dev,
881 "version " DRV_VERSION "\n");
882
883 /* We have to find the bridge first */
884
885 for (sets = &sis_chipsets[0]; sets->device; sets++) {
886 host = pci_get_device(PCI_VENDOR_ID_SI, sets->device, NULL);
887 if (host != NULL) {
888 chipset = sets; /* Match found */
889 if (sets->device == 0x630) { /* SIS630 */
890 u8 host_rev;
891 pci_read_config_byte(host, PCI_REVISION_ID, &host_rev);
892 if (host_rev >= 0x30) /* 630 ET */
893 chipset = &sis100_early;
894 }
895 break;
896 }
897 }
898
899 /* Look for concealed bridges */
900 if (chipset == NULL) {
901 /* Second check */
902 u32 idemisc;
903 u16 trueid;
904
905 /* Disable ID masking and register remapping then
906 see what the real ID is */
907
908 pci_read_config_dword(pdev, 0x54, &idemisc);
909 pci_write_config_dword(pdev, 0x54, idemisc & 0x7fffffff);
910 pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid);
911 pci_write_config_dword(pdev, 0x54, idemisc);
912
913 switch(trueid) {
914 case 0x5518: /* SIS 962/963 */
915 chipset = &sis133;
916 if ((idemisc & 0x40000000) == 0) {
917 pci_write_config_dword(pdev, 0x54, idemisc | 0x40000000);
918 printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n");
919 }
920 break;
921 case 0x0180: /* SIS 965/965L */
922 chipset = &sis133;
923 break;
924 case 0x1180: /* SIS 966/966L */
925 chipset = &sis133;
926 break;
927 }
928 }
929
930 /* Further check */
931 if (chipset == NULL) {
932 struct pci_dev *lpc_bridge;
933 u16 trueid;
934 u8 prefctl;
935 u8 idecfg;
936 u8 sbrev;
937
938 /* Try the second unmasking technique */
939 pci_read_config_byte(pdev, 0x4a, &idecfg);
940 pci_write_config_byte(pdev, 0x4a, idecfg | 0x10);
941 pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid);
942 pci_write_config_byte(pdev, 0x4a, idecfg);
943
944 switch(trueid) {
945 case 0x5517:
946 lpc_bridge = pci_get_slot(pdev->bus, 0x10); /* Bus 0 Dev 2 Fn 0 */
947 if (lpc_bridge == NULL)
948 break;
949 pci_read_config_byte(lpc_bridge, PCI_REVISION_ID, &sbrev);
950 pci_read_config_byte(pdev, 0x49, &prefctl);
951 pci_dev_put(lpc_bridge);
952
953 if (sbrev == 0x10 && (prefctl & 0x80)) {
954 chipset = &sis133_early;
955 break;
956 }
957 chipset = &sis100;
958 break;
959 }
960 }
961 pci_dev_put(host);
962
963 /* No chipset info, no support */
964 if (chipset == NULL)
965 return -ENODEV;
966
967 port = chipset->info;
968 port->private_data = chipset;
969
970 sis_fixup(pdev, chipset);
971
972 port_info[0] = port_info[1] = port;
973 return ata_pci_init_one(pdev, port_info, 2);
974 }
975
976 static const struct pci_device_id sis_pci_tbl[] = {
977 { PCI_VDEVICE(SI, 0x5513), }, /* SiS 5513 */
978 { PCI_VDEVICE(SI, 0x5518), }, /* SiS 5518 */
979
980 { }
981 };
982
983 static struct pci_driver sis_pci_driver = {
984 .name = DRV_NAME,
985 .id_table = sis_pci_tbl,
986 .probe = sis_init_one,
987 .remove = ata_pci_remove_one,
988 #ifdef CONFIG_PM
989 .suspend = ata_pci_device_suspend,
990 .resume = ata_pci_device_resume,
991 #endif
992 };
993
994 static int __init sis_init(void)
995 {
996 return pci_register_driver(&sis_pci_driver);
997 }
998
999 static void __exit sis_exit(void)
1000 {
1001 pci_unregister_driver(&sis_pci_driver);
1002 }
1003
1004 module_init(sis_init);
1005 module_exit(sis_exit);
1006
1007 MODULE_AUTHOR("Alan Cox");
1008 MODULE_DESCRIPTION("SCSI low-level driver for SiS ATA");
1009 MODULE_LICENSE("GPL");
1010 MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
1011 MODULE_VERSION(DRV_VERSION);
1012
WRT350N Kernel Patches