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[POWERPC] Walnut zImage wrapper
[wrt350n-kernel.git] / drivers / serial / sb1250-duart.c
blob201253755011c457180937522a88ae0ad7b60e68
1 /*
2 * drivers/serial/sb1250-duart.c
3 *
4 * Support for the asynchronous serial interface (DUART) included
5 * in the BCM1250 and derived System-On-a-Chip (SOC) devices.
6 *
7 * Copyright (c) 2007 Maciej W. Rozycki
8 *
9 * Derived from drivers/char/sb1250_duart.c for which the following
10 * copyright applies:
11 *
12 * Copyright (c) 2000, 2001, 2002, 2003, 2004 Broadcom Corporation
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version
17 * 2 of the License, or (at your option) any later version.
18 *
19 * References:
20 *
21 * "BCM1250/BCM1125/BCM1125H User Manual", Broadcom Corporation
22 */
23
24 #if defined(CONFIG_SERIAL_SB1250_DUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
25 #define SUPPORT_SYSRQ
26 #endif
27
28 #include <linux/compiler.h>
29 #include <linux/console.h>
30 #include <linux/delay.h>
31 #include <linux/errno.h>
32 #include <linux/init.h>
33 #include <linux/interrupt.h>
34 #include <linux/ioport.h>
35 #include <linux/kernel.h>
36 #include <linux/major.h>
37 #include <linux/serial.h>
38 #include <linux/serial_core.h>
39 #include <linux/spinlock.h>
40 #include <linux/sysrq.h>
41 #include <linux/tty.h>
42 #include <linux/types.h>
43
44 #include <asm/atomic.h>
45 #include <asm/io.h>
46 #include <asm/war.h>
47
48 #include <asm/sibyte/sb1250.h>
49 #include <asm/sibyte/sb1250_uart.h>
50 #include <asm/sibyte/swarm.h>
51
52
53 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
54 #include <asm/sibyte/bcm1480_regs.h>
55 #include <asm/sibyte/bcm1480_int.h>
56
57 #define SBD_CHANREGS(line) A_BCM1480_DUART_CHANREG((line), 0)
58 #define SBD_CTRLREGS(line) A_BCM1480_DUART_CTRLREG((line), 0)
59 #define SBD_INT(line) (K_BCM1480_INT_UART_0 + (line))
60
61 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
62 #include <asm/sibyte/sb1250_regs.h>
63 #include <asm/sibyte/sb1250_int.h>
64
65 #define SBD_CHANREGS(line) A_DUART_CHANREG((line), 0)
66 #define SBD_CTRLREGS(line) A_DUART_CTRLREG(0)
67 #define SBD_INT(line) (K_INT_UART_0 + (line))
68
69 #else
70 #error invalid SB1250 UART configuration
71
72 #endif
73
74
75 MODULE_AUTHOR("Maciej W. Rozycki <macro@linux-mips.org>");
76 MODULE_DESCRIPTION("BCM1xxx on-chip DUART serial driver");
77 MODULE_LICENSE("GPL");
78
79
80 #define DUART_MAX_CHIP 2
81 #define DUART_MAX_SIDE 2
82
83 /*
84 * Per-port state.
85 */
86 struct sbd_port {
87 struct sbd_duart *duart;
88 struct uart_port port;
89 unsigned char __iomem *memctrl;
90 int tx_stopped;
91 int initialised;
92 };
93
94 /*
95 * Per-DUART state for the shared register space.
96 */
97 struct sbd_duart {
98 struct sbd_port sport[2];
99 unsigned long mapctrl;
100 atomic_t map_guard;
101 };
102
103 #define to_sport(uport) container_of(uport, struct sbd_port, port)
104
105 static struct sbd_duart sbd_duarts[DUART_MAX_CHIP];
106
107
108 /*
109 * Reading and writing SB1250 DUART registers.
110 *
111 * There are three register spaces: two per-channel ones and
112 * a shared one. We have to define accessors appropriately.
113 * All registers are 64-bit and all but the Baud Rate Clock
114 * registers only define 8 least significant bits. There is
115 * also a workaround to take into account. Raw accessors use
116 * the full register width, but cooked ones truncate it
117 * intentionally so that the rest of the driver does not care.
118 */
119 static u64 __read_sbdchn(struct sbd_port *sport, int reg)
120 {
121 void __iomem *csr = sport->port.membase + reg;
122
123 return __raw_readq(csr);
124 }
125
126 static u64 __read_sbdshr(struct sbd_port *sport, int reg)
127 {
128 void __iomem *csr = sport->memctrl + reg;
129
130 return __raw_readq(csr);
131 }
132
133 static void __write_sbdchn(struct sbd_port *sport, int reg, u64 value)
134 {
135 void __iomem *csr = sport->port.membase + reg;
136
137 __raw_writeq(value, csr);
138 }
139
140 static void __write_sbdshr(struct sbd_port *sport, int reg, u64 value)
141 {
142 void __iomem *csr = sport->memctrl + reg;
143
144 __raw_writeq(value, csr);
145 }
146
147 /*
148 * In bug 1956, we get glitches that can mess up uart registers. This
149 * "read-mode-reg after any register access" is an accepted workaround.
150 */
151 static void __war_sbd1956(struct sbd_port *sport)
152 {
153 __read_sbdchn(sport, R_DUART_MODE_REG_1);
154 __read_sbdchn(sport, R_DUART_MODE_REG_2);
155 }
156
157 static unsigned char read_sbdchn(struct sbd_port *sport, int reg)
158 {
159 unsigned char retval;
160
161 retval = __read_sbdchn(sport, reg);
162 if (SIBYTE_1956_WAR)
163 __war_sbd1956(sport);
164 return retval;
165 }
166
167 static unsigned char read_sbdshr(struct sbd_port *sport, int reg)
168 {
169 unsigned char retval;
170
171 retval = __read_sbdshr(sport, reg);
172 if (SIBYTE_1956_WAR)
173 __war_sbd1956(sport);
174 return retval;
175 }
176
177 static void write_sbdchn(struct sbd_port *sport, int reg, unsigned int value)
178 {
179 __write_sbdchn(sport, reg, value);
180 if (SIBYTE_1956_WAR)
181 __war_sbd1956(sport);
182 }
183
184 static void write_sbdshr(struct sbd_port *sport, int reg, unsigned int value)
185 {
186 __write_sbdshr(sport, reg, value);
187 if (SIBYTE_1956_WAR)
188 __war_sbd1956(sport);
189 }
190
191
192 static int sbd_receive_ready(struct sbd_port *sport)
193 {
194 return read_sbdchn(sport, R_DUART_STATUS) & M_DUART_RX_RDY;
195 }
196
197 static int sbd_receive_drain(struct sbd_port *sport)
198 {
199 int loops = 10000;
200
201 while (sbd_receive_ready(sport) && loops--)
202 read_sbdchn(sport, R_DUART_RX_HOLD);
203 return loops;
204 }
205
206 static int __maybe_unused sbd_transmit_ready(struct sbd_port *sport)
207 {
208 return read_sbdchn(sport, R_DUART_STATUS) & M_DUART_TX_RDY;
209 }
210
211 static int __maybe_unused sbd_transmit_drain(struct sbd_port *sport)
212 {
213 int loops = 10000;
214
215 while (!sbd_transmit_ready(sport) && loops--)
216 udelay(2);
217 return loops;
218 }
219
220 static int sbd_transmit_empty(struct sbd_port *sport)
221 {
222 return read_sbdchn(sport, R_DUART_STATUS) & M_DUART_TX_EMT;
223 }
224
225 static int sbd_line_drain(struct sbd_port *sport)
226 {
227 int loops = 10000;
228
229 while (!sbd_transmit_empty(sport) && loops--)
230 udelay(2);
231 return loops;
232 }
233
234
235 static unsigned int sbd_tx_empty(struct uart_port *uport)
236 {
237 struct sbd_port *sport = to_sport(uport);
238
239 return sbd_transmit_empty(sport) ? TIOCSER_TEMT : 0;
240 }
241
242 static unsigned int sbd_get_mctrl(struct uart_port *uport)
243 {
244 struct sbd_port *sport = to_sport(uport);
245 unsigned int mctrl, status;
246
247 status = read_sbdshr(sport, R_DUART_IN_PORT);
248 status >>= (uport->line) % 2;
249 mctrl = (!(status & M_DUART_IN_PIN0_VAL) ? TIOCM_CTS : 0) |
250 (!(status & M_DUART_IN_PIN4_VAL) ? TIOCM_CAR : 0) |
251 (!(status & M_DUART_RIN0_PIN) ? TIOCM_RNG : 0) |
252 (!(status & M_DUART_IN_PIN2_VAL) ? TIOCM_DSR : 0);
253 return mctrl;
254 }
255
256 static void sbd_set_mctrl(struct uart_port *uport, unsigned int mctrl)
257 {
258 struct sbd_port *sport = to_sport(uport);
259 unsigned int clr = 0, set = 0, mode2;
260
261 if (mctrl & TIOCM_DTR)
262 set |= M_DUART_SET_OPR2;
263 else
264 clr |= M_DUART_CLR_OPR2;
265 if (mctrl & TIOCM_RTS)
266 set |= M_DUART_SET_OPR0;
267 else
268 clr |= M_DUART_CLR_OPR0;
269 clr <<= (uport->line) % 2;
270 set <<= (uport->line) % 2;
271
272 mode2 = read_sbdchn(sport, R_DUART_MODE_REG_2);
273 mode2 &= ~M_DUART_CHAN_MODE;
274 if (mctrl & TIOCM_LOOP)
275 mode2 |= V_DUART_CHAN_MODE_LCL_LOOP;
276 else
277 mode2 |= V_DUART_CHAN_MODE_NORMAL;
278
279 write_sbdshr(sport, R_DUART_CLEAR_OPR, clr);
280 write_sbdshr(sport, R_DUART_SET_OPR, set);
281 write_sbdchn(sport, R_DUART_MODE_REG_2, mode2);
282 }
283
284 static void sbd_stop_tx(struct uart_port *uport)
285 {
286 struct sbd_port *sport = to_sport(uport);
287
288 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS);
289 sport->tx_stopped = 1;
290 };
291
292 static void sbd_start_tx(struct uart_port *uport)
293 {
294 struct sbd_port *sport = to_sport(uport);
295 unsigned int mask;
296
297 /* Enable tx interrupts. */
298 mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2));
299 mask |= M_DUART_IMR_TX;
300 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask);
301
302 /* Go!, go!, go!... */
303 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_EN);
304 sport->tx_stopped = 0;
305 };
306
307 static void sbd_stop_rx(struct uart_port *uport)
308 {
309 struct sbd_port *sport = to_sport(uport);
310
311 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), 0);
312 };
313
314 static void sbd_enable_ms(struct uart_port *uport)
315 {
316 struct sbd_port *sport = to_sport(uport);
317
318 write_sbdchn(sport, R_DUART_AUXCTL_X,
319 M_DUART_CIN_CHNG_ENA | M_DUART_CTS_CHNG_ENA);
320 }
321
322 static void sbd_break_ctl(struct uart_port *uport, int break_state)
323 {
324 struct sbd_port *sport = to_sport(uport);
325
326 if (break_state == -1)
327 write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_START_BREAK);
328 else
329 write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_STOP_BREAK);
330 }
331
332
333 static void sbd_receive_chars(struct sbd_port *sport)
334 {
335 struct uart_port *uport = &sport->port;
336 struct uart_icount *icount;
337 unsigned int status, ch, flag;
338 int count;
339
340 for (count = 16; count; count--) {
341 status = read_sbdchn(sport, R_DUART_STATUS);
342 if (!(status & M_DUART_RX_RDY))
343 break;
344
345 ch = read_sbdchn(sport, R_DUART_RX_HOLD);
346
347 flag = TTY_NORMAL;
348
349 icount = &uport->icount;
350 icount->rx++;
351
352 if (unlikely(status &
353 (M_DUART_RCVD_BRK | M_DUART_FRM_ERR |
354 M_DUART_PARITY_ERR | M_DUART_OVRUN_ERR))) {
355 if (status & M_DUART_RCVD_BRK) {
356 icount->brk++;
357 if (uart_handle_break(uport))
358 continue;
359 } else if (status & M_DUART_FRM_ERR)
360 icount->frame++;
361 else if (status & M_DUART_PARITY_ERR)
362 icount->parity++;
363 if (status & M_DUART_OVRUN_ERR)
364 icount->overrun++;
365
366 status &= uport->read_status_mask;
367 if (status & M_DUART_RCVD_BRK)
368 flag = TTY_BREAK;
369 else if (status & M_DUART_FRM_ERR)
370 flag = TTY_FRAME;
371 else if (status & M_DUART_PARITY_ERR)
372 flag = TTY_PARITY;
373 }
374
375 if (uart_handle_sysrq_char(uport, ch))
376 continue;
377
378 uart_insert_char(uport, status, M_DUART_OVRUN_ERR, ch, flag);
379 }
380
381 tty_flip_buffer_push(uport->info->tty);
382 }
383
384 static void sbd_transmit_chars(struct sbd_port *sport)
385 {
386 struct uart_port *uport = &sport->port;
387 struct circ_buf *xmit = &sport->port.info->xmit;
388 unsigned int mask;
389 int stop_tx;
390
391 /* XON/XOFF chars. */
392 if (sport->port.x_char) {
393 write_sbdchn(sport, R_DUART_TX_HOLD, sport->port.x_char);
394 sport->port.icount.tx++;
395 sport->port.x_char = 0;
396 return;
397 }
398
399 /* If nothing to do or stopped or hardware stopped. */
400 stop_tx = (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port));
401
402 /* Send char. */
403 if (!stop_tx) {
404 write_sbdchn(sport, R_DUART_TX_HOLD, xmit->buf[xmit->tail]);
405 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
406 sport->port.icount.tx++;
407
408 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
409 uart_write_wakeup(&sport->port);
410 }
411
412 /* Are we are done? */
413 if (stop_tx || uart_circ_empty(xmit)) {
414 /* Disable tx interrupts. */
415 mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2));
416 mask &= ~M_DUART_IMR_TX;
417 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask);
418 }
419 }
420
421 static void sbd_status_handle(struct sbd_port *sport)
422 {
423 struct uart_port *uport = &sport->port;
424 unsigned int delta;
425
426 delta = read_sbdshr(sport, R_DUART_INCHREG((uport->line) % 2));
427 delta >>= (uport->line) % 2;
428
429 if (delta & (M_DUART_IN_PIN0_VAL << S_DUART_IN_PIN_CHNG))
430 uart_handle_cts_change(uport, !(delta & M_DUART_IN_PIN0_VAL));
431
432 if (delta & (M_DUART_IN_PIN2_VAL << S_DUART_IN_PIN_CHNG))
433 uport->icount.dsr++;
434
435 if (delta & ((M_DUART_IN_PIN2_VAL | M_DUART_IN_PIN0_VAL) <<
436 S_DUART_IN_PIN_CHNG))
437 wake_up_interruptible(&uport->info->delta_msr_wait);
438 }
439
440 static irqreturn_t sbd_interrupt(int irq, void *dev_id)
441 {
442 struct sbd_port *sport = dev_id;
443 struct uart_port *uport = &sport->port;
444 irqreturn_t status = IRQ_NONE;
445 unsigned int intstat;
446 int count;
447
448 for (count = 16; count; count--) {
449 intstat = read_sbdshr(sport,
450 R_DUART_ISRREG((uport->line) % 2));
451 intstat &= read_sbdshr(sport,
452 R_DUART_IMRREG((uport->line) % 2));
453 intstat &= M_DUART_ISR_ALL;
454 if (!intstat)
455 break;
456
457 if (intstat & M_DUART_ISR_RX)
458 sbd_receive_chars(sport);
459 if (intstat & M_DUART_ISR_IN)
460 sbd_status_handle(sport);
461 if (intstat & M_DUART_ISR_TX)
462 sbd_transmit_chars(sport);
463
464 status = IRQ_HANDLED;
465 }
466
467 return status;
468 }
469
470
471 static int sbd_startup(struct uart_port *uport)
472 {
473 struct sbd_port *sport = to_sport(uport);
474 unsigned int mode1;
475 int ret;
476
477 ret = request_irq(sport->port.irq, sbd_interrupt,
478 IRQF_SHARED, "sb1250-duart", sport);
479 if (ret)
480 return ret;
481
482 /* Clear the receive FIFO. */
483 sbd_receive_drain(sport);
484
485 /* Clear the interrupt registers. */
486 write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT);
487 read_sbdshr(sport, R_DUART_INCHREG((uport->line) % 2));
488
489 /* Set rx/tx interrupt to FIFO available. */
490 mode1 = read_sbdchn(sport, R_DUART_MODE_REG_1);
491 mode1 &= ~(M_DUART_RX_IRQ_SEL_RXFULL | M_DUART_TX_IRQ_SEL_TXEMPT);
492 write_sbdchn(sport, R_DUART_MODE_REG_1, mode1);
493
494 /* Disable tx, enable rx. */
495 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS | M_DUART_RX_EN);
496 sport->tx_stopped = 1;
497
498 /* Enable interrupts. */
499 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2),
500 M_DUART_IMR_IN | M_DUART_IMR_RX);
501
502 return 0;
503 }
504
505 static void sbd_shutdown(struct uart_port *uport)
506 {
507 struct sbd_port *sport = to_sport(uport);
508
509 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS | M_DUART_RX_DIS);
510 sport->tx_stopped = 1;
511 free_irq(sport->port.irq, sport);
512 }
513
514
515 static void sbd_init_port(struct sbd_port *sport)
516 {
517 struct uart_port *uport = &sport->port;
518
519 if (sport->initialised)
520 return;
521
522 /* There is no DUART reset feature, so just set some sane defaults. */
523 write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_RESET_TX);
524 write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_RESET_RX);
525 write_sbdchn(sport, R_DUART_MODE_REG_1, V_DUART_BITS_PER_CHAR_8);
526 write_sbdchn(sport, R_DUART_MODE_REG_2, 0);
527 write_sbdchn(sport, R_DUART_FULL_CTL,
528 V_DUART_INT_TIME(0) | V_DUART_SIG_FULL(15));
529 write_sbdchn(sport, R_DUART_OPCR_X, 0);
530 write_sbdchn(sport, R_DUART_AUXCTL_X, 0);
531 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), 0);
532
533 sport->initialised = 1;
534 }
535
536 static void sbd_set_termios(struct uart_port *uport, struct ktermios *termios,
537 struct ktermios *old_termios)
538 {
539 struct sbd_port *sport = to_sport(uport);
540 unsigned int mode1 = 0, mode2 = 0, aux = 0;
541 unsigned int mode1mask = 0, mode2mask = 0, auxmask = 0;
542 unsigned int oldmode1, oldmode2, oldaux;
543 unsigned int baud, brg;
544 unsigned int command;
545
546 mode1mask |= ~(M_DUART_PARITY_MODE | M_DUART_PARITY_TYPE_ODD |
547 M_DUART_BITS_PER_CHAR);
548 mode2mask |= ~M_DUART_STOP_BIT_LEN_2;
549 auxmask |= ~M_DUART_CTS_CHNG_ENA;
550
551 /* Byte size. */
552 switch (termios->c_cflag & CSIZE) {
553 case CS5:
554 case CS6:
555 /* Unsupported, leave unchanged. */
556 mode1mask |= M_DUART_PARITY_MODE;
557 break;
558 case CS7:
559 mode1 |= V_DUART_BITS_PER_CHAR_7;
560 break;
561 case CS8:
562 default:
563 mode1 |= V_DUART_BITS_PER_CHAR_8;
564 break;
565 }
566
567 /* Parity and stop bits. */
568 if (termios->c_cflag & CSTOPB)
569 mode2 |= M_DUART_STOP_BIT_LEN_2;
570 else
571 mode2 |= M_DUART_STOP_BIT_LEN_1;
572 if (termios->c_cflag & PARENB)
573 mode1 |= V_DUART_PARITY_MODE_ADD;
574 else
575 mode1 |= V_DUART_PARITY_MODE_NONE;
576 if (termios->c_cflag & PARODD)
577 mode1 |= M_DUART_PARITY_TYPE_ODD;
578 else
579 mode1 |= M_DUART_PARITY_TYPE_EVEN;
580
581 baud = uart_get_baud_rate(uport, termios, old_termios, 1200, 5000000);
582 brg = V_DUART_BAUD_RATE(baud);
583 /* The actual lower bound is 1221bps, so compensate. */
584 if (brg > M_DUART_CLK_COUNTER)
585 brg = M_DUART_CLK_COUNTER;
586
587 uart_update_timeout(uport, termios->c_cflag, baud);
588
589 uport->read_status_mask = M_DUART_OVRUN_ERR;
590 if (termios->c_iflag & INPCK)
591 uport->read_status_mask |= M_DUART_FRM_ERR |
592 M_DUART_PARITY_ERR;
593 if (termios->c_iflag & (BRKINT | PARMRK))
594 uport->read_status_mask |= M_DUART_RCVD_BRK;
595
596 uport->ignore_status_mask = 0;
597 if (termios->c_iflag & IGNPAR)
598 uport->ignore_status_mask |= M_DUART_FRM_ERR |
599 M_DUART_PARITY_ERR;
600 if (termios->c_iflag & IGNBRK) {
601 uport->ignore_status_mask |= M_DUART_RCVD_BRK;
602 if (termios->c_iflag & IGNPAR)
603 uport->ignore_status_mask |= M_DUART_OVRUN_ERR;
604 }
605
606 if (termios->c_cflag & CREAD)
607 command = M_DUART_RX_EN;
608 else
609 command = M_DUART_RX_DIS;
610
611 if (termios->c_cflag & CRTSCTS)
612 aux |= M_DUART_CTS_CHNG_ENA;
613 else
614 aux &= ~M_DUART_CTS_CHNG_ENA;
615
616 spin_lock(&uport->lock);
617
618 if (sport->tx_stopped)
619 command |= M_DUART_TX_DIS;
620 else
621 command |= M_DUART_TX_EN;
622
623 oldmode1 = read_sbdchn(sport, R_DUART_MODE_REG_1) & mode1mask;
624 oldmode2 = read_sbdchn(sport, R_DUART_MODE_REG_2) & mode2mask;
625 oldaux = read_sbdchn(sport, R_DUART_AUXCTL_X) & auxmask;
626
627 if (!sport->tx_stopped)
628 sbd_line_drain(sport);
629 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS | M_DUART_RX_DIS);
630
631 write_sbdchn(sport, R_DUART_MODE_REG_1, mode1 | oldmode1);
632 write_sbdchn(sport, R_DUART_MODE_REG_2, mode2 | oldmode2);
633 write_sbdchn(sport, R_DUART_CLK_SEL, brg);
634 write_sbdchn(sport, R_DUART_AUXCTL_X, aux | oldaux);
635
636 write_sbdchn(sport, R_DUART_CMD, command);
637
638 spin_unlock(&uport->lock);
639 }
640
641
642 static const char *sbd_type(struct uart_port *uport)
643 {
644 return "SB1250 DUART";
645 }
646
647 static void sbd_release_port(struct uart_port *uport)
648 {
649 struct sbd_port *sport = to_sport(uport);
650 struct sbd_duart *duart = sport->duart;
651 int map_guard;
652
653 iounmap(sport->memctrl);
654 sport->memctrl = NULL;
655 iounmap(uport->membase);
656 uport->membase = NULL;
657
658 map_guard = atomic_add_return(-1, &duart->map_guard);
659 if (!map_guard)
660 release_mem_region(duart->mapctrl, DUART_CHANREG_SPACING);
661 release_mem_region(uport->mapbase, DUART_CHANREG_SPACING);
662 }
663
664 static int sbd_map_port(struct uart_port *uport)
665 {
666 const char *err = KERN_ERR "sbd: Cannot map MMIO\n";
667 struct sbd_port *sport = to_sport(uport);
668 struct sbd_duart *duart = sport->duart;
669
670 if (!uport->membase)
671 uport->membase = ioremap_nocache(uport->mapbase,
672 DUART_CHANREG_SPACING);
673 if (!uport->membase) {
674 printk(err);
675 return -ENOMEM;
676 }
677
678 if (!sport->memctrl)
679 sport->memctrl = ioremap_nocache(duart->mapctrl,
680 DUART_CHANREG_SPACING);
681 if (!sport->memctrl) {
682 printk(err);
683 iounmap(uport->membase);
684 uport->membase = NULL;
685 return -ENOMEM;
686 }
687
688 return 0;
689 }
690
691 static int sbd_request_port(struct uart_port *uport)
692 {
693 const char *err = KERN_ERR "sbd: Unable to reserve MMIO resource\n";
694 struct sbd_duart *duart = to_sport(uport)->duart;
695 int map_guard;
696 int ret = 0;
697
698 if (!request_mem_region(uport->mapbase, DUART_CHANREG_SPACING,
699 "sb1250-duart")) {
700 printk(err);
701 return -EBUSY;
702 }
703 map_guard = atomic_add_return(1, &duart->map_guard);
704 if (map_guard == 1) {
705 if (!request_mem_region(duart->mapctrl, DUART_CHANREG_SPACING,
706 "sb1250-duart")) {
707 atomic_add(-1, &duart->map_guard);
708 printk(err);
709 ret = -EBUSY;
710 }
711 }
712 if (!ret) {
713 ret = sbd_map_port(uport);
714 if (ret) {
715 map_guard = atomic_add_return(-1, &duart->map_guard);
716 if (!map_guard)
717 release_mem_region(duart->mapctrl,
718 DUART_CHANREG_SPACING);
719 }
720 }
721 if (ret) {
722 release_mem_region(uport->mapbase, DUART_CHANREG_SPACING);
723 return ret;
724 }
725 return 0;
726 }
727
728 static void sbd_config_port(struct uart_port *uport, int flags)
729 {
730 struct sbd_port *sport = to_sport(uport);
731
732 if (flags & UART_CONFIG_TYPE) {
733 if (sbd_request_port(uport))
734 return;
735
736 uport->type = PORT_SB1250_DUART;
737
738 sbd_init_port(sport);
739 }
740 }
741
742 static int sbd_verify_port(struct uart_port *uport, struct serial_struct *ser)
743 {
744 int ret = 0;
745
746 if (ser->type != PORT_UNKNOWN && ser->type != PORT_SB1250_DUART)
747 ret = -EINVAL;
748 if (ser->irq != uport->irq)
749 ret = -EINVAL;
750 if (ser->baud_base != uport->uartclk / 16)
751 ret = -EINVAL;
752 return ret;
753 }
754
755
756 static const struct uart_ops sbd_ops = {
757 .tx_empty = sbd_tx_empty,
758 .set_mctrl = sbd_set_mctrl,
759 .get_mctrl = sbd_get_mctrl,
760 .stop_tx = sbd_stop_tx,
761 .start_tx = sbd_start_tx,
762 .stop_rx = sbd_stop_rx,
763 .enable_ms = sbd_enable_ms,
764 .break_ctl = sbd_break_ctl,
765 .startup = sbd_startup,
766 .shutdown = sbd_shutdown,
767 .set_termios = sbd_set_termios,
768 .type = sbd_type,
769 .release_port = sbd_release_port,
770 .request_port = sbd_request_port,
771 .config_port = sbd_config_port,
772 .verify_port = sbd_verify_port,
773 };
774
775 /* Initialize SB1250 DUART port structures. */
776 static void __init sbd_probe_duarts(void)
777 {
778 static int probed;
779 int chip, side;
780 int max_lines, line;
781
782 if (probed)
783 return;
784
785 /* Set the number of available units based on the SOC type. */
786 switch (soc_type) {
787 case K_SYS_SOC_TYPE_BCM1x55:
788 case K_SYS_SOC_TYPE_BCM1x80:
789 max_lines = 4;
790 break;
791 default:
792 /* Assume at least two serial ports at the normal address. */
793 max_lines = 2;
794 break;
795 }
796
797 probed = 1;
798
799 for (chip = 0, line = 0; chip < DUART_MAX_CHIP && line < max_lines;
800 chip++) {
801 sbd_duarts[chip].mapctrl = SBD_CTRLREGS(line);
802
803 for (side = 0; side < DUART_MAX_SIDE && line < max_lines;
804 side++, line++) {
805 struct sbd_port *sport = &sbd_duarts[chip].sport[side];
806 struct uart_port *uport = &sport->port;
807
808 sport->duart = &sbd_duarts[chip];
809
810 uport->irq = SBD_INT(line);
811 uport->uartclk = 100000000 / 20 * 16;
812 uport->fifosize = 16;
813 uport->iotype = UPIO_MEM;
814 uport->flags = UPF_BOOT_AUTOCONF;
815 uport->ops = &sbd_ops;
816 uport->line = line;
817 uport->mapbase = SBD_CHANREGS(line);
818 }
819 }
820 }
821
822
823 #ifdef CONFIG_SERIAL_SB1250_DUART_CONSOLE
824 /*
825 * Serial console stuff. Very basic, polling driver for doing serial
826 * console output. The console_sem is held by the caller, so we
827 * shouldn't be interrupted for more console activity.
828 */
829 static void sbd_console_putchar(struct uart_port *uport, int ch)
830 {
831 struct sbd_port *sport = to_sport(uport);
832
833 sbd_transmit_drain(sport);
834 write_sbdchn(sport, R_DUART_TX_HOLD, ch);
835 }
836
837 static void sbd_console_write(struct console *co, const char *s,
838 unsigned int count)
839 {
840 int chip = co->index / DUART_MAX_SIDE;
841 int side = co->index % DUART_MAX_SIDE;
842 struct sbd_port *sport = &sbd_duarts[chip].sport[side];
843 struct uart_port *uport = &sport->port;
844 unsigned long flags;
845 unsigned int mask;
846
847 /* Disable transmit interrupts and enable the transmitter. */
848 spin_lock_irqsave(&uport->lock, flags);
849 mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2));
850 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2),
851 mask & ~M_DUART_IMR_TX);
852 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_EN);
853 spin_unlock_irqrestore(&uport->lock, flags);
854
855 uart_console_write(&sport->port, s, count, sbd_console_putchar);
856
857 /* Restore transmit interrupts and the transmitter enable. */
858 spin_lock_irqsave(&uport->lock, flags);
859 sbd_line_drain(sport);
860 if (sport->tx_stopped)
861 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS);
862 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask);
863 spin_unlock_irqrestore(&uport->lock, flags);
864 }
865
866 static int __init sbd_console_setup(struct console *co, char *options)
867 {
868 int chip = co->index / DUART_MAX_SIDE;
869 int side = co->index % DUART_MAX_SIDE;
870 struct sbd_port *sport = &sbd_duarts[chip].sport[side];
871 struct uart_port *uport = &sport->port;
872 int baud = 115200;
873 int bits = 8;
874 int parity = 'n';
875 int flow = 'n';
876 int ret;
877
878 if (!sport->duart)
879 return -ENXIO;
880
881 ret = sbd_map_port(uport);
882 if (ret)
883 return ret;
884
885 sbd_init_port(sport);
886
887 if (options)
888 uart_parse_options(options, &baud, &parity, &bits, &flow);
889 return uart_set_options(uport, co, baud, parity, bits, flow);
890 }
891
892 static struct uart_driver sbd_reg;
893 static struct console sbd_console = {
894 .name = "duart",
895 .write = sbd_console_write,
896 .device = uart_console_device,
897 .setup = sbd_console_setup,
898 .flags = CON_PRINTBUFFER,
899 .index = -1,
900 .data = &sbd_reg
901 };
902
903 static int __init sbd_serial_console_init(void)
904 {
905 sbd_probe_duarts();
906 register_console(&sbd_console);
907
908 return 0;
909 }
910
911 console_initcall(sbd_serial_console_init);
912
913 #define SERIAL_SB1250_DUART_CONSOLE &sbd_console
914 #else
915 #define SERIAL_SB1250_DUART_CONSOLE NULL
916 #endif /* CONFIG_SERIAL_SB1250_DUART_CONSOLE */
917
918
919 static struct uart_driver sbd_reg = {
920 .owner = THIS_MODULE,
921 .driver_name = "serial",
922 .dev_name = "duart",
923 .major = TTY_MAJOR,
924 .minor = SB1250_DUART_MINOR_BASE,
925 .nr = DUART_MAX_CHIP * DUART_MAX_SIDE,
926 .cons = SERIAL_SB1250_DUART_CONSOLE,
927 };
928
929 /* Set up the driver and register it. */
930 static int __init sbd_init(void)
931 {
932 int i, ret;
933
934 sbd_probe_duarts();
935
936 ret = uart_register_driver(&sbd_reg);
937 if (ret)
938 return ret;
939
940 for (i = 0; i < DUART_MAX_CHIP * DUART_MAX_SIDE; i++) {
941 struct sbd_duart *duart = &sbd_duarts[i / DUART_MAX_SIDE];
942 struct sbd_port *sport = &duart->sport[i % DUART_MAX_SIDE];
943 struct uart_port *uport = &sport->port;
944
945 if (sport->duart)
946 uart_add_one_port(&sbd_reg, uport);
947 }
948
949 return 0;
950 }
951
952 /* Unload the driver. Unregister stuff, get ready to go away. */
953 static void __exit sbd_exit(void)
954 {
955 int i;
956
957 for (i = DUART_MAX_CHIP * DUART_MAX_SIDE - 1; i >= 0; i--) {
958 struct sbd_duart *duart = &sbd_duarts[i / DUART_MAX_SIDE];
959 struct sbd_port *sport = &duart->sport[i % DUART_MAX_SIDE];
960 struct uart_port *uport = &sport->port;
961
962 if (sport->duart)
963 uart_remove_one_port(&sbd_reg, uport);
964 }
965
966 uart_unregister_driver(&sbd_reg);
967 }
968
969 module_init(sbd_init);
970 module_exit(sbd_exit);
WRT350N Kernel Patches