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[wrt350n-kernel.git] / include / asm-mips / mipsmtregs.h
blob294bca12cd3fd443183aeb85cdb505f7d1822484
1 /*
2 * MT regs definitions, follows on from mipsregs.h
3 * Copyright (C) 2004 - 2005 MIPS Technologies, Inc. All rights reserved.
4 * Elizabeth Clarke et. al.
5 *
6 */
7 #ifndef _ASM_MIPSMTREGS_H
8 #define _ASM_MIPSMTREGS_H
9
10 #include <asm/mipsregs.h>
11 #include <asm/war.h>
12
13 #ifndef __ASSEMBLY__
14
15 /*
16 * C macros
17 */
18
19 #define read_c0_mvpcontrol() __read_32bit_c0_register($0, 1)
20 #define write_c0_mvpcontrol(val) __write_32bit_c0_register($0, 1, val)
21
22 #define read_c0_mvpconf0() __read_32bit_c0_register($0, 2)
23 #define read_c0_mvpconf1() __read_32bit_c0_register($0, 3)
24
25 #define read_c0_vpecontrol() __read_32bit_c0_register($1, 1)
26 #define write_c0_vpecontrol(val) __write_32bit_c0_register($1, 1, val)
27
28 #define read_c0_vpeconf0() __read_32bit_c0_register($1, 2)
29 #define write_c0_vpeconf0(val) __write_32bit_c0_register($1, 2, val)
30
31 #define read_c0_tcstatus() __read_32bit_c0_register($2, 1)
32 #define write_c0_tcstatus(val) __write_32bit_c0_register($2, 1, val)
33
34 #define read_c0_tcbind() __read_32bit_c0_register($2, 2)
35
36 #define read_c0_tccontext() __read_32bit_c0_register($2, 5)
37 #define write_c0_tccontext(val) __write_32bit_c0_register($2, 5, val)
38
39 #else /* Assembly */
40 /*
41 * Macros for use in assembly language code
42 */
43
44 #define CP0_MVPCONTROL $0,1
45 #define CP0_MVPCONF0 $0,2
46 #define CP0_MVPCONF1 $0,3
47 #define CP0_VPECONTROL $1,1
48 #define CP0_VPECONF0 $1,2
49 #define CP0_VPECONF1 $1,3
50 #define CP0_YQMASK $1,4
51 #define CP0_VPESCHEDULE $1,5
52 #define CP0_VPESCHEFBK $1,6
53 #define CP0_TCSTATUS $2,1
54 #define CP0_TCBIND $2,2
55 #define CP0_TCRESTART $2,3
56 #define CP0_TCHALT $2,4
57 #define CP0_TCCONTEXT $2,5
58 #define CP0_TCSCHEDULE $2,6
59 #define CP0_TCSCHEFBK $2,7
60 #define CP0_SRSCONF0 $6,1
61 #define CP0_SRSCONF1 $6,2
62 #define CP0_SRSCONF2 $6,3
63 #define CP0_SRSCONF3 $6,4
64 #define CP0_SRSCONF4 $6,5
65
66 #endif
67
68 /* MVPControl fields */
69 #define MVPCONTROL_EVP (_ULCAST_(1))
70
71 #define MVPCONTROL_VPC_SHIFT 1
72 #define MVPCONTROL_VPC (_ULCAST_(1) << MVPCONTROL_VPC_SHIFT)
73
74 #define MVPCONTROL_STLB_SHIFT 2
75 #define MVPCONTROL_STLB (_ULCAST_(1) << MVPCONTROL_STLB_SHIFT)
76
77
78 /* MVPConf0 fields */
79 #define MVPCONF0_PTC_SHIFT 0
80 #define MVPCONF0_PTC ( _ULCAST_(0xff))
81 #define MVPCONF0_PVPE_SHIFT 10
82 #define MVPCONF0_PVPE ( _ULCAST_(0xf) << MVPCONF0_PVPE_SHIFT)
83 #define MVPCONF0_TCA_SHIFT 15
84 #define MVPCONF0_TCA ( _ULCAST_(1) << MVPCONF0_TCA_SHIFT)
85 #define MVPCONF0_PTLBE_SHIFT 16
86 #define MVPCONF0_PTLBE (_ULCAST_(0x3ff) << MVPCONF0_PTLBE_SHIFT)
87 #define MVPCONF0_TLBS_SHIFT 29
88 #define MVPCONF0_TLBS (_ULCAST_(1) << MVPCONF0_TLBS_SHIFT)
89 #define MVPCONF0_M_SHIFT 31
90 #define MVPCONF0_M (_ULCAST_(0x1) << MVPCONF0_M_SHIFT)
91
92
93 /* config3 fields */
94 #define CONFIG3_MT_SHIFT 2
95 #define CONFIG3_MT (_ULCAST_(1) << CONFIG3_MT_SHIFT)
96
97
98 /* VPEControl fields (per VPE) */
99 #define VPECONTROL_TARGTC (_ULCAST_(0xff))
100
101 #define VPECONTROL_TE_SHIFT 15
102 #define VPECONTROL_TE (_ULCAST_(1) << VPECONTROL_TE_SHIFT)
103 #define VPECONTROL_EXCPT_SHIFT 16
104 #define VPECONTROL_EXCPT (_ULCAST_(0x7) << VPECONTROL_EXCPT_SHIFT)
105
106 /* Thread Exception Codes for EXCPT field */
107 #define THREX_TU 0
108 #define THREX_TO 1
109 #define THREX_IYQ 2
110 #define THREX_GSX 3
111 #define THREX_YSCH 4
112 #define THREX_GSSCH 5
113
114 #define VPECONTROL_GSI_SHIFT 20
115 #define VPECONTROL_GSI (_ULCAST_(1) << VPECONTROL_GSI_SHIFT)
116 #define VPECONTROL_YSI_SHIFT 21
117 #define VPECONTROL_YSI (_ULCAST_(1) << VPECONTROL_YSI_SHIFT)
118
119 /* VPEConf0 fields (per VPE) */
120 #define VPECONF0_VPA_SHIFT 0
121 #define VPECONF0_VPA (_ULCAST_(1) << VPECONF0_VPA_SHIFT)
122 #define VPECONF0_MVP_SHIFT 1
123 #define VPECONF0_MVP (_ULCAST_(1) << VPECONF0_MVP_SHIFT)
124 #define VPECONF0_XTC_SHIFT 21
125 #define VPECONF0_XTC (_ULCAST_(0xff) << VPECONF0_XTC_SHIFT)
126
127 /* TCStatus fields (per TC) */
128 #define TCSTATUS_TASID (_ULCAST_(0xff))
129 #define TCSTATUS_IXMT_SHIFT 10
130 #define TCSTATUS_IXMT (_ULCAST_(1) << TCSTATUS_IXMT_SHIFT)
131 #define TCSTATUS_TKSU_SHIFT 11
132 #define TCSTATUS_TKSU (_ULCAST_(3) << TCSTATUS_TKSU_SHIFT)
133 #define TCSTATUS_A_SHIFT 13
134 #define TCSTATUS_A (_ULCAST_(1) << TCSTATUS_A_SHIFT)
135 #define TCSTATUS_DA_SHIFT 15
136 #define TCSTATUS_DA (_ULCAST_(1) << TCSTATUS_DA_SHIFT)
137 #define TCSTATUS_DT_SHIFT 20
138 #define TCSTATUS_DT (_ULCAST_(1) << TCSTATUS_DT_SHIFT)
139 #define TCSTATUS_TDS_SHIFT 21
140 #define TCSTATUS_TDS (_ULCAST_(1) << TCSTATUS_TDS_SHIFT)
141 #define TCSTATUS_TSST_SHIFT 22
142 #define TCSTATUS_TSST (_ULCAST_(1) << TCSTATUS_TSST_SHIFT)
143 #define TCSTATUS_RNST_SHIFT 23
144 #define TCSTATUS_RNST (_ULCAST_(3) << TCSTATUS_RNST_SHIFT)
145 /* Codes for RNST */
146 #define TC_RUNNING 0
147 #define TC_WAITING 1
148 #define TC_YIELDING 2
149 #define TC_GATED 3
150
151 #define TCSTATUS_TMX_SHIFT 27
152 #define TCSTATUS_TMX (_ULCAST_(1) << TCSTATUS_TMX_SHIFT)
153 /* TCStatus TCU bits can use same definitions/offsets as CU bits in Status */
154
155 /* TCBind */
156 #define TCBIND_CURVPE_SHIFT 0
157 #define TCBIND_CURVPE (_ULCAST_(0xf))
158
159 #define TCBIND_CURTC_SHIFT 21
160
161 #define TCBIND_CURTC (_ULCAST_(0xff) << TCBIND_CURTC_SHIFT)
162
163 /* TCHalt */
164 #define TCHALT_H (_ULCAST_(1))
165
166 #ifndef __ASSEMBLY__
167
168 static inline unsigned int dvpe(void)
169 {
170 int res = 0;
171
172 __asm__ __volatile__(
173 " .set push \n"
174 " .set noreorder \n"
175 " .set noat \n"
176 " .set mips32r2 \n"
177 " .word 0x41610001 # dvpe $1 \n"
178 " move %0, $1 \n"
179 " ehb \n"
180 " .set pop \n"
181 : "=r" (res));
182
183 instruction_hazard();
184
185 return res;
186 }
187
188 static inline void __raw_evpe(void)
189 {
190 __asm__ __volatile__(
191 " .set push \n"
192 " .set noreorder \n"
193 " .set noat \n"
194 " .set mips32r2 \n"
195 " .word 0x41600021 # evpe \n"
196 " ehb \n"
197 " .set pop \n");
198 }
199
200 /* Enable multiMT if previous suggested it should be.
201 EMT_ENABLE to force */
202
203 #define EVPE_ENABLE MVPCONTROL_EVP
204
205 static inline void evpe(int previous)
206 {
207 if ((previous & MVPCONTROL_EVP))
208 __raw_evpe();
209 }
210
211 static inline unsigned int dmt(void)
212 {
213 int res;
214
215 __asm__ __volatile__(
216 " .set push \n"
217 " .set mips32r2 \n"
218 " .set noat \n"
219 " .word 0x41610BC1 # dmt $1 \n"
220 " ehb \n"
221 " move %0, $1 \n"
222 " .set pop \n"
223 : "=r" (res));
224
225 instruction_hazard();
226
227 return res;
228 }
229
230 static inline void __raw_emt(void)
231 {
232 __asm__ __volatile__(
233 " .set noreorder \n"
234 " .set mips32r2 \n"
235 " .word 0x41600be1 # emt \n"
236 " ehb \n"
237 " .set mips0 \n"
238 " .set reorder");
239 }
240
241 /* enable multiVPE if previous suggested it should be.
242 EVPE_ENABLE to force */
243
244 #define EMT_ENABLE VPECONTROL_TE
245
246 static inline void emt(int previous)
247 {
248 if ((previous & EMT_ENABLE))
249 __raw_emt();
250 }
251
252 static inline void ehb(void)
253 {
254 __asm__ __volatile__(
255 " .set mips32r2 \n"
256 " ehb \n"
257 " .set mips0 \n");
258 }
259
260 #define mftc0(rt,sel) \
261 ({ \
262 unsigned long __res; \
263 \
264 __asm__ __volatile__( \
265 " .set push \n" \
266 " .set mips32r2 \n" \
267 " .set noat \n" \
268 " # mftc0 $1, $" #rt ", " #sel " \n" \
269 " .word 0x41000800 | (" #rt " << 16) | " #sel " \n" \
270 " move %0, $1 \n" \
271 " .set pop \n" \
272 : "=r" (__res)); \
273 \
274 __res; \
275 })
276
277 #define mftgpr(rt) \
278 ({ \
279 unsigned long __res; \
280 \
281 __asm__ __volatile__( \
282 " .set push \n" \
283 " .set noat \n" \
284 " .set mips32r2 \n" \
285 " # mftgpr $1," #rt " \n" \
286 " .word 0x41000820 | (" #rt " << 16) \n" \
287 " move %0, $1 \n" \
288 " .set pop \n" \
289 : "=r" (__res)); \
290 \
291 __res; \
292 })
293
294 #define mftr(rt,u,sel) \
295 ({ \
296 unsigned long __res; \
297 \
298 __asm__ __volatile__( \
299 " mftr %0, " #rt ", " #u ", " #sel " \n" \
300 : "=r" (__res)); \
301 \
302 __res; \
303 })
304
305 #define mttgpr(rd,v) \
306 do { \
307 __asm__ __volatile__( \
308 " .set push \n" \
309 " .set mips32r2 \n" \
310 " .set noat \n" \
311 " move $1, %0 \n" \
312 " # mttgpr $1, " #rd " \n" \
313 " .word 0x41810020 | (" #rd " << 11) \n" \
314 " .set pop \n" \
315 : : "r" (v)); \
316 } while (0)
317
318 #define mttc0(rd,sel,v) \
319 ({ \
320 __asm__ __volatile__( \
321 " .set push \n" \
322 " .set mips32r2 \n" \
323 " .set noat \n" \
324 " move $1, %0 \n" \
325 " # mttc0 %0," #rd ", " #sel " \n" \
326 " .word 0x41810000 | (" #rd " << 11) | " #sel " \n" \
327 " .set pop \n" \
328 : \
329 : "r" (v)); \
330 })
331
332
333 #define mttr(rd,u,sel,v) \
334 ({ \
335 __asm__ __volatile__( \
336 "mttr %0," #rd ", " #u ", " #sel \
337 : : "r" (v)); \
338 })
339
340
341 #define settc(tc) \
342 do { \
343 write_c0_vpecontrol((read_c0_vpecontrol()&~VPECONTROL_TARGTC) | (tc)); \
344 ehb(); \
345 } while (0)
346
347
348 /* you *must* set the target tc (settc) before trying to use these */
349 #define read_vpe_c0_vpecontrol() mftc0(1, 1)
350 #define write_vpe_c0_vpecontrol(val) mttc0(1, 1, val)
351 #define read_vpe_c0_vpeconf0() mftc0(1, 2)
352 #define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val)
353 #define read_vpe_c0_count() mftc0(9, 0)
354 #define write_vpe_c0_count(val) mttc0(9, 0, val)
355 #define read_vpe_c0_status() mftc0(12, 0)
356 #define write_vpe_c0_status(val) mttc0(12, 0, val)
357 #define read_vpe_c0_cause() mftc0(13, 0)
358 #define write_vpe_c0_cause(val) mttc0(13, 0, val)
359 #define read_vpe_c0_config() mftc0(16, 0)
360 #define write_vpe_c0_config(val) mttc0(16, 0, val)
361 #define read_vpe_c0_config1() mftc0(16, 1)
362 #define write_vpe_c0_config1(val) mttc0(16, 1, val)
363 #define read_vpe_c0_config7() mftc0(16, 7)
364 #define write_vpe_c0_config7(val) mttc0(16, 7, val)
365 #define read_vpe_c0_ebase() mftc0(15,1)
366 #define write_vpe_c0_ebase(val) mttc0(15, 1, val)
367 #define write_vpe_c0_compare(val) mttc0(11, 0, val)
368 #define read_vpe_c0_badvaddr() mftc0(8, 0)
369 #define read_vpe_c0_epc() mftc0(14, 0)
370 #define write_vpe_c0_epc(val) mttc0(14, 0, val)
371
372
373 /* TC */
374 #define read_tc_c0_tcstatus() mftc0(2, 1)
375 #define write_tc_c0_tcstatus(val) mttc0(2,1,val)
376 #define read_tc_c0_tcbind() mftc0(2, 2)
377 #define write_tc_c0_tcbind(val) mttc0(2,2,val)
378 #define read_tc_c0_tcrestart() mftc0(2, 3)
379 #define write_tc_c0_tcrestart(val) mttc0(2,3,val)
380 #define read_tc_c0_tchalt() mftc0(2, 4)
381 #define write_tc_c0_tchalt(val) mttc0(2,4,val)
382 #define read_tc_c0_tccontext() mftc0(2, 5)
383 #define write_tc_c0_tccontext(val) mttc0(2,5,val)
384
385 /* GPR */
386 #define read_tc_gpr_sp() mftgpr(29)
387 #define write_tc_gpr_sp(val) mttgpr(29, val)
388 #define read_tc_gpr_gp() mftgpr(28)
389 #define write_tc_gpr_gp(val) mttgpr(28, val)
390
391 __BUILD_SET_C0(mvpcontrol)
392
393 #endif /* Not __ASSEMBLY__ */
394
395 #endif
WRT350N Kernel Patches