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Blackfin arch: Add label to call new GPIO API
[wrt350n-kernel.git] / drivers / net / e1000 / e1000_hw.c
blob8604adbe351cc07dc2b004896af8c4cd338d9331
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /* e1000_hw.c
30 * Shared functions for accessing and configuring the MAC
31 */
32
33
34 #include "e1000_hw.h"
35
36 static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
37 static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
38 static int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data);
39 static int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
40 static int32_t e1000_get_software_semaphore(struct e1000_hw *hw);
41 static void e1000_release_software_semaphore(struct e1000_hw *hw);
42
43 static uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw);
44 static int32_t e1000_check_downshift(struct e1000_hw *hw);
45 static int32_t e1000_check_polarity(struct e1000_hw *hw, e1000_rev_polarity *polarity);
46 static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
47 static void e1000_clear_vfta(struct e1000_hw *hw);
48 static int32_t e1000_commit_shadow_ram(struct e1000_hw *hw);
49 static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, boolean_t link_up);
50 static int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw);
51 static int32_t e1000_detect_gig_phy(struct e1000_hw *hw);
52 static int32_t e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank);
53 static int32_t e1000_get_auto_rd_done(struct e1000_hw *hw);
54 static int32_t e1000_get_cable_length(struct e1000_hw *hw, uint16_t *min_length, uint16_t *max_length);
55 static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
56 static int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw);
57 static int32_t e1000_get_software_flag(struct e1000_hw *hw);
58 static int32_t e1000_ich8_cycle_init(struct e1000_hw *hw);
59 static int32_t e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout);
60 static int32_t e1000_id_led_init(struct e1000_hw *hw);
61 static int32_t e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, uint32_t cnf_base_addr, uint32_t cnf_size);
62 static int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw);
63 static void e1000_init_rx_addrs(struct e1000_hw *hw);
64 static void e1000_initialize_hardware_bits(struct e1000_hw *hw);
65 static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
66 static int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);
67 static int32_t e1000_mng_enable_host_if(struct e1000_hw *hw);
68 static int32_t e1000_mng_host_if_write(struct e1000_hw *hw, uint8_t *buffer, uint16_t length, uint16_t offset, uint8_t *sum);
69 static int32_t e1000_mng_write_cmd_header(struct e1000_hw* hw, struct e1000_host_mng_command_header* hdr);
70 static int32_t e1000_mng_write_commit(struct e1000_hw *hw);
71 static int32_t e1000_phy_ife_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
72 static int32_t e1000_phy_igp_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
73 static int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
74 static int32_t e1000_write_eeprom_eewr(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
75 static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);
76 static int32_t e1000_phy_m88_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
77 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
78 static int32_t e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t *data);
79 static int32_t e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte);
80 static int32_t e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte);
81 static int32_t e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data);
82 static int32_t e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t *data);
83 static int32_t e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t data);
84 static int32_t e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
85 static int32_t e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
86 static void e1000_release_software_flag(struct e1000_hw *hw);
87 static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active);
88 static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active);
89 static int32_t e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop);
90 static void e1000_set_pci_express_master_disable(struct e1000_hw *hw);
91 static int32_t e1000_wait_autoneg(struct e1000_hw *hw);
92 static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value);
93 static int32_t e1000_set_phy_type(struct e1000_hw *hw);
94 static void e1000_phy_init_script(struct e1000_hw *hw);
95 static int32_t e1000_setup_copper_link(struct e1000_hw *hw);
96 static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
97 static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
98 static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw);
99 static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw);
100 static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
101 static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
102 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data,
103 uint16_t count);
104 static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw);
105 static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw);
106 static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset,
107 uint16_t words, uint16_t *data);
108 static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw,
109 uint16_t offset, uint16_t words,
110 uint16_t *data);
111 static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw);
112 static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
113 static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
114 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data,
115 uint16_t count);
116 static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
117 uint16_t phy_data);
118 static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr,
119 uint16_t *phy_data);
120 static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count);
121 static int32_t e1000_acquire_eeprom(struct e1000_hw *hw);
122 static void e1000_release_eeprom(struct e1000_hw *hw);
123 static void e1000_standby_eeprom(struct e1000_hw *hw);
124 static int32_t e1000_set_vco_speed(struct e1000_hw *hw);
125 static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw);
126 static int32_t e1000_set_phy_mode(struct e1000_hw *hw);
127 static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer);
128 static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length);
129 static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw,
130 uint16_t duplex);
131 static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw);
132
133 /* IGP cable length table */
134 static const
135 uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
136 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
137 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
138 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
139 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
140 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
141 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
142 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
143 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
144
145 static const
146 uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
147 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
148 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
149 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
150 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
151 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
152 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
153 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
154 104, 109, 114, 118, 121, 124};
155
156 /******************************************************************************
157 * Set the phy type member in the hw struct.
158 *
159 * hw - Struct containing variables accessed by shared code
160 *****************************************************************************/
161 static int32_t
162 e1000_set_phy_type(struct e1000_hw *hw)
163 {
164 DEBUGFUNC("e1000_set_phy_type");
165
166 if (hw->mac_type == e1000_undefined)
167 return -E1000_ERR_PHY_TYPE;
168
169 switch (hw->phy_id) {
170 case M88E1000_E_PHY_ID:
171 case M88E1000_I_PHY_ID:
172 case M88E1011_I_PHY_ID:
173 case M88E1111_I_PHY_ID:
174 hw->phy_type = e1000_phy_m88;
175 break;
176 case IGP01E1000_I_PHY_ID:
177 if (hw->mac_type == e1000_82541 ||
178 hw->mac_type == e1000_82541_rev_2 ||
179 hw->mac_type == e1000_82547 ||
180 hw->mac_type == e1000_82547_rev_2) {
181 hw->phy_type = e1000_phy_igp;
182 break;
183 }
184 case IGP03E1000_E_PHY_ID:
185 hw->phy_type = e1000_phy_igp_3;
186 break;
187 case IFE_E_PHY_ID:
188 case IFE_PLUS_E_PHY_ID:
189 case IFE_C_E_PHY_ID:
190 hw->phy_type = e1000_phy_ife;
191 break;
192 case GG82563_E_PHY_ID:
193 if (hw->mac_type == e1000_80003es2lan) {
194 hw->phy_type = e1000_phy_gg82563;
195 break;
196 }
197 /* Fall Through */
198 default:
199 /* Should never have loaded on this device */
200 hw->phy_type = e1000_phy_undefined;
201 return -E1000_ERR_PHY_TYPE;
202 }
203
204 return E1000_SUCCESS;
205 }
206
207 /******************************************************************************
208 * IGP phy init script - initializes the GbE PHY
209 *
210 * hw - Struct containing variables accessed by shared code
211 *****************************************************************************/
212 static void
213 e1000_phy_init_script(struct e1000_hw *hw)
214 {
215 uint32_t ret_val;
216 uint16_t phy_saved_data;
217
218 DEBUGFUNC("e1000_phy_init_script");
219
220 if (hw->phy_init_script) {
221 msleep(20);
222
223 /* Save off the current value of register 0x2F5B to be restored at
224 * the end of this routine. */
225 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
226
227 /* Disabled the PHY transmitter */
228 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
229
230 msleep(20);
231
232 e1000_write_phy_reg(hw,0x0000,0x0140);
233
234 msleep(5);
235
236 switch (hw->mac_type) {
237 case e1000_82541:
238 case e1000_82547:
239 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
240
241 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
242
243 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
244
245 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
246
247 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
248
249 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
250
251 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
252
253 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
254
255 e1000_write_phy_reg(hw, 0x2010, 0x0008);
256 break;
257
258 case e1000_82541_rev_2:
259 case e1000_82547_rev_2:
260 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
261 break;
262 default:
263 break;
264 }
265
266 e1000_write_phy_reg(hw, 0x0000, 0x3300);
267
268 msleep(20);
269
270 /* Now enable the transmitter */
271 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
272
273 if (hw->mac_type == e1000_82547) {
274 uint16_t fused, fine, coarse;
275
276 /* Move to analog registers page */
277 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
278
279 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
280 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
281
282 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
283 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
284
285 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
286 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
287 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
288 } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
289 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
290
291 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
292 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
293 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
294
295 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
296 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
297 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
298 }
299 }
300 }
301 }
302
303 /******************************************************************************
304 * Set the mac type member in the hw struct.
305 *
306 * hw - Struct containing variables accessed by shared code
307 *****************************************************************************/
308 int32_t
309 e1000_set_mac_type(struct e1000_hw *hw)
310 {
311 DEBUGFUNC("e1000_set_mac_type");
312
313 switch (hw->device_id) {
314 case E1000_DEV_ID_82542:
315 switch (hw->revision_id) {
316 case E1000_82542_2_0_REV_ID:
317 hw->mac_type = e1000_82542_rev2_0;
318 break;
319 case E1000_82542_2_1_REV_ID:
320 hw->mac_type = e1000_82542_rev2_1;
321 break;
322 default:
323 /* Invalid 82542 revision ID */
324 return -E1000_ERR_MAC_TYPE;
325 }
326 break;
327 case E1000_DEV_ID_82543GC_FIBER:
328 case E1000_DEV_ID_82543GC_COPPER:
329 hw->mac_type = e1000_82543;
330 break;
331 case E1000_DEV_ID_82544EI_COPPER:
332 case E1000_DEV_ID_82544EI_FIBER:
333 case E1000_DEV_ID_82544GC_COPPER:
334 case E1000_DEV_ID_82544GC_LOM:
335 hw->mac_type = e1000_82544;
336 break;
337 case E1000_DEV_ID_82540EM:
338 case E1000_DEV_ID_82540EM_LOM:
339 case E1000_DEV_ID_82540EP:
340 case E1000_DEV_ID_82540EP_LOM:
341 case E1000_DEV_ID_82540EP_LP:
342 hw->mac_type = e1000_82540;
343 break;
344 case E1000_DEV_ID_82545EM_COPPER:
345 case E1000_DEV_ID_82545EM_FIBER:
346 hw->mac_type = e1000_82545;
347 break;
348 case E1000_DEV_ID_82545GM_COPPER:
349 case E1000_DEV_ID_82545GM_FIBER:
350 case E1000_DEV_ID_82545GM_SERDES:
351 hw->mac_type = e1000_82545_rev_3;
352 break;
353 case E1000_DEV_ID_82546EB_COPPER:
354 case E1000_DEV_ID_82546EB_FIBER:
355 case E1000_DEV_ID_82546EB_QUAD_COPPER:
356 hw->mac_type = e1000_82546;
357 break;
358 case E1000_DEV_ID_82546GB_COPPER:
359 case E1000_DEV_ID_82546GB_FIBER:
360 case E1000_DEV_ID_82546GB_SERDES:
361 case E1000_DEV_ID_82546GB_PCIE:
362 case E1000_DEV_ID_82546GB_QUAD_COPPER:
363 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
364 hw->mac_type = e1000_82546_rev_3;
365 break;
366 case E1000_DEV_ID_82541EI:
367 case E1000_DEV_ID_82541EI_MOBILE:
368 case E1000_DEV_ID_82541ER_LOM:
369 hw->mac_type = e1000_82541;
370 break;
371 case E1000_DEV_ID_82541ER:
372 case E1000_DEV_ID_82541GI:
373 case E1000_DEV_ID_82541GI_LF:
374 case E1000_DEV_ID_82541GI_MOBILE:
375 hw->mac_type = e1000_82541_rev_2;
376 break;
377 case E1000_DEV_ID_82547EI:
378 case E1000_DEV_ID_82547EI_MOBILE:
379 hw->mac_type = e1000_82547;
380 break;
381 case E1000_DEV_ID_82547GI:
382 hw->mac_type = e1000_82547_rev_2;
383 break;
384 case E1000_DEV_ID_82571EB_COPPER:
385 case E1000_DEV_ID_82571EB_FIBER:
386 case E1000_DEV_ID_82571EB_SERDES:
387 case E1000_DEV_ID_82571EB_SERDES_DUAL:
388 case E1000_DEV_ID_82571EB_SERDES_QUAD:
389 case E1000_DEV_ID_82571EB_QUAD_COPPER:
390 case E1000_DEV_ID_82571PT_QUAD_COPPER:
391 case E1000_DEV_ID_82571EB_QUAD_FIBER:
392 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
393 hw->mac_type = e1000_82571;
394 break;
395 case E1000_DEV_ID_82572EI_COPPER:
396 case E1000_DEV_ID_82572EI_FIBER:
397 case E1000_DEV_ID_82572EI_SERDES:
398 case E1000_DEV_ID_82572EI:
399 hw->mac_type = e1000_82572;
400 break;
401 case E1000_DEV_ID_82573E:
402 case E1000_DEV_ID_82573E_IAMT:
403 case E1000_DEV_ID_82573L:
404 hw->mac_type = e1000_82573;
405 break;
406 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
407 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
408 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
409 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
410 hw->mac_type = e1000_80003es2lan;
411 break;
412 case E1000_DEV_ID_ICH8_IGP_M_AMT:
413 case E1000_DEV_ID_ICH8_IGP_AMT:
414 case E1000_DEV_ID_ICH8_IGP_C:
415 case E1000_DEV_ID_ICH8_IFE:
416 case E1000_DEV_ID_ICH8_IFE_GT:
417 case E1000_DEV_ID_ICH8_IFE_G:
418 case E1000_DEV_ID_ICH8_IGP_M:
419 hw->mac_type = e1000_ich8lan;
420 break;
421 default:
422 /* Should never have loaded on this device */
423 return -E1000_ERR_MAC_TYPE;
424 }
425
426 switch (hw->mac_type) {
427 case e1000_ich8lan:
428 hw->swfwhw_semaphore_present = TRUE;
429 hw->asf_firmware_present = TRUE;
430 break;
431 case e1000_80003es2lan:
432 hw->swfw_sync_present = TRUE;
433 /* fall through */
434 case e1000_82571:
435 case e1000_82572:
436 case e1000_82573:
437 hw->eeprom_semaphore_present = TRUE;
438 /* fall through */
439 case e1000_82541:
440 case e1000_82547:
441 case e1000_82541_rev_2:
442 case e1000_82547_rev_2:
443 hw->asf_firmware_present = TRUE;
444 break;
445 default:
446 break;
447 }
448
449 /* The 82543 chip does not count tx_carrier_errors properly in
450 * FD mode
451 */
452 if (hw->mac_type == e1000_82543)
453 hw->bad_tx_carr_stats_fd = TRUE;
454
455 /* capable of receiving management packets to the host */
456 if (hw->mac_type >= e1000_82571)
457 hw->has_manc2h = TRUE;
458
459 /* In rare occasions, ESB2 systems would end up started without
460 * the RX unit being turned on.
461 */
462 if (hw->mac_type == e1000_80003es2lan)
463 hw->rx_needs_kicking = TRUE;
464
465 if (hw->mac_type > e1000_82544)
466 hw->has_smbus = TRUE;
467
468 return E1000_SUCCESS;
469 }
470
471 /*****************************************************************************
472 * Set media type and TBI compatibility.
473 *
474 * hw - Struct containing variables accessed by shared code
475 * **************************************************************************/
476 void
477 e1000_set_media_type(struct e1000_hw *hw)
478 {
479 uint32_t status;
480
481 DEBUGFUNC("e1000_set_media_type");
482
483 if (hw->mac_type != e1000_82543) {
484 /* tbi_compatibility is only valid on 82543 */
485 hw->tbi_compatibility_en = FALSE;
486 }
487
488 switch (hw->device_id) {
489 case E1000_DEV_ID_82545GM_SERDES:
490 case E1000_DEV_ID_82546GB_SERDES:
491 case E1000_DEV_ID_82571EB_SERDES:
492 case E1000_DEV_ID_82571EB_SERDES_DUAL:
493 case E1000_DEV_ID_82571EB_SERDES_QUAD:
494 case E1000_DEV_ID_82572EI_SERDES:
495 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
496 hw->media_type = e1000_media_type_internal_serdes;
497 break;
498 default:
499 switch (hw->mac_type) {
500 case e1000_82542_rev2_0:
501 case e1000_82542_rev2_1:
502 hw->media_type = e1000_media_type_fiber;
503 break;
504 case e1000_ich8lan:
505 case e1000_82573:
506 /* The STATUS_TBIMODE bit is reserved or reused for the this
507 * device.
508 */
509 hw->media_type = e1000_media_type_copper;
510 break;
511 default:
512 status = E1000_READ_REG(hw, STATUS);
513 if (status & E1000_STATUS_TBIMODE) {
514 hw->media_type = e1000_media_type_fiber;
515 /* tbi_compatibility not valid on fiber */
516 hw->tbi_compatibility_en = FALSE;
517 } else {
518 hw->media_type = e1000_media_type_copper;
519 }
520 break;
521 }
522 }
523 }
524
525 /******************************************************************************
526 * Reset the transmit and receive units; mask and clear all interrupts.
527 *
528 * hw - Struct containing variables accessed by shared code
529 *****************************************************************************/
530 int32_t
531 e1000_reset_hw(struct e1000_hw *hw)
532 {
533 uint32_t ctrl;
534 uint32_t ctrl_ext;
535 uint32_t icr;
536 uint32_t manc;
537 uint32_t led_ctrl;
538 uint32_t timeout;
539 uint32_t extcnf_ctrl;
540 int32_t ret_val;
541
542 DEBUGFUNC("e1000_reset_hw");
543
544 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
545 if (hw->mac_type == e1000_82542_rev2_0) {
546 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
547 e1000_pci_clear_mwi(hw);
548 }
549
550 if (hw->bus_type == e1000_bus_type_pci_express) {
551 /* Prevent the PCI-E bus from sticking if there is no TLP connection
552 * on the last TLP read/write transaction when MAC is reset.
553 */
554 if (e1000_disable_pciex_master(hw) != E1000_SUCCESS) {
555 DEBUGOUT("PCI-E Master disable polling has failed.\n");
556 }
557 }
558
559 /* Clear interrupt mask to stop board from generating interrupts */
560 DEBUGOUT("Masking off all interrupts\n");
561 E1000_WRITE_REG(hw, IMC, 0xffffffff);
562
563 /* Disable the Transmit and Receive units. Then delay to allow
564 * any pending transactions to complete before we hit the MAC with
565 * the global reset.
566 */
567 E1000_WRITE_REG(hw, RCTL, 0);
568 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
569 E1000_WRITE_FLUSH(hw);
570
571 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
572 hw->tbi_compatibility_on = FALSE;
573
574 /* Delay to allow any outstanding PCI transactions to complete before
575 * resetting the device
576 */
577 msleep(10);
578
579 ctrl = E1000_READ_REG(hw, CTRL);
580
581 /* Must reset the PHY before resetting the MAC */
582 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
583 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
584 msleep(5);
585 }
586
587 /* Must acquire the MDIO ownership before MAC reset.
588 * Ownership defaults to firmware after a reset. */
589 if (hw->mac_type == e1000_82573) {
590 timeout = 10;
591
592 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
593 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
594
595 do {
596 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
597 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
598
599 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
600 break;
601 else
602 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
603
604 msleep(2);
605 timeout--;
606 } while (timeout);
607 }
608
609 /* Workaround for ICH8 bit corruption issue in FIFO memory */
610 if (hw->mac_type == e1000_ich8lan) {
611 /* Set Tx and Rx buffer allocation to 8k apiece. */
612 E1000_WRITE_REG(hw, PBA, E1000_PBA_8K);
613 /* Set Packet Buffer Size to 16k. */
614 E1000_WRITE_REG(hw, PBS, E1000_PBS_16K);
615 }
616
617 /* Issue a global reset to the MAC. This will reset the chip's
618 * transmit, receive, DMA, and link units. It will not effect
619 * the current PCI configuration. The global reset bit is self-
620 * clearing, and should clear within a microsecond.
621 */
622 DEBUGOUT("Issuing a global reset to MAC\n");
623
624 switch (hw->mac_type) {
625 case e1000_82544:
626 case e1000_82540:
627 case e1000_82545:
628 case e1000_82546:
629 case e1000_82541:
630 case e1000_82541_rev_2:
631 /* These controllers can't ack the 64-bit write when issuing the
632 * reset, so use IO-mapping as a workaround to issue the reset */
633 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
634 break;
635 case e1000_82545_rev_3:
636 case e1000_82546_rev_3:
637 /* Reset is performed on a shadow of the control register */
638 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
639 break;
640 case e1000_ich8lan:
641 if (!hw->phy_reset_disable &&
642 e1000_check_phy_reset_block(hw) == E1000_SUCCESS) {
643 /* e1000_ich8lan PHY HW reset requires MAC CORE reset
644 * at the same time to make sure the interface between
645 * MAC and the external PHY is reset.
646 */
647 ctrl |= E1000_CTRL_PHY_RST;
648 }
649
650 e1000_get_software_flag(hw);
651 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
652 msleep(5);
653 break;
654 default:
655 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
656 break;
657 }
658
659 /* After MAC reset, force reload of EEPROM to restore power-on settings to
660 * device. Later controllers reload the EEPROM automatically, so just wait
661 * for reload to complete.
662 */
663 switch (hw->mac_type) {
664 case e1000_82542_rev2_0:
665 case e1000_82542_rev2_1:
666 case e1000_82543:
667 case e1000_82544:
668 /* Wait for reset to complete */
669 udelay(10);
670 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
671 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
672 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
673 E1000_WRITE_FLUSH(hw);
674 /* Wait for EEPROM reload */
675 msleep(2);
676 break;
677 case e1000_82541:
678 case e1000_82541_rev_2:
679 case e1000_82547:
680 case e1000_82547_rev_2:
681 /* Wait for EEPROM reload */
682 msleep(20);
683 break;
684 case e1000_82573:
685 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
686 udelay(10);
687 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
688 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
689 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
690 E1000_WRITE_FLUSH(hw);
691 }
692 /* fall through */
693 default:
694 /* Auto read done will delay 5ms or poll based on mac type */
695 ret_val = e1000_get_auto_rd_done(hw);
696 if (ret_val)
697 return ret_val;
698 break;
699 }
700
701 /* Disable HW ARPs on ASF enabled adapters */
702 if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {
703 manc = E1000_READ_REG(hw, MANC);
704 manc &= ~(E1000_MANC_ARP_EN);
705 E1000_WRITE_REG(hw, MANC, manc);
706 }
707
708 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
709 e1000_phy_init_script(hw);
710
711 /* Configure activity LED after PHY reset */
712 led_ctrl = E1000_READ_REG(hw, LEDCTL);
713 led_ctrl &= IGP_ACTIVITY_LED_MASK;
714 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
715 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
716 }
717
718 /* Clear interrupt mask to stop board from generating interrupts */
719 DEBUGOUT("Masking off all interrupts\n");
720 E1000_WRITE_REG(hw, IMC, 0xffffffff);
721
722 /* Clear any pending interrupt events. */
723 icr = E1000_READ_REG(hw, ICR);
724
725 /* If MWI was previously enabled, reenable it. */
726 if (hw->mac_type == e1000_82542_rev2_0) {
727 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
728 e1000_pci_set_mwi(hw);
729 }
730
731 if (hw->mac_type == e1000_ich8lan) {
732 uint32_t kab = E1000_READ_REG(hw, KABGTXD);
733 kab |= E1000_KABGTXD_BGSQLBIAS;
734 E1000_WRITE_REG(hw, KABGTXD, kab);
735 }
736
737 return E1000_SUCCESS;
738 }
739
740 /******************************************************************************
741 *
742 * Initialize a number of hardware-dependent bits
743 *
744 * hw: Struct containing variables accessed by shared code
745 *
746 * This function contains hardware limitation workarounds for PCI-E adapters
747 *
748 *****************************************************************************/
749 static void
750 e1000_initialize_hardware_bits(struct e1000_hw *hw)
751 {
752 if ((hw->mac_type >= e1000_82571) && (!hw->initialize_hw_bits_disable)) {
753 /* Settings common to all PCI-express silicon */
754 uint32_t reg_ctrl, reg_ctrl_ext;
755 uint32_t reg_tarc0, reg_tarc1;
756 uint32_t reg_tctl;
757 uint32_t reg_txdctl, reg_txdctl1;
758
759 /* link autonegotiation/sync workarounds */
760 reg_tarc0 = E1000_READ_REG(hw, TARC0);
761 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
762
763 /* Enable not-done TX descriptor counting */
764 reg_txdctl = E1000_READ_REG(hw, TXDCTL);
765 reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
766 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
767 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
768 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
769 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
770
771 switch (hw->mac_type) {
772 case e1000_82571:
773 case e1000_82572:
774 /* Clear PHY TX compatible mode bits */
775 reg_tarc1 = E1000_READ_REG(hw, TARC1);
776 reg_tarc1 &= ~((1 << 30)|(1 << 29));
777
778 /* link autonegotiation/sync workarounds */
779 reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
780
781 /* TX ring control fixes */
782 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
783
784 /* Multiple read bit is reversed polarity */
785 reg_tctl = E1000_READ_REG(hw, TCTL);
786 if (reg_tctl & E1000_TCTL_MULR)
787 reg_tarc1 &= ~(1 << 28);
788 else
789 reg_tarc1 |= (1 << 28);
790
791 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
792 break;
793 case e1000_82573:
794 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
795 reg_ctrl_ext &= ~(1 << 23);
796 reg_ctrl_ext |= (1 << 22);
797
798 /* TX byte count fix */
799 reg_ctrl = E1000_READ_REG(hw, CTRL);
800 reg_ctrl &= ~(1 << 29);
801
802 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
803 E1000_WRITE_REG(hw, CTRL, reg_ctrl);
804 break;
805 case e1000_80003es2lan:
806 /* improve small packet performace for fiber/serdes */
807 if ((hw->media_type == e1000_media_type_fiber) ||
808 (hw->media_type == e1000_media_type_internal_serdes)) {
809 reg_tarc0 &= ~(1 << 20);
810 }
811
812 /* Multiple read bit is reversed polarity */
813 reg_tctl = E1000_READ_REG(hw, TCTL);
814 reg_tarc1 = E1000_READ_REG(hw, TARC1);
815 if (reg_tctl & E1000_TCTL_MULR)
816 reg_tarc1 &= ~(1 << 28);
817 else
818 reg_tarc1 |= (1 << 28);
819
820 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
821 break;
822 case e1000_ich8lan:
823 /* Reduce concurrent DMA requests to 3 from 4 */
824 if ((hw->revision_id < 3) ||
825 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
826 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
827 reg_tarc0 |= ((1 << 29)|(1 << 28));
828
829 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
830 reg_ctrl_ext |= (1 << 22);
831 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
832
833 /* workaround TX hang with TSO=on */
834 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
835
836 /* Multiple read bit is reversed polarity */
837 reg_tctl = E1000_READ_REG(hw, TCTL);
838 reg_tarc1 = E1000_READ_REG(hw, TARC1);
839 if (reg_tctl & E1000_TCTL_MULR)
840 reg_tarc1 &= ~(1 << 28);
841 else
842 reg_tarc1 |= (1 << 28);
843
844 /* workaround TX hang with TSO=on */
845 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
846
847 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
848 break;
849 default:
850 break;
851 }
852
853 E1000_WRITE_REG(hw, TARC0, reg_tarc0);
854 }
855 }
856
857 /******************************************************************************
858 * Performs basic configuration of the adapter.
859 *
860 * hw - Struct containing variables accessed by shared code
861 *
862 * Assumes that the controller has previously been reset and is in a
863 * post-reset uninitialized state. Initializes the receive address registers,
864 * multicast table, and VLAN filter table. Calls routines to setup link
865 * configuration and flow control settings. Clears all on-chip counters. Leaves
866 * the transmit and receive units disabled and uninitialized.
867 *****************************************************************************/
868 int32_t
869 e1000_init_hw(struct e1000_hw *hw)
870 {
871 uint32_t ctrl;
872 uint32_t i;
873 int32_t ret_val;
874 uint16_t pcix_cmd_word;
875 uint16_t pcix_stat_hi_word;
876 uint16_t cmd_mmrbc;
877 uint16_t stat_mmrbc;
878 uint32_t mta_size;
879 uint32_t reg_data;
880 uint32_t ctrl_ext;
881
882 DEBUGFUNC("e1000_init_hw");
883
884 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
885 if ((hw->mac_type == e1000_ich8lan) &&
886 ((hw->revision_id < 3) ||
887 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
888 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
889 reg_data = E1000_READ_REG(hw, STATUS);
890 reg_data &= ~0x80000000;
891 E1000_WRITE_REG(hw, STATUS, reg_data);
892 }
893
894 /* Initialize Identification LED */
895 ret_val = e1000_id_led_init(hw);
896 if (ret_val) {
897 DEBUGOUT("Error Initializing Identification LED\n");
898 return ret_val;
899 }
900
901 /* Set the media type and TBI compatibility */
902 e1000_set_media_type(hw);
903
904 /* Must be called after e1000_set_media_type because media_type is used */
905 e1000_initialize_hardware_bits(hw);
906
907 /* Disabling VLAN filtering. */
908 DEBUGOUT("Initializing the IEEE VLAN\n");
909 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
910 if (hw->mac_type != e1000_ich8lan) {
911 if (hw->mac_type < e1000_82545_rev_3)
912 E1000_WRITE_REG(hw, VET, 0);
913 e1000_clear_vfta(hw);
914 }
915
916 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
917 if (hw->mac_type == e1000_82542_rev2_0) {
918 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
919 e1000_pci_clear_mwi(hw);
920 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
921 E1000_WRITE_FLUSH(hw);
922 msleep(5);
923 }
924
925 /* Setup the receive address. This involves initializing all of the Receive
926 * Address Registers (RARs 0 - 15).
927 */
928 e1000_init_rx_addrs(hw);
929
930 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
931 if (hw->mac_type == e1000_82542_rev2_0) {
932 E1000_WRITE_REG(hw, RCTL, 0);
933 E1000_WRITE_FLUSH(hw);
934 msleep(1);
935 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
936 e1000_pci_set_mwi(hw);
937 }
938
939 /* Zero out the Multicast HASH table */
940 DEBUGOUT("Zeroing the MTA\n");
941 mta_size = E1000_MC_TBL_SIZE;
942 if (hw->mac_type == e1000_ich8lan)
943 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
944 for (i = 0; i < mta_size; i++) {
945 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
946 /* use write flush to prevent Memory Write Block (MWB) from
947 * occuring when accessing our register space */
948 E1000_WRITE_FLUSH(hw);
949 }
950
951 /* Set the PCI priority bit correctly in the CTRL register. This
952 * determines if the adapter gives priority to receives, or if it
953 * gives equal priority to transmits and receives. Valid only on
954 * 82542 and 82543 silicon.
955 */
956 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
957 ctrl = E1000_READ_REG(hw, CTRL);
958 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
959 }
960
961 switch (hw->mac_type) {
962 case e1000_82545_rev_3:
963 case e1000_82546_rev_3:
964 break;
965 default:
966 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
967 if (hw->bus_type == e1000_bus_type_pcix) {
968 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
969 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
970 &pcix_stat_hi_word);
971 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
972 PCIX_COMMAND_MMRBC_SHIFT;
973 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
974 PCIX_STATUS_HI_MMRBC_SHIFT;
975 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
976 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
977 if (cmd_mmrbc > stat_mmrbc) {
978 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
979 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
980 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
981 &pcix_cmd_word);
982 }
983 }
984 break;
985 }
986
987 /* More time needed for PHY to initialize */
988 if (hw->mac_type == e1000_ich8lan)
989 msleep(15);
990
991 /* Call a subroutine to configure the link and setup flow control. */
992 ret_val = e1000_setup_link(hw);
993
994 /* Set the transmit descriptor write-back policy */
995 if (hw->mac_type > e1000_82544) {
996 ctrl = E1000_READ_REG(hw, TXDCTL);
997 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
998 E1000_WRITE_REG(hw, TXDCTL, ctrl);
999 }
1000
1001 if (hw->mac_type == e1000_82573) {
1002 e1000_enable_tx_pkt_filtering(hw);
1003 }
1004
1005 switch (hw->mac_type) {
1006 default:
1007 break;
1008 case e1000_80003es2lan:
1009 /* Enable retransmit on late collisions */
1010 reg_data = E1000_READ_REG(hw, TCTL);
1011 reg_data |= E1000_TCTL_RTLC;
1012 E1000_WRITE_REG(hw, TCTL, reg_data);
1013
1014 /* Configure Gigabit Carry Extend Padding */
1015 reg_data = E1000_READ_REG(hw, TCTL_EXT);
1016 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
1017 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
1018 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
1019
1020 /* Configure Transmit Inter-Packet Gap */
1021 reg_data = E1000_READ_REG(hw, TIPG);
1022 reg_data &= ~E1000_TIPG_IPGT_MASK;
1023 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1024 E1000_WRITE_REG(hw, TIPG, reg_data);
1025
1026 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
1027 reg_data &= ~0x00100000;
1028 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
1029 /* Fall through */
1030 case e1000_82571:
1031 case e1000_82572:
1032 case e1000_ich8lan:
1033 ctrl = E1000_READ_REG(hw, TXDCTL1);
1034 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
1035 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
1036 break;
1037 }
1038
1039
1040 if (hw->mac_type == e1000_82573) {
1041 uint32_t gcr = E1000_READ_REG(hw, GCR);
1042 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1043 E1000_WRITE_REG(hw, GCR, gcr);
1044 }
1045
1046 /* Clear all of the statistics registers (clear on read). It is
1047 * important that we do this after we have tried to establish link
1048 * because the symbol error count will increment wildly if there
1049 * is no link.
1050 */
1051 e1000_clear_hw_cntrs(hw);
1052
1053 /* ICH8 No-snoop bits are opposite polarity.
1054 * Set to snoop by default after reset. */
1055 if (hw->mac_type == e1000_ich8lan)
1056 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
1057
1058 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
1059 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1060 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1061 /* Relaxed ordering must be disabled to avoid a parity
1062 * error crash in a PCI slot. */
1063 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1064 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1065 }
1066
1067 return ret_val;
1068 }
1069
1070 /******************************************************************************
1071 * Adjust SERDES output amplitude based on EEPROM setting.
1072 *
1073 * hw - Struct containing variables accessed by shared code.
1074 *****************************************************************************/
1075 static int32_t
1076 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
1077 {
1078 uint16_t eeprom_data;
1079 int32_t ret_val;
1080
1081 DEBUGFUNC("e1000_adjust_serdes_amplitude");
1082
1083 if (hw->media_type != e1000_media_type_internal_serdes)
1084 return E1000_SUCCESS;
1085
1086 switch (hw->mac_type) {
1087 case e1000_82545_rev_3:
1088 case e1000_82546_rev_3:
1089 break;
1090 default:
1091 return E1000_SUCCESS;
1092 }
1093
1094 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);
1095 if (ret_val) {
1096 return ret_val;
1097 }
1098
1099 if (eeprom_data != EEPROM_RESERVED_WORD) {
1100 /* Adjust SERDES output amplitude only. */
1101 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
1102 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
1103 if (ret_val)
1104 return ret_val;
1105 }
1106
1107 return E1000_SUCCESS;
1108 }
1109
1110 /******************************************************************************
1111 * Configures flow control and link settings.
1112 *
1113 * hw - Struct containing variables accessed by shared code
1114 *
1115 * Determines which flow control settings to use. Calls the apropriate media-
1116 * specific link configuration function. Configures the flow control settings.
1117 * Assuming the adapter has a valid link partner, a valid link should be
1118 * established. Assumes the hardware has previously been reset and the
1119 * transmitter and receiver are not enabled.
1120 *****************************************************************************/
1121 int32_t
1122 e1000_setup_link(struct e1000_hw *hw)
1123 {
1124 uint32_t ctrl_ext;
1125 int32_t ret_val;
1126 uint16_t eeprom_data;
1127
1128 DEBUGFUNC("e1000_setup_link");
1129
1130 /* In the case of the phy reset being blocked, we already have a link.
1131 * We do not have to set it up again. */
1132 if (e1000_check_phy_reset_block(hw))
1133 return E1000_SUCCESS;
1134
1135 /* Read and store word 0x0F of the EEPROM. This word contains bits
1136 * that determine the hardware's default PAUSE (flow control) mode,
1137 * a bit that determines whether the HW defaults to enabling or
1138 * disabling auto-negotiation, and the direction of the
1139 * SW defined pins. If there is no SW over-ride of the flow
1140 * control setting, then the variable hw->fc will
1141 * be initialized based on a value in the EEPROM.
1142 */
1143 if (hw->fc == E1000_FC_DEFAULT) {
1144 switch (hw->mac_type) {
1145 case e1000_ich8lan:
1146 case e1000_82573:
1147 hw->fc = E1000_FC_FULL;
1148 break;
1149 default:
1150 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1151 1, &eeprom_data);
1152 if (ret_val) {
1153 DEBUGOUT("EEPROM Read Error\n");
1154 return -E1000_ERR_EEPROM;
1155 }
1156 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1157 hw->fc = E1000_FC_NONE;
1158 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1159 EEPROM_WORD0F_ASM_DIR)
1160 hw->fc = E1000_FC_TX_PAUSE;
1161 else
1162 hw->fc = E1000_FC_FULL;
1163 break;
1164 }
1165 }
1166
1167 /* We want to save off the original Flow Control configuration just
1168 * in case we get disconnected and then reconnected into a different
1169 * hub or switch with different Flow Control capabilities.
1170 */
1171 if (hw->mac_type == e1000_82542_rev2_0)
1172 hw->fc &= (~E1000_FC_TX_PAUSE);
1173
1174 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1175 hw->fc &= (~E1000_FC_RX_PAUSE);
1176
1177 hw->original_fc = hw->fc;
1178
1179 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
1180
1181 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
1182 * polarity value for the SW controlled pins, and setup the
1183 * Extended Device Control reg with that info.
1184 * This is needed because one of the SW controlled pins is used for
1185 * signal detection. So this should be done before e1000_setup_pcs_link()
1186 * or e1000_phy_setup() is called.
1187 */
1188 if (hw->mac_type == e1000_82543) {
1189 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1190 1, &eeprom_data);
1191 if (ret_val) {
1192 DEBUGOUT("EEPROM Read Error\n");
1193 return -E1000_ERR_EEPROM;
1194 }
1195 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1196 SWDPIO__EXT_SHIFT);
1197 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1198 }
1199
1200 /* Call the necessary subroutine to configure the link. */
1201 ret_val = (hw->media_type == e1000_media_type_copper) ?
1202 e1000_setup_copper_link(hw) :
1203 e1000_setup_fiber_serdes_link(hw);
1204
1205 /* Initialize the flow control address, type, and PAUSE timer
1206 * registers to their default values. This is done even if flow
1207 * control is disabled, because it does not hurt anything to
1208 * initialize these registers.
1209 */
1210 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1211
1212 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
1213 if (hw->mac_type != e1000_ich8lan) {
1214 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1215 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1216 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1217 }
1218
1219 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1220
1221 /* Set the flow control receive threshold registers. Normally,
1222 * these registers will be set to a default threshold that may be
1223 * adjusted later by the driver's runtime code. However, if the
1224 * ability to transmit pause frames in not enabled, then these
1225 * registers will be set to 0.
1226 */
1227 if (!(hw->fc & E1000_FC_TX_PAUSE)) {
1228 E1000_WRITE_REG(hw, FCRTL, 0);
1229 E1000_WRITE_REG(hw, FCRTH, 0);
1230 } else {
1231 /* We need to set up the Receive Threshold high and low water marks
1232 * as well as (optionally) enabling the transmission of XON frames.
1233 */
1234 if (hw->fc_send_xon) {
1235 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
1236 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1237 } else {
1238 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
1239 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1240 }
1241 }
1242 return ret_val;
1243 }
1244
1245 /******************************************************************************
1246 * Sets up link for a fiber based or serdes based adapter
1247 *
1248 * hw - Struct containing variables accessed by shared code
1249 *
1250 * Manipulates Physical Coding Sublayer functions in order to configure
1251 * link. Assumes the hardware has been previously reset and the transmitter
1252 * and receiver are not enabled.
1253 *****************************************************************************/
1254 static int32_t
1255 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1256 {
1257 uint32_t ctrl;
1258 uint32_t status;
1259 uint32_t txcw = 0;
1260 uint32_t i;
1261 uint32_t signal = 0;
1262 int32_t ret_val;
1263
1264 DEBUGFUNC("e1000_setup_fiber_serdes_link");
1265
1266 /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists
1267 * until explicitly turned off or a power cycle is performed. A read to
1268 * the register does not indicate its status. Therefore, we ensure
1269 * loopback mode is disabled during initialization.
1270 */
1271 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572)
1272 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK);
1273
1274 /* On adapters with a MAC newer than 82544, SWDP 1 will be
1275 * set when the optics detect a signal. On older adapters, it will be
1276 * cleared when there is a signal. This applies to fiber media only.
1277 * If we're on serdes media, adjust the output amplitude to value
1278 * set in the EEPROM.
1279 */
1280 ctrl = E1000_READ_REG(hw, CTRL);
1281 if (hw->media_type == e1000_media_type_fiber)
1282 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
1283
1284 ret_val = e1000_adjust_serdes_amplitude(hw);
1285 if (ret_val)
1286 return ret_val;
1287
1288 /* Take the link out of reset */
1289 ctrl &= ~(E1000_CTRL_LRST);
1290
1291 /* Adjust VCO speed to improve BER performance */
1292 ret_val = e1000_set_vco_speed(hw);
1293 if (ret_val)
1294 return ret_val;
1295
1296 e1000_config_collision_dist(hw);
1297
1298 /* Check for a software override of the flow control settings, and setup
1299 * the device accordingly. If auto-negotiation is enabled, then software
1300 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
1301 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
1302 * auto-negotiation is disabled, then software will have to manually
1303 * configure the two flow control enable bits in the CTRL register.
1304 *
1305 * The possible values of the "fc" parameter are:
1306 * 0: Flow control is completely disabled
1307 * 1: Rx flow control is enabled (we can receive pause frames, but
1308 * not send pause frames).
1309 * 2: Tx flow control is enabled (we can send pause frames but we do
1310 * not support receiving pause frames).
1311 * 3: Both Rx and TX flow control (symmetric) are enabled.
1312 */
1313 switch (hw->fc) {
1314 case E1000_FC_NONE:
1315 /* Flow control is completely disabled by a software over-ride. */
1316 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1317 break;
1318 case E1000_FC_RX_PAUSE:
1319 /* RX Flow control is enabled and TX Flow control is disabled by a
1320 * software over-ride. Since there really isn't a way to advertise
1321 * that we are capable of RX Pause ONLY, we will advertise that we
1322 * support both symmetric and asymmetric RX PAUSE. Later, we will
1323 * disable the adapter's ability to send PAUSE frames.
1324 */
1325 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1326 break;
1327 case E1000_FC_TX_PAUSE:
1328 /* TX Flow control is enabled, and RX Flow control is disabled, by a
1329 * software over-ride.
1330 */
1331 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1332 break;
1333 case E1000_FC_FULL:
1334 /* Flow control (both RX and TX) is enabled by a software over-ride. */
1335 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1336 break;
1337 default:
1338 DEBUGOUT("Flow control param set incorrectly\n");
1339 return -E1000_ERR_CONFIG;
1340 break;
1341 }
1342
1343 /* Since auto-negotiation is enabled, take the link out of reset (the link
1344 * will be in reset, because we previously reset the chip). This will
1345 * restart auto-negotiation. If auto-neogtiation is successful then the
1346 * link-up status bit will be set and the flow control enable bits (RFCE
1347 * and TFCE) will be set according to their negotiated value.
1348 */
1349 DEBUGOUT("Auto-negotiation enabled\n");
1350
1351 E1000_WRITE_REG(hw, TXCW, txcw);
1352 E1000_WRITE_REG(hw, CTRL, ctrl);
1353 E1000_WRITE_FLUSH(hw);
1354
1355 hw->txcw = txcw;
1356 msleep(1);
1357
1358 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
1359 * indication in the Device Status Register. Time-out if a link isn't
1360 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
1361 * less than 500 milliseconds even if the other end is doing it in SW).
1362 * For internal serdes, we just assume a signal is present, then poll.
1363 */
1364 if (hw->media_type == e1000_media_type_internal_serdes ||
1365 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1366 DEBUGOUT("Looking for Link\n");
1367 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
1368 msleep(10);
1369 status = E1000_READ_REG(hw, STATUS);
1370 if (status & E1000_STATUS_LU) break;
1371 }
1372 if (i == (LINK_UP_TIMEOUT / 10)) {
1373 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1374 hw->autoneg_failed = 1;
1375 /* AutoNeg failed to achieve a link, so we'll call
1376 * e1000_check_for_link. This routine will force the link up if
1377 * we detect a signal. This will allow us to communicate with
1378 * non-autonegotiating link partners.
1379 */
1380 ret_val = e1000_check_for_link(hw);
1381 if (ret_val) {
1382 DEBUGOUT("Error while checking for link\n");
1383 return ret_val;
1384 }
1385 hw->autoneg_failed = 0;
1386 } else {
1387 hw->autoneg_failed = 0;
1388 DEBUGOUT("Valid Link Found\n");
1389 }
1390 } else {
1391 DEBUGOUT("No Signal Detected\n");
1392 }
1393 return E1000_SUCCESS;
1394 }
1395
1396 /******************************************************************************
1397 * Make sure we have a valid PHY and change PHY mode before link setup.
1398 *
1399 * hw - Struct containing variables accessed by shared code
1400 ******************************************************************************/
1401 static int32_t
1402 e1000_copper_link_preconfig(struct e1000_hw *hw)
1403 {
1404 uint32_t ctrl;
1405 int32_t ret_val;
1406 uint16_t phy_data;
1407
1408 DEBUGFUNC("e1000_copper_link_preconfig");
1409
1410 ctrl = E1000_READ_REG(hw, CTRL);
1411 /* With 82543, we need to force speed and duplex on the MAC equal to what
1412 * the PHY speed and duplex configuration is. In addition, we need to
1413 * perform a hardware reset on the PHY to take it out of reset.
1414 */
1415 if (hw->mac_type > e1000_82543) {
1416 ctrl |= E1000_CTRL_SLU;
1417 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1418 E1000_WRITE_REG(hw, CTRL, ctrl);
1419 } else {
1420 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1421 E1000_WRITE_REG(hw, CTRL, ctrl);
1422 ret_val = e1000_phy_hw_reset(hw);
1423 if (ret_val)
1424 return ret_val;
1425 }
1426
1427 /* Make sure we have a valid PHY */
1428 ret_val = e1000_detect_gig_phy(hw);
1429 if (ret_val) {
1430 DEBUGOUT("Error, did not detect valid phy.\n");
1431 return ret_val;
1432 }
1433 DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
1434
1435 /* Set PHY to class A mode (if necessary) */
1436 ret_val = e1000_set_phy_mode(hw);
1437 if (ret_val)
1438 return ret_val;
1439
1440 if ((hw->mac_type == e1000_82545_rev_3) ||
1441 (hw->mac_type == e1000_82546_rev_3)) {
1442 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1443 phy_data |= 0x00000008;
1444 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1445 }
1446
1447 if (hw->mac_type <= e1000_82543 ||
1448 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1449 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
1450 hw->phy_reset_disable = FALSE;
1451
1452 return E1000_SUCCESS;
1453 }
1454
1455
1456 /********************************************************************
1457 * Copper link setup for e1000_phy_igp series.
1458 *
1459 * hw - Struct containing variables accessed by shared code
1460 *********************************************************************/
1461 static int32_t
1462 e1000_copper_link_igp_setup(struct e1000_hw *hw)
1463 {
1464 uint32_t led_ctrl;
1465 int32_t ret_val;
1466 uint16_t phy_data;
1467
1468 DEBUGFUNC("e1000_copper_link_igp_setup");
1469
1470 if (hw->phy_reset_disable)
1471 return E1000_SUCCESS;
1472
1473 ret_val = e1000_phy_reset(hw);
1474 if (ret_val) {
1475 DEBUGOUT("Error Resetting the PHY\n");
1476 return ret_val;
1477 }
1478
1479 /* Wait 15ms for MAC to configure PHY from eeprom settings */
1480 msleep(15);
1481 if (hw->mac_type != e1000_ich8lan) {
1482 /* Configure activity LED after PHY reset */
1483 led_ctrl = E1000_READ_REG(hw, LEDCTL);
1484 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1485 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1486 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
1487 }
1488
1489 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
1490 if (hw->phy_type == e1000_phy_igp) {
1491 /* disable lplu d3 during driver init */
1492 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
1493 if (ret_val) {
1494 DEBUGOUT("Error Disabling LPLU D3\n");
1495 return ret_val;
1496 }
1497 }
1498
1499 /* disable lplu d0 during driver init */
1500 ret_val = e1000_set_d0_lplu_state(hw, FALSE);
1501 if (ret_val) {
1502 DEBUGOUT("Error Disabling LPLU D0\n");
1503 return ret_val;
1504 }
1505 /* Configure mdi-mdix settings */
1506 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1507 if (ret_val)
1508 return ret_val;
1509
1510 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1511 hw->dsp_config_state = e1000_dsp_config_disabled;
1512 /* Force MDI for earlier revs of the IGP PHY */
1513 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX);
1514 hw->mdix = 1;
1515
1516 } else {
1517 hw->dsp_config_state = e1000_dsp_config_enabled;
1518 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1519
1520 switch (hw->mdix) {
1521 case 1:
1522 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1523 break;
1524 case 2:
1525 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1526 break;
1527 case 0:
1528 default:
1529 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1530 break;
1531 }
1532 }
1533 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1534 if (ret_val)
1535 return ret_val;
1536
1537 /* set auto-master slave resolution settings */
1538 if (hw->autoneg) {
1539 e1000_ms_type phy_ms_setting = hw->master_slave;
1540
1541 if (hw->ffe_config_state == e1000_ffe_config_active)
1542 hw->ffe_config_state = e1000_ffe_config_enabled;
1543
1544 if (hw->dsp_config_state == e1000_dsp_config_activated)
1545 hw->dsp_config_state = e1000_dsp_config_enabled;
1546
1547 /* when autonegotiation advertisment is only 1000Mbps then we
1548 * should disable SmartSpeed and enable Auto MasterSlave
1549 * resolution as hardware default. */
1550 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1551 /* Disable SmartSpeed */
1552 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1553 &phy_data);
1554 if (ret_val)
1555 return ret_val;
1556 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1557 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1558 phy_data);
1559 if (ret_val)
1560 return ret_val;
1561 /* Set auto Master/Slave resolution process */
1562 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1563 if (ret_val)
1564 return ret_val;
1565 phy_data &= ~CR_1000T_MS_ENABLE;
1566 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1567 if (ret_val)
1568 return ret_val;
1569 }
1570
1571 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1572 if (ret_val)
1573 return ret_val;
1574
1575 /* load defaults for future use */
1576 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1577 ((phy_data & CR_1000T_MS_VALUE) ?
1578 e1000_ms_force_master :
1579 e1000_ms_force_slave) :
1580 e1000_ms_auto;
1581
1582 switch (phy_ms_setting) {
1583 case e1000_ms_force_master:
1584 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1585 break;
1586 case e1000_ms_force_slave:
1587 phy_data |= CR_1000T_MS_ENABLE;
1588 phy_data &= ~(CR_1000T_MS_VALUE);
1589 break;
1590 case e1000_ms_auto:
1591 phy_data &= ~CR_1000T_MS_ENABLE;
1592 default:
1593 break;
1594 }
1595 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1596 if (ret_val)
1597 return ret_val;
1598 }
1599
1600 return E1000_SUCCESS;
1601 }
1602
1603 /********************************************************************
1604 * Copper link setup for e1000_phy_gg82563 series.
1605 *
1606 * hw - Struct containing variables accessed by shared code
1607 *********************************************************************/
1608 static int32_t
1609 e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1610 {
1611 int32_t ret_val;
1612 uint16_t phy_data;
1613 uint32_t reg_data;
1614
1615 DEBUGFUNC("e1000_copper_link_ggp_setup");
1616
1617 if (!hw->phy_reset_disable) {
1618
1619 /* Enable CRS on TX for half-duplex operation. */
1620 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1621 &phy_data);
1622 if (ret_val)
1623 return ret_val;
1624
1625 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
1626 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
1627 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
1628
1629 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1630 phy_data);
1631 if (ret_val)
1632 return ret_val;
1633
1634 /* Options:
1635 * MDI/MDI-X = 0 (default)
1636 * 0 - Auto for all speeds
1637 * 1 - MDI mode
1638 * 2 - MDI-X mode
1639 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1640 */
1641 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data);
1642 if (ret_val)
1643 return ret_val;
1644
1645 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
1646
1647 switch (hw->mdix) {
1648 case 1:
1649 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
1650 break;
1651 case 2:
1652 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1653 break;
1654 case 0:
1655 default:
1656 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1657 break;
1658 }
1659
1660 /* Options:
1661 * disable_polarity_correction = 0 (default)
1662 * Automatic Correction for Reversed Cable Polarity
1663 * 0 - Disabled
1664 * 1 - Enabled
1665 */
1666 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1667 if (hw->disable_polarity_correction == 1)
1668 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1669 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
1670
1671 if (ret_val)
1672 return ret_val;
1673
1674 /* SW Reset the PHY so all changes take effect */
1675 ret_val = e1000_phy_reset(hw);
1676 if (ret_val) {
1677 DEBUGOUT("Error Resetting the PHY\n");
1678 return ret_val;
1679 }
1680 } /* phy_reset_disable */
1681
1682 if (hw->mac_type == e1000_80003es2lan) {
1683 /* Bypass RX and TX FIFO's */
1684 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
1685 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS |
1686 E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
1687 if (ret_val)
1688 return ret_val;
1689
1690 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data);
1691 if (ret_val)
1692 return ret_val;
1693
1694 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1695 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data);
1696
1697 if (ret_val)
1698 return ret_val;
1699
1700 reg_data = E1000_READ_REG(hw, CTRL_EXT);
1701 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1702 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
1703
1704 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1705 &phy_data);
1706 if (ret_val)
1707 return ret_val;
1708
1709 /* Do not init these registers when the HW is in IAMT mode, since the
1710 * firmware will have already initialized them. We only initialize
1711 * them if the HW is not in IAMT mode.
1712 */
1713 if (e1000_check_mng_mode(hw) == FALSE) {
1714 /* Enable Electrical Idle on the PHY */
1715 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1716 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1717 phy_data);
1718 if (ret_val)
1719 return ret_val;
1720
1721 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1722 &phy_data);
1723 if (ret_val)
1724 return ret_val;
1725
1726 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1727 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1728 phy_data);
1729
1730 if (ret_val)
1731 return ret_val;
1732 }
1733
1734 /* Workaround: Disable padding in Kumeran interface in the MAC
1735 * and in the PHY to avoid CRC errors.
1736 */
1737 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1738 &phy_data);
1739 if (ret_val)
1740 return ret_val;
1741 phy_data |= GG82563_ICR_DIS_PADDING;
1742 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1743 phy_data);
1744 if (ret_val)
1745 return ret_val;
1746 }
1747
1748 return E1000_SUCCESS;
1749 }
1750
1751 /********************************************************************
1752 * Copper link setup for e1000_phy_m88 series.
1753 *
1754 * hw - Struct containing variables accessed by shared code
1755 *********************************************************************/
1756 static int32_t
1757 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1758 {
1759 int32_t ret_val;
1760 uint16_t phy_data;
1761
1762 DEBUGFUNC("e1000_copper_link_mgp_setup");
1763
1764 if (hw->phy_reset_disable)
1765 return E1000_SUCCESS;
1766
1767 /* Enable CRS on TX. This must be set for half-duplex operation. */
1768 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1769 if (ret_val)
1770 return ret_val;
1771
1772 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1773
1774 /* Options:
1775 * MDI/MDI-X = 0 (default)
1776 * 0 - Auto for all speeds
1777 * 1 - MDI mode
1778 * 2 - MDI-X mode
1779 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1780 */
1781 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1782
1783 switch (hw->mdix) {
1784 case 1:
1785 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1786 break;
1787 case 2:
1788 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1789 break;
1790 case 3:
1791 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1792 break;
1793 case 0:
1794 default:
1795 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1796 break;
1797 }
1798
1799 /* Options:
1800 * disable_polarity_correction = 0 (default)
1801 * Automatic Correction for Reversed Cable Polarity
1802 * 0 - Disabled
1803 * 1 - Enabled
1804 */
1805 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1806 if (hw->disable_polarity_correction == 1)
1807 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1808 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1809 if (ret_val)
1810 return ret_val;
1811
1812 if (hw->phy_revision < M88E1011_I_REV_4) {
1813 /* Force TX_CLK in the Extended PHY Specific Control Register
1814 * to 25MHz clock.
1815 */
1816 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1817 if (ret_val)
1818 return ret_val;
1819
1820 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1821
1822 if ((hw->phy_revision == E1000_REVISION_2) &&
1823 (hw->phy_id == M88E1111_I_PHY_ID)) {
1824 /* Vidalia Phy, set the downshift counter to 5x */
1825 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
1826 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1827 ret_val = e1000_write_phy_reg(hw,
1828 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1829 if (ret_val)
1830 return ret_val;
1831 } else {
1832 /* Configure Master and Slave downshift values */
1833 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1834 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1835 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1836 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1837 ret_val = e1000_write_phy_reg(hw,
1838 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1839 if (ret_val)
1840 return ret_val;
1841 }
1842 }
1843
1844 /* SW Reset the PHY so all changes take effect */
1845 ret_val = e1000_phy_reset(hw);
1846 if (ret_val) {
1847 DEBUGOUT("Error Resetting the PHY\n");
1848 return ret_val;
1849 }
1850
1851 return E1000_SUCCESS;
1852 }
1853
1854 /********************************************************************
1855 * Setup auto-negotiation and flow control advertisements,
1856 * and then perform auto-negotiation.
1857 *
1858 * hw - Struct containing variables accessed by shared code
1859 *********************************************************************/
1860 static int32_t
1861 e1000_copper_link_autoneg(struct e1000_hw *hw)
1862 {
1863 int32_t ret_val;
1864 uint16_t phy_data;
1865
1866 DEBUGFUNC("e1000_copper_link_autoneg");
1867
1868 /* Perform some bounds checking on the hw->autoneg_advertised
1869 * parameter. If this variable is zero, then set it to the default.
1870 */
1871 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1872
1873 /* If autoneg_advertised is zero, we assume it was not defaulted
1874 * by the calling code so we set to advertise full capability.
1875 */
1876 if (hw->autoneg_advertised == 0)
1877 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1878
1879 /* IFE phy only supports 10/100 */
1880 if (hw->phy_type == e1000_phy_ife)
1881 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
1882
1883 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1884 ret_val = e1000_phy_setup_autoneg(hw);
1885 if (ret_val) {
1886 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1887 return ret_val;
1888 }
1889 DEBUGOUT("Restarting Auto-Neg\n");
1890
1891 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1892 * the Auto Neg Restart bit in the PHY control register.
1893 */
1894 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1895 if (ret_val)
1896 return ret_val;
1897
1898 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1899 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1900 if (ret_val)
1901 return ret_val;
1902
1903 /* Does the user want to wait for Auto-Neg to complete here, or
1904 * check at a later time (for example, callback routine).
1905 */
1906 if (hw->wait_autoneg_complete) {
1907 ret_val = e1000_wait_autoneg(hw);
1908 if (ret_val) {
1909 DEBUGOUT("Error while waiting for autoneg to complete\n");
1910 return ret_val;
1911 }
1912 }
1913
1914 hw->get_link_status = TRUE;
1915
1916 return E1000_SUCCESS;
1917 }
1918
1919 /******************************************************************************
1920 * Config the MAC and the PHY after link is up.
1921 * 1) Set up the MAC to the current PHY speed/duplex
1922 * if we are on 82543. If we
1923 * are on newer silicon, we only need to configure
1924 * collision distance in the Transmit Control Register.
1925 * 2) Set up flow control on the MAC to that established with
1926 * the link partner.
1927 * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
1928 *
1929 * hw - Struct containing variables accessed by shared code
1930 ******************************************************************************/
1931 static int32_t
1932 e1000_copper_link_postconfig(struct e1000_hw *hw)
1933 {
1934 int32_t ret_val;
1935 DEBUGFUNC("e1000_copper_link_postconfig");
1936
1937 if (hw->mac_type >= e1000_82544) {
1938 e1000_config_collision_dist(hw);
1939 } else {
1940 ret_val = e1000_config_mac_to_phy(hw);
1941 if (ret_val) {
1942 DEBUGOUT("Error configuring MAC to PHY settings\n");
1943 return ret_val;
1944 }
1945 }
1946 ret_val = e1000_config_fc_after_link_up(hw);
1947 if (ret_val) {
1948 DEBUGOUT("Error Configuring Flow Control\n");
1949 return ret_val;
1950 }
1951
1952 /* Config DSP to improve Giga link quality */
1953 if (hw->phy_type == e1000_phy_igp) {
1954 ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
1955 if (ret_val) {
1956 DEBUGOUT("Error Configuring DSP after link up\n");
1957 return ret_val;
1958 }
1959 }
1960
1961 return E1000_SUCCESS;
1962 }
1963
1964 /******************************************************************************
1965 * Detects which PHY is present and setup the speed and duplex
1966 *
1967 * hw - Struct containing variables accessed by shared code
1968 ******************************************************************************/
1969 static int32_t
1970 e1000_setup_copper_link(struct e1000_hw *hw)
1971 {
1972 int32_t ret_val;
1973 uint16_t i;
1974 uint16_t phy_data;
1975 uint16_t reg_data;
1976
1977 DEBUGFUNC("e1000_setup_copper_link");
1978
1979 switch (hw->mac_type) {
1980 case e1000_80003es2lan:
1981 case e1000_ich8lan:
1982 /* Set the mac to wait the maximum time between each
1983 * iteration and increase the max iterations when
1984 * polling the phy; this fixes erroneous timeouts at 10Mbps. */
1985 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
1986 if (ret_val)
1987 return ret_val;
1988 ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
1989 if (ret_val)
1990 return ret_val;
1991 reg_data |= 0x3F;
1992 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
1993 if (ret_val)
1994 return ret_val;
1995 default:
1996 break;
1997 }
1998
1999 /* Check if it is a valid PHY and set PHY mode if necessary. */
2000 ret_val = e1000_copper_link_preconfig(hw);
2001 if (ret_val)
2002 return ret_val;
2003
2004 switch (hw->mac_type) {
2005 case e1000_80003es2lan:
2006 /* Kumeran registers are written-only */
2007 reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
2008 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
2009 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
2010 reg_data);
2011 if (ret_val)
2012 return ret_val;
2013 break;
2014 default:
2015 break;
2016 }
2017
2018 if (hw->phy_type == e1000_phy_igp ||
2019 hw->phy_type == e1000_phy_igp_3 ||
2020 hw->phy_type == e1000_phy_igp_2) {
2021 ret_val = e1000_copper_link_igp_setup(hw);
2022 if (ret_val)
2023 return ret_val;
2024 } else if (hw->phy_type == e1000_phy_m88) {
2025 ret_val = e1000_copper_link_mgp_setup(hw);
2026 if (ret_val)
2027 return ret_val;
2028 } else if (hw->phy_type == e1000_phy_gg82563) {
2029 ret_val = e1000_copper_link_ggp_setup(hw);
2030 if (ret_val)
2031 return ret_val;
2032 }
2033
2034 if (hw->autoneg) {
2035 /* Setup autoneg and flow control advertisement
2036 * and perform autonegotiation */
2037 ret_val = e1000_copper_link_autoneg(hw);
2038 if (ret_val)
2039 return ret_val;
2040 } else {
2041 /* PHY will be set to 10H, 10F, 100H,or 100F
2042 * depending on value from forced_speed_duplex. */
2043 DEBUGOUT("Forcing speed and duplex\n");
2044 ret_val = e1000_phy_force_speed_duplex(hw);
2045 if (ret_val) {
2046 DEBUGOUT("Error Forcing Speed and Duplex\n");
2047 return ret_val;
2048 }
2049 }
2050
2051 /* Check link status. Wait up to 100 microseconds for link to become
2052 * valid.
2053 */
2054 for (i = 0; i < 10; i++) {
2055 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2056 if (ret_val)
2057 return ret_val;
2058 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2059 if (ret_val)
2060 return ret_val;
2061
2062 if (phy_data & MII_SR_LINK_STATUS) {
2063 /* Config the MAC and PHY after link is up */
2064 ret_val = e1000_copper_link_postconfig(hw);
2065 if (ret_val)
2066 return ret_val;
2067
2068 DEBUGOUT("Valid link established!!!\n");
2069 return E1000_SUCCESS;
2070 }
2071 udelay(10);
2072 }
2073
2074 DEBUGOUT("Unable to establish link!!!\n");
2075 return E1000_SUCCESS;
2076 }
2077
2078 /******************************************************************************
2079 * Configure the MAC-to-PHY interface for 10/100Mbps
2080 *
2081 * hw - Struct containing variables accessed by shared code
2082 ******************************************************************************/
2083 static int32_t
2084 e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
2085 {
2086 int32_t ret_val = E1000_SUCCESS;
2087 uint32_t tipg;
2088 uint16_t reg_data;
2089
2090 DEBUGFUNC("e1000_configure_kmrn_for_10_100");
2091
2092 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
2093 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
2094 reg_data);
2095 if (ret_val)
2096 return ret_val;
2097
2098 /* Configure Transmit Inter-Packet Gap */
2099 tipg = E1000_READ_REG(hw, TIPG);
2100 tipg &= ~E1000_TIPG_IPGT_MASK;
2101 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
2102 E1000_WRITE_REG(hw, TIPG, tipg);
2103
2104 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
2105
2106 if (ret_val)
2107 return ret_val;
2108
2109 if (duplex == HALF_DUPLEX)
2110 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
2111 else
2112 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2113
2114 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
2115
2116 return ret_val;
2117 }
2118
2119 static int32_t
2120 e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
2121 {
2122 int32_t ret_val = E1000_SUCCESS;
2123 uint16_t reg_data;
2124 uint32_t tipg;
2125
2126 DEBUGFUNC("e1000_configure_kmrn_for_1000");
2127
2128 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
2129 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
2130 reg_data);
2131 if (ret_val)
2132 return ret_val;
2133
2134 /* Configure Transmit Inter-Packet Gap */
2135 tipg = E1000_READ_REG(hw, TIPG);
2136 tipg &= ~E1000_TIPG_IPGT_MASK;
2137 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
2138 E1000_WRITE_REG(hw, TIPG, tipg);
2139
2140 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
2141
2142 if (ret_val)
2143 return ret_val;
2144
2145 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2146 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
2147
2148 return ret_val;
2149 }
2150
2151 /******************************************************************************
2152 * Configures PHY autoneg and flow control advertisement settings
2153 *
2154 * hw - Struct containing variables accessed by shared code
2155 ******************************************************************************/
2156 int32_t
2157 e1000_phy_setup_autoneg(struct e1000_hw *hw)
2158 {
2159 int32_t ret_val;
2160 uint16_t mii_autoneg_adv_reg;
2161 uint16_t mii_1000t_ctrl_reg;
2162
2163 DEBUGFUNC("e1000_phy_setup_autoneg");
2164
2165 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
2166 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
2167 if (ret_val)
2168 return ret_val;
2169
2170 if (hw->phy_type != e1000_phy_ife) {
2171 /* Read the MII 1000Base-T Control Register (Address 9). */
2172 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
2173 if (ret_val)
2174 return ret_val;
2175 } else
2176 mii_1000t_ctrl_reg=0;
2177
2178 /* Need to parse both autoneg_advertised and fc and set up
2179 * the appropriate PHY registers. First we will parse for
2180 * autoneg_advertised software override. Since we can advertise
2181 * a plethora of combinations, we need to check each bit
2182 * individually.
2183 */
2184
2185 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
2186 * Advertisement Register (Address 4) and the 1000 mb speed bits in
2187 * the 1000Base-T Control Register (Address 9).
2188 */
2189 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
2190 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
2191
2192 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
2193
2194 /* Do we want to advertise 10 Mb Half Duplex? */
2195 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
2196 DEBUGOUT("Advertise 10mb Half duplex\n");
2197 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
2198 }
2199
2200 /* Do we want to advertise 10 Mb Full Duplex? */
2201 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
2202 DEBUGOUT("Advertise 10mb Full duplex\n");
2203 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
2204 }
2205
2206 /* Do we want to advertise 100 Mb Half Duplex? */
2207 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
2208 DEBUGOUT("Advertise 100mb Half duplex\n");
2209 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
2210 }
2211
2212 /* Do we want to advertise 100 Mb Full Duplex? */
2213 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
2214 DEBUGOUT("Advertise 100mb Full duplex\n");
2215 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
2216 }
2217
2218 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
2219 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
2220 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
2221 }
2222
2223 /* Do we want to advertise 1000 Mb Full Duplex? */
2224 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
2225 DEBUGOUT("Advertise 1000mb Full duplex\n");
2226 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
2227 if (hw->phy_type == e1000_phy_ife) {
2228 DEBUGOUT("e1000_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n");
2229 }
2230 }
2231
2232 /* Check for a software override of the flow control settings, and
2233 * setup the PHY advertisement registers accordingly. If
2234 * auto-negotiation is enabled, then software will have to set the
2235 * "PAUSE" bits to the correct value in the Auto-Negotiation
2236 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
2237 *
2238 * The possible values of the "fc" parameter are:
2239 * 0: Flow control is completely disabled
2240 * 1: Rx flow control is enabled (we can receive pause frames
2241 * but not send pause frames).
2242 * 2: Tx flow control is enabled (we can send pause frames
2243 * but we do not support receiving pause frames).
2244 * 3: Both Rx and TX flow control (symmetric) are enabled.
2245 * other: No software override. The flow control configuration
2246 * in the EEPROM is used.
2247 */
2248 switch (hw->fc) {
2249 case E1000_FC_NONE: /* 0 */
2250 /* Flow control (RX & TX) is completely disabled by a
2251 * software over-ride.
2252 */
2253 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2254 break;
2255 case E1000_FC_RX_PAUSE: /* 1 */
2256 /* RX Flow control is enabled, and TX Flow control is
2257 * disabled, by a software over-ride.
2258 */
2259 /* Since there really isn't a way to advertise that we are
2260 * capable of RX Pause ONLY, we will advertise that we
2261 * support both symmetric and asymmetric RX PAUSE. Later
2262 * (in e1000_config_fc_after_link_up) we will disable the
2263 *hw's ability to send PAUSE frames.
2264 */
2265 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2266 break;
2267 case E1000_FC_TX_PAUSE: /* 2 */
2268 /* TX Flow control is enabled, and RX Flow control is
2269 * disabled, by a software over-ride.
2270 */
2271 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
2272 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
2273 break;
2274 case E1000_FC_FULL: /* 3 */
2275 /* Flow control (both RX and TX) is enabled by a software
2276 * over-ride.
2277 */
2278 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2279 break;
2280 default:
2281 DEBUGOUT("Flow control param set incorrectly\n");
2282 return -E1000_ERR_CONFIG;
2283 }
2284
2285 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
2286 if (ret_val)
2287 return ret_val;
2288
2289 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
2290
2291 if (hw->phy_type != e1000_phy_ife) {
2292 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
2293 if (ret_val)
2294 return ret_val;
2295 }
2296
2297 return E1000_SUCCESS;
2298 }
2299
2300 /******************************************************************************
2301 * Force PHY speed and duplex settings to hw->forced_speed_duplex
2302 *
2303 * hw - Struct containing variables accessed by shared code
2304 ******************************************************************************/
2305 static int32_t
2306 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2307 {
2308 uint32_t ctrl;
2309 int32_t ret_val;
2310 uint16_t mii_ctrl_reg;
2311 uint16_t mii_status_reg;
2312 uint16_t phy_data;
2313 uint16_t i;
2314
2315 DEBUGFUNC("e1000_phy_force_speed_duplex");
2316
2317 /* Turn off Flow control if we are forcing speed and duplex. */
2318 hw->fc = E1000_FC_NONE;
2319
2320 DEBUGOUT1("hw->fc = %d\n", hw->fc);
2321
2322 /* Read the Device Control Register. */
2323 ctrl = E1000_READ_REG(hw, CTRL);
2324
2325 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
2326 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2327 ctrl &= ~(DEVICE_SPEED_MASK);
2328
2329 /* Clear the Auto Speed Detect Enable bit. */
2330 ctrl &= ~E1000_CTRL_ASDE;
2331
2332 /* Read the MII Control Register. */
2333 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
2334 if (ret_val)
2335 return ret_val;
2336
2337 /* We need to disable autoneg in order to force link and duplex. */
2338
2339 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
2340
2341 /* Are we forcing Full or Half Duplex? */
2342 if (hw->forced_speed_duplex == e1000_100_full ||
2343 hw->forced_speed_duplex == e1000_10_full) {
2344 /* We want to force full duplex so we SET the full duplex bits in the
2345 * Device and MII Control Registers.
2346 */
2347 ctrl |= E1000_CTRL_FD;
2348 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
2349 DEBUGOUT("Full Duplex\n");
2350 } else {
2351 /* We want to force half duplex so we CLEAR the full duplex bits in
2352 * the Device and MII Control Registers.
2353 */
2354 ctrl &= ~E1000_CTRL_FD;
2355 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
2356 DEBUGOUT("Half Duplex\n");
2357 }
2358
2359 /* Are we forcing 100Mbps??? */
2360 if (hw->forced_speed_duplex == e1000_100_full ||
2361 hw->forced_speed_duplex == e1000_100_half) {
2362 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
2363 ctrl |= E1000_CTRL_SPD_100;
2364 mii_ctrl_reg |= MII_CR_SPEED_100;
2365 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
2366 DEBUGOUT("Forcing 100mb ");
2367 } else {
2368 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
2369 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2370 mii_ctrl_reg |= MII_CR_SPEED_10;
2371 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
2372 DEBUGOUT("Forcing 10mb ");
2373 }
2374
2375 e1000_config_collision_dist(hw);
2376
2377 /* Write the configured values back to the Device Control Reg. */
2378 E1000_WRITE_REG(hw, CTRL, ctrl);
2379
2380 if ((hw->phy_type == e1000_phy_m88) ||
2381 (hw->phy_type == e1000_phy_gg82563)) {
2382 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2383 if (ret_val)
2384 return ret_val;
2385
2386 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
2387 * forced whenever speed are duplex are forced.
2388 */
2389 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2390 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2391 if (ret_val)
2392 return ret_val;
2393
2394 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
2395
2396 /* Need to reset the PHY or these changes will be ignored */
2397 mii_ctrl_reg |= MII_CR_RESET;
2398
2399 /* Disable MDI-X support for 10/100 */
2400 } else if (hw->phy_type == e1000_phy_ife) {
2401 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
2402 if (ret_val)
2403 return ret_val;
2404
2405 phy_data &= ~IFE_PMC_AUTO_MDIX;
2406 phy_data &= ~IFE_PMC_FORCE_MDIX;
2407
2408 ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data);
2409 if (ret_val)
2410 return ret_val;
2411
2412 } else {
2413 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
2414 * forced whenever speed or duplex are forced.
2415 */
2416 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2417 if (ret_val)
2418 return ret_val;
2419
2420 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2421 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2422
2423 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2424 if (ret_val)
2425 return ret_val;
2426 }
2427
2428 /* Write back the modified PHY MII control register. */
2429 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
2430 if (ret_val)
2431 return ret_val;
2432
2433 udelay(1);
2434
2435 /* The wait_autoneg_complete flag may be a little misleading here.
2436 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
2437 * But we do want to delay for a period while forcing only so we
2438 * don't generate false No Link messages. So we will wait here
2439 * only if the user has set wait_autoneg_complete to 1, which is
2440 * the default.
2441 */
2442 if (hw->wait_autoneg_complete) {
2443 /* We will wait for autoneg to complete. */
2444 DEBUGOUT("Waiting for forced speed/duplex link.\n");
2445 mii_status_reg = 0;
2446
2447 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2448 for (i = PHY_FORCE_TIME; i > 0; i--) {
2449 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2450 * to be set.
2451 */
2452 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2453 if (ret_val)
2454 return ret_val;
2455
2456 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2457 if (ret_val)
2458 return ret_val;
2459
2460 if (mii_status_reg & MII_SR_LINK_STATUS) break;
2461 msleep(100);
2462 }
2463 if ((i == 0) &&
2464 ((hw->phy_type == e1000_phy_m88) ||
2465 (hw->phy_type == e1000_phy_gg82563))) {
2466 /* We didn't get link. Reset the DSP and wait again for link. */
2467 ret_val = e1000_phy_reset_dsp(hw);
2468 if (ret_val) {
2469 DEBUGOUT("Error Resetting PHY DSP\n");
2470 return ret_val;
2471 }
2472 }
2473 /* This loop will early-out if the link condition has been met. */
2474 for (i = PHY_FORCE_TIME; i > 0; i--) {
2475 if (mii_status_reg & MII_SR_LINK_STATUS) break;
2476 msleep(100);
2477 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2478 * to be set.
2479 */
2480 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2481 if (ret_val)
2482 return ret_val;
2483
2484 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2485 if (ret_val)
2486 return ret_val;
2487 }
2488 }
2489
2490 if (hw->phy_type == e1000_phy_m88) {
2491 /* Because we reset the PHY above, we need to re-force TX_CLK in the
2492 * Extended PHY Specific Control Register to 25MHz clock. This value
2493 * defaults back to a 2.5MHz clock when the PHY is reset.
2494 */
2495 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
2496 if (ret_val)
2497 return ret_val;
2498
2499 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2500 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2501 if (ret_val)
2502 return ret_val;
2503
2504 /* In addition, because of the s/w reset above, we need to enable CRS on
2505 * TX. This must be set for both full and half duplex operation.
2506 */
2507 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2508 if (ret_val)
2509 return ret_val;
2510
2511 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2512 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2513 if (ret_val)
2514 return ret_val;
2515
2516 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2517 (!hw->autoneg) && (hw->forced_speed_duplex == e1000_10_full ||
2518 hw->forced_speed_duplex == e1000_10_half)) {
2519 ret_val = e1000_polarity_reversal_workaround(hw);
2520 if (ret_val)
2521 return ret_val;
2522 }
2523 } else if (hw->phy_type == e1000_phy_gg82563) {
2524 /* The TX_CLK of the Extended PHY Specific Control Register defaults
2525 * to 2.5MHz on a reset. We need to re-force it back to 25MHz, if
2526 * we're not in a forced 10/duplex configuration. */
2527 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2528 if (ret_val)
2529 return ret_val;
2530
2531 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
2532 if ((hw->forced_speed_duplex == e1000_10_full) ||
2533 (hw->forced_speed_duplex == e1000_10_half))
2534 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ;
2535 else
2536 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ;
2537
2538 /* Also due to the reset, we need to enable CRS on Tx. */
2539 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2540
2541 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2542 if (ret_val)
2543 return ret_val;
2544 }
2545 return E1000_SUCCESS;
2546 }
2547
2548 /******************************************************************************
2549 * Sets the collision distance in the Transmit Control register
2550 *
2551 * hw - Struct containing variables accessed by shared code
2552 *
2553 * Link should have been established previously. Reads the speed and duplex
2554 * information from the Device Status register.
2555 ******************************************************************************/
2556 void
2557 e1000_config_collision_dist(struct e1000_hw *hw)
2558 {
2559 uint32_t tctl, coll_dist;
2560
2561 DEBUGFUNC("e1000_config_collision_dist");
2562
2563 if (hw->mac_type < e1000_82543)
2564 coll_dist = E1000_COLLISION_DISTANCE_82542;
2565 else
2566 coll_dist = E1000_COLLISION_DISTANCE;
2567
2568 tctl = E1000_READ_REG(hw, TCTL);
2569
2570 tctl &= ~E1000_TCTL_COLD;
2571 tctl |= coll_dist << E1000_COLD_SHIFT;
2572
2573 E1000_WRITE_REG(hw, TCTL, tctl);
2574 E1000_WRITE_FLUSH(hw);
2575 }
2576
2577 /******************************************************************************
2578 * Sets MAC speed and duplex settings to reflect the those in the PHY
2579 *
2580 * hw - Struct containing variables accessed by shared code
2581 * mii_reg - data to write to the MII control register
2582 *
2583 * The contents of the PHY register containing the needed information need to
2584 * be passed in.
2585 ******************************************************************************/
2586 static int32_t
2587 e1000_config_mac_to_phy(struct e1000_hw *hw)
2588 {
2589 uint32_t ctrl;
2590 int32_t ret_val;
2591 uint16_t phy_data;
2592
2593 DEBUGFUNC("e1000_config_mac_to_phy");
2594
2595 /* 82544 or newer MAC, Auto Speed Detection takes care of
2596 * MAC speed/duplex configuration.*/
2597 if (hw->mac_type >= e1000_82544)
2598 return E1000_SUCCESS;
2599
2600 /* Read the Device Control Register and set the bits to Force Speed
2601 * and Duplex.
2602 */
2603 ctrl = E1000_READ_REG(hw, CTRL);
2604 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2605 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
2606
2607 /* Set up duplex in the Device Control and Transmit Control
2608 * registers depending on negotiated values.
2609 */
2610 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2611 if (ret_val)
2612 return ret_val;
2613
2614 if (phy_data & M88E1000_PSSR_DPLX)
2615 ctrl |= E1000_CTRL_FD;
2616 else
2617 ctrl &= ~E1000_CTRL_FD;
2618
2619 e1000_config_collision_dist(hw);
2620
2621 /* Set up speed in the Device Control register depending on
2622 * negotiated values.
2623 */
2624 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
2625 ctrl |= E1000_CTRL_SPD_1000;
2626 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
2627 ctrl |= E1000_CTRL_SPD_100;
2628
2629 /* Write the configured values back to the Device Control Reg. */
2630 E1000_WRITE_REG(hw, CTRL, ctrl);
2631 return E1000_SUCCESS;
2632 }
2633
2634 /******************************************************************************
2635 * Forces the MAC's flow control settings.
2636 *
2637 * hw - Struct containing variables accessed by shared code
2638 *
2639 * Sets the TFCE and RFCE bits in the device control register to reflect
2640 * the adapter settings. TFCE and RFCE need to be explicitly set by
2641 * software when a Copper PHY is used because autonegotiation is managed
2642 * by the PHY rather than the MAC. Software must also configure these
2643 * bits when link is forced on a fiber connection.
2644 *****************************************************************************/
2645 int32_t
2646 e1000_force_mac_fc(struct e1000_hw *hw)
2647 {
2648 uint32_t ctrl;
2649
2650 DEBUGFUNC("e1000_force_mac_fc");
2651
2652 /* Get the current configuration of the Device Control Register */
2653 ctrl = E1000_READ_REG(hw, CTRL);
2654
2655 /* Because we didn't get link via the internal auto-negotiation
2656 * mechanism (we either forced link or we got link via PHY
2657 * auto-neg), we have to manually enable/disable transmit an
2658 * receive flow control.
2659 *
2660 * The "Case" statement below enables/disable flow control
2661 * according to the "hw->fc" parameter.
2662 *
2663 * The possible values of the "fc" parameter are:
2664 * 0: Flow control is completely disabled
2665 * 1: Rx flow control is enabled (we can receive pause
2666 * frames but not send pause frames).
2667 * 2: Tx flow control is enabled (we can send pause frames
2668 * frames but we do not receive pause frames).
2669 * 3: Both Rx and TX flow control (symmetric) is enabled.
2670 * other: No other values should be possible at this point.
2671 */
2672
2673 switch (hw->fc) {
2674 case E1000_FC_NONE:
2675 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
2676 break;
2677 case E1000_FC_RX_PAUSE:
2678 ctrl &= (~E1000_CTRL_TFCE);
2679 ctrl |= E1000_CTRL_RFCE;
2680 break;
2681 case E1000_FC_TX_PAUSE:
2682 ctrl &= (~E1000_CTRL_RFCE);
2683 ctrl |= E1000_CTRL_TFCE;
2684 break;
2685 case E1000_FC_FULL:
2686 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
2687 break;
2688 default:
2689 DEBUGOUT("Flow control param set incorrectly\n");
2690 return -E1000_ERR_CONFIG;
2691 }
2692
2693 /* Disable TX Flow Control for 82542 (rev 2.0) */
2694 if (hw->mac_type == e1000_82542_rev2_0)
2695 ctrl &= (~E1000_CTRL_TFCE);
2696
2697 E1000_WRITE_REG(hw, CTRL, ctrl);
2698 return E1000_SUCCESS;
2699 }
2700
2701 /******************************************************************************
2702 * Configures flow control settings after link is established
2703 *
2704 * hw - Struct containing variables accessed by shared code
2705 *
2706 * Should be called immediately after a valid link has been established.
2707 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
2708 * and autonegotiation is enabled, the MAC flow control settings will be set
2709 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
2710 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
2711 *****************************************************************************/
2712 static int32_t
2713 e1000_config_fc_after_link_up(struct e1000_hw *hw)
2714 {
2715 int32_t ret_val;
2716 uint16_t mii_status_reg;
2717 uint16_t mii_nway_adv_reg;
2718 uint16_t mii_nway_lp_ability_reg;
2719 uint16_t speed;
2720 uint16_t duplex;
2721
2722 DEBUGFUNC("e1000_config_fc_after_link_up");
2723
2724 /* Check for the case where we have fiber media and auto-neg failed
2725 * so we had to force link. In this case, we need to force the
2726 * configuration of the MAC to match the "fc" parameter.
2727 */
2728 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
2729 ((hw->media_type == e1000_media_type_internal_serdes) &&
2730 (hw->autoneg_failed)) ||
2731 ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
2732 ret_val = e1000_force_mac_fc(hw);
2733 if (ret_val) {
2734 DEBUGOUT("Error forcing flow control settings\n");
2735 return ret_val;
2736 }
2737 }
2738
2739 /* Check for the case where we have copper media and auto-neg is
2740 * enabled. In this case, we need to check and see if Auto-Neg
2741 * has completed, and if so, how the PHY and link partner has
2742 * flow control configured.
2743 */
2744 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
2745 /* Read the MII Status Register and check to see if AutoNeg
2746 * has completed. We read this twice because this reg has
2747 * some "sticky" (latched) bits.
2748 */
2749 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2750 if (ret_val)
2751 return ret_val;
2752 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2753 if (ret_val)
2754 return ret_val;
2755
2756 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
2757 /* The AutoNeg process has completed, so we now need to
2758 * read both the Auto Negotiation Advertisement Register
2759 * (Address 4) and the Auto_Negotiation Base Page Ability
2760 * Register (Address 5) to determine how flow control was
2761 * negotiated.
2762 */
2763 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2764 &mii_nway_adv_reg);
2765 if (ret_val)
2766 return ret_val;
2767 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2768 &mii_nway_lp_ability_reg);
2769 if (ret_val)
2770 return ret_val;
2771
2772 /* Two bits in the Auto Negotiation Advertisement Register
2773 * (Address 4) and two bits in the Auto Negotiation Base
2774 * Page Ability Register (Address 5) determine flow control
2775 * for both the PHY and the link partner. The following
2776 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
2777 * 1999, describes these PAUSE resolution bits and how flow
2778 * control is determined based upon these settings.
2779 * NOTE: DC = Don't Care
2780 *
2781 * LOCAL DEVICE | LINK PARTNER
2782 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
2783 *-------|---------|-------|---------|--------------------
2784 * 0 | 0 | DC | DC | E1000_FC_NONE
2785 * 0 | 1 | 0 | DC | E1000_FC_NONE
2786 * 0 | 1 | 1 | 0 | E1000_FC_NONE
2787 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2788 * 1 | 0 | 0 | DC | E1000_FC_NONE
2789 * 1 | DC | 1 | DC | E1000_FC_FULL
2790 * 1 | 1 | 0 | 0 | E1000_FC_NONE
2791 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
2792 *
2793 */
2794 /* Are both PAUSE bits set to 1? If so, this implies
2795 * Symmetric Flow Control is enabled at both ends. The
2796 * ASM_DIR bits are irrelevant per the spec.
2797 *
2798 * For Symmetric Flow Control:
2799 *
2800 * LOCAL DEVICE | LINK PARTNER
2801 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2802 *-------|---------|-------|---------|--------------------
2803 * 1 | DC | 1 | DC | E1000_FC_FULL
2804 *
2805 */
2806 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2807 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
2808 /* Now we need to check if the user selected RX ONLY
2809 * of pause frames. In this case, we had to advertise
2810 * FULL flow control because we could not advertise RX
2811 * ONLY. Hence, we must now check to see if we need to
2812 * turn OFF the TRANSMISSION of PAUSE frames.
2813 */
2814 if (hw->original_fc == E1000_FC_FULL) {
2815 hw->fc = E1000_FC_FULL;
2816 DEBUGOUT("Flow Control = FULL.\n");
2817 } else {
2818 hw->fc = E1000_FC_RX_PAUSE;
2819 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2820 }
2821 }
2822 /* For receiving PAUSE frames ONLY.
2823 *
2824 * LOCAL DEVICE | LINK PARTNER
2825 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2826 *-------|---------|-------|---------|--------------------
2827 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2828 *
2829 */
2830 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2831 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2832 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2833 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2834 hw->fc = E1000_FC_TX_PAUSE;
2835 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2836 }
2837 /* For transmitting PAUSE frames ONLY.
2838 *
2839 * LOCAL DEVICE | LINK PARTNER
2840 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2841 *-------|---------|-------|---------|--------------------
2842 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
2843 *
2844 */
2845 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2846 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2847 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2848 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2849 hw->fc = E1000_FC_RX_PAUSE;
2850 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2851 }
2852 /* Per the IEEE spec, at this point flow control should be
2853 * disabled. However, we want to consider that we could
2854 * be connected to a legacy switch that doesn't advertise
2855 * desired flow control, but can be forced on the link
2856 * partner. So if we advertised no flow control, that is
2857 * what we will resolve to. If we advertised some kind of
2858 * receive capability (Rx Pause Only or Full Flow Control)
2859 * and the link partner advertised none, we will configure
2860 * ourselves to enable Rx Flow Control only. We can do
2861 * this safely for two reasons: If the link partner really
2862 * didn't want flow control enabled, and we enable Rx, no
2863 * harm done since we won't be receiving any PAUSE frames
2864 * anyway. If the intent on the link partner was to have
2865 * flow control enabled, then by us enabling RX only, we
2866 * can at least receive pause frames and process them.
2867 * This is a good idea because in most cases, since we are
2868 * predominantly a server NIC, more times than not we will
2869 * be asked to delay transmission of packets than asking
2870 * our link partner to pause transmission of frames.
2871 */
2872 else if ((hw->original_fc == E1000_FC_NONE ||
2873 hw->original_fc == E1000_FC_TX_PAUSE) ||
2874 hw->fc_strict_ieee) {
2875 hw->fc = E1000_FC_NONE;
2876 DEBUGOUT("Flow Control = NONE.\n");
2877 } else {
2878 hw->fc = E1000_FC_RX_PAUSE;
2879 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2880 }
2881
2882 /* Now we need to do one last check... If we auto-
2883 * negotiated to HALF DUPLEX, flow control should not be
2884 * enabled per IEEE 802.3 spec.
2885 */
2886 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
2887 if (ret_val) {
2888 DEBUGOUT("Error getting link speed and duplex\n");
2889 return ret_val;
2890 }
2891
2892 if (duplex == HALF_DUPLEX)
2893 hw->fc = E1000_FC_NONE;
2894
2895 /* Now we call a subroutine to actually force the MAC
2896 * controller to use the correct flow control settings.
2897 */
2898 ret_val = e1000_force_mac_fc(hw);
2899 if (ret_val) {
2900 DEBUGOUT("Error forcing flow control settings\n");
2901 return ret_val;
2902 }
2903 } else {
2904 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
2905 }
2906 }
2907 return E1000_SUCCESS;
2908 }
2909
2910 /******************************************************************************
2911 * Checks to see if the link status of the hardware has changed.
2912 *
2913 * hw - Struct containing variables accessed by shared code
2914 *
2915 * Called by any function that needs to check the link status of the adapter.
2916 *****************************************************************************/
2917 int32_t
2918 e1000_check_for_link(struct e1000_hw *hw)
2919 {
2920 uint32_t rxcw = 0;
2921 uint32_t ctrl;
2922 uint32_t status;
2923 uint32_t rctl;
2924 uint32_t icr;
2925 uint32_t signal = 0;
2926 int32_t ret_val;
2927 uint16_t phy_data;
2928
2929 DEBUGFUNC("e1000_check_for_link");
2930
2931 ctrl = E1000_READ_REG(hw, CTRL);
2932 status = E1000_READ_REG(hw, STATUS);
2933
2934 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
2935 * set when the optics detect a signal. On older adapters, it will be
2936 * cleared when there is a signal. This applies to fiber media only.
2937 */
2938 if ((hw->media_type == e1000_media_type_fiber) ||
2939 (hw->media_type == e1000_media_type_internal_serdes)) {
2940 rxcw = E1000_READ_REG(hw, RXCW);
2941
2942 if (hw->media_type == e1000_media_type_fiber) {
2943 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
2944 if (status & E1000_STATUS_LU)
2945 hw->get_link_status = FALSE;
2946 }
2947 }
2948
2949 /* If we have a copper PHY then we only want to go out to the PHY
2950 * registers to see if Auto-Neg has completed and/or if our link
2951 * status has changed. The get_link_status flag will be set if we
2952 * receive a Link Status Change interrupt or we have Rx Sequence
2953 * Errors.
2954 */
2955 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2956 /* First we want to see if the MII Status Register reports
2957 * link. If so, then we want to get the current speed/duplex
2958 * of the PHY.
2959 * Read the register twice since the link bit is sticky.
2960 */
2961 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2962 if (ret_val)
2963 return ret_val;
2964 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2965 if (ret_val)
2966 return ret_val;
2967
2968 if (phy_data & MII_SR_LINK_STATUS) {
2969 hw->get_link_status = FALSE;
2970 /* Check if there was DownShift, must be checked immediately after
2971 * link-up */
2972 e1000_check_downshift(hw);
2973
2974 /* If we are on 82544 or 82543 silicon and speed/duplex
2975 * are forced to 10H or 10F, then we will implement the polarity
2976 * reversal workaround. We disable interrupts first, and upon
2977 * returning, place the devices interrupt state to its previous
2978 * value except for the link status change interrupt which will
2979 * happen due to the execution of this workaround.
2980 */
2981
2982 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2983 (!hw->autoneg) &&
2984 (hw->forced_speed_duplex == e1000_10_full ||
2985 hw->forced_speed_duplex == e1000_10_half)) {
2986 E1000_WRITE_REG(hw, IMC, 0xffffffff);
2987 ret_val = e1000_polarity_reversal_workaround(hw);
2988 icr = E1000_READ_REG(hw, ICR);
2989 E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC));
2990 E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK);
2991 }
2992
2993 } else {
2994 /* No link detected */
2995 e1000_config_dsp_after_link_change(hw, FALSE);
2996 return 0;
2997 }
2998
2999 /* If we are forcing speed/duplex, then we simply return since
3000 * we have already determined whether we have link or not.
3001 */
3002 if (!hw->autoneg) return -E1000_ERR_CONFIG;
3003
3004 /* optimize the dsp settings for the igp phy */
3005 e1000_config_dsp_after_link_change(hw, TRUE);
3006
3007 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
3008 * have Si on board that is 82544 or newer, Auto
3009 * Speed Detection takes care of MAC speed/duplex
3010 * configuration. So we only need to configure Collision
3011 * Distance in the MAC. Otherwise, we need to force
3012 * speed/duplex on the MAC to the current PHY speed/duplex
3013 * settings.
3014 */
3015 if (hw->mac_type >= e1000_82544)
3016 e1000_config_collision_dist(hw);
3017 else {
3018 ret_val = e1000_config_mac_to_phy(hw);
3019 if (ret_val) {
3020 DEBUGOUT("Error configuring MAC to PHY settings\n");
3021 return ret_val;
3022 }
3023 }
3024
3025 /* Configure Flow Control now that Auto-Neg has completed. First, we
3026 * need to restore the desired flow control settings because we may
3027 * have had to re-autoneg with a different link partner.
3028 */
3029 ret_val = e1000_config_fc_after_link_up(hw);
3030 if (ret_val) {
3031 DEBUGOUT("Error configuring flow control\n");
3032 return ret_val;
3033 }
3034
3035 /* At this point we know that we are on copper and we have
3036 * auto-negotiated link. These are conditions for checking the link
3037 * partner capability register. We use the link speed to determine if
3038 * TBI compatibility needs to be turned on or off. If the link is not
3039 * at gigabit speed, then TBI compatibility is not needed. If we are
3040 * at gigabit speed, we turn on TBI compatibility.
3041 */
3042 if (hw->tbi_compatibility_en) {
3043 uint16_t speed, duplex;
3044 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
3045 if (ret_val) {
3046 DEBUGOUT("Error getting link speed and duplex\n");
3047 return ret_val;
3048 }
3049 if (speed != SPEED_1000) {
3050 /* If link speed is not set to gigabit speed, we do not need
3051 * to enable TBI compatibility.
3052 */
3053 if (hw->tbi_compatibility_on) {
3054 /* If we previously were in the mode, turn it off. */
3055 rctl = E1000_READ_REG(hw, RCTL);
3056 rctl &= ~E1000_RCTL_SBP;
3057 E1000_WRITE_REG(hw, RCTL, rctl);
3058 hw->tbi_compatibility_on = FALSE;
3059 }
3060 } else {
3061 /* If TBI compatibility is was previously off, turn it on. For
3062 * compatibility with a TBI link partner, we will store bad
3063 * packets. Some frames have an additional byte on the end and
3064 * will look like CRC errors to to the hardware.
3065 */
3066 if (!hw->tbi_compatibility_on) {
3067 hw->tbi_compatibility_on = TRUE;
3068 rctl = E1000_READ_REG(hw, RCTL);
3069 rctl |= E1000_RCTL_SBP;
3070 E1000_WRITE_REG(hw, RCTL, rctl);
3071 }
3072 }
3073 }
3074 }
3075 /* If we don't have link (auto-negotiation failed or link partner cannot
3076 * auto-negotiate), the cable is plugged in (we have signal), and our
3077 * link partner is not trying to auto-negotiate with us (we are receiving
3078 * idles or data), we need to force link up. We also need to give
3079 * auto-negotiation time to complete, in case the cable was just plugged
3080 * in. The autoneg_failed flag does this.
3081 */
3082 else if ((((hw->media_type == e1000_media_type_fiber) &&
3083 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
3084 (hw->media_type == e1000_media_type_internal_serdes)) &&
3085 (!(status & E1000_STATUS_LU)) &&
3086 (!(rxcw & E1000_RXCW_C))) {
3087 if (hw->autoneg_failed == 0) {
3088 hw->autoneg_failed = 1;
3089 return 0;
3090 }
3091 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
3092
3093 /* Disable auto-negotiation in the TXCW register */
3094 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
3095
3096 /* Force link-up and also force full-duplex. */
3097 ctrl = E1000_READ_REG(hw, CTRL);
3098 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
3099 E1000_WRITE_REG(hw, CTRL, ctrl);
3100
3101 /* Configure Flow Control after forcing link up. */
3102 ret_val = e1000_config_fc_after_link_up(hw);
3103 if (ret_val) {
3104 DEBUGOUT("Error configuring flow control\n");
3105 return ret_val;
3106 }
3107 }
3108 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
3109 * auto-negotiation in the TXCW register and disable forced link in the
3110 * Device Control register in an attempt to auto-negotiate with our link
3111 * partner.
3112 */
3113 else if (((hw->media_type == e1000_media_type_fiber) ||
3114 (hw->media_type == e1000_media_type_internal_serdes)) &&
3115 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
3116 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
3117 E1000_WRITE_REG(hw, TXCW, hw->txcw);
3118 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
3119
3120 hw->serdes_link_down = FALSE;
3121 }
3122 /* If we force link for non-auto-negotiation switch, check link status
3123 * based on MAC synchronization for internal serdes media type.
3124 */
3125 else if ((hw->media_type == e1000_media_type_internal_serdes) &&
3126 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
3127 /* SYNCH bit and IV bit are sticky. */
3128 udelay(10);
3129 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
3130 if (!(rxcw & E1000_RXCW_IV)) {
3131 hw->serdes_link_down = FALSE;
3132 DEBUGOUT("SERDES: Link is up.\n");
3133 }
3134 } else {
3135 hw->serdes_link_down = TRUE;
3136 DEBUGOUT("SERDES: Link is down.\n");
3137 }
3138 }
3139 if ((hw->media_type == e1000_media_type_internal_serdes) &&
3140 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
3141 hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS));
3142 }
3143 return E1000_SUCCESS;
3144 }
3145
3146 /******************************************************************************
3147 * Detects the current speed and duplex settings of the hardware.
3148 *
3149 * hw - Struct containing variables accessed by shared code
3150 * speed - Speed of the connection
3151 * duplex - Duplex setting of the connection
3152 *****************************************************************************/
3153 int32_t
3154 e1000_get_speed_and_duplex(struct e1000_hw *hw,
3155 uint16_t *speed,
3156 uint16_t *duplex)
3157 {
3158 uint32_t status;
3159 int32_t ret_val;
3160 uint16_t phy_data;
3161
3162 DEBUGFUNC("e1000_get_speed_and_duplex");
3163
3164 if (hw->mac_type >= e1000_82543) {
3165 status = E1000_READ_REG(hw, STATUS);
3166 if (status & E1000_STATUS_SPEED_1000) {
3167 *speed = SPEED_1000;
3168 DEBUGOUT("1000 Mbs, ");
3169 } else if (status & E1000_STATUS_SPEED_100) {
3170 *speed = SPEED_100;
3171 DEBUGOUT("100 Mbs, ");
3172 } else {
3173 *speed = SPEED_10;
3174 DEBUGOUT("10 Mbs, ");
3175 }
3176
3177 if (status & E1000_STATUS_FD) {
3178 *duplex = FULL_DUPLEX;
3179 DEBUGOUT("Full Duplex\n");
3180 } else {
3181 *duplex = HALF_DUPLEX;
3182 DEBUGOUT(" Half Duplex\n");
3183 }
3184 } else {
3185 DEBUGOUT("1000 Mbs, Full Duplex\n");
3186 *speed = SPEED_1000;
3187 *duplex = FULL_DUPLEX;
3188 }
3189
3190 /* IGP01 PHY may advertise full duplex operation after speed downgrade even
3191 * if it is operating at half duplex. Here we set the duplex settings to
3192 * match the duplex in the link partner's capabilities.
3193 */
3194 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
3195 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
3196 if (ret_val)
3197 return ret_val;
3198
3199 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
3200 *duplex = HALF_DUPLEX;
3201 else {
3202 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
3203 if (ret_val)
3204 return ret_val;
3205 if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
3206 (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3207 *duplex = HALF_DUPLEX;
3208 }
3209 }
3210
3211 if ((hw->mac_type == e1000_80003es2lan) &&
3212 (hw->media_type == e1000_media_type_copper)) {
3213 if (*speed == SPEED_1000)
3214 ret_val = e1000_configure_kmrn_for_1000(hw);
3215 else
3216 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
3217 if (ret_val)
3218 return ret_val;
3219 }
3220
3221 if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
3222 ret_val = e1000_kumeran_lock_loss_workaround(hw);
3223 if (ret_val)
3224 return ret_val;
3225 }
3226
3227 return E1000_SUCCESS;
3228 }
3229
3230 /******************************************************************************
3231 * Blocks until autoneg completes or times out (~4.5 seconds)
3232 *
3233 * hw - Struct containing variables accessed by shared code
3234 ******************************************************************************/
3235 static int32_t
3236 e1000_wait_autoneg(struct e1000_hw *hw)
3237 {
3238 int32_t ret_val;
3239 uint16_t i;
3240 uint16_t phy_data;
3241
3242 DEBUGFUNC("e1000_wait_autoneg");
3243 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
3244
3245 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
3246 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
3247 /* Read the MII Status Register and wait for Auto-Neg
3248 * Complete bit to be set.
3249 */
3250 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3251 if (ret_val)
3252 return ret_val;
3253 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3254 if (ret_val)
3255 return ret_val;
3256 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
3257 return E1000_SUCCESS;
3258 }
3259 msleep(100);
3260 }
3261 return E1000_SUCCESS;
3262 }
3263
3264 /******************************************************************************
3265 * Raises the Management Data Clock
3266 *
3267 * hw - Struct containing variables accessed by shared code
3268 * ctrl - Device control register's current value
3269 ******************************************************************************/
3270 static void
3271 e1000_raise_mdi_clk(struct e1000_hw *hw,
3272 uint32_t *ctrl)
3273 {
3274 /* Raise the clock input to the Management Data Clock (by setting the MDC
3275 * bit), and then delay 10 microseconds.
3276 */
3277 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
3278 E1000_WRITE_FLUSH(hw);
3279 udelay(10);
3280 }
3281
3282 /******************************************************************************
3283 * Lowers the Management Data Clock
3284 *
3285 * hw - Struct containing variables accessed by shared code
3286 * ctrl - Device control register's current value
3287 ******************************************************************************/
3288 static void
3289 e1000_lower_mdi_clk(struct e1000_hw *hw,
3290 uint32_t *ctrl)
3291 {
3292 /* Lower the clock input to the Management Data Clock (by clearing the MDC
3293 * bit), and then delay 10 microseconds.
3294 */
3295 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
3296 E1000_WRITE_FLUSH(hw);
3297 udelay(10);
3298 }
3299
3300 /******************************************************************************
3301 * Shifts data bits out to the PHY
3302 *
3303 * hw - Struct containing variables accessed by shared code
3304 * data - Data to send out to the PHY
3305 * count - Number of bits to shift out
3306 *
3307 * Bits are shifted out in MSB to LSB order.
3308 ******************************************************************************/
3309 static void
3310 e1000_shift_out_mdi_bits(struct e1000_hw *hw,
3311 uint32_t data,
3312 uint16_t count)
3313 {
3314 uint32_t ctrl;
3315 uint32_t mask;
3316
3317 /* We need to shift "count" number of bits out to the PHY. So, the value
3318 * in the "data" parameter will be shifted out to the PHY one bit at a
3319 * time. In order to do this, "data" must be broken down into bits.
3320 */
3321 mask = 0x01;
3322 mask <<= (count - 1);
3323
3324 ctrl = E1000_READ_REG(hw, CTRL);
3325
3326 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
3327 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
3328
3329 while (mask) {
3330 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
3331 * then raising and lowering the Management Data Clock. A "0" is
3332 * shifted out to the PHY by setting the MDIO bit to "0" and then
3333 * raising and lowering the clock.
3334 */
3335 if (data & mask)
3336 ctrl |= E1000_CTRL_MDIO;
3337 else
3338 ctrl &= ~E1000_CTRL_MDIO;
3339
3340 E1000_WRITE_REG(hw, CTRL, ctrl);
3341 E1000_WRITE_FLUSH(hw);
3342
3343 udelay(10);
3344
3345 e1000_raise_mdi_clk(hw, &ctrl);
3346 e1000_lower_mdi_clk(hw, &ctrl);
3347
3348 mask = mask >> 1;
3349 }
3350 }
3351
3352 /******************************************************************************
3353 * Shifts data bits in from the PHY
3354 *
3355 * hw - Struct containing variables accessed by shared code
3356 *
3357 * Bits are shifted in in MSB to LSB order.
3358 ******************************************************************************/
3359 static uint16_t
3360 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
3361 {
3362 uint32_t ctrl;
3363 uint16_t data = 0;
3364 uint8_t i;
3365
3366 /* In order to read a register from the PHY, we need to shift in a total
3367 * of 18 bits from the PHY. The first two bit (turnaround) times are used
3368 * to avoid contention on the MDIO pin when a read operation is performed.
3369 * These two bits are ignored by us and thrown away. Bits are "shifted in"
3370 * by raising the input to the Management Data Clock (setting the MDC bit),
3371 * and then reading the value of the MDIO bit.
3372 */
3373 ctrl = E1000_READ_REG(hw, CTRL);
3374
3375 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
3376 ctrl &= ~E1000_CTRL_MDIO_DIR;
3377 ctrl &= ~E1000_CTRL_MDIO;
3378
3379 E1000_WRITE_REG(hw, CTRL, ctrl);
3380 E1000_WRITE_FLUSH(hw);
3381
3382 /* Raise and Lower the clock before reading in the data. This accounts for
3383 * the turnaround bits. The first clock occurred when we clocked out the
3384 * last bit of the Register Address.
3385 */
3386 e1000_raise_mdi_clk(hw, &ctrl);
3387 e1000_lower_mdi_clk(hw, &ctrl);
3388
3389 for (data = 0, i = 0; i < 16; i++) {
3390 data = data << 1;
3391 e1000_raise_mdi_clk(hw, &ctrl);
3392 ctrl = E1000_READ_REG(hw, CTRL);
3393 /* Check to see if we shifted in a "1". */
3394 if (ctrl & E1000_CTRL_MDIO)
3395 data |= 1;
3396 e1000_lower_mdi_clk(hw, &ctrl);
3397 }
3398
3399 e1000_raise_mdi_clk(hw, &ctrl);
3400 e1000_lower_mdi_clk(hw, &ctrl);
3401
3402 return data;
3403 }
3404
3405 static int32_t
3406 e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
3407 {
3408 uint32_t swfw_sync = 0;
3409 uint32_t swmask = mask;
3410 uint32_t fwmask = mask << 16;
3411 int32_t timeout = 200;
3412
3413 DEBUGFUNC("e1000_swfw_sync_acquire");
3414
3415 if (hw->swfwhw_semaphore_present)
3416 return e1000_get_software_flag(hw);
3417
3418 if (!hw->swfw_sync_present)
3419 return e1000_get_hw_eeprom_semaphore(hw);
3420
3421 while (timeout) {
3422 if (e1000_get_hw_eeprom_semaphore(hw))
3423 return -E1000_ERR_SWFW_SYNC;
3424
3425 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
3426 if (!(swfw_sync & (fwmask | swmask))) {
3427 break;
3428 }
3429
3430 /* firmware currently using resource (fwmask) */
3431 /* or other software thread currently using resource (swmask) */
3432 e1000_put_hw_eeprom_semaphore(hw);
3433 mdelay(5);
3434 timeout--;
3435 }
3436
3437 if (!timeout) {
3438 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
3439 return -E1000_ERR_SWFW_SYNC;
3440 }
3441
3442 swfw_sync |= swmask;
3443 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
3444
3445 e1000_put_hw_eeprom_semaphore(hw);
3446 return E1000_SUCCESS;
3447 }
3448
3449 static void
3450 e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
3451 {
3452 uint32_t swfw_sync;
3453 uint32_t swmask = mask;
3454
3455 DEBUGFUNC("e1000_swfw_sync_release");
3456
3457 if (hw->swfwhw_semaphore_present) {
3458 e1000_release_software_flag(hw);
3459 return;
3460 }
3461
3462 if (!hw->swfw_sync_present) {
3463 e1000_put_hw_eeprom_semaphore(hw);
3464 return;
3465 }
3466
3467 /* if (e1000_get_hw_eeprom_semaphore(hw))
3468 * return -E1000_ERR_SWFW_SYNC; */
3469 while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS);
3470 /* empty */
3471
3472 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
3473 swfw_sync &= ~swmask;
3474 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
3475
3476 e1000_put_hw_eeprom_semaphore(hw);
3477 }
3478
3479 /*****************************************************************************
3480 * Reads the value from a PHY register, if the value is on a specific non zero
3481 * page, sets the page first.
3482 * hw - Struct containing variables accessed by shared code
3483 * reg_addr - address of the PHY register to read
3484 ******************************************************************************/
3485 int32_t
3486 e1000_read_phy_reg(struct e1000_hw *hw,
3487 uint32_t reg_addr,
3488 uint16_t *phy_data)
3489 {
3490 uint32_t ret_val;
3491 uint16_t swfw;
3492
3493 DEBUGFUNC("e1000_read_phy_reg");
3494
3495 if ((hw->mac_type == e1000_80003es2lan) &&
3496 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3497 swfw = E1000_SWFW_PHY1_SM;
3498 } else {
3499 swfw = E1000_SWFW_PHY0_SM;
3500 }
3501 if (e1000_swfw_sync_acquire(hw, swfw))
3502 return -E1000_ERR_SWFW_SYNC;
3503
3504 if ((hw->phy_type == e1000_phy_igp ||
3505 hw->phy_type == e1000_phy_igp_3 ||
3506 hw->phy_type == e1000_phy_igp_2) &&
3507 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3508 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3509 (uint16_t)reg_addr);
3510 if (ret_val) {
3511 e1000_swfw_sync_release(hw, swfw);
3512 return ret_val;
3513 }
3514 } else if (hw->phy_type == e1000_phy_gg82563) {
3515 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3516 (hw->mac_type == e1000_80003es2lan)) {
3517 /* Select Configuration Page */
3518 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3519 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3520 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3521 } else {
3522 /* Use Alternative Page Select register to access
3523 * registers 30 and 31
3524 */
3525 ret_val = e1000_write_phy_reg_ex(hw,
3526 GG82563_PHY_PAGE_SELECT_ALT,
3527 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3528 }
3529
3530 if (ret_val) {
3531 e1000_swfw_sync_release(hw, swfw);
3532 return ret_val;
3533 }
3534 }
3535 }
3536
3537 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3538 phy_data);
3539
3540 e1000_swfw_sync_release(hw, swfw);
3541 return ret_val;
3542 }
3543
3544 static int32_t
3545 e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
3546 uint16_t *phy_data)
3547 {
3548 uint32_t i;
3549 uint32_t mdic = 0;
3550 const uint32_t phy_addr = 1;
3551
3552 DEBUGFUNC("e1000_read_phy_reg_ex");
3553
3554 if (reg_addr > MAX_PHY_REG_ADDRESS) {
3555 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3556 return -E1000_ERR_PARAM;
3557 }
3558
3559 if (hw->mac_type > e1000_82543) {
3560 /* Set up Op-code, Phy Address, and register address in the MDI
3561 * Control register. The MAC will take care of interfacing with the
3562 * PHY to retrieve the desired data.
3563 */
3564 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
3565 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3566 (E1000_MDIC_OP_READ));
3567
3568 E1000_WRITE_REG(hw, MDIC, mdic);
3569
3570 /* Poll the ready bit to see if the MDI read completed */
3571 for (i = 0; i < 64; i++) {
3572 udelay(50);
3573 mdic = E1000_READ_REG(hw, MDIC);
3574 if (mdic & E1000_MDIC_READY) break;
3575 }
3576 if (!(mdic & E1000_MDIC_READY)) {
3577 DEBUGOUT("MDI Read did not complete\n");
3578 return -E1000_ERR_PHY;
3579 }
3580 if (mdic & E1000_MDIC_ERROR) {
3581 DEBUGOUT("MDI Error\n");
3582 return -E1000_ERR_PHY;
3583 }
3584 *phy_data = (uint16_t) mdic;
3585 } else {
3586 /* We must first send a preamble through the MDIO pin to signal the
3587 * beginning of an MII instruction. This is done by sending 32
3588 * consecutive "1" bits.
3589 */
3590 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3591
3592 /* Now combine the next few fields that are required for a read
3593 * operation. We use this method instead of calling the
3594 * e1000_shift_out_mdi_bits routine five different times. The format of
3595 * a MII read instruction consists of a shift out of 14 bits and is
3596 * defined as follows:
3597 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
3598 * followed by a shift in of 18 bits. This first two bits shifted in
3599 * are TurnAround bits used to avoid contention on the MDIO pin when a
3600 * READ operation is performed. These two bits are thrown away
3601 * followed by a shift in of 16 bits which contains the desired data.
3602 */
3603 mdic = ((reg_addr) | (phy_addr << 5) |
3604 (PHY_OP_READ << 10) | (PHY_SOF << 12));
3605
3606 e1000_shift_out_mdi_bits(hw, mdic, 14);
3607
3608 /* Now that we've shifted out the read command to the MII, we need to
3609 * "shift in" the 16-bit value (18 total bits) of the requested PHY
3610 * register address.
3611 */
3612 *phy_data = e1000_shift_in_mdi_bits(hw);
3613 }
3614 return E1000_SUCCESS;
3615 }
3616
3617 /******************************************************************************
3618 * Writes a value to a PHY register
3619 *
3620 * hw - Struct containing variables accessed by shared code
3621 * reg_addr - address of the PHY register to write
3622 * data - data to write to the PHY
3623 ******************************************************************************/
3624 int32_t
3625 e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
3626 uint16_t phy_data)
3627 {
3628 uint32_t ret_val;
3629 uint16_t swfw;
3630
3631 DEBUGFUNC("e1000_write_phy_reg");
3632
3633 if ((hw->mac_type == e1000_80003es2lan) &&
3634 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3635 swfw = E1000_SWFW_PHY1_SM;
3636 } else {
3637 swfw = E1000_SWFW_PHY0_SM;
3638 }
3639 if (e1000_swfw_sync_acquire(hw, swfw))
3640 return -E1000_ERR_SWFW_SYNC;
3641
3642 if ((hw->phy_type == e1000_phy_igp ||
3643 hw->phy_type == e1000_phy_igp_3 ||
3644 hw->phy_type == e1000_phy_igp_2) &&
3645 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3646 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3647 (uint16_t)reg_addr);
3648 if (ret_val) {
3649 e1000_swfw_sync_release(hw, swfw);
3650 return ret_val;
3651 }
3652 } else if (hw->phy_type == e1000_phy_gg82563) {
3653 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3654 (hw->mac_type == e1000_80003es2lan)) {
3655 /* Select Configuration Page */
3656 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3657 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3658 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3659 } else {
3660 /* Use Alternative Page Select register to access
3661 * registers 30 and 31
3662 */
3663 ret_val = e1000_write_phy_reg_ex(hw,
3664 GG82563_PHY_PAGE_SELECT_ALT,
3665 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3666 }
3667
3668 if (ret_val) {
3669 e1000_swfw_sync_release(hw, swfw);
3670 return ret_val;
3671 }
3672 }
3673 }
3674
3675 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3676 phy_data);
3677
3678 e1000_swfw_sync_release(hw, swfw);
3679 return ret_val;
3680 }
3681
3682 static int32_t
3683 e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
3684 uint16_t phy_data)
3685 {
3686 uint32_t i;
3687 uint32_t mdic = 0;
3688 const uint32_t phy_addr = 1;
3689
3690 DEBUGFUNC("e1000_write_phy_reg_ex");
3691
3692 if (reg_addr > MAX_PHY_REG_ADDRESS) {
3693 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3694 return -E1000_ERR_PARAM;
3695 }
3696
3697 if (hw->mac_type > e1000_82543) {
3698 /* Set up Op-code, Phy Address, register address, and data intended
3699 * for the PHY register in the MDI Control register. The MAC will take
3700 * care of interfacing with the PHY to send the desired data.
3701 */
3702 mdic = (((uint32_t) phy_data) |
3703 (reg_addr << E1000_MDIC_REG_SHIFT) |
3704 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3705 (E1000_MDIC_OP_WRITE));
3706
3707 E1000_WRITE_REG(hw, MDIC, mdic);
3708
3709 /* Poll the ready bit to see if the MDI read completed */
3710 for (i = 0; i < 641; i++) {
3711 udelay(5);
3712 mdic = E1000_READ_REG(hw, MDIC);
3713 if (mdic & E1000_MDIC_READY) break;
3714 }
3715 if (!(mdic & E1000_MDIC_READY)) {
3716 DEBUGOUT("MDI Write did not complete\n");
3717 return -E1000_ERR_PHY;
3718 }
3719 } else {
3720 /* We'll need to use the SW defined pins to shift the write command
3721 * out to the PHY. We first send a preamble to the PHY to signal the
3722 * beginning of the MII instruction. This is done by sending 32
3723 * consecutive "1" bits.
3724 */
3725 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3726
3727 /* Now combine the remaining required fields that will indicate a
3728 * write operation. We use this method instead of calling the
3729 * e1000_shift_out_mdi_bits routine for each field in the command. The
3730 * format of a MII write instruction is as follows:
3731 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
3732 */
3733 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
3734 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
3735 mdic <<= 16;
3736 mdic |= (uint32_t) phy_data;
3737
3738 e1000_shift_out_mdi_bits(hw, mdic, 32);
3739 }
3740
3741 return E1000_SUCCESS;
3742 }
3743
3744 static int32_t
3745 e1000_read_kmrn_reg(struct e1000_hw *hw,
3746 uint32_t reg_addr,
3747 uint16_t *data)
3748 {
3749 uint32_t reg_val;
3750 uint16_t swfw;
3751 DEBUGFUNC("e1000_read_kmrn_reg");
3752
3753 if ((hw->mac_type == e1000_80003es2lan) &&
3754 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3755 swfw = E1000_SWFW_PHY1_SM;
3756 } else {
3757 swfw = E1000_SWFW_PHY0_SM;
3758 }
3759 if (e1000_swfw_sync_acquire(hw, swfw))
3760 return -E1000_ERR_SWFW_SYNC;
3761
3762 /* Write register address */
3763 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3764 E1000_KUMCTRLSTA_OFFSET) |
3765 E1000_KUMCTRLSTA_REN;
3766 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
3767 udelay(2);
3768
3769 /* Read the data returned */
3770 reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
3771 *data = (uint16_t)reg_val;
3772
3773 e1000_swfw_sync_release(hw, swfw);
3774 return E1000_SUCCESS;
3775 }
3776
3777 static int32_t
3778 e1000_write_kmrn_reg(struct e1000_hw *hw,
3779 uint32_t reg_addr,
3780 uint16_t data)
3781 {
3782 uint32_t reg_val;
3783 uint16_t swfw;
3784 DEBUGFUNC("e1000_write_kmrn_reg");
3785
3786 if ((hw->mac_type == e1000_80003es2lan) &&
3787 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3788 swfw = E1000_SWFW_PHY1_SM;
3789 } else {
3790 swfw = E1000_SWFW_PHY0_SM;
3791 }
3792 if (e1000_swfw_sync_acquire(hw, swfw))
3793 return -E1000_ERR_SWFW_SYNC;
3794
3795 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3796 E1000_KUMCTRLSTA_OFFSET) | data;
3797 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
3798 udelay(2);
3799
3800 e1000_swfw_sync_release(hw, swfw);
3801 return E1000_SUCCESS;
3802 }
3803
3804 /******************************************************************************
3805 * Returns the PHY to the power-on reset state
3806 *
3807 * hw - Struct containing variables accessed by shared code
3808 ******************************************************************************/
3809 int32_t
3810 e1000_phy_hw_reset(struct e1000_hw *hw)
3811 {
3812 uint32_t ctrl, ctrl_ext;
3813 uint32_t led_ctrl;
3814 int32_t ret_val;
3815 uint16_t swfw;
3816
3817 DEBUGFUNC("e1000_phy_hw_reset");
3818
3819 /* In the case of the phy reset being blocked, it's not an error, we
3820 * simply return success without performing the reset. */
3821 ret_val = e1000_check_phy_reset_block(hw);
3822 if (ret_val)
3823 return E1000_SUCCESS;
3824
3825 DEBUGOUT("Resetting Phy...\n");
3826
3827 if (hw->mac_type > e1000_82543) {
3828 if ((hw->mac_type == e1000_80003es2lan) &&
3829 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3830 swfw = E1000_SWFW_PHY1_SM;
3831 } else {
3832 swfw = E1000_SWFW_PHY0_SM;
3833 }
3834 if (e1000_swfw_sync_acquire(hw, swfw)) {
3835 DEBUGOUT("Unable to acquire swfw sync\n");
3836 return -E1000_ERR_SWFW_SYNC;
3837 }
3838 /* Read the device control register and assert the E1000_CTRL_PHY_RST
3839 * bit. Then, take it out of reset.
3840 * For pre-e1000_82571 hardware, we delay for 10ms between the assert
3841 * and deassert. For e1000_82571 hardware and later, we instead delay
3842 * for 50us between and 10ms after the deassertion.
3843 */
3844 ctrl = E1000_READ_REG(hw, CTRL);
3845 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
3846 E1000_WRITE_FLUSH(hw);
3847
3848 if (hw->mac_type < e1000_82571)
3849 msleep(10);
3850 else
3851 udelay(100);
3852
3853 E1000_WRITE_REG(hw, CTRL, ctrl);
3854 E1000_WRITE_FLUSH(hw);
3855
3856 if (hw->mac_type >= e1000_82571)
3857 mdelay(10);
3858
3859 e1000_swfw_sync_release(hw, swfw);
3860 } else {
3861 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
3862 * bit to put the PHY into reset. Then, take it out of reset.
3863 */
3864 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
3865 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
3866 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
3867 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3868 E1000_WRITE_FLUSH(hw);
3869 msleep(10);
3870 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
3871 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3872 E1000_WRITE_FLUSH(hw);
3873 }
3874 udelay(150);
3875
3876 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
3877 /* Configure activity LED after PHY reset */
3878 led_ctrl = E1000_READ_REG(hw, LEDCTL);
3879 led_ctrl &= IGP_ACTIVITY_LED_MASK;
3880 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
3881 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
3882 }
3883
3884 /* Wait for FW to finish PHY configuration. */
3885 ret_val = e1000_get_phy_cfg_done(hw);
3886 if (ret_val != E1000_SUCCESS)
3887 return ret_val;
3888 e1000_release_software_semaphore(hw);
3889
3890 if ((hw->mac_type == e1000_ich8lan) && (hw->phy_type == e1000_phy_igp_3))
3891 ret_val = e1000_init_lcd_from_nvm(hw);
3892
3893 return ret_val;
3894 }
3895
3896 /******************************************************************************
3897 * Resets the PHY
3898 *
3899 * hw - Struct containing variables accessed by shared code
3900 *
3901 * Sets bit 15 of the MII Control register
3902 ******************************************************************************/
3903 int32_t
3904 e1000_phy_reset(struct e1000_hw *hw)
3905 {
3906 int32_t ret_val;
3907 uint16_t phy_data;
3908
3909 DEBUGFUNC("e1000_phy_reset");
3910
3911 /* In the case of the phy reset being blocked, it's not an error, we
3912 * simply return success without performing the reset. */
3913 ret_val = e1000_check_phy_reset_block(hw);
3914 if (ret_val)
3915 return E1000_SUCCESS;
3916
3917 switch (hw->phy_type) {
3918 case e1000_phy_igp:
3919 case e1000_phy_igp_2:
3920 case e1000_phy_igp_3:
3921 case e1000_phy_ife:
3922 ret_val = e1000_phy_hw_reset(hw);
3923 if (ret_val)
3924 return ret_val;
3925 break;
3926 default:
3927 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
3928 if (ret_val)
3929 return ret_val;
3930
3931 phy_data |= MII_CR_RESET;
3932 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
3933 if (ret_val)
3934 return ret_val;
3935
3936 udelay(1);
3937 break;
3938 }
3939
3940 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
3941 e1000_phy_init_script(hw);
3942
3943 return E1000_SUCCESS;
3944 }
3945
3946 /******************************************************************************
3947 * Work-around for 82566 power-down: on D3 entry-
3948 * 1) disable gigabit link
3949 * 2) write VR power-down enable
3950 * 3) read it back
3951 * if successful continue, else issue LCD reset and repeat
3952 *
3953 * hw - struct containing variables accessed by shared code
3954 ******************************************************************************/
3955 void
3956 e1000_phy_powerdown_workaround(struct e1000_hw *hw)
3957 {
3958 int32_t reg;
3959 uint16_t phy_data;
3960 int32_t retry = 0;
3961
3962 DEBUGFUNC("e1000_phy_powerdown_workaround");
3963
3964 if (hw->phy_type != e1000_phy_igp_3)
3965 return;
3966
3967 do {
3968 /* Disable link */
3969 reg = E1000_READ_REG(hw, PHY_CTRL);
3970 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3971 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3972
3973 /* Write VR power-down enable - bits 9:8 should be 10b */
3974 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3975 phy_data |= (1 << 9);
3976 phy_data &= ~(1 << 8);
3977 e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data);
3978
3979 /* Read it back and test */
3980 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3981 if (((phy_data & IGP3_VR_CTRL_MODE_MASK) == IGP3_VR_CTRL_MODE_SHUT) || retry)
3982 break;
3983
3984 /* Issue PHY reset and repeat at most one more time */
3985 reg = E1000_READ_REG(hw, CTRL);
3986 E1000_WRITE_REG(hw, CTRL, reg | E1000_CTRL_PHY_RST);
3987 retry++;
3988 } while (retry);
3989
3990 return;
3991
3992 }
3993
3994 /******************************************************************************
3995 * Work-around for 82566 Kumeran PCS lock loss:
3996 * On link status change (i.e. PCI reset, speed change) and link is up and
3997 * speed is gigabit-
3998 * 0) if workaround is optionally disabled do nothing
3999 * 1) wait 1ms for Kumeran link to come up
4000 * 2) check Kumeran Diagnostic register PCS lock loss bit
4001 * 3) if not set the link is locked (all is good), otherwise...
4002 * 4) reset the PHY
4003 * 5) repeat up to 10 times
4004 * Note: this is only called for IGP3 copper when speed is 1gb.
4005 *
4006 * hw - struct containing variables accessed by shared code
4007 ******************************************************************************/
4008 static int32_t
4009 e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
4010 {
4011 int32_t ret_val;
4012 int32_t reg;
4013 int32_t cnt;
4014 uint16_t phy_data;
4015
4016 if (hw->kmrn_lock_loss_workaround_disabled)
4017 return E1000_SUCCESS;
4018
4019 /* Make sure link is up before proceeding. If not just return.
4020 * Attempting this while link is negotiating fouled up link
4021 * stability */
4022 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4023 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4024
4025 if (phy_data & MII_SR_LINK_STATUS) {
4026 for (cnt = 0; cnt < 10; cnt++) {
4027 /* read once to clear */
4028 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
4029 if (ret_val)
4030 return ret_val;
4031 /* and again to get new status */
4032 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
4033 if (ret_val)
4034 return ret_val;
4035
4036 /* check for PCS lock */
4037 if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
4038 return E1000_SUCCESS;
4039
4040 /* Issue PHY reset */
4041 e1000_phy_hw_reset(hw);
4042 mdelay(5);
4043 }
4044 /* Disable GigE link negotiation */
4045 reg = E1000_READ_REG(hw, PHY_CTRL);
4046 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
4047 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4048
4049 /* unable to acquire PCS lock */
4050 return E1000_ERR_PHY;
4051 }
4052
4053 return E1000_SUCCESS;
4054 }
4055
4056 /******************************************************************************
4057 * Probes the expected PHY address for known PHY IDs
4058 *
4059 * hw - Struct containing variables accessed by shared code
4060 ******************************************************************************/
4061 static int32_t
4062 e1000_detect_gig_phy(struct e1000_hw *hw)
4063 {
4064 int32_t phy_init_status, ret_val;
4065 uint16_t phy_id_high, phy_id_low;
4066 boolean_t match = FALSE;
4067
4068 DEBUGFUNC("e1000_detect_gig_phy");
4069
4070 if (hw->phy_id != 0)
4071 return E1000_SUCCESS;
4072
4073 /* The 82571 firmware may still be configuring the PHY. In this
4074 * case, we cannot access the PHY until the configuration is done. So
4075 * we explicitly set the PHY values. */
4076 if (hw->mac_type == e1000_82571 ||
4077 hw->mac_type == e1000_82572) {
4078 hw->phy_id = IGP01E1000_I_PHY_ID;
4079 hw->phy_type = e1000_phy_igp_2;
4080 return E1000_SUCCESS;
4081 }
4082
4083 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a work-
4084 * around that forces PHY page 0 to be set or the reads fail. The rest of
4085 * the code in this routine uses e1000_read_phy_reg to read the PHY ID.
4086 * So for ESB-2 we need to have this set so our reads won't fail. If the
4087 * attached PHY is not a e1000_phy_gg82563, the routines below will figure
4088 * this out as well. */
4089 if (hw->mac_type == e1000_80003es2lan)
4090 hw->phy_type = e1000_phy_gg82563;
4091
4092 /* Read the PHY ID Registers to identify which PHY is onboard. */
4093 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
4094 if (ret_val)
4095 return ret_val;
4096
4097 hw->phy_id = (uint32_t) (phy_id_high << 16);
4098 udelay(20);
4099 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4100 if (ret_val)
4101 return ret_val;
4102
4103 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
4104 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
4105
4106 switch (hw->mac_type) {
4107 case e1000_82543:
4108 if (hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
4109 break;
4110 case e1000_82544:
4111 if (hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
4112 break;
4113 case e1000_82540:
4114 case e1000_82545:
4115 case e1000_82545_rev_3:
4116 case e1000_82546:
4117 case e1000_82546_rev_3:
4118 if (hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
4119 break;
4120 case e1000_82541:
4121 case e1000_82541_rev_2:
4122 case e1000_82547:
4123 case e1000_82547_rev_2:
4124 if (hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
4125 break;
4126 case e1000_82573:
4127 if (hw->phy_id == M88E1111_I_PHY_ID) match = TRUE;
4128 break;
4129 case e1000_80003es2lan:
4130 if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE;
4131 break;
4132 case e1000_ich8lan:
4133 if (hw->phy_id == IGP03E1000_E_PHY_ID) match = TRUE;
4134 if (hw->phy_id == IFE_E_PHY_ID) match = TRUE;
4135 if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE;
4136 if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE;
4137 break;
4138 default:
4139 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
4140 return -E1000_ERR_CONFIG;
4141 }
4142 phy_init_status = e1000_set_phy_type(hw);
4143
4144 if ((match) && (phy_init_status == E1000_SUCCESS)) {
4145 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
4146 return E1000_SUCCESS;
4147 }
4148 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
4149 return -E1000_ERR_PHY;
4150 }
4151
4152 /******************************************************************************
4153 * Resets the PHY's DSP
4154 *
4155 * hw - Struct containing variables accessed by shared code
4156 ******************************************************************************/
4157 static int32_t
4158 e1000_phy_reset_dsp(struct e1000_hw *hw)
4159 {
4160 int32_t ret_val;
4161 DEBUGFUNC("e1000_phy_reset_dsp");
4162
4163 do {
4164 if (hw->phy_type != e1000_phy_gg82563) {
4165 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
4166 if (ret_val) break;
4167 }
4168 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
4169 if (ret_val) break;
4170 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
4171 if (ret_val) break;
4172 ret_val = E1000_SUCCESS;
4173 } while (0);
4174
4175 return ret_val;
4176 }
4177
4178 /******************************************************************************
4179 * Get PHY information from various PHY registers for igp PHY only.
4180 *
4181 * hw - Struct containing variables accessed by shared code
4182 * phy_info - PHY information structure
4183 ******************************************************************************/
4184 static int32_t
4185 e1000_phy_igp_get_info(struct e1000_hw *hw,
4186 struct e1000_phy_info *phy_info)
4187 {
4188 int32_t ret_val;
4189 uint16_t phy_data, min_length, max_length, average;
4190 e1000_rev_polarity polarity;
4191
4192 DEBUGFUNC("e1000_phy_igp_get_info");
4193
4194 /* The downshift status is checked only once, after link is established,
4195 * and it stored in the hw->speed_downgraded parameter. */
4196 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4197
4198 /* IGP01E1000 does not need to support it. */
4199 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
4200
4201 /* IGP01E1000 always correct polarity reversal */
4202 phy_info->polarity_correction = e1000_polarity_reversal_enabled;
4203
4204 /* Check polarity status */
4205 ret_val = e1000_check_polarity(hw, &polarity);
4206 if (ret_val)
4207 return ret_val;
4208
4209 phy_info->cable_polarity = polarity;
4210
4211 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
4212 if (ret_val)
4213 return ret_val;
4214
4215 phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & IGP01E1000_PSSR_MDIX) >>
4216 IGP01E1000_PSSR_MDIX_SHIFT);
4217
4218 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
4219 IGP01E1000_PSSR_SPEED_1000MBPS) {
4220 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
4221 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
4222 if (ret_val)
4223 return ret_val;
4224
4225 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4226 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
4227 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4228 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4229 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
4230 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4231
4232 /* Get cable length */
4233 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
4234 if (ret_val)
4235 return ret_val;
4236
4237 /* Translate to old method */
4238 average = (max_length + min_length) / 2;
4239
4240 if (average <= e1000_igp_cable_length_50)
4241 phy_info->cable_length = e1000_cable_length_50;
4242 else if (average <= e1000_igp_cable_length_80)
4243 phy_info->cable_length = e1000_cable_length_50_80;
4244 else if (average <= e1000_igp_cable_length_110)
4245 phy_info->cable_length = e1000_cable_length_80_110;
4246 else if (average <= e1000_igp_cable_length_140)
4247 phy_info->cable_length = e1000_cable_length_110_140;
4248 else
4249 phy_info->cable_length = e1000_cable_length_140;
4250 }
4251
4252 return E1000_SUCCESS;
4253 }
4254
4255 /******************************************************************************
4256 * Get PHY information from various PHY registers for ife PHY only.
4257 *
4258 * hw - Struct containing variables accessed by shared code
4259 * phy_info - PHY information structure
4260 ******************************************************************************/
4261 static int32_t
4262 e1000_phy_ife_get_info(struct e1000_hw *hw,
4263 struct e1000_phy_info *phy_info)
4264 {
4265 int32_t ret_val;
4266 uint16_t phy_data;
4267 e1000_rev_polarity polarity;
4268
4269 DEBUGFUNC("e1000_phy_ife_get_info");
4270
4271 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4272 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
4273
4274 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
4275 if (ret_val)
4276 return ret_val;
4277 phy_info->polarity_correction =
4278 ((phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >>
4279 IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT) ?
4280 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
4281
4282 if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) {
4283 ret_val = e1000_check_polarity(hw, &polarity);
4284 if (ret_val)
4285 return ret_val;
4286 } else {
4287 /* Polarity is forced. */
4288 polarity = ((phy_data & IFE_PSC_FORCE_POLARITY) >>
4289 IFE_PSC_FORCE_POLARITY_SHIFT) ?
4290 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
4291 }
4292 phy_info->cable_polarity = polarity;
4293
4294 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
4295 if (ret_val)
4296 return ret_val;
4297
4298 phy_info->mdix_mode = (e1000_auto_x_mode)
4299 ((phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >>
4300 IFE_PMC_MDIX_MODE_SHIFT);
4301
4302 return E1000_SUCCESS;
4303 }
4304
4305 /******************************************************************************
4306 * Get PHY information from various PHY registers fot m88 PHY only.
4307 *
4308 * hw - Struct containing variables accessed by shared code
4309 * phy_info - PHY information structure
4310 ******************************************************************************/
4311 static int32_t
4312 e1000_phy_m88_get_info(struct e1000_hw *hw,
4313 struct e1000_phy_info *phy_info)
4314 {
4315 int32_t ret_val;
4316 uint16_t phy_data;
4317 e1000_rev_polarity polarity;
4318
4319 DEBUGFUNC("e1000_phy_m88_get_info");
4320
4321 /* The downshift status is checked only once, after link is established,
4322 * and it stored in the hw->speed_downgraded parameter. */
4323 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4324
4325 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
4326 if (ret_val)
4327 return ret_val;
4328
4329 phy_info->extended_10bt_distance =
4330 ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
4331 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?
4332 e1000_10bt_ext_dist_enable_lower : e1000_10bt_ext_dist_enable_normal;
4333
4334 phy_info->polarity_correction =
4335 ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
4336 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?
4337 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
4338
4339 /* Check polarity status */
4340 ret_val = e1000_check_polarity(hw, &polarity);
4341 if (ret_val)
4342 return ret_val;
4343 phy_info->cable_polarity = polarity;
4344
4345 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
4346 if (ret_val)
4347 return ret_val;
4348
4349 phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & M88E1000_PSSR_MDIX) >>
4350 M88E1000_PSSR_MDIX_SHIFT);
4351
4352 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
4353 /* Cable Length Estimation and Local/Remote Receiver Information
4354 * are only valid at 1000 Mbps.
4355 */
4356 if (hw->phy_type != e1000_phy_gg82563) {
4357 phy_info->cable_length = (e1000_cable_length)((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
4358 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
4359 } else {
4360 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
4361 &phy_data);
4362 if (ret_val)
4363 return ret_val;
4364
4365 phy_info->cable_length = (e1000_cable_length)(phy_data & GG82563_DSPD_CABLE_LENGTH);
4366 }
4367
4368 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
4369 if (ret_val)
4370 return ret_val;
4371
4372 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4373 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
4374 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4375 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4376 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
4377 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4378
4379 }
4380
4381 return E1000_SUCCESS;
4382 }
4383
4384 /******************************************************************************
4385 * Get PHY information from various PHY registers
4386 *
4387 * hw - Struct containing variables accessed by shared code
4388 * phy_info - PHY information structure
4389 ******************************************************************************/
4390 int32_t
4391 e1000_phy_get_info(struct e1000_hw *hw,
4392 struct e1000_phy_info *phy_info)
4393 {
4394 int32_t ret_val;
4395 uint16_t phy_data;
4396
4397 DEBUGFUNC("e1000_phy_get_info");
4398
4399 phy_info->cable_length = e1000_cable_length_undefined;
4400 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
4401 phy_info->cable_polarity = e1000_rev_polarity_undefined;
4402 phy_info->downshift = e1000_downshift_undefined;
4403 phy_info->polarity_correction = e1000_polarity_reversal_undefined;
4404 phy_info->mdix_mode = e1000_auto_x_mode_undefined;
4405 phy_info->local_rx = e1000_1000t_rx_status_undefined;
4406 phy_info->remote_rx = e1000_1000t_rx_status_undefined;
4407
4408 if (hw->media_type != e1000_media_type_copper) {
4409 DEBUGOUT("PHY info is only valid for copper media\n");
4410 return -E1000_ERR_CONFIG;
4411 }
4412
4413 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4414 if (ret_val)
4415 return ret_val;
4416
4417 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4418 if (ret_val)
4419 return ret_val;
4420
4421 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
4422 DEBUGOUT("PHY info is only valid if link is up\n");
4423 return -E1000_ERR_CONFIG;
4424 }
4425
4426 if (hw->phy_type == e1000_phy_igp ||
4427 hw->phy_type == e1000_phy_igp_3 ||
4428 hw->phy_type == e1000_phy_igp_2)
4429 return e1000_phy_igp_get_info(hw, phy_info);
4430 else if (hw->phy_type == e1000_phy_ife)
4431 return e1000_phy_ife_get_info(hw, phy_info);
4432 else
4433 return e1000_phy_m88_get_info(hw, phy_info);
4434 }
4435
4436 int32_t
4437 e1000_validate_mdi_setting(struct e1000_hw *hw)
4438 {
4439 DEBUGFUNC("e1000_validate_mdi_settings");
4440
4441 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
4442 DEBUGOUT("Invalid MDI setting detected\n");
4443 hw->mdix = 1;
4444 return -E1000_ERR_CONFIG;
4445 }
4446 return E1000_SUCCESS;
4447 }
4448
4449
4450 /******************************************************************************
4451 * Sets up eeprom variables in the hw struct. Must be called after mac_type
4452 * is configured. Additionally, if this is ICH8, the flash controller GbE
4453 * registers must be mapped, or this will crash.
4454 *
4455 * hw - Struct containing variables accessed by shared code
4456 *****************************************************************************/
4457 int32_t
4458 e1000_init_eeprom_params(struct e1000_hw *hw)
4459 {
4460 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4461 uint32_t eecd = E1000_READ_REG(hw, EECD);
4462 int32_t ret_val = E1000_SUCCESS;
4463 uint16_t eeprom_size;
4464
4465 DEBUGFUNC("e1000_init_eeprom_params");
4466
4467 switch (hw->mac_type) {
4468 case e1000_82542_rev2_0:
4469 case e1000_82542_rev2_1:
4470 case e1000_82543:
4471 case e1000_82544:
4472 eeprom->type = e1000_eeprom_microwire;
4473 eeprom->word_size = 64;
4474 eeprom->opcode_bits = 3;
4475 eeprom->address_bits = 6;
4476 eeprom->delay_usec = 50;
4477 eeprom->use_eerd = FALSE;
4478 eeprom->use_eewr = FALSE;
4479 break;
4480 case e1000_82540:
4481 case e1000_82545:
4482 case e1000_82545_rev_3:
4483 case e1000_82546:
4484 case e1000_82546_rev_3:
4485 eeprom->type = e1000_eeprom_microwire;
4486 eeprom->opcode_bits = 3;
4487 eeprom->delay_usec = 50;
4488 if (eecd & E1000_EECD_SIZE) {
4489 eeprom->word_size = 256;
4490 eeprom->address_bits = 8;
4491 } else {
4492 eeprom->word_size = 64;
4493 eeprom->address_bits = 6;
4494 }
4495 eeprom->use_eerd = FALSE;
4496 eeprom->use_eewr = FALSE;
4497 break;
4498 case e1000_82541:
4499 case e1000_82541_rev_2:
4500 case e1000_82547:
4501 case e1000_82547_rev_2:
4502 if (eecd & E1000_EECD_TYPE) {
4503 eeprom->type = e1000_eeprom_spi;
4504 eeprom->opcode_bits = 8;
4505 eeprom->delay_usec = 1;
4506 if (eecd & E1000_EECD_ADDR_BITS) {
4507 eeprom->page_size = 32;
4508 eeprom->address_bits = 16;
4509 } else {
4510 eeprom->page_size = 8;
4511 eeprom->address_bits = 8;
4512 }
4513 } else {
4514 eeprom->type = e1000_eeprom_microwire;
4515 eeprom->opcode_bits = 3;
4516 eeprom->delay_usec = 50;
4517 if (eecd & E1000_EECD_ADDR_BITS) {
4518 eeprom->word_size = 256;
4519 eeprom->address_bits = 8;
4520 } else {
4521 eeprom->word_size = 64;
4522 eeprom->address_bits = 6;
4523 }
4524 }
4525 eeprom->use_eerd = FALSE;
4526 eeprom->use_eewr = FALSE;
4527 break;
4528 case e1000_82571:
4529 case e1000_82572:
4530 eeprom->type = e1000_eeprom_spi;
4531 eeprom->opcode_bits = 8;
4532 eeprom->delay_usec = 1;
4533 if (eecd & E1000_EECD_ADDR_BITS) {
4534 eeprom->page_size = 32;
4535 eeprom->address_bits = 16;
4536 } else {
4537 eeprom->page_size = 8;
4538 eeprom->address_bits = 8;
4539 }
4540 eeprom->use_eerd = FALSE;
4541 eeprom->use_eewr = FALSE;
4542 break;
4543 case e1000_82573:
4544 eeprom->type = e1000_eeprom_spi;
4545 eeprom->opcode_bits = 8;
4546 eeprom->delay_usec = 1;
4547 if (eecd & E1000_EECD_ADDR_BITS) {
4548 eeprom->page_size = 32;
4549 eeprom->address_bits = 16;
4550 } else {
4551 eeprom->page_size = 8;
4552 eeprom->address_bits = 8;
4553 }
4554 eeprom->use_eerd = TRUE;
4555 eeprom->use_eewr = TRUE;
4556 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
4557 eeprom->type = e1000_eeprom_flash;
4558 eeprom->word_size = 2048;
4559
4560 /* Ensure that the Autonomous FLASH update bit is cleared due to
4561 * Flash update issue on parts which use a FLASH for NVM. */
4562 eecd &= ~E1000_EECD_AUPDEN;
4563 E1000_WRITE_REG(hw, EECD, eecd);
4564 }
4565 break;
4566 case e1000_80003es2lan:
4567 eeprom->type = e1000_eeprom_spi;
4568 eeprom->opcode_bits = 8;
4569 eeprom->delay_usec = 1;
4570 if (eecd & E1000_EECD_ADDR_BITS) {
4571 eeprom->page_size = 32;
4572 eeprom->address_bits = 16;
4573 } else {
4574 eeprom->page_size = 8;
4575 eeprom->address_bits = 8;
4576 }
4577 eeprom->use_eerd = TRUE;
4578 eeprom->use_eewr = FALSE;
4579 break;
4580 case e1000_ich8lan:
4581 {
4582 int32_t i = 0;
4583 uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG);
4584
4585 eeprom->type = e1000_eeprom_ich8;
4586 eeprom->use_eerd = FALSE;
4587 eeprom->use_eewr = FALSE;
4588 eeprom->word_size = E1000_SHADOW_RAM_WORDS;
4589
4590 /* Zero the shadow RAM structure. But don't load it from NVM
4591 * so as to save time for driver init */
4592 if (hw->eeprom_shadow_ram != NULL) {
4593 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4594 hw->eeprom_shadow_ram[i].modified = FALSE;
4595 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
4596 }
4597 }
4598
4599 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
4600 ICH_FLASH_SECTOR_SIZE;
4601
4602 hw->flash_bank_size = ((flash_size >> 16) & ICH_GFPREG_BASE_MASK) + 1;
4603 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
4604
4605 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
4606
4607 hw->flash_bank_size /= 2 * sizeof(uint16_t);
4608
4609 break;
4610 }
4611 default:
4612 break;
4613 }
4614
4615 if (eeprom->type == e1000_eeprom_spi) {
4616 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
4617 * 32KB (incremented by powers of 2).
4618 */
4619 if (hw->mac_type <= e1000_82547_rev_2) {
4620 /* Set to default value for initial eeprom read. */
4621 eeprom->word_size = 64;
4622 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
4623 if (ret_val)
4624 return ret_val;
4625 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
4626 /* 256B eeprom size was not supported in earlier hardware, so we
4627 * bump eeprom_size up one to ensure that "1" (which maps to 256B)
4628 * is never the result used in the shifting logic below. */
4629 if (eeprom_size)
4630 eeprom_size++;
4631 } else {
4632 eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >>
4633 E1000_EECD_SIZE_EX_SHIFT);
4634 }
4635
4636 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
4637 }
4638 return ret_val;
4639 }
4640
4641 /******************************************************************************
4642 * Raises the EEPROM's clock input.
4643 *
4644 * hw - Struct containing variables accessed by shared code
4645 * eecd - EECD's current value
4646 *****************************************************************************/
4647 static void
4648 e1000_raise_ee_clk(struct e1000_hw *hw,
4649 uint32_t *eecd)
4650 {
4651 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
4652 * wait <delay> microseconds.
4653 */
4654 *eecd = *eecd | E1000_EECD_SK;
4655 E1000_WRITE_REG(hw, EECD, *eecd);
4656 E1000_WRITE_FLUSH(hw);
4657 udelay(hw->eeprom.delay_usec);
4658 }
4659
4660 /******************************************************************************
4661 * Lowers the EEPROM's clock input.
4662 *
4663 * hw - Struct containing variables accessed by shared code
4664 * eecd - EECD's current value
4665 *****************************************************************************/
4666 static void
4667 e1000_lower_ee_clk(struct e1000_hw *hw,
4668 uint32_t *eecd)
4669 {
4670 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
4671 * wait 50 microseconds.
4672 */
4673 *eecd = *eecd & ~E1000_EECD_SK;
4674 E1000_WRITE_REG(hw, EECD, *eecd);
4675 E1000_WRITE_FLUSH(hw);
4676 udelay(hw->eeprom.delay_usec);
4677 }
4678
4679 /******************************************************************************
4680 * Shift data bits out to the EEPROM.
4681 *
4682 * hw - Struct containing variables accessed by shared code
4683 * data - data to send to the EEPROM
4684 * count - number of bits to shift out
4685 *****************************************************************************/
4686 static void
4687 e1000_shift_out_ee_bits(struct e1000_hw *hw,
4688 uint16_t data,
4689 uint16_t count)
4690 {
4691 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4692 uint32_t eecd;
4693 uint32_t mask;
4694
4695 /* We need to shift "count" bits out to the EEPROM. So, value in the
4696 * "data" parameter will be shifted out to the EEPROM one bit at a time.
4697 * In order to do this, "data" must be broken down into bits.
4698 */
4699 mask = 0x01 << (count - 1);
4700 eecd = E1000_READ_REG(hw, EECD);
4701 if (eeprom->type == e1000_eeprom_microwire) {
4702 eecd &= ~E1000_EECD_DO;
4703 } else if (eeprom->type == e1000_eeprom_spi) {
4704 eecd |= E1000_EECD_DO;
4705 }
4706 do {
4707 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
4708 * and then raising and then lowering the clock (the SK bit controls
4709 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
4710 * by setting "DI" to "0" and then raising and then lowering the clock.
4711 */
4712 eecd &= ~E1000_EECD_DI;
4713
4714 if (data & mask)
4715 eecd |= E1000_EECD_DI;
4716
4717 E1000_WRITE_REG(hw, EECD, eecd);
4718 E1000_WRITE_FLUSH(hw);
4719
4720 udelay(eeprom->delay_usec);
4721
4722 e1000_raise_ee_clk(hw, &eecd);
4723 e1000_lower_ee_clk(hw, &eecd);
4724
4725 mask = mask >> 1;
4726
4727 } while (mask);
4728
4729 /* We leave the "DI" bit set to "0" when we leave this routine. */
4730 eecd &= ~E1000_EECD_DI;
4731 E1000_WRITE_REG(hw, EECD, eecd);
4732 }
4733
4734 /******************************************************************************
4735 * Shift data bits in from the EEPROM
4736 *
4737 * hw - Struct containing variables accessed by shared code
4738 *****************************************************************************/
4739 static uint16_t
4740 e1000_shift_in_ee_bits(struct e1000_hw *hw,
4741 uint16_t count)
4742 {
4743 uint32_t eecd;
4744 uint32_t i;
4745 uint16_t data;
4746
4747 /* In order to read a register from the EEPROM, we need to shift 'count'
4748 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
4749 * input to the EEPROM (setting the SK bit), and then reading the value of
4750 * the "DO" bit. During this "shifting in" process the "DI" bit should
4751 * always be clear.
4752 */
4753
4754 eecd = E1000_READ_REG(hw, EECD);
4755
4756 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
4757 data = 0;
4758
4759 for (i = 0; i < count; i++) {
4760 data = data << 1;
4761 e1000_raise_ee_clk(hw, &eecd);
4762
4763 eecd = E1000_READ_REG(hw, EECD);
4764
4765 eecd &= ~(E1000_EECD_DI);
4766 if (eecd & E1000_EECD_DO)
4767 data |= 1;
4768
4769 e1000_lower_ee_clk(hw, &eecd);
4770 }
4771
4772 return data;
4773 }
4774
4775 /******************************************************************************
4776 * Prepares EEPROM for access
4777 *
4778 * hw - Struct containing variables accessed by shared code
4779 *
4780 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
4781 * function should be called before issuing a command to the EEPROM.
4782 *****************************************************************************/
4783 static int32_t
4784 e1000_acquire_eeprom(struct e1000_hw *hw)
4785 {
4786 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4787 uint32_t eecd, i=0;
4788
4789 DEBUGFUNC("e1000_acquire_eeprom");
4790
4791 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
4792 return -E1000_ERR_SWFW_SYNC;
4793 eecd = E1000_READ_REG(hw, EECD);
4794
4795 if (hw->mac_type != e1000_82573) {
4796 /* Request EEPROM Access */
4797 if (hw->mac_type > e1000_82544) {
4798 eecd |= E1000_EECD_REQ;
4799 E1000_WRITE_REG(hw, EECD, eecd);
4800 eecd = E1000_READ_REG(hw, EECD);
4801 while ((!(eecd & E1000_EECD_GNT)) &&
4802 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
4803 i++;
4804 udelay(5);
4805 eecd = E1000_READ_REG(hw, EECD);
4806 }
4807 if (!(eecd & E1000_EECD_GNT)) {
4808 eecd &= ~E1000_EECD_REQ;
4809 E1000_WRITE_REG(hw, EECD, eecd);
4810 DEBUGOUT("Could not acquire EEPROM grant\n");
4811 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
4812 return -E1000_ERR_EEPROM;
4813 }
4814 }
4815 }
4816
4817 /* Setup EEPROM for Read/Write */
4818
4819 if (eeprom->type == e1000_eeprom_microwire) {
4820 /* Clear SK and DI */
4821 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
4822 E1000_WRITE_REG(hw, EECD, eecd);
4823
4824 /* Set CS */
4825 eecd |= E1000_EECD_CS;
4826 E1000_WRITE_REG(hw, EECD, eecd);
4827 } else if (eeprom->type == e1000_eeprom_spi) {
4828 /* Clear SK and CS */
4829 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4830 E1000_WRITE_REG(hw, EECD, eecd);
4831 udelay(1);
4832 }
4833
4834 return E1000_SUCCESS;
4835 }
4836
4837 /******************************************************************************
4838 * Returns EEPROM to a "standby" state
4839 *
4840 * hw - Struct containing variables accessed by shared code
4841 *****************************************************************************/
4842 static void
4843 e1000_standby_eeprom(struct e1000_hw *hw)
4844 {
4845 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4846 uint32_t eecd;
4847
4848 eecd = E1000_READ_REG(hw, EECD);
4849
4850 if (eeprom->type == e1000_eeprom_microwire) {
4851 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4852 E1000_WRITE_REG(hw, EECD, eecd);
4853 E1000_WRITE_FLUSH(hw);
4854 udelay(eeprom->delay_usec);
4855
4856 /* Clock high */
4857 eecd |= E1000_EECD_SK;
4858 E1000_WRITE_REG(hw, EECD, eecd);
4859 E1000_WRITE_FLUSH(hw);
4860 udelay(eeprom->delay_usec);
4861
4862 /* Select EEPROM */
4863 eecd |= E1000_EECD_CS;
4864 E1000_WRITE_REG(hw, EECD, eecd);
4865 E1000_WRITE_FLUSH(hw);
4866 udelay(eeprom->delay_usec);
4867
4868 /* Clock low */
4869 eecd &= ~E1000_EECD_SK;
4870 E1000_WRITE_REG(hw, EECD, eecd);
4871 E1000_WRITE_FLUSH(hw);
4872 udelay(eeprom->delay_usec);
4873 } else if (eeprom->type == e1000_eeprom_spi) {
4874 /* Toggle CS to flush commands */
4875 eecd |= E1000_EECD_CS;
4876 E1000_WRITE_REG(hw, EECD, eecd);
4877 E1000_WRITE_FLUSH(hw);
4878 udelay(eeprom->delay_usec);
4879 eecd &= ~E1000_EECD_CS;
4880 E1000_WRITE_REG(hw, EECD, eecd);
4881 E1000_WRITE_FLUSH(hw);
4882 udelay(eeprom->delay_usec);
4883 }
4884 }
4885
4886 /******************************************************************************
4887 * Terminates a command by inverting the EEPROM's chip select pin
4888 *
4889 * hw - Struct containing variables accessed by shared code
4890 *****************************************************************************/
4891 static void
4892 e1000_release_eeprom(struct e1000_hw *hw)
4893 {
4894 uint32_t eecd;
4895
4896 DEBUGFUNC("e1000_release_eeprom");
4897
4898 eecd = E1000_READ_REG(hw, EECD);
4899
4900 if (hw->eeprom.type == e1000_eeprom_spi) {
4901 eecd |= E1000_EECD_CS; /* Pull CS high */
4902 eecd &= ~E1000_EECD_SK; /* Lower SCK */
4903
4904 E1000_WRITE_REG(hw, EECD, eecd);
4905
4906 udelay(hw->eeprom.delay_usec);
4907 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
4908 /* cleanup eeprom */
4909
4910 /* CS on Microwire is active-high */
4911 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
4912
4913 E1000_WRITE_REG(hw, EECD, eecd);
4914
4915 /* Rising edge of clock */
4916 eecd |= E1000_EECD_SK;
4917 E1000_WRITE_REG(hw, EECD, eecd);
4918 E1000_WRITE_FLUSH(hw);
4919 udelay(hw->eeprom.delay_usec);
4920
4921 /* Falling edge of clock */
4922 eecd &= ~E1000_EECD_SK;
4923 E1000_WRITE_REG(hw, EECD, eecd);
4924 E1000_WRITE_FLUSH(hw);
4925 udelay(hw->eeprom.delay_usec);
4926 }
4927
4928 /* Stop requesting EEPROM access */
4929 if (hw->mac_type > e1000_82544) {
4930 eecd &= ~E1000_EECD_REQ;
4931 E1000_WRITE_REG(hw, EECD, eecd);
4932 }
4933
4934 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
4935 }
4936
4937 /******************************************************************************
4938 * Reads a 16 bit word from the EEPROM.
4939 *
4940 * hw - Struct containing variables accessed by shared code
4941 *****************************************************************************/
4942 static int32_t
4943 e1000_spi_eeprom_ready(struct e1000_hw *hw)
4944 {
4945 uint16_t retry_count = 0;
4946 uint8_t spi_stat_reg;
4947
4948 DEBUGFUNC("e1000_spi_eeprom_ready");
4949
4950 /* Read "Status Register" repeatedly until the LSB is cleared. The
4951 * EEPROM will signal that the command has been completed by clearing
4952 * bit 0 of the internal status register. If it's not cleared within
4953 * 5 milliseconds, then error out.
4954 */
4955 retry_count = 0;
4956 do {
4957 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
4958 hw->eeprom.opcode_bits);
4959 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
4960 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
4961 break;
4962
4963 udelay(5);
4964 retry_count += 5;
4965
4966 e1000_standby_eeprom(hw);
4967 } while (retry_count < EEPROM_MAX_RETRY_SPI);
4968
4969 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
4970 * only 0-5mSec on 5V devices)
4971 */
4972 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
4973 DEBUGOUT("SPI EEPROM Status error\n");
4974 return -E1000_ERR_EEPROM;
4975 }
4976
4977 return E1000_SUCCESS;
4978 }
4979
4980 /******************************************************************************
4981 * Reads a 16 bit word from the EEPROM.
4982 *
4983 * hw - Struct containing variables accessed by shared code
4984 * offset - offset of word in the EEPROM to read
4985 * data - word read from the EEPROM
4986 * words - number of words to read
4987 *****************************************************************************/
4988 int32_t
4989 e1000_read_eeprom(struct e1000_hw *hw,
4990 uint16_t offset,
4991 uint16_t words,
4992 uint16_t *data)
4993 {
4994 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4995 uint32_t i = 0;
4996
4997 DEBUGFUNC("e1000_read_eeprom");
4998
4999 /* If eeprom is not yet detected, do so now */
5000 if (eeprom->word_size == 0)
5001 e1000_init_eeprom_params(hw);
5002
5003 /* A check for invalid values: offset too large, too many words, and not
5004 * enough words.
5005 */
5006 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
5007 (words == 0)) {
5008 DEBUGOUT2("\"words\" parameter out of bounds. Words = %d, size = %d\n", offset, eeprom->word_size);
5009 return -E1000_ERR_EEPROM;
5010 }
5011
5012 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
5013 * directly. In this case, we need to acquire the EEPROM so that
5014 * FW or other port software does not interrupt.
5015 */
5016 if (e1000_is_onboard_nvm_eeprom(hw) == TRUE &&
5017 hw->eeprom.use_eerd == FALSE) {
5018 /* Prepare the EEPROM for bit-bang reading */
5019 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
5020 return -E1000_ERR_EEPROM;
5021 }
5022
5023 /* Eerd register EEPROM access requires no eeprom aquire/release */
5024 if (eeprom->use_eerd == TRUE)
5025 return e1000_read_eeprom_eerd(hw, offset, words, data);
5026
5027 /* ICH EEPROM access is done via the ICH flash controller */
5028 if (eeprom->type == e1000_eeprom_ich8)
5029 return e1000_read_eeprom_ich8(hw, offset, words, data);
5030
5031 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
5032 * acquired the EEPROM at this point, so any returns should relase it */
5033 if (eeprom->type == e1000_eeprom_spi) {
5034 uint16_t word_in;
5035 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
5036
5037 if (e1000_spi_eeprom_ready(hw)) {
5038 e1000_release_eeprom(hw);
5039 return -E1000_ERR_EEPROM;
5040 }
5041
5042 e1000_standby_eeprom(hw);
5043
5044 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
5045 if ((eeprom->address_bits == 8) && (offset >= 128))
5046 read_opcode |= EEPROM_A8_OPCODE_SPI;
5047
5048 /* Send the READ command (opcode + addr) */
5049 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
5050 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
5051
5052 /* Read the data. The address of the eeprom internally increments with
5053 * each byte (spi) being read, saving on the overhead of eeprom setup
5054 * and tear-down. The address counter will roll over if reading beyond
5055 * the size of the eeprom, thus allowing the entire memory to be read
5056 * starting from any offset. */
5057 for (i = 0; i < words; i++) {
5058 word_in = e1000_shift_in_ee_bits(hw, 16);
5059 data[i] = (word_in >> 8) | (word_in << 8);
5060 }
5061 } else if (eeprom->type == e1000_eeprom_microwire) {
5062 for (i = 0; i < words; i++) {
5063 /* Send the READ command (opcode + addr) */
5064 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
5065 eeprom->opcode_bits);
5066 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
5067 eeprom->address_bits);
5068
5069 /* Read the data. For microwire, each word requires the overhead
5070 * of eeprom setup and tear-down. */
5071 data[i] = e1000_shift_in_ee_bits(hw, 16);
5072 e1000_standby_eeprom(hw);
5073 }
5074 }
5075
5076 /* End this read operation */
5077 e1000_release_eeprom(hw);
5078
5079 return E1000_SUCCESS;
5080 }
5081
5082 /******************************************************************************
5083 * Reads a 16 bit word from the EEPROM using the EERD register.
5084 *
5085 * hw - Struct containing variables accessed by shared code
5086 * offset - offset of word in the EEPROM to read
5087 * data - word read from the EEPROM
5088 * words - number of words to read
5089 *****************************************************************************/
5090 static int32_t
5091 e1000_read_eeprom_eerd(struct e1000_hw *hw,
5092 uint16_t offset,
5093 uint16_t words,
5094 uint16_t *data)
5095 {
5096 uint32_t i, eerd = 0;
5097 int32_t error = 0;
5098
5099 for (i = 0; i < words; i++) {
5100 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
5101 E1000_EEPROM_RW_REG_START;
5102
5103 E1000_WRITE_REG(hw, EERD, eerd);
5104 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
5105
5106 if (error) {
5107 break;
5108 }
5109 data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA);
5110
5111 }
5112
5113 return error;
5114 }
5115
5116 /******************************************************************************
5117 * Writes a 16 bit word from the EEPROM using the EEWR register.
5118 *
5119 * hw - Struct containing variables accessed by shared code
5120 * offset - offset of word in the EEPROM to read
5121 * data - word read from the EEPROM
5122 * words - number of words to read
5123 *****************************************************************************/
5124 static int32_t
5125 e1000_write_eeprom_eewr(struct e1000_hw *hw,
5126 uint16_t offset,
5127 uint16_t words,
5128 uint16_t *data)
5129 {
5130 uint32_t register_value = 0;
5131 uint32_t i = 0;
5132 int32_t error = 0;
5133
5134 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
5135 return -E1000_ERR_SWFW_SYNC;
5136
5137 for (i = 0; i < words; i++) {
5138 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) |
5139 ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) |
5140 E1000_EEPROM_RW_REG_START;
5141
5142 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
5143 if (error) {
5144 break;
5145 }
5146
5147 E1000_WRITE_REG(hw, EEWR, register_value);
5148
5149 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
5150
5151 if (error) {
5152 break;
5153 }
5154 }
5155
5156 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
5157 return error;
5158 }
5159
5160 /******************************************************************************
5161 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
5162 *
5163 * hw - Struct containing variables accessed by shared code
5164 *****************************************************************************/
5165 static int32_t
5166 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
5167 {
5168 uint32_t attempts = 100000;
5169 uint32_t i, reg = 0;
5170 int32_t done = E1000_ERR_EEPROM;
5171
5172 for (i = 0; i < attempts; i++) {
5173 if (eerd == E1000_EEPROM_POLL_READ)
5174 reg = E1000_READ_REG(hw, EERD);
5175 else
5176 reg = E1000_READ_REG(hw, EEWR);
5177
5178 if (reg & E1000_EEPROM_RW_REG_DONE) {
5179 done = E1000_SUCCESS;
5180 break;
5181 }
5182 udelay(5);
5183 }
5184
5185 return done;
5186 }
5187
5188 /***************************************************************************
5189 * Description: Determines if the onboard NVM is FLASH or EEPROM.
5190 *
5191 * hw - Struct containing variables accessed by shared code
5192 ****************************************************************************/
5193 static boolean_t
5194 e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
5195 {
5196 uint32_t eecd = 0;
5197
5198 DEBUGFUNC("e1000_is_onboard_nvm_eeprom");
5199
5200 if (hw->mac_type == e1000_ich8lan)
5201 return FALSE;
5202
5203 if (hw->mac_type == e1000_82573) {
5204 eecd = E1000_READ_REG(hw, EECD);
5205
5206 /* Isolate bits 15 & 16 */
5207 eecd = ((eecd >> 15) & 0x03);
5208
5209 /* If both bits are set, device is Flash type */
5210 if (eecd == 0x03) {
5211 return FALSE;
5212 }
5213 }
5214 return TRUE;
5215 }
5216
5217 /******************************************************************************
5218 * Verifies that the EEPROM has a valid checksum
5219 *
5220 * hw - Struct containing variables accessed by shared code
5221 *
5222 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
5223 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
5224 * valid.
5225 *****************************************************************************/
5226 int32_t
5227 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
5228 {
5229 uint16_t checksum = 0;
5230 uint16_t i, eeprom_data;
5231
5232 DEBUGFUNC("e1000_validate_eeprom_checksum");
5233
5234 if ((hw->mac_type == e1000_82573) &&
5235 (e1000_is_onboard_nvm_eeprom(hw) == FALSE)) {
5236 /* Check bit 4 of word 10h. If it is 0, firmware is done updating
5237 * 10h-12h. Checksum may need to be fixed. */
5238 e1000_read_eeprom(hw, 0x10, 1, &eeprom_data);
5239 if ((eeprom_data & 0x10) == 0) {
5240 /* Read 0x23 and check bit 15. This bit is a 1 when the checksum
5241 * has already been fixed. If the checksum is still wrong and this
5242 * bit is a 1, we need to return bad checksum. Otherwise, we need
5243 * to set this bit to a 1 and update the checksum. */
5244 e1000_read_eeprom(hw, 0x23, 1, &eeprom_data);
5245 if ((eeprom_data & 0x8000) == 0) {
5246 eeprom_data |= 0x8000;
5247 e1000_write_eeprom(hw, 0x23, 1, &eeprom_data);
5248 e1000_update_eeprom_checksum(hw);
5249 }
5250 }
5251 }
5252
5253 if (hw->mac_type == e1000_ich8lan) {
5254 /* Drivers must allocate the shadow ram structure for the
5255 * EEPROM checksum to be updated. Otherwise, this bit as well
5256 * as the checksum must both be set correctly for this
5257 * validation to pass.
5258 */
5259 e1000_read_eeprom(hw, 0x19, 1, &eeprom_data);
5260 if ((eeprom_data & 0x40) == 0) {
5261 eeprom_data |= 0x40;
5262 e1000_write_eeprom(hw, 0x19, 1, &eeprom_data);
5263 e1000_update_eeprom_checksum(hw);
5264 }
5265 }
5266
5267 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
5268 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
5269 DEBUGOUT("EEPROM Read Error\n");
5270 return -E1000_ERR_EEPROM;
5271 }
5272 checksum += eeprom_data;
5273 }
5274
5275 if (checksum == (uint16_t) EEPROM_SUM)
5276 return E1000_SUCCESS;
5277 else {
5278 DEBUGOUT("EEPROM Checksum Invalid\n");
5279 return -E1000_ERR_EEPROM;
5280 }
5281 }
5282
5283 /******************************************************************************
5284 * Calculates the EEPROM checksum and writes it to the EEPROM
5285 *
5286 * hw - Struct containing variables accessed by shared code
5287 *
5288 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
5289 * Writes the difference to word offset 63 of the EEPROM.
5290 *****************************************************************************/
5291 int32_t
5292 e1000_update_eeprom_checksum(struct e1000_hw *hw)
5293 {
5294 uint32_t ctrl_ext;
5295 uint16_t checksum = 0;
5296 uint16_t i, eeprom_data;
5297
5298 DEBUGFUNC("e1000_update_eeprom_checksum");
5299
5300 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
5301 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
5302 DEBUGOUT("EEPROM Read Error\n");
5303 return -E1000_ERR_EEPROM;
5304 }
5305 checksum += eeprom_data;
5306 }
5307 checksum = (uint16_t) EEPROM_SUM - checksum;
5308 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
5309 DEBUGOUT("EEPROM Write Error\n");
5310 return -E1000_ERR_EEPROM;
5311 } else if (hw->eeprom.type == e1000_eeprom_flash) {
5312 e1000_commit_shadow_ram(hw);
5313 } else if (hw->eeprom.type == e1000_eeprom_ich8) {
5314 e1000_commit_shadow_ram(hw);
5315 /* Reload the EEPROM, or else modifications will not appear
5316 * until after next adapter reset. */
5317 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5318 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
5319 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5320 msleep(10);
5321 }
5322 return E1000_SUCCESS;
5323 }
5324
5325 /******************************************************************************
5326 * Parent function for writing words to the different EEPROM types.
5327 *
5328 * hw - Struct containing variables accessed by shared code
5329 * offset - offset within the EEPROM to be written to
5330 * words - number of words to write
5331 * data - 16 bit word to be written to the EEPROM
5332 *
5333 * If e1000_update_eeprom_checksum is not called after this function, the
5334 * EEPROM will most likely contain an invalid checksum.
5335 *****************************************************************************/
5336 int32_t
5337 e1000_write_eeprom(struct e1000_hw *hw,
5338 uint16_t offset,
5339 uint16_t words,
5340 uint16_t *data)
5341 {
5342 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5343 int32_t status = 0;
5344
5345 DEBUGFUNC("e1000_write_eeprom");
5346
5347 /* If eeprom is not yet detected, do so now */
5348 if (eeprom->word_size == 0)
5349 e1000_init_eeprom_params(hw);
5350
5351 /* A check for invalid values: offset too large, too many words, and not
5352 * enough words.
5353 */
5354 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
5355 (words == 0)) {
5356 DEBUGOUT("\"words\" parameter out of bounds\n");
5357 return -E1000_ERR_EEPROM;
5358 }
5359
5360 /* 82573 writes only through eewr */
5361 if (eeprom->use_eewr == TRUE)
5362 return e1000_write_eeprom_eewr(hw, offset, words, data);
5363
5364 if (eeprom->type == e1000_eeprom_ich8)
5365 return e1000_write_eeprom_ich8(hw, offset, words, data);
5366
5367 /* Prepare the EEPROM for writing */
5368 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
5369 return -E1000_ERR_EEPROM;
5370
5371 if (eeprom->type == e1000_eeprom_microwire) {
5372 status = e1000_write_eeprom_microwire(hw, offset, words, data);
5373 } else {
5374 status = e1000_write_eeprom_spi(hw, offset, words, data);
5375 msleep(10);
5376 }
5377
5378 /* Done with writing */
5379 e1000_release_eeprom(hw);
5380
5381 return status;
5382 }
5383
5384 /******************************************************************************
5385 * Writes a 16 bit word to a given offset in an SPI EEPROM.
5386 *
5387 * hw - Struct containing variables accessed by shared code
5388 * offset - offset within the EEPROM to be written to
5389 * words - number of words to write
5390 * data - pointer to array of 8 bit words to be written to the EEPROM
5391 *
5392 *****************************************************************************/
5393 static int32_t
5394 e1000_write_eeprom_spi(struct e1000_hw *hw,
5395 uint16_t offset,
5396 uint16_t words,
5397 uint16_t *data)
5398 {
5399 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5400 uint16_t widx = 0;
5401
5402 DEBUGFUNC("e1000_write_eeprom_spi");
5403
5404 while (widx < words) {
5405 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI;
5406
5407 if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
5408
5409 e1000_standby_eeprom(hw);
5410
5411 /* Send the WRITE ENABLE command (8 bit opcode ) */
5412 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
5413 eeprom->opcode_bits);
5414
5415 e1000_standby_eeprom(hw);
5416
5417 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
5418 if ((eeprom->address_bits == 8) && (offset >= 128))
5419 write_opcode |= EEPROM_A8_OPCODE_SPI;
5420
5421 /* Send the Write command (8-bit opcode + addr) */
5422 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
5423
5424 e1000_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2),
5425 eeprom->address_bits);
5426
5427 /* Send the data */
5428
5429 /* Loop to allow for up to whole page write (32 bytes) of eeprom */
5430 while (widx < words) {
5431 uint16_t word_out = data[widx];
5432 word_out = (word_out >> 8) | (word_out << 8);
5433 e1000_shift_out_ee_bits(hw, word_out, 16);
5434 widx++;
5435
5436 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
5437 * operation, while the smaller eeproms are capable of an 8-byte
5438 * PAGE WRITE operation. Break the inner loop to pass new address
5439 */
5440 if ((((offset + widx)*2) % eeprom->page_size) == 0) {
5441 e1000_standby_eeprom(hw);
5442 break;
5443 }
5444 }
5445 }
5446
5447 return E1000_SUCCESS;
5448 }
5449
5450 /******************************************************************************
5451 * Writes a 16 bit word to a given offset in a Microwire EEPROM.
5452 *
5453 * hw - Struct containing variables accessed by shared code
5454 * offset - offset within the EEPROM to be written to
5455 * words - number of words to write
5456 * data - pointer to array of 16 bit words to be written to the EEPROM
5457 *
5458 *****************************************************************************/
5459 static int32_t
5460 e1000_write_eeprom_microwire(struct e1000_hw *hw,
5461 uint16_t offset,
5462 uint16_t words,
5463 uint16_t *data)
5464 {
5465 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5466 uint32_t eecd;
5467 uint16_t words_written = 0;
5468 uint16_t i = 0;
5469
5470 DEBUGFUNC("e1000_write_eeprom_microwire");
5471
5472 /* Send the write enable command to the EEPROM (3-bit opcode plus
5473 * 6/8-bit dummy address beginning with 11). It's less work to include
5474 * the 11 of the dummy address as part of the opcode than it is to shift
5475 * it over the correct number of bits for the address. This puts the
5476 * EEPROM into write/erase mode.
5477 */
5478 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
5479 (uint16_t)(eeprom->opcode_bits + 2));
5480
5481 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
5482
5483 /* Prepare the EEPROM */
5484 e1000_standby_eeprom(hw);
5485
5486 while (words_written < words) {
5487 /* Send the Write command (3-bit opcode + addr) */
5488 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
5489 eeprom->opcode_bits);
5490
5491 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + words_written),
5492 eeprom->address_bits);
5493
5494 /* Send the data */
5495 e1000_shift_out_ee_bits(hw, data[words_written], 16);
5496
5497 /* Toggle the CS line. This in effect tells the EEPROM to execute
5498 * the previous command.
5499 */
5500 e1000_standby_eeprom(hw);
5501
5502 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
5503 * signal that the command has been completed by raising the DO signal.
5504 * If DO does not go high in 10 milliseconds, then error out.
5505 */
5506 for (i = 0; i < 200; i++) {
5507 eecd = E1000_READ_REG(hw, EECD);
5508 if (eecd & E1000_EECD_DO) break;
5509 udelay(50);
5510 }
5511 if (i == 200) {
5512 DEBUGOUT("EEPROM Write did not complete\n");
5513 return -E1000_ERR_EEPROM;
5514 }
5515
5516 /* Recover from write */
5517 e1000_standby_eeprom(hw);
5518
5519 words_written++;
5520 }
5521
5522 /* Send the write disable command to the EEPROM (3-bit opcode plus
5523 * 6/8-bit dummy address beginning with 10). It's less work to include
5524 * the 10 of the dummy address as part of the opcode than it is to shift
5525 * it over the correct number of bits for the address. This takes the
5526 * EEPROM out of write/erase mode.
5527 */
5528 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
5529 (uint16_t)(eeprom->opcode_bits + 2));
5530
5531 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
5532
5533 return E1000_SUCCESS;
5534 }
5535
5536 /******************************************************************************
5537 * Flushes the cached eeprom to NVM. This is done by saving the modified values
5538 * in the eeprom cache and the non modified values in the currently active bank
5539 * to the new bank.
5540 *
5541 * hw - Struct containing variables accessed by shared code
5542 * offset - offset of word in the EEPROM to read
5543 * data - word read from the EEPROM
5544 * words - number of words to read
5545 *****************************************************************************/
5546 static int32_t
5547 e1000_commit_shadow_ram(struct e1000_hw *hw)
5548 {
5549 uint32_t attempts = 100000;
5550 uint32_t eecd = 0;
5551 uint32_t flop = 0;
5552 uint32_t i = 0;
5553 int32_t error = E1000_SUCCESS;
5554 uint32_t old_bank_offset = 0;
5555 uint32_t new_bank_offset = 0;
5556 uint8_t low_byte = 0;
5557 uint8_t high_byte = 0;
5558 boolean_t sector_write_failed = FALSE;
5559
5560 if (hw->mac_type == e1000_82573) {
5561 /* The flop register will be used to determine if flash type is STM */
5562 flop = E1000_READ_REG(hw, FLOP);
5563 for (i=0; i < attempts; i++) {
5564 eecd = E1000_READ_REG(hw, EECD);
5565 if ((eecd & E1000_EECD_FLUPD) == 0) {
5566 break;
5567 }
5568 udelay(5);
5569 }
5570
5571 if (i == attempts) {
5572 return -E1000_ERR_EEPROM;
5573 }
5574
5575 /* If STM opcode located in bits 15:8 of flop, reset firmware */
5576 if ((flop & 0xFF00) == E1000_STM_OPCODE) {
5577 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET);
5578 }
5579
5580 /* Perform the flash update */
5581 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD);
5582
5583 for (i=0; i < attempts; i++) {
5584 eecd = E1000_READ_REG(hw, EECD);
5585 if ((eecd & E1000_EECD_FLUPD) == 0) {
5586 break;
5587 }
5588 udelay(5);
5589 }
5590
5591 if (i == attempts) {
5592 return -E1000_ERR_EEPROM;
5593 }
5594 }
5595
5596 if (hw->mac_type == e1000_ich8lan && hw->eeprom_shadow_ram != NULL) {
5597 /* We're writing to the opposite bank so if we're on bank 1,
5598 * write to bank 0 etc. We also need to erase the segment that
5599 * is going to be written */
5600 if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) {
5601 new_bank_offset = hw->flash_bank_size * 2;
5602 old_bank_offset = 0;
5603 e1000_erase_ich8_4k_segment(hw, 1);
5604 } else {
5605 old_bank_offset = hw->flash_bank_size * 2;
5606 new_bank_offset = 0;
5607 e1000_erase_ich8_4k_segment(hw, 0);
5608 }
5609
5610 sector_write_failed = FALSE;
5611 /* Loop for every byte in the shadow RAM,
5612 * which is in units of words. */
5613 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5614 /* Determine whether to write the value stored
5615 * in the other NVM bank or a modified value stored
5616 * in the shadow RAM */
5617 if (hw->eeprom_shadow_ram[i].modified == TRUE) {
5618 low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word;
5619 udelay(100);
5620 error = e1000_verify_write_ich8_byte(hw,
5621 (i << 1) + new_bank_offset, low_byte);
5622
5623 if (error != E1000_SUCCESS)
5624 sector_write_failed = TRUE;
5625 else {
5626 high_byte =
5627 (uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8);
5628 udelay(100);
5629 }
5630 } else {
5631 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5632 &low_byte);
5633 udelay(100);
5634 error = e1000_verify_write_ich8_byte(hw,
5635 (i << 1) + new_bank_offset, low_byte);
5636
5637 if (error != E1000_SUCCESS)
5638 sector_write_failed = TRUE;
5639 else {
5640 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5641 &high_byte);
5642 udelay(100);
5643 }
5644 }
5645
5646 /* If the write of the low byte was successful, go ahread and
5647 * write the high byte while checking to make sure that if it
5648 * is the signature byte, then it is handled properly */
5649 if (sector_write_failed == FALSE) {
5650 /* If the word is 0x13, then make sure the signature bits
5651 * (15:14) are 11b until the commit has completed.
5652 * This will allow us to write 10b which indicates the
5653 * signature is valid. We want to do this after the write
5654 * has completed so that we don't mark the segment valid
5655 * while the write is still in progress */
5656 if (i == E1000_ICH_NVM_SIG_WORD)
5657 high_byte = E1000_ICH_NVM_SIG_MASK | high_byte;
5658
5659 error = e1000_verify_write_ich8_byte(hw,
5660 (i << 1) + new_bank_offset + 1, high_byte);
5661 if (error != E1000_SUCCESS)
5662 sector_write_failed = TRUE;
5663
5664 } else {
5665 /* If the write failed then break from the loop and
5666 * return an error */
5667 break;
5668 }
5669 }
5670
5671 /* Don't bother writing the segment valid bits if sector
5672 * programming failed. */
5673 if (sector_write_failed == FALSE) {
5674 /* Finally validate the new segment by setting bit 15:14
5675 * to 10b in word 0x13 , this can be done without an
5676 * erase as well since these bits are 11 to start with
5677 * and we need to change bit 14 to 0b */
5678 e1000_read_ich8_byte(hw,
5679 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
5680 &high_byte);
5681 high_byte &= 0xBF;
5682 error = e1000_verify_write_ich8_byte(hw,
5683 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, high_byte);
5684 /* And invalidate the previously valid segment by setting
5685 * its signature word (0x13) high_byte to 0b. This can be
5686 * done without an erase because flash erase sets all bits
5687 * to 1's. We can write 1's to 0's without an erase */
5688 if (error == E1000_SUCCESS) {
5689 error = e1000_verify_write_ich8_byte(hw,
5690 E1000_ICH_NVM_SIG_WORD * 2 + 1 + old_bank_offset, 0);
5691 }
5692
5693 /* Clear the now not used entry in the cache */
5694 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5695 hw->eeprom_shadow_ram[i].modified = FALSE;
5696 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
5697 }
5698 }
5699 }
5700
5701 return error;
5702 }
5703
5704 /******************************************************************************
5705 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
5706 * second function of dual function devices
5707 *
5708 * hw - Struct containing variables accessed by shared code
5709 *****************************************************************************/
5710 int32_t
5711 e1000_read_mac_addr(struct e1000_hw * hw)
5712 {
5713 uint16_t offset;
5714 uint16_t eeprom_data, i;
5715
5716 DEBUGFUNC("e1000_read_mac_addr");
5717
5718 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
5719 offset = i >> 1;
5720 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
5721 DEBUGOUT("EEPROM Read Error\n");
5722 return -E1000_ERR_EEPROM;
5723 }
5724 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
5725 hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
5726 }
5727
5728 switch (hw->mac_type) {
5729 default:
5730 break;
5731 case e1000_82546:
5732 case e1000_82546_rev_3:
5733 case e1000_82571:
5734 case e1000_80003es2lan:
5735 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
5736 hw->perm_mac_addr[5] ^= 0x01;
5737 break;
5738 }
5739
5740 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
5741 hw->mac_addr[i] = hw->perm_mac_addr[i];
5742 return E1000_SUCCESS;
5743 }
5744
5745 /******************************************************************************
5746 * Initializes receive address filters.
5747 *
5748 * hw - Struct containing variables accessed by shared code
5749 *
5750 * Places the MAC address in receive address register 0 and clears the rest
5751 * of the receive addresss registers. Clears the multicast table. Assumes
5752 * the receiver is in reset when the routine is called.
5753 *****************************************************************************/
5754 static void
5755 e1000_init_rx_addrs(struct e1000_hw *hw)
5756 {
5757 uint32_t i;
5758 uint32_t rar_num;
5759
5760 DEBUGFUNC("e1000_init_rx_addrs");
5761
5762 /* Setup the receive address. */
5763 DEBUGOUT("Programming MAC Address into RAR[0]\n");
5764
5765 e1000_rar_set(hw, hw->mac_addr, 0);
5766
5767 rar_num = E1000_RAR_ENTRIES;
5768
5769 /* Reserve a spot for the Locally Administered Address to work around
5770 * an 82571 issue in which a reset on one port will reload the MAC on
5771 * the other port. */
5772 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
5773 rar_num -= 1;
5774 if (hw->mac_type == e1000_ich8lan)
5775 rar_num = E1000_RAR_ENTRIES_ICH8LAN;
5776
5777 /* Zero out the other 15 receive addresses. */
5778 DEBUGOUT("Clearing RAR[1-15]\n");
5779 for (i = 1; i < rar_num; i++) {
5780 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5781 E1000_WRITE_FLUSH(hw);
5782 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
5783 E1000_WRITE_FLUSH(hw);
5784 }
5785 }
5786
5787 /******************************************************************************
5788 * Hashes an address to determine its location in the multicast table
5789 *
5790 * hw - Struct containing variables accessed by shared code
5791 * mc_addr - the multicast address to hash
5792 *****************************************************************************/
5793 uint32_t
5794 e1000_hash_mc_addr(struct e1000_hw *hw,
5795 uint8_t *mc_addr)
5796 {
5797 uint32_t hash_value = 0;
5798
5799 /* The portion of the address that is used for the hash table is
5800 * determined by the mc_filter_type setting.
5801 */
5802 switch (hw->mc_filter_type) {
5803 /* [0] [1] [2] [3] [4] [5]
5804 * 01 AA 00 12 34 56
5805 * LSB MSB
5806 */
5807 case 0:
5808 if (hw->mac_type == e1000_ich8lan) {
5809 /* [47:38] i.e. 0x158 for above example address */
5810 hash_value = ((mc_addr[4] >> 6) | (((uint16_t) mc_addr[5]) << 2));
5811 } else {
5812 /* [47:36] i.e. 0x563 for above example address */
5813 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5814 }
5815 break;
5816 case 1:
5817 if (hw->mac_type == e1000_ich8lan) {
5818 /* [46:37] i.e. 0x2B1 for above example address */
5819 hash_value = ((mc_addr[4] >> 5) | (((uint16_t) mc_addr[5]) << 3));
5820 } else {
5821 /* [46:35] i.e. 0xAC6 for above example address */
5822 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
5823 }
5824 break;
5825 case 2:
5826 if (hw->mac_type == e1000_ich8lan) {
5827 /*[45:36] i.e. 0x163 for above example address */
5828 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5829 } else {
5830 /* [45:34] i.e. 0x5D8 for above example address */
5831 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5832 }
5833 break;
5834 case 3:
5835 if (hw->mac_type == e1000_ich8lan) {
5836 /* [43:34] i.e. 0x18D for above example address */
5837 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5838 } else {
5839 /* [43:32] i.e. 0x634 for above example address */
5840 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
5841 }
5842 break;
5843 }
5844
5845 hash_value &= 0xFFF;
5846 if (hw->mac_type == e1000_ich8lan)
5847 hash_value &= 0x3FF;
5848
5849 return hash_value;
5850 }
5851
5852 /******************************************************************************
5853 * Sets the bit in the multicast table corresponding to the hash value.
5854 *
5855 * hw - Struct containing variables accessed by shared code
5856 * hash_value - Multicast address hash value
5857 *****************************************************************************/
5858 void
5859 e1000_mta_set(struct e1000_hw *hw,
5860 uint32_t hash_value)
5861 {
5862 uint32_t hash_bit, hash_reg;
5863 uint32_t mta;
5864 uint32_t temp;
5865
5866 /* The MTA is a register array of 128 32-bit registers.
5867 * It is treated like an array of 4096 bits. We want to set
5868 * bit BitArray[hash_value]. So we figure out what register
5869 * the bit is in, read it, OR in the new bit, then write
5870 * back the new value. The register is determined by the
5871 * upper 7 bits of the hash value and the bit within that
5872 * register are determined by the lower 5 bits of the value.
5873 */
5874 hash_reg = (hash_value >> 5) & 0x7F;
5875 if (hw->mac_type == e1000_ich8lan)
5876 hash_reg &= 0x1F;
5877
5878 hash_bit = hash_value & 0x1F;
5879
5880 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
5881
5882 mta |= (1 << hash_bit);
5883
5884 /* If we are on an 82544 and we are trying to write an odd offset
5885 * in the MTA, save off the previous entry before writing and
5886 * restore the old value after writing.
5887 */
5888 if ((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
5889 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
5890 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5891 E1000_WRITE_FLUSH(hw);
5892 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
5893 E1000_WRITE_FLUSH(hw);
5894 } else {
5895 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
5896 E1000_WRITE_FLUSH(hw);
5897 }
5898 }
5899
5900 /******************************************************************************
5901 * Puts an ethernet address into a receive address register.
5902 *
5903 * hw - Struct containing variables accessed by shared code
5904 * addr - Address to put into receive address register
5905 * index - Receive address register to write
5906 *****************************************************************************/
5907 void
5908 e1000_rar_set(struct e1000_hw *hw,
5909 uint8_t *addr,
5910 uint32_t index)
5911 {
5912 uint32_t rar_low, rar_high;
5913
5914 /* HW expects these in little endian so we reverse the byte order
5915 * from network order (big endian) to little endian
5916 */
5917 rar_low = ((uint32_t) addr[0] |
5918 ((uint32_t) addr[1] << 8) |
5919 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
5920 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8));
5921
5922 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
5923 * unit hang.
5924 *
5925 * Description:
5926 * If there are any Rx frames queued up or otherwise present in the HW
5927 * before RSS is enabled, and then we enable RSS, the HW Rx unit will
5928 * hang. To work around this issue, we have to disable receives and
5929 * flush out all Rx frames before we enable RSS. To do so, we modify we
5930 * redirect all Rx traffic to manageability and then reset the HW.
5931 * This flushes away Rx frames, and (since the redirections to
5932 * manageability persists across resets) keeps new ones from coming in
5933 * while we work. Then, we clear the Address Valid AV bit for all MAC
5934 * addresses and undo the re-direction to manageability.
5935 * Now, frames are coming in again, but the MAC won't accept them, so
5936 * far so good. We now proceed to initialize RSS (if necessary) and
5937 * configure the Rx unit. Last, we re-enable the AV bits and continue
5938 * on our merry way.
5939 */
5940 switch (hw->mac_type) {
5941 case e1000_82571:
5942 case e1000_82572:
5943 case e1000_80003es2lan:
5944 if (hw->leave_av_bit_off == TRUE)
5945 break;
5946 default:
5947 /* Indicate to hardware the Address is Valid. */
5948 rar_high |= E1000_RAH_AV;
5949 break;
5950 }
5951
5952 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
5953 E1000_WRITE_FLUSH(hw);
5954 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
5955 E1000_WRITE_FLUSH(hw);
5956 }
5957
5958 /******************************************************************************
5959 * Writes a value to the specified offset in the VLAN filter table.
5960 *
5961 * hw - Struct containing variables accessed by shared code
5962 * offset - Offset in VLAN filer table to write
5963 * value - Value to write into VLAN filter table
5964 *****************************************************************************/
5965 void
5966 e1000_write_vfta(struct e1000_hw *hw,
5967 uint32_t offset,
5968 uint32_t value)
5969 {
5970 uint32_t temp;
5971
5972 if (hw->mac_type == e1000_ich8lan)
5973 return;
5974
5975 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
5976 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
5977 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5978 E1000_WRITE_FLUSH(hw);
5979 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
5980 E1000_WRITE_FLUSH(hw);
5981 } else {
5982 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5983 E1000_WRITE_FLUSH(hw);
5984 }
5985 }
5986
5987 /******************************************************************************
5988 * Clears the VLAN filer table
5989 *
5990 * hw - Struct containing variables accessed by shared code
5991 *****************************************************************************/
5992 static void
5993 e1000_clear_vfta(struct e1000_hw *hw)
5994 {
5995 uint32_t offset;
5996 uint32_t vfta_value = 0;
5997 uint32_t vfta_offset = 0;
5998 uint32_t vfta_bit_in_reg = 0;
5999
6000 if (hw->mac_type == e1000_ich8lan)
6001 return;
6002
6003 if (hw->mac_type == e1000_82573) {
6004 if (hw->mng_cookie.vlan_id != 0) {
6005 /* The VFTA is a 4096b bit-field, each identifying a single VLAN
6006 * ID. The following operations determine which 32b entry
6007 * (i.e. offset) into the array we want to set the VLAN ID
6008 * (i.e. bit) of the manageability unit. */
6009 vfta_offset = (hw->mng_cookie.vlan_id >>
6010 E1000_VFTA_ENTRY_SHIFT) &
6011 E1000_VFTA_ENTRY_MASK;
6012 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
6013 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
6014 }
6015 }
6016 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
6017 /* If the offset we want to clear is the same offset of the
6018 * manageability VLAN ID, then clear all bits except that of the
6019 * manageability unit */
6020 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
6021 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
6022 E1000_WRITE_FLUSH(hw);
6023 }
6024 }
6025
6026 static int32_t
6027 e1000_id_led_init(struct e1000_hw * hw)
6028 {
6029 uint32_t ledctl;
6030 const uint32_t ledctl_mask = 0x000000FF;
6031 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON;
6032 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
6033 uint16_t eeprom_data, i, temp;
6034 const uint16_t led_mask = 0x0F;
6035
6036 DEBUGFUNC("e1000_id_led_init");
6037
6038 if (hw->mac_type < e1000_82540) {
6039 /* Nothing to do */
6040 return E1000_SUCCESS;
6041 }
6042
6043 ledctl = E1000_READ_REG(hw, LEDCTL);
6044 hw->ledctl_default = ledctl;
6045 hw->ledctl_mode1 = hw->ledctl_default;
6046 hw->ledctl_mode2 = hw->ledctl_default;
6047
6048 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
6049 DEBUGOUT("EEPROM Read Error\n");
6050 return -E1000_ERR_EEPROM;
6051 }
6052
6053 if ((hw->mac_type == e1000_82573) &&
6054 (eeprom_data == ID_LED_RESERVED_82573))
6055 eeprom_data = ID_LED_DEFAULT_82573;
6056 else if ((eeprom_data == ID_LED_RESERVED_0000) ||
6057 (eeprom_data == ID_LED_RESERVED_FFFF)) {
6058 if (hw->mac_type == e1000_ich8lan)
6059 eeprom_data = ID_LED_DEFAULT_ICH8LAN;
6060 else
6061 eeprom_data = ID_LED_DEFAULT;
6062 }
6063
6064 for (i = 0; i < 4; i++) {
6065 temp = (eeprom_data >> (i << 2)) & led_mask;
6066 switch (temp) {
6067 case ID_LED_ON1_DEF2:
6068 case ID_LED_ON1_ON2:
6069 case ID_LED_ON1_OFF2:
6070 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
6071 hw->ledctl_mode1 |= ledctl_on << (i << 3);
6072 break;
6073 case ID_LED_OFF1_DEF2:
6074 case ID_LED_OFF1_ON2:
6075 case ID_LED_OFF1_OFF2:
6076 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
6077 hw->ledctl_mode1 |= ledctl_off << (i << 3);
6078 break;
6079 default:
6080 /* Do nothing */
6081 break;
6082 }
6083 switch (temp) {
6084 case ID_LED_DEF1_ON2:
6085 case ID_LED_ON1_ON2:
6086 case ID_LED_OFF1_ON2:
6087 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
6088 hw->ledctl_mode2 |= ledctl_on << (i << 3);
6089 break;
6090 case ID_LED_DEF1_OFF2:
6091 case ID_LED_ON1_OFF2:
6092 case ID_LED_OFF1_OFF2:
6093 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
6094 hw->ledctl_mode2 |= ledctl_off << (i << 3);
6095 break;
6096 default:
6097 /* Do nothing */
6098 break;
6099 }
6100 }
6101 return E1000_SUCCESS;
6102 }
6103
6104 /******************************************************************************
6105 * Prepares SW controlable LED for use and saves the current state of the LED.
6106 *
6107 * hw - Struct containing variables accessed by shared code
6108 *****************************************************************************/
6109 int32_t
6110 e1000_setup_led(struct e1000_hw *hw)
6111 {
6112 uint32_t ledctl;
6113 int32_t ret_val = E1000_SUCCESS;
6114
6115 DEBUGFUNC("e1000_setup_led");
6116
6117 switch (hw->mac_type) {
6118 case e1000_82542_rev2_0:
6119 case e1000_82542_rev2_1:
6120 case e1000_82543:
6121 case e1000_82544:
6122 /* No setup necessary */
6123 break;
6124 case e1000_82541:
6125 case e1000_82547:
6126 case e1000_82541_rev_2:
6127 case e1000_82547_rev_2:
6128 /* Turn off PHY Smart Power Down (if enabled) */
6129 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
6130 &hw->phy_spd_default);
6131 if (ret_val)
6132 return ret_val;
6133 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6134 (uint16_t)(hw->phy_spd_default &
6135 ~IGP01E1000_GMII_SPD));
6136 if (ret_val)
6137 return ret_val;
6138 /* Fall Through */
6139 default:
6140 if (hw->media_type == e1000_media_type_fiber) {
6141 ledctl = E1000_READ_REG(hw, LEDCTL);
6142 /* Save current LEDCTL settings */
6143 hw->ledctl_default = ledctl;
6144 /* Turn off LED0 */
6145 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
6146 E1000_LEDCTL_LED0_BLINK |
6147 E1000_LEDCTL_LED0_MODE_MASK);
6148 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
6149 E1000_LEDCTL_LED0_MODE_SHIFT);
6150 E1000_WRITE_REG(hw, LEDCTL, ledctl);
6151 } else if (hw->media_type == e1000_media_type_copper)
6152 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
6153 break;
6154 }
6155
6156 return E1000_SUCCESS;
6157 }
6158
6159
6160 /******************************************************************************
6161 * Used on 82571 and later Si that has LED blink bits.
6162 * Callers must use their own timer and should have already called
6163 * e1000_id_led_init()
6164 * Call e1000_cleanup led() to stop blinking
6165 *
6166 * hw - Struct containing variables accessed by shared code
6167 *****************************************************************************/
6168 int32_t
6169 e1000_blink_led_start(struct e1000_hw *hw)
6170 {
6171 int16_t i;
6172 uint32_t ledctl_blink = 0;
6173
6174 DEBUGFUNC("e1000_id_led_blink_on");
6175
6176 if (hw->mac_type < e1000_82571) {
6177 /* Nothing to do */
6178 return E1000_SUCCESS;
6179 }
6180 if (hw->media_type == e1000_media_type_fiber) {
6181 /* always blink LED0 for PCI-E fiber */
6182 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
6183 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
6184 } else {
6185 /* set the blink bit for each LED that's "on" (0x0E) in ledctl_mode2 */
6186 ledctl_blink = hw->ledctl_mode2;
6187 for (i=0; i < 4; i++)
6188 if (((hw->ledctl_mode2 >> (i * 8)) & 0xFF) ==
6189 E1000_LEDCTL_MODE_LED_ON)
6190 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << (i * 8));
6191 }
6192
6193 E1000_WRITE_REG(hw, LEDCTL, ledctl_blink);
6194
6195 return E1000_SUCCESS;
6196 }
6197
6198 /******************************************************************************
6199 * Restores the saved state of the SW controlable LED.
6200 *
6201 * hw - Struct containing variables accessed by shared code
6202 *****************************************************************************/
6203 int32_t
6204 e1000_cleanup_led(struct e1000_hw *hw)
6205 {
6206 int32_t ret_val = E1000_SUCCESS;
6207
6208 DEBUGFUNC("e1000_cleanup_led");
6209
6210 switch (hw->mac_type) {
6211 case e1000_82542_rev2_0:
6212 case e1000_82542_rev2_1:
6213 case e1000_82543:
6214 case e1000_82544:
6215 /* No cleanup necessary */
6216 break;
6217 case e1000_82541:
6218 case e1000_82547:
6219 case e1000_82541_rev_2:
6220 case e1000_82547_rev_2:
6221 /* Turn on PHY Smart Power Down (if previously enabled) */
6222 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6223 hw->phy_spd_default);
6224 if (ret_val)
6225 return ret_val;
6226 /* Fall Through */
6227 default:
6228 if (hw->phy_type == e1000_phy_ife) {
6229 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
6230 break;
6231 }
6232 /* Restore LEDCTL settings */
6233 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
6234 break;
6235 }
6236
6237 return E1000_SUCCESS;
6238 }
6239
6240 /******************************************************************************
6241 * Turns on the software controllable LED
6242 *
6243 * hw - Struct containing variables accessed by shared code
6244 *****************************************************************************/
6245 int32_t
6246 e1000_led_on(struct e1000_hw *hw)
6247 {
6248 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
6249
6250 DEBUGFUNC("e1000_led_on");
6251
6252 switch (hw->mac_type) {
6253 case e1000_82542_rev2_0:
6254 case e1000_82542_rev2_1:
6255 case e1000_82543:
6256 /* Set SW Defineable Pin 0 to turn on the LED */
6257 ctrl |= E1000_CTRL_SWDPIN0;
6258 ctrl |= E1000_CTRL_SWDPIO0;
6259 break;
6260 case e1000_82544:
6261 if (hw->media_type == e1000_media_type_fiber) {
6262 /* Set SW Defineable Pin 0 to turn on the LED */
6263 ctrl |= E1000_CTRL_SWDPIN0;
6264 ctrl |= E1000_CTRL_SWDPIO0;
6265 } else {
6266 /* Clear SW Defineable Pin 0 to turn on the LED */
6267 ctrl &= ~E1000_CTRL_SWDPIN0;
6268 ctrl |= E1000_CTRL_SWDPIO0;
6269 }
6270 break;
6271 default:
6272 if (hw->media_type == e1000_media_type_fiber) {
6273 /* Clear SW Defineable Pin 0 to turn on the LED */
6274 ctrl &= ~E1000_CTRL_SWDPIN0;
6275 ctrl |= E1000_CTRL_SWDPIO0;
6276 } else if (hw->phy_type == e1000_phy_ife) {
6277 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6278 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
6279 } else if (hw->media_type == e1000_media_type_copper) {
6280 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
6281 return E1000_SUCCESS;
6282 }
6283 break;
6284 }
6285
6286 E1000_WRITE_REG(hw, CTRL, ctrl);
6287
6288 return E1000_SUCCESS;
6289 }
6290
6291 /******************************************************************************
6292 * Turns off the software controllable LED
6293 *
6294 * hw - Struct containing variables accessed by shared code
6295 *****************************************************************************/
6296 int32_t
6297 e1000_led_off(struct e1000_hw *hw)
6298 {
6299 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
6300
6301 DEBUGFUNC("e1000_led_off");
6302
6303 switch (hw->mac_type) {
6304 case e1000_82542_rev2_0:
6305 case e1000_82542_rev2_1:
6306 case e1000_82543:
6307 /* Clear SW Defineable Pin 0 to turn off the LED */
6308 ctrl &= ~E1000_CTRL_SWDPIN0;
6309 ctrl |= E1000_CTRL_SWDPIO0;
6310 break;
6311 case e1000_82544:
6312 if (hw->media_type == e1000_media_type_fiber) {
6313 /* Clear SW Defineable Pin 0 to turn off the LED */
6314 ctrl &= ~E1000_CTRL_SWDPIN0;
6315 ctrl |= E1000_CTRL_SWDPIO0;
6316 } else {
6317 /* Set SW Defineable Pin 0 to turn off the LED */
6318 ctrl |= E1000_CTRL_SWDPIN0;
6319 ctrl |= E1000_CTRL_SWDPIO0;
6320 }
6321 break;
6322 default:
6323 if (hw->media_type == e1000_media_type_fiber) {
6324 /* Set SW Defineable Pin 0 to turn off the LED */
6325 ctrl |= E1000_CTRL_SWDPIN0;
6326 ctrl |= E1000_CTRL_SWDPIO0;
6327 } else if (hw->phy_type == e1000_phy_ife) {
6328 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6329 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
6330 } else if (hw->media_type == e1000_media_type_copper) {
6331 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
6332 return E1000_SUCCESS;
6333 }
6334 break;
6335 }
6336
6337 E1000_WRITE_REG(hw, CTRL, ctrl);
6338
6339 return E1000_SUCCESS;
6340 }
6341
6342 /******************************************************************************
6343 * Clears all hardware statistics counters.
6344 *
6345 * hw - Struct containing variables accessed by shared code
6346 *****************************************************************************/
6347 static void
6348 e1000_clear_hw_cntrs(struct e1000_hw *hw)
6349 {
6350 volatile uint32_t temp;
6351
6352 temp = E1000_READ_REG(hw, CRCERRS);
6353 temp = E1000_READ_REG(hw, SYMERRS);
6354 temp = E1000_READ_REG(hw, MPC);
6355 temp = E1000_READ_REG(hw, SCC);
6356 temp = E1000_READ_REG(hw, ECOL);
6357 temp = E1000_READ_REG(hw, MCC);
6358 temp = E1000_READ_REG(hw, LATECOL);
6359 temp = E1000_READ_REG(hw, COLC);
6360 temp = E1000_READ_REG(hw, DC);
6361 temp = E1000_READ_REG(hw, SEC);
6362 temp = E1000_READ_REG(hw, RLEC);
6363 temp = E1000_READ_REG(hw, XONRXC);
6364 temp = E1000_READ_REG(hw, XONTXC);
6365 temp = E1000_READ_REG(hw, XOFFRXC);
6366 temp = E1000_READ_REG(hw, XOFFTXC);
6367 temp = E1000_READ_REG(hw, FCRUC);
6368
6369 if (hw->mac_type != e1000_ich8lan) {
6370 temp = E1000_READ_REG(hw, PRC64);
6371 temp = E1000_READ_REG(hw, PRC127);
6372 temp = E1000_READ_REG(hw, PRC255);
6373 temp = E1000_READ_REG(hw, PRC511);
6374 temp = E1000_READ_REG(hw, PRC1023);
6375 temp = E1000_READ_REG(hw, PRC1522);
6376 }
6377
6378 temp = E1000_READ_REG(hw, GPRC);
6379 temp = E1000_READ_REG(hw, BPRC);
6380 temp = E1000_READ_REG(hw, MPRC);
6381 temp = E1000_READ_REG(hw, GPTC);
6382 temp = E1000_READ_REG(hw, GORCL);
6383 temp = E1000_READ_REG(hw, GORCH);
6384 temp = E1000_READ_REG(hw, GOTCL);
6385 temp = E1000_READ_REG(hw, GOTCH);
6386 temp = E1000_READ_REG(hw, RNBC);
6387 temp = E1000_READ_REG(hw, RUC);
6388 temp = E1000_READ_REG(hw, RFC);
6389 temp = E1000_READ_REG(hw, ROC);
6390 temp = E1000_READ_REG(hw, RJC);
6391 temp = E1000_READ_REG(hw, TORL);
6392 temp = E1000_READ_REG(hw, TORH);
6393 temp = E1000_READ_REG(hw, TOTL);
6394 temp = E1000_READ_REG(hw, TOTH);
6395 temp = E1000_READ_REG(hw, TPR);
6396 temp = E1000_READ_REG(hw, TPT);
6397
6398 if (hw->mac_type != e1000_ich8lan) {
6399 temp = E1000_READ_REG(hw, PTC64);
6400 temp = E1000_READ_REG(hw, PTC127);
6401 temp = E1000_READ_REG(hw, PTC255);
6402 temp = E1000_READ_REG(hw, PTC511);
6403 temp = E1000_READ_REG(hw, PTC1023);
6404 temp = E1000_READ_REG(hw, PTC1522);
6405 }
6406
6407 temp = E1000_READ_REG(hw, MPTC);
6408 temp = E1000_READ_REG(hw, BPTC);
6409
6410 if (hw->mac_type < e1000_82543) return;
6411
6412 temp = E1000_READ_REG(hw, ALGNERRC);
6413 temp = E1000_READ_REG(hw, RXERRC);
6414 temp = E1000_READ_REG(hw, TNCRS);
6415 temp = E1000_READ_REG(hw, CEXTERR);
6416 temp = E1000_READ_REG(hw, TSCTC);
6417 temp = E1000_READ_REG(hw, TSCTFC);
6418
6419 if (hw->mac_type <= e1000_82544) return;
6420
6421 temp = E1000_READ_REG(hw, MGTPRC);
6422 temp = E1000_READ_REG(hw, MGTPDC);
6423 temp = E1000_READ_REG(hw, MGTPTC);
6424
6425 if (hw->mac_type <= e1000_82547_rev_2) return;
6426
6427 temp = E1000_READ_REG(hw, IAC);
6428 temp = E1000_READ_REG(hw, ICRXOC);
6429
6430 if (hw->mac_type == e1000_ich8lan) return;
6431
6432 temp = E1000_READ_REG(hw, ICRXPTC);
6433 temp = E1000_READ_REG(hw, ICRXATC);
6434 temp = E1000_READ_REG(hw, ICTXPTC);
6435 temp = E1000_READ_REG(hw, ICTXATC);
6436 temp = E1000_READ_REG(hw, ICTXQEC);
6437 temp = E1000_READ_REG(hw, ICTXQMTC);
6438 temp = E1000_READ_REG(hw, ICRXDMTC);
6439 }
6440
6441 /******************************************************************************
6442 * Resets Adaptive IFS to its default state.
6443 *
6444 * hw - Struct containing variables accessed by shared code
6445 *
6446 * Call this after e1000_init_hw. You may override the IFS defaults by setting
6447 * hw->ifs_params_forced to TRUE. However, you must initialize hw->
6448 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
6449 * before calling this function.
6450 *****************************************************************************/
6451 void
6452 e1000_reset_adaptive(struct e1000_hw *hw)
6453 {
6454 DEBUGFUNC("e1000_reset_adaptive");
6455
6456 if (hw->adaptive_ifs) {
6457 if (!hw->ifs_params_forced) {
6458 hw->current_ifs_val = 0;
6459 hw->ifs_min_val = IFS_MIN;
6460 hw->ifs_max_val = IFS_MAX;
6461 hw->ifs_step_size = IFS_STEP;
6462 hw->ifs_ratio = IFS_RATIO;
6463 }
6464 hw->in_ifs_mode = FALSE;
6465 E1000_WRITE_REG(hw, AIT, 0);
6466 } else {
6467 DEBUGOUT("Not in Adaptive IFS mode!\n");
6468 }
6469 }
6470
6471 /******************************************************************************
6472 * Called during the callback/watchdog routine to update IFS value based on
6473 * the ratio of transmits to collisions.
6474 *
6475 * hw - Struct containing variables accessed by shared code
6476 * tx_packets - Number of transmits since last callback
6477 * total_collisions - Number of collisions since last callback
6478 *****************************************************************************/
6479 void
6480 e1000_update_adaptive(struct e1000_hw *hw)
6481 {
6482 DEBUGFUNC("e1000_update_adaptive");
6483
6484 if (hw->adaptive_ifs) {
6485 if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
6486 if (hw->tx_packet_delta > MIN_NUM_XMITS) {
6487 hw->in_ifs_mode = TRUE;
6488 if (hw->current_ifs_val < hw->ifs_max_val) {
6489 if (hw->current_ifs_val == 0)
6490 hw->current_ifs_val = hw->ifs_min_val;
6491 else
6492 hw->current_ifs_val += hw->ifs_step_size;
6493 E1000_WRITE_REG(hw, AIT, hw->current_ifs_val);
6494 }
6495 }
6496 } else {
6497 if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
6498 hw->current_ifs_val = 0;
6499 hw->in_ifs_mode = FALSE;
6500 E1000_WRITE_REG(hw, AIT, 0);
6501 }
6502 }
6503 } else {
6504 DEBUGOUT("Not in Adaptive IFS mode!\n");
6505 }
6506 }
6507
6508 /******************************************************************************
6509 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
6510 *
6511 * hw - Struct containing variables accessed by shared code
6512 * frame_len - The length of the frame in question
6513 * mac_addr - The Ethernet destination address of the frame in question
6514 *****************************************************************************/
6515 void
6516 e1000_tbi_adjust_stats(struct e1000_hw *hw,
6517 struct e1000_hw_stats *stats,
6518 uint32_t frame_len,
6519 uint8_t *mac_addr)
6520 {
6521 uint64_t carry_bit;
6522
6523 /* First adjust the frame length. */
6524 frame_len--;
6525 /* We need to adjust the statistics counters, since the hardware
6526 * counters overcount this packet as a CRC error and undercount
6527 * the packet as a good packet
6528 */
6529 /* This packet should not be counted as a CRC error. */
6530 stats->crcerrs--;
6531 /* This packet does count as a Good Packet Received. */
6532 stats->gprc++;
6533
6534 /* Adjust the Good Octets received counters */
6535 carry_bit = 0x80000000 & stats->gorcl;
6536 stats->gorcl += frame_len;
6537 /* If the high bit of Gorcl (the low 32 bits of the Good Octets
6538 * Received Count) was one before the addition,
6539 * AND it is zero after, then we lost the carry out,
6540 * need to add one to Gorch (Good Octets Received Count High).
6541 * This could be simplified if all environments supported
6542 * 64-bit integers.
6543 */
6544 if (carry_bit && ((stats->gorcl & 0x80000000) == 0))
6545 stats->gorch++;
6546 /* Is this a broadcast or multicast? Check broadcast first,
6547 * since the test for a multicast frame will test positive on
6548 * a broadcast frame.
6549 */
6550 if ((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
6551 /* Broadcast packet */
6552 stats->bprc++;
6553 else if (*mac_addr & 0x01)
6554 /* Multicast packet */
6555 stats->mprc++;
6556
6557 if (frame_len == hw->max_frame_size) {
6558 /* In this case, the hardware has overcounted the number of
6559 * oversize frames.
6560 */
6561 if (stats->roc > 0)
6562 stats->roc--;
6563 }
6564
6565 /* Adjust the bin counters when the extra byte put the frame in the
6566 * wrong bin. Remember that the frame_len was adjusted above.
6567 */
6568 if (frame_len == 64) {
6569 stats->prc64++;
6570 stats->prc127--;
6571 } else if (frame_len == 127) {
6572 stats->prc127++;
6573 stats->prc255--;
6574 } else if (frame_len == 255) {
6575 stats->prc255++;
6576 stats->prc511--;
6577 } else if (frame_len == 511) {
6578 stats->prc511++;
6579 stats->prc1023--;
6580 } else if (frame_len == 1023) {
6581 stats->prc1023++;
6582 stats->prc1522--;
6583 } else if (frame_len == 1522) {
6584 stats->prc1522++;
6585 }
6586 }
6587
6588 /******************************************************************************
6589 * Gets the current PCI bus type, speed, and width of the hardware
6590 *
6591 * hw - Struct containing variables accessed by shared code
6592 *****************************************************************************/
6593 void
6594 e1000_get_bus_info(struct e1000_hw *hw)
6595 {
6596 int32_t ret_val;
6597 uint16_t pci_ex_link_status;
6598 uint32_t status;
6599
6600 switch (hw->mac_type) {
6601 case e1000_82542_rev2_0:
6602 case e1000_82542_rev2_1:
6603 hw->bus_type = e1000_bus_type_pci;
6604 hw->bus_speed = e1000_bus_speed_unknown;
6605 hw->bus_width = e1000_bus_width_unknown;
6606 break;
6607 case e1000_82571:
6608 case e1000_82572:
6609 case e1000_82573:
6610 case e1000_80003es2lan:
6611 hw->bus_type = e1000_bus_type_pci_express;
6612 hw->bus_speed = e1000_bus_speed_2500;
6613 ret_val = e1000_read_pcie_cap_reg(hw,
6614 PCI_EX_LINK_STATUS,
6615 &pci_ex_link_status);
6616 if (ret_val)
6617 hw->bus_width = e1000_bus_width_unknown;
6618 else
6619 hw->bus_width = (pci_ex_link_status & PCI_EX_LINK_WIDTH_MASK) >>
6620 PCI_EX_LINK_WIDTH_SHIFT;
6621 break;
6622 case e1000_ich8lan:
6623 hw->bus_type = e1000_bus_type_pci_express;
6624 hw->bus_speed = e1000_bus_speed_2500;
6625 hw->bus_width = e1000_bus_width_pciex_1;
6626 break;
6627 default:
6628 status = E1000_READ_REG(hw, STATUS);
6629 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
6630 e1000_bus_type_pcix : e1000_bus_type_pci;
6631
6632 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
6633 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
6634 e1000_bus_speed_66 : e1000_bus_speed_120;
6635 } else if (hw->bus_type == e1000_bus_type_pci) {
6636 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
6637 e1000_bus_speed_66 : e1000_bus_speed_33;
6638 } else {
6639 switch (status & E1000_STATUS_PCIX_SPEED) {
6640 case E1000_STATUS_PCIX_SPEED_66:
6641 hw->bus_speed = e1000_bus_speed_66;
6642 break;
6643 case E1000_STATUS_PCIX_SPEED_100:
6644 hw->bus_speed = e1000_bus_speed_100;
6645 break;
6646 case E1000_STATUS_PCIX_SPEED_133:
6647 hw->bus_speed = e1000_bus_speed_133;
6648 break;
6649 default:
6650 hw->bus_speed = e1000_bus_speed_reserved;
6651 break;
6652 }
6653 }
6654 hw->bus_width = (status & E1000_STATUS_BUS64) ?
6655 e1000_bus_width_64 : e1000_bus_width_32;
6656 break;
6657 }
6658 }
6659
6660 /******************************************************************************
6661 * Writes a value to one of the devices registers using port I/O (as opposed to
6662 * memory mapped I/O). Only 82544 and newer devices support port I/O.
6663 *
6664 * hw - Struct containing variables accessed by shared code
6665 * offset - offset to write to
6666 * value - value to write
6667 *****************************************************************************/
6668 static void
6669 e1000_write_reg_io(struct e1000_hw *hw,
6670 uint32_t offset,
6671 uint32_t value)
6672 {
6673 unsigned long io_addr = hw->io_base;
6674 unsigned long io_data = hw->io_base + 4;
6675
6676 e1000_io_write(hw, io_addr, offset);
6677 e1000_io_write(hw, io_data, value);
6678 }
6679
6680 /******************************************************************************
6681 * Estimates the cable length.
6682 *
6683 * hw - Struct containing variables accessed by shared code
6684 * min_length - The estimated minimum length
6685 * max_length - The estimated maximum length
6686 *
6687 * returns: - E1000_ERR_XXX
6688 * E1000_SUCCESS
6689 *
6690 * This function always returns a ranged length (minimum & maximum).
6691 * So for M88 phy's, this function interprets the one value returned from the
6692 * register to the minimum and maximum range.
6693 * For IGP phy's, the function calculates the range by the AGC registers.
6694 *****************************************************************************/
6695 static int32_t
6696 e1000_get_cable_length(struct e1000_hw *hw,
6697 uint16_t *min_length,
6698 uint16_t *max_length)
6699 {
6700 int32_t ret_val;
6701 uint16_t agc_value = 0;
6702 uint16_t i, phy_data;
6703 uint16_t cable_length;
6704
6705 DEBUGFUNC("e1000_get_cable_length");
6706
6707 *min_length = *max_length = 0;
6708
6709 /* Use old method for Phy older than IGP */
6710 if (hw->phy_type == e1000_phy_m88) {
6711
6712 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6713 &phy_data);
6714 if (ret_val)
6715 return ret_val;
6716 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
6717 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
6718
6719 /* Convert the enum value to ranged values */
6720 switch (cable_length) {
6721 case e1000_cable_length_50:
6722 *min_length = 0;
6723 *max_length = e1000_igp_cable_length_50;
6724 break;
6725 case e1000_cable_length_50_80:
6726 *min_length = e1000_igp_cable_length_50;
6727 *max_length = e1000_igp_cable_length_80;
6728 break;
6729 case e1000_cable_length_80_110:
6730 *min_length = e1000_igp_cable_length_80;
6731 *max_length = e1000_igp_cable_length_110;
6732 break;
6733 case e1000_cable_length_110_140:
6734 *min_length = e1000_igp_cable_length_110;
6735 *max_length = e1000_igp_cable_length_140;
6736 break;
6737 case e1000_cable_length_140:
6738 *min_length = e1000_igp_cable_length_140;
6739 *max_length = e1000_igp_cable_length_170;
6740 break;
6741 default:
6742 return -E1000_ERR_PHY;
6743 break;
6744 }
6745 } else if (hw->phy_type == e1000_phy_gg82563) {
6746 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
6747 &phy_data);
6748 if (ret_val)
6749 return ret_val;
6750 cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH;
6751
6752 switch (cable_length) {
6753 case e1000_gg_cable_length_60:
6754 *min_length = 0;
6755 *max_length = e1000_igp_cable_length_60;
6756 break;
6757 case e1000_gg_cable_length_60_115:
6758 *min_length = e1000_igp_cable_length_60;
6759 *max_length = e1000_igp_cable_length_115;
6760 break;
6761 case e1000_gg_cable_length_115_150:
6762 *min_length = e1000_igp_cable_length_115;
6763 *max_length = e1000_igp_cable_length_150;
6764 break;
6765 case e1000_gg_cable_length_150:
6766 *min_length = e1000_igp_cable_length_150;
6767 *max_length = e1000_igp_cable_length_180;
6768 break;
6769 default:
6770 return -E1000_ERR_PHY;
6771 break;
6772 }
6773 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
6774 uint16_t cur_agc_value;
6775 uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
6776 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6777 {IGP01E1000_PHY_AGC_A,
6778 IGP01E1000_PHY_AGC_B,
6779 IGP01E1000_PHY_AGC_C,
6780 IGP01E1000_PHY_AGC_D};
6781 /* Read the AGC registers for all channels */
6782 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
6783
6784 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6785 if (ret_val)
6786 return ret_val;
6787
6788 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
6789
6790 /* Value bound check. */
6791 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
6792 (cur_agc_value == 0))
6793 return -E1000_ERR_PHY;
6794
6795 agc_value += cur_agc_value;
6796
6797 /* Update minimal AGC value. */
6798 if (min_agc_value > cur_agc_value)
6799 min_agc_value = cur_agc_value;
6800 }
6801
6802 /* Remove the minimal AGC result for length < 50m */
6803 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
6804 agc_value -= min_agc_value;
6805
6806 /* Get the average length of the remaining 3 channels */
6807 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
6808 } else {
6809 /* Get the average length of all the 4 channels. */
6810 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
6811 }
6812
6813 /* Set the range of the calculated length. */
6814 *min_length = ((e1000_igp_cable_length_table[agc_value] -
6815 IGP01E1000_AGC_RANGE) > 0) ?
6816 (e1000_igp_cable_length_table[agc_value] -
6817 IGP01E1000_AGC_RANGE) : 0;
6818 *max_length = e1000_igp_cable_length_table[agc_value] +
6819 IGP01E1000_AGC_RANGE;
6820 } else if (hw->phy_type == e1000_phy_igp_2 ||
6821 hw->phy_type == e1000_phy_igp_3) {
6822 uint16_t cur_agc_index, max_agc_index = 0;
6823 uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1;
6824 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
6825 {IGP02E1000_PHY_AGC_A,
6826 IGP02E1000_PHY_AGC_B,
6827 IGP02E1000_PHY_AGC_C,
6828 IGP02E1000_PHY_AGC_D};
6829 /* Read the AGC registers for all channels */
6830 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
6831 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6832 if (ret_val)
6833 return ret_val;
6834
6835 /* Getting bits 15:9, which represent the combination of course and
6836 * fine gain values. The result is a number that can be put into
6837 * the lookup table to obtain the approximate cable length. */
6838 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
6839 IGP02E1000_AGC_LENGTH_MASK;
6840
6841 /* Array index bound check. */
6842 if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) ||
6843 (cur_agc_index == 0))
6844 return -E1000_ERR_PHY;
6845
6846 /* Remove min & max AGC values from calculation. */
6847 if (e1000_igp_2_cable_length_table[min_agc_index] >
6848 e1000_igp_2_cable_length_table[cur_agc_index])
6849 min_agc_index = cur_agc_index;
6850 if (e1000_igp_2_cable_length_table[max_agc_index] <
6851 e1000_igp_2_cable_length_table[cur_agc_index])
6852 max_agc_index = cur_agc_index;
6853
6854 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
6855 }
6856
6857 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
6858 e1000_igp_2_cable_length_table[max_agc_index]);
6859 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
6860
6861 /* Calculate cable length with the error range of +/- 10 meters. */
6862 *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
6863 (agc_value - IGP02E1000_AGC_RANGE) : 0;
6864 *max_length = agc_value + IGP02E1000_AGC_RANGE;
6865 }
6866
6867 return E1000_SUCCESS;
6868 }
6869
6870 /******************************************************************************
6871 * Check the cable polarity
6872 *
6873 * hw - Struct containing variables accessed by shared code
6874 * polarity - output parameter : 0 - Polarity is not reversed
6875 * 1 - Polarity is reversed.
6876 *
6877 * returns: - E1000_ERR_XXX
6878 * E1000_SUCCESS
6879 *
6880 * For phy's older then IGP, this function simply reads the polarity bit in the
6881 * Phy Status register. For IGP phy's, this bit is valid only if link speed is
6882 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
6883 * return 0. If the link speed is 1000 Mbps the polarity status is in the
6884 * IGP01E1000_PHY_PCS_INIT_REG.
6885 *****************************************************************************/
6886 static int32_t
6887 e1000_check_polarity(struct e1000_hw *hw,
6888 e1000_rev_polarity *polarity)
6889 {
6890 int32_t ret_val;
6891 uint16_t phy_data;
6892
6893 DEBUGFUNC("e1000_check_polarity");
6894
6895 if ((hw->phy_type == e1000_phy_m88) ||
6896 (hw->phy_type == e1000_phy_gg82563)) {
6897 /* return the Polarity bit in the Status register. */
6898 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6899 &phy_data);
6900 if (ret_val)
6901 return ret_val;
6902 *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >>
6903 M88E1000_PSSR_REV_POLARITY_SHIFT) ?
6904 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6905
6906 } else if (hw->phy_type == e1000_phy_igp ||
6907 hw->phy_type == e1000_phy_igp_3 ||
6908 hw->phy_type == e1000_phy_igp_2) {
6909 /* Read the Status register to check the speed */
6910 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
6911 &phy_data);
6912 if (ret_val)
6913 return ret_val;
6914
6915 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
6916 * find the polarity status */
6917 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
6918 IGP01E1000_PSSR_SPEED_1000MBPS) {
6919
6920 /* Read the GIG initialization PCS register (0x00B4) */
6921 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
6922 &phy_data);
6923 if (ret_val)
6924 return ret_val;
6925
6926 /* Check the polarity bits */
6927 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ?
6928 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6929 } else {
6930 /* For 10 Mbps, read the polarity bit in the status register. (for
6931 * 100 Mbps this bit is always 0) */
6932 *polarity = (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ?
6933 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6934 }
6935 } else if (hw->phy_type == e1000_phy_ife) {
6936 ret_val = e1000_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL,
6937 &phy_data);
6938 if (ret_val)
6939 return ret_val;
6940 *polarity = ((phy_data & IFE_PESC_POLARITY_REVERSED) >>
6941 IFE_PESC_POLARITY_REVERSED_SHIFT) ?
6942 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6943 }
6944 return E1000_SUCCESS;
6945 }
6946
6947 /******************************************************************************
6948 * Check if Downshift occured
6949 *
6950 * hw - Struct containing variables accessed by shared code
6951 * downshift - output parameter : 0 - No Downshift ocured.
6952 * 1 - Downshift ocured.
6953 *
6954 * returns: - E1000_ERR_XXX
6955 * E1000_SUCCESS
6956 *
6957 * For phy's older then IGP, this function reads the Downshift bit in the Phy
6958 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
6959 * Link Health register. In IGP this bit is latched high, so the driver must
6960 * read it immediately after link is established.
6961 *****************************************************************************/
6962 static int32_t
6963 e1000_check_downshift(struct e1000_hw *hw)
6964 {
6965 int32_t ret_val;
6966 uint16_t phy_data;
6967
6968 DEBUGFUNC("e1000_check_downshift");
6969
6970 if (hw->phy_type == e1000_phy_igp ||
6971 hw->phy_type == e1000_phy_igp_3 ||
6972 hw->phy_type == e1000_phy_igp_2) {
6973 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
6974 &phy_data);
6975 if (ret_val)
6976 return ret_val;
6977
6978 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
6979 } else if ((hw->phy_type == e1000_phy_m88) ||
6980 (hw->phy_type == e1000_phy_gg82563)) {
6981 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6982 &phy_data);
6983 if (ret_val)
6984 return ret_val;
6985
6986 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
6987 M88E1000_PSSR_DOWNSHIFT_SHIFT;
6988 } else if (hw->phy_type == e1000_phy_ife) {
6989 /* e1000_phy_ife supports 10/100 speed only */
6990 hw->speed_downgraded = FALSE;
6991 }
6992
6993 return E1000_SUCCESS;
6994 }
6995
6996 /*****************************************************************************
6997 *
6998 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
6999 * gigabit link is achieved to improve link quality.
7000 *
7001 * hw: Struct containing variables accessed by shared code
7002 *
7003 * returns: - E1000_ERR_PHY if fail to read/write the PHY
7004 * E1000_SUCCESS at any other case.
7005 *
7006 ****************************************************************************/
7007
7008 static int32_t
7009 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
7010 boolean_t link_up)
7011 {
7012 int32_t ret_val;
7013 uint16_t phy_data, phy_saved_data, speed, duplex, i;
7014 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
7015 {IGP01E1000_PHY_AGC_PARAM_A,
7016 IGP01E1000_PHY_AGC_PARAM_B,
7017 IGP01E1000_PHY_AGC_PARAM_C,
7018 IGP01E1000_PHY_AGC_PARAM_D};
7019 uint16_t min_length, max_length;
7020
7021 DEBUGFUNC("e1000_config_dsp_after_link_change");
7022
7023 if (hw->phy_type != e1000_phy_igp)
7024 return E1000_SUCCESS;
7025
7026 if (link_up) {
7027 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
7028 if (ret_val) {
7029 DEBUGOUT("Error getting link speed and duplex\n");
7030 return ret_val;
7031 }
7032
7033 if (speed == SPEED_1000) {
7034
7035 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
7036 if (ret_val)
7037 return ret_val;
7038
7039 if ((hw->dsp_config_state == e1000_dsp_config_enabled) &&
7040 min_length >= e1000_igp_cable_length_50) {
7041
7042 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
7043 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
7044 &phy_data);
7045 if (ret_val)
7046 return ret_val;
7047
7048 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
7049
7050 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
7051 phy_data);
7052 if (ret_val)
7053 return ret_val;
7054 }
7055 hw->dsp_config_state = e1000_dsp_config_activated;
7056 }
7057
7058 if ((hw->ffe_config_state == e1000_ffe_config_enabled) &&
7059 (min_length < e1000_igp_cable_length_50)) {
7060
7061 uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
7062 uint32_t idle_errs = 0;
7063
7064 /* clear previous idle error counts */
7065 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
7066 &phy_data);
7067 if (ret_val)
7068 return ret_val;
7069
7070 for (i = 0; i < ffe_idle_err_timeout; i++) {
7071 udelay(1000);
7072 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
7073 &phy_data);
7074 if (ret_val)
7075 return ret_val;
7076
7077 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
7078 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
7079 hw->ffe_config_state = e1000_ffe_config_active;
7080
7081 ret_val = e1000_write_phy_reg(hw,
7082 IGP01E1000_PHY_DSP_FFE,
7083 IGP01E1000_PHY_DSP_FFE_CM_CP);
7084 if (ret_val)
7085 return ret_val;
7086 break;
7087 }
7088
7089 if (idle_errs)
7090 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
7091 }
7092 }
7093 }
7094 } else {
7095 if (hw->dsp_config_state == e1000_dsp_config_activated) {
7096 /* Save off the current value of register 0x2F5B to be restored at
7097 * the end of the routines. */
7098 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7099
7100 if (ret_val)
7101 return ret_val;
7102
7103 /* Disable the PHY transmitter */
7104 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
7105
7106 if (ret_val)
7107 return ret_val;
7108
7109 mdelay(20);
7110
7111 ret_val = e1000_write_phy_reg(hw, 0x0000,
7112 IGP01E1000_IEEE_FORCE_GIGA);
7113 if (ret_val)
7114 return ret_val;
7115 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
7116 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
7117 if (ret_val)
7118 return ret_val;
7119
7120 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
7121 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
7122
7123 ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data);
7124 if (ret_val)
7125 return ret_val;
7126 }
7127
7128 ret_val = e1000_write_phy_reg(hw, 0x0000,
7129 IGP01E1000_IEEE_RESTART_AUTONEG);
7130 if (ret_val)
7131 return ret_val;
7132
7133 mdelay(20);
7134
7135 /* Now enable the transmitter */
7136 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7137
7138 if (ret_val)
7139 return ret_val;
7140
7141 hw->dsp_config_state = e1000_dsp_config_enabled;
7142 }
7143
7144 if (hw->ffe_config_state == e1000_ffe_config_active) {
7145 /* Save off the current value of register 0x2F5B to be restored at
7146 * the end of the routines. */
7147 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7148
7149 if (ret_val)
7150 return ret_val;
7151
7152 /* Disable the PHY transmitter */
7153 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
7154
7155 if (ret_val)
7156 return ret_val;
7157
7158 mdelay(20);
7159
7160 ret_val = e1000_write_phy_reg(hw, 0x0000,
7161 IGP01E1000_IEEE_FORCE_GIGA);
7162 if (ret_val)
7163 return ret_val;
7164 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
7165 IGP01E1000_PHY_DSP_FFE_DEFAULT);
7166 if (ret_val)
7167 return ret_val;
7168
7169 ret_val = e1000_write_phy_reg(hw, 0x0000,
7170 IGP01E1000_IEEE_RESTART_AUTONEG);
7171 if (ret_val)
7172 return ret_val;
7173
7174 mdelay(20);
7175
7176 /* Now enable the transmitter */
7177 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7178
7179 if (ret_val)
7180 return ret_val;
7181
7182 hw->ffe_config_state = e1000_ffe_config_enabled;
7183 }
7184 }
7185 return E1000_SUCCESS;
7186 }
7187
7188 /*****************************************************************************
7189 * Set PHY to class A mode
7190 * Assumes the following operations will follow to enable the new class mode.
7191 * 1. Do a PHY soft reset
7192 * 2. Restart auto-negotiation or force link.
7193 *
7194 * hw - Struct containing variables accessed by shared code
7195 ****************************************************************************/
7196 static int32_t
7197 e1000_set_phy_mode(struct e1000_hw *hw)
7198 {
7199 int32_t ret_val;
7200 uint16_t eeprom_data;
7201
7202 DEBUGFUNC("e1000_set_phy_mode");
7203
7204 if ((hw->mac_type == e1000_82545_rev_3) &&
7205 (hw->media_type == e1000_media_type_copper)) {
7206 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
7207 if (ret_val) {
7208 return ret_val;
7209 }
7210
7211 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
7212 (eeprom_data & EEPROM_PHY_CLASS_A)) {
7213 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
7214 if (ret_val)
7215 return ret_val;
7216 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
7217 if (ret_val)
7218 return ret_val;
7219
7220 hw->phy_reset_disable = FALSE;
7221 }
7222 }
7223
7224 return E1000_SUCCESS;
7225 }
7226
7227 /*****************************************************************************
7228 *
7229 * This function sets the lplu state according to the active flag. When
7230 * activating lplu this function also disables smart speed and vise versa.
7231 * lplu will not be activated unless the device autonegotiation advertisment
7232 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
7233 * hw: Struct containing variables accessed by shared code
7234 * active - true to enable lplu false to disable lplu.
7235 *
7236 * returns: - E1000_ERR_PHY if fail to read/write the PHY
7237 * E1000_SUCCESS at any other case.
7238 *
7239 ****************************************************************************/
7240
7241 static int32_t
7242 e1000_set_d3_lplu_state(struct e1000_hw *hw,
7243 boolean_t active)
7244 {
7245 uint32_t phy_ctrl = 0;
7246 int32_t ret_val;
7247 uint16_t phy_data;
7248 DEBUGFUNC("e1000_set_d3_lplu_state");
7249
7250 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
7251 && hw->phy_type != e1000_phy_igp_3)
7252 return E1000_SUCCESS;
7253
7254 /* During driver activity LPLU should not be used or it will attain link
7255 * from the lowest speeds starting from 10Mbps. The capability is used for
7256 * Dx transitions and states */
7257 if (hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
7258 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
7259 if (ret_val)
7260 return ret_val;
7261 } else if (hw->mac_type == e1000_ich8lan) {
7262 /* MAC writes into PHY register based on the state transition
7263 * and start auto-negotiation. SW driver can overwrite the settings
7264 * in CSR PHY power control E1000_PHY_CTRL register. */
7265 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
7266 } else {
7267 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7268 if (ret_val)
7269 return ret_val;
7270 }
7271
7272 if (!active) {
7273 if (hw->mac_type == e1000_82541_rev_2 ||
7274 hw->mac_type == e1000_82547_rev_2) {
7275 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
7276 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
7277 if (ret_val)
7278 return ret_val;
7279 } else {
7280 if (hw->mac_type == e1000_ich8lan) {
7281 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
7282 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7283 } else {
7284 phy_data &= ~IGP02E1000_PM_D3_LPLU;
7285 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7286 phy_data);
7287 if (ret_val)
7288 return ret_val;
7289 }
7290 }
7291
7292 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
7293 * Dx states where the power conservation is most important. During
7294 * driver activity we should enable SmartSpeed, so performance is
7295 * maintained. */
7296 if (hw->smart_speed == e1000_smart_speed_on) {
7297 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7298 &phy_data);
7299 if (ret_val)
7300 return ret_val;
7301
7302 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7303 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7304 phy_data);
7305 if (ret_val)
7306 return ret_val;
7307 } else if (hw->smart_speed == e1000_smart_speed_off) {
7308 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7309 &phy_data);
7310 if (ret_val)
7311 return ret_val;
7312
7313 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7314 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7315 phy_data);
7316 if (ret_val)
7317 return ret_val;
7318 }
7319
7320 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
7321 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
7322 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
7323
7324 if (hw->mac_type == e1000_82541_rev_2 ||
7325 hw->mac_type == e1000_82547_rev_2) {
7326 phy_data |= IGP01E1000_GMII_FLEX_SPD;
7327 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
7328 if (ret_val)
7329 return ret_val;
7330 } else {
7331 if (hw->mac_type == e1000_ich8lan) {
7332 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
7333 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7334 } else {
7335 phy_data |= IGP02E1000_PM_D3_LPLU;
7336 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7337 phy_data);
7338 if (ret_val)
7339 return ret_val;
7340 }
7341 }
7342
7343 /* When LPLU is enabled we should disable SmartSpeed */
7344 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
7345 if (ret_val)
7346 return ret_val;
7347
7348 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7349 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
7350 if (ret_val)
7351 return ret_val;
7352
7353 }
7354 return E1000_SUCCESS;
7355 }
7356
7357 /*****************************************************************************
7358 *
7359 * This function sets the lplu d0 state according to the active flag. When
7360 * activating lplu this function also disables smart speed and vise versa.
7361 * lplu will not be activated unless the device autonegotiation advertisment
7362 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
7363 * hw: Struct containing variables accessed by shared code
7364 * active - true to enable lplu false to disable lplu.
7365 *
7366 * returns: - E1000_ERR_PHY if fail to read/write the PHY
7367 * E1000_SUCCESS at any other case.
7368 *
7369 ****************************************************************************/
7370
7371 static int32_t
7372 e1000_set_d0_lplu_state(struct e1000_hw *hw,
7373 boolean_t active)
7374 {
7375 uint32_t phy_ctrl = 0;
7376 int32_t ret_val;
7377 uint16_t phy_data;
7378 DEBUGFUNC("e1000_set_d0_lplu_state");
7379
7380 if (hw->mac_type <= e1000_82547_rev_2)
7381 return E1000_SUCCESS;
7382
7383 if (hw->mac_type == e1000_ich8lan) {
7384 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
7385 } else {
7386 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7387 if (ret_val)
7388 return ret_val;
7389 }
7390
7391 if (!active) {
7392 if (hw->mac_type == e1000_ich8lan) {
7393 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
7394 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7395 } else {
7396 phy_data &= ~IGP02E1000_PM_D0_LPLU;
7397 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7398 if (ret_val)
7399 return ret_val;
7400 }
7401
7402 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
7403 * Dx states where the power conservation is most important. During
7404 * driver activity we should enable SmartSpeed, so performance is
7405 * maintained. */
7406 if (hw->smart_speed == e1000_smart_speed_on) {
7407 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7408 &phy_data);
7409 if (ret_val)
7410 return ret_val;
7411
7412 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7413 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7414 phy_data);
7415 if (ret_val)
7416 return ret_val;
7417 } else if (hw->smart_speed == e1000_smart_speed_off) {
7418 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7419 &phy_data);
7420 if (ret_val)
7421 return ret_val;
7422
7423 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7424 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7425 phy_data);
7426 if (ret_val)
7427 return ret_val;
7428 }
7429
7430
7431 } else {
7432
7433 if (hw->mac_type == e1000_ich8lan) {
7434 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
7435 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7436 } else {
7437 phy_data |= IGP02E1000_PM_D0_LPLU;
7438 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7439 if (ret_val)
7440 return ret_val;
7441 }
7442
7443 /* When LPLU is enabled we should disable SmartSpeed */
7444 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
7445 if (ret_val)
7446 return ret_val;
7447
7448 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7449 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
7450 if (ret_val)
7451 return ret_val;
7452
7453 }
7454 return E1000_SUCCESS;
7455 }
7456
7457 /******************************************************************************
7458 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
7459 *
7460 * hw - Struct containing variables accessed by shared code
7461 *****************************************************************************/
7462 static int32_t
7463 e1000_set_vco_speed(struct e1000_hw *hw)
7464 {
7465 int32_t ret_val;
7466 uint16_t default_page = 0;
7467 uint16_t phy_data;
7468
7469 DEBUGFUNC("e1000_set_vco_speed");
7470
7471 switch (hw->mac_type) {
7472 case e1000_82545_rev_3:
7473 case e1000_82546_rev_3:
7474 break;
7475 default:
7476 return E1000_SUCCESS;
7477 }
7478
7479 /* Set PHY register 30, page 5, bit 8 to 0 */
7480
7481 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
7482 if (ret_val)
7483 return ret_val;
7484
7485 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
7486 if (ret_val)
7487 return ret_val;
7488
7489 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
7490 if (ret_val)
7491 return ret_val;
7492
7493 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
7494 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
7495 if (ret_val)
7496 return ret_val;
7497
7498 /* Set PHY register 30, page 4, bit 11 to 1 */
7499
7500 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
7501 if (ret_val)
7502 return ret_val;
7503
7504 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
7505 if (ret_val)
7506 return ret_val;
7507
7508 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
7509 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
7510 if (ret_val)
7511 return ret_val;
7512
7513 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
7514 if (ret_val)
7515 return ret_val;
7516
7517 return E1000_SUCCESS;
7518 }
7519
7520
7521 /*****************************************************************************
7522 * This function reads the cookie from ARC ram.
7523 *
7524 * returns: - E1000_SUCCESS .
7525 ****************************************************************************/
7526 static int32_t
7527 e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer)
7528 {
7529 uint8_t i;
7530 uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET;
7531 uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH;
7532
7533 length = (length >> 2);
7534 offset = (offset >> 2);
7535
7536 for (i = 0; i < length; i++) {
7537 *((uint32_t *) buffer + i) =
7538 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i);
7539 }
7540 return E1000_SUCCESS;
7541 }
7542
7543
7544 /*****************************************************************************
7545 * This function checks whether the HOST IF is enabled for command operaton
7546 * and also checks whether the previous command is completed.
7547 * It busy waits in case of previous command is not completed.
7548 *
7549 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or
7550 * timeout
7551 * - E1000_SUCCESS for success.
7552 ****************************************************************************/
7553 static int32_t
7554 e1000_mng_enable_host_if(struct e1000_hw * hw)
7555 {
7556 uint32_t hicr;
7557 uint8_t i;
7558
7559 /* Check that the host interface is enabled. */
7560 hicr = E1000_READ_REG(hw, HICR);
7561 if ((hicr & E1000_HICR_EN) == 0) {
7562 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
7563 return -E1000_ERR_HOST_INTERFACE_COMMAND;
7564 }
7565 /* check the previous command is completed */
7566 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
7567 hicr = E1000_READ_REG(hw, HICR);
7568 if (!(hicr & E1000_HICR_C))
7569 break;
7570 mdelay(1);
7571 }
7572
7573 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
7574 DEBUGOUT("Previous command timeout failed .\n");
7575 return -E1000_ERR_HOST_INTERFACE_COMMAND;
7576 }
7577 return E1000_SUCCESS;
7578 }
7579
7580 /*****************************************************************************
7581 * This function writes the buffer content at the offset given on the host if.
7582 * It also does alignment considerations to do the writes in most efficient way.
7583 * Also fills up the sum of the buffer in *buffer parameter.
7584 *
7585 * returns - E1000_SUCCESS for success.
7586 ****************************************************************************/
7587 static int32_t
7588 e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer,
7589 uint16_t length, uint16_t offset, uint8_t *sum)
7590 {
7591 uint8_t *tmp;
7592 uint8_t *bufptr = buffer;
7593 uint32_t data = 0;
7594 uint16_t remaining, i, j, prev_bytes;
7595
7596 /* sum = only sum of the data and it is not checksum */
7597
7598 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
7599 return -E1000_ERR_PARAM;
7600 }
7601
7602 tmp = (uint8_t *)&data;
7603 prev_bytes = offset & 0x3;
7604 offset &= 0xFFFC;
7605 offset >>= 2;
7606
7607 if (prev_bytes) {
7608 data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset);
7609 for (j = prev_bytes; j < sizeof(uint32_t); j++) {
7610 *(tmp + j) = *bufptr++;
7611 *sum += *(tmp + j);
7612 }
7613 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data);
7614 length -= j - prev_bytes;
7615 offset++;
7616 }
7617
7618 remaining = length & 0x3;
7619 length -= remaining;
7620
7621 /* Calculate length in DWORDs */
7622 length >>= 2;
7623
7624 /* The device driver writes the relevant command block into the
7625 * ram area. */
7626 for (i = 0; i < length; i++) {
7627 for (j = 0; j < sizeof(uint32_t); j++) {
7628 *(tmp + j) = *bufptr++;
7629 *sum += *(tmp + j);
7630 }
7631
7632 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7633 }
7634 if (remaining) {
7635 for (j = 0; j < sizeof(uint32_t); j++) {
7636 if (j < remaining)
7637 *(tmp + j) = *bufptr++;
7638 else
7639 *(tmp + j) = 0;
7640
7641 *sum += *(tmp + j);
7642 }
7643 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7644 }
7645
7646 return E1000_SUCCESS;
7647 }
7648
7649
7650 /*****************************************************************************
7651 * This function writes the command header after does the checksum calculation.
7652 *
7653 * returns - E1000_SUCCESS for success.
7654 ****************************************************************************/
7655 static int32_t
7656 e1000_mng_write_cmd_header(struct e1000_hw * hw,
7657 struct e1000_host_mng_command_header * hdr)
7658 {
7659 uint16_t i;
7660 uint8_t sum;
7661 uint8_t *buffer;
7662
7663 /* Write the whole command header structure which includes sum of
7664 * the buffer */
7665
7666 uint16_t length = sizeof(struct e1000_host_mng_command_header);
7667
7668 sum = hdr->checksum;
7669 hdr->checksum = 0;
7670
7671 buffer = (uint8_t *) hdr;
7672 i = length;
7673 while (i--)
7674 sum += buffer[i];
7675
7676 hdr->checksum = 0 - sum;
7677
7678 length >>= 2;
7679 /* The device driver writes the relevant command block into the ram area. */
7680 for (i = 0; i < length; i++) {
7681 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i));
7682 E1000_WRITE_FLUSH(hw);
7683 }
7684
7685 return E1000_SUCCESS;
7686 }
7687
7688
7689 /*****************************************************************************
7690 * This function indicates to ARC that a new command is pending which completes
7691 * one write operation by the driver.
7692 *
7693 * returns - E1000_SUCCESS for success.
7694 ****************************************************************************/
7695 static int32_t
7696 e1000_mng_write_commit(struct e1000_hw * hw)
7697 {
7698 uint32_t hicr;
7699
7700 hicr = E1000_READ_REG(hw, HICR);
7701 /* Setting this bit tells the ARC that a new command is pending. */
7702 E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C);
7703
7704 return E1000_SUCCESS;
7705 }
7706
7707
7708 /*****************************************************************************
7709 * This function checks the mode of the firmware.
7710 *
7711 * returns - TRUE when the mode is IAMT or FALSE.
7712 ****************************************************************************/
7713 boolean_t
7714 e1000_check_mng_mode(struct e1000_hw *hw)
7715 {
7716 uint32_t fwsm;
7717
7718 fwsm = E1000_READ_REG(hw, FWSM);
7719
7720 if (hw->mac_type == e1000_ich8lan) {
7721 if ((fwsm & E1000_FWSM_MODE_MASK) ==
7722 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
7723 return TRUE;
7724 } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
7725 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
7726 return TRUE;
7727
7728 return FALSE;
7729 }
7730
7731
7732 /*****************************************************************************
7733 * This function writes the dhcp info .
7734 ****************************************************************************/
7735 int32_t
7736 e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer,
7737 uint16_t length)
7738 {
7739 int32_t ret_val;
7740 struct e1000_host_mng_command_header hdr;
7741
7742 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
7743 hdr.command_length = length;
7744 hdr.reserved1 = 0;
7745 hdr.reserved2 = 0;
7746 hdr.checksum = 0;
7747
7748 ret_val = e1000_mng_enable_host_if(hw);
7749 if (ret_val == E1000_SUCCESS) {
7750 ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr),
7751 &(hdr.checksum));
7752 if (ret_val == E1000_SUCCESS) {
7753 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
7754 if (ret_val == E1000_SUCCESS)
7755 ret_val = e1000_mng_write_commit(hw);
7756 }
7757 }
7758 return ret_val;
7759 }
7760
7761
7762 /*****************************************************************************
7763 * This function calculates the checksum.
7764 *
7765 * returns - checksum of buffer contents.
7766 ****************************************************************************/
7767 static uint8_t
7768 e1000_calculate_mng_checksum(char *buffer, uint32_t length)
7769 {
7770 uint8_t sum = 0;
7771 uint32_t i;
7772
7773 if (!buffer)
7774 return 0;
7775
7776 for (i=0; i < length; i++)
7777 sum += buffer[i];
7778
7779 return (uint8_t) (0 - sum);
7780 }
7781
7782 /*****************************************************************************
7783 * This function checks whether tx pkt filtering needs to be enabled or not.
7784 *
7785 * returns - TRUE for packet filtering or FALSE.
7786 ****************************************************************************/
7787 boolean_t
7788 e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
7789 {
7790 /* called in init as well as watchdog timer functions */
7791
7792 int32_t ret_val, checksum;
7793 boolean_t tx_filter = FALSE;
7794 struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
7795 uint8_t *buffer = (uint8_t *) &(hw->mng_cookie);
7796
7797 if (e1000_check_mng_mode(hw)) {
7798 ret_val = e1000_mng_enable_host_if(hw);
7799 if (ret_val == E1000_SUCCESS) {
7800 ret_val = e1000_host_if_read_cookie(hw, buffer);
7801 if (ret_val == E1000_SUCCESS) {
7802 checksum = hdr->checksum;
7803 hdr->checksum = 0;
7804 if ((hdr->signature == E1000_IAMT_SIGNATURE) &&
7805 checksum == e1000_calculate_mng_checksum((char *)buffer,
7806 E1000_MNG_DHCP_COOKIE_LENGTH)) {
7807 if (hdr->status &
7808 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT)
7809 tx_filter = TRUE;
7810 } else
7811 tx_filter = TRUE;
7812 } else
7813 tx_filter = TRUE;
7814 }
7815 }
7816
7817 hw->tx_pkt_filtering = tx_filter;
7818 return tx_filter;
7819 }
7820
7821 /******************************************************************************
7822 * Verifies the hardware needs to allow ARPs to be processed by the host
7823 *
7824 * hw - Struct containing variables accessed by shared code
7825 *
7826 * returns: - TRUE/FALSE
7827 *
7828 *****************************************************************************/
7829 uint32_t
7830 e1000_enable_mng_pass_thru(struct e1000_hw *hw)
7831 {
7832 uint32_t manc;
7833 uint32_t fwsm, factps;
7834
7835 if (hw->asf_firmware_present) {
7836 manc = E1000_READ_REG(hw, MANC);
7837
7838 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
7839 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
7840 return FALSE;
7841 if (e1000_arc_subsystem_valid(hw) == TRUE) {
7842 fwsm = E1000_READ_REG(hw, FWSM);
7843 factps = E1000_READ_REG(hw, FACTPS);
7844
7845 if ((((fwsm & E1000_FWSM_MODE_MASK) >> E1000_FWSM_MODE_SHIFT) ==
7846 e1000_mng_mode_pt) && !(factps & E1000_FACTPS_MNGCG))
7847 return TRUE;
7848 } else
7849 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
7850 return TRUE;
7851 }
7852 return FALSE;
7853 }
7854
7855 static int32_t
7856 e1000_polarity_reversal_workaround(struct e1000_hw *hw)
7857 {
7858 int32_t ret_val;
7859 uint16_t mii_status_reg;
7860 uint16_t i;
7861
7862 /* Polarity reversal workaround for forced 10F/10H links. */
7863
7864 /* Disable the transmitter on the PHY */
7865
7866 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
7867 if (ret_val)
7868 return ret_val;
7869 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
7870 if (ret_val)
7871 return ret_val;
7872
7873 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
7874 if (ret_val)
7875 return ret_val;
7876
7877 /* This loop will early-out if the NO link condition has been met. */
7878 for (i = PHY_FORCE_TIME; i > 0; i--) {
7879 /* Read the MII Status Register and wait for Link Status bit
7880 * to be clear.
7881 */
7882
7883 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7884 if (ret_val)
7885 return ret_val;
7886
7887 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7888 if (ret_val)
7889 return ret_val;
7890
7891 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break;
7892 mdelay(100);
7893 }
7894
7895 /* Recommended delay time after link has been lost */
7896 mdelay(1000);
7897
7898 /* Now we will re-enable th transmitter on the PHY */
7899
7900 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
7901 if (ret_val)
7902 return ret_val;
7903 mdelay(50);
7904 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
7905 if (ret_val)
7906 return ret_val;
7907 mdelay(50);
7908 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
7909 if (ret_val)
7910 return ret_val;
7911 mdelay(50);
7912 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
7913 if (ret_val)
7914 return ret_val;
7915
7916 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
7917 if (ret_val)
7918 return ret_val;
7919
7920 /* This loop will early-out if the link condition has been met. */
7921 for (i = PHY_FORCE_TIME; i > 0; i--) {
7922 /* Read the MII Status Register and wait for Link Status bit
7923 * to be set.
7924 */
7925
7926 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7927 if (ret_val)
7928 return ret_val;
7929
7930 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
7931 if (ret_val)
7932 return ret_val;
7933
7934 if (mii_status_reg & MII_SR_LINK_STATUS) break;
7935 mdelay(100);
7936 }
7937 return E1000_SUCCESS;
7938 }
7939
7940 /***************************************************************************
7941 *
7942 * Disables PCI-Express master access.
7943 *
7944 * hw: Struct containing variables accessed by shared code
7945 *
7946 * returns: - none.
7947 *
7948 ***************************************************************************/
7949 static void
7950 e1000_set_pci_express_master_disable(struct e1000_hw *hw)
7951 {
7952 uint32_t ctrl;
7953
7954 DEBUGFUNC("e1000_set_pci_express_master_disable");
7955
7956 if (hw->bus_type != e1000_bus_type_pci_express)
7957 return;
7958
7959 ctrl = E1000_READ_REG(hw, CTRL);
7960 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
7961 E1000_WRITE_REG(hw, CTRL, ctrl);
7962 }
7963
7964 /*******************************************************************************
7965 *
7966 * Disables PCI-Express master access and verifies there are no pending requests
7967 *
7968 * hw: Struct containing variables accessed by shared code
7969 *
7970 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't
7971 * caused the master requests to be disabled.
7972 * E1000_SUCCESS master requests disabled.
7973 *
7974 ******************************************************************************/
7975 int32_t
7976 e1000_disable_pciex_master(struct e1000_hw *hw)
7977 {
7978 int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */
7979
7980 DEBUGFUNC("e1000_disable_pciex_master");
7981
7982 if (hw->bus_type != e1000_bus_type_pci_express)
7983 return E1000_SUCCESS;
7984
7985 e1000_set_pci_express_master_disable(hw);
7986
7987 while (timeout) {
7988 if (!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
7989 break;
7990 else
7991 udelay(100);
7992 timeout--;
7993 }
7994
7995 if (!timeout) {
7996 DEBUGOUT("Master requests are pending.\n");
7997 return -E1000_ERR_MASTER_REQUESTS_PENDING;
7998 }
7999
8000 return E1000_SUCCESS;
8001 }
8002
8003 /*******************************************************************************
8004 *
8005 * Check for EEPROM Auto Read bit done.
8006 *
8007 * hw: Struct containing variables accessed by shared code
8008 *
8009 * returns: - E1000_ERR_RESET if fail to reset MAC
8010 * E1000_SUCCESS at any other case.
8011 *
8012 ******************************************************************************/
8013 static int32_t
8014 e1000_get_auto_rd_done(struct e1000_hw *hw)
8015 {
8016 int32_t timeout = AUTO_READ_DONE_TIMEOUT;
8017
8018 DEBUGFUNC("e1000_get_auto_rd_done");
8019
8020 switch (hw->mac_type) {
8021 default:
8022 msleep(5);
8023 break;
8024 case e1000_82571:
8025 case e1000_82572:
8026 case e1000_82573:
8027 case e1000_80003es2lan:
8028 case e1000_ich8lan:
8029 while (timeout) {
8030 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD)
8031 break;
8032 else msleep(1);
8033 timeout--;
8034 }
8035
8036 if (!timeout) {
8037 DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
8038 return -E1000_ERR_RESET;
8039 }
8040 break;
8041 }
8042
8043 /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high.
8044 * Need to wait for PHY configuration completion before accessing NVM
8045 * and PHY. */
8046 if (hw->mac_type == e1000_82573)
8047 msleep(25);
8048
8049 return E1000_SUCCESS;
8050 }
8051
8052 /***************************************************************************
8053 * Checks if the PHY configuration is done
8054 *
8055 * hw: Struct containing variables accessed by shared code
8056 *
8057 * returns: - E1000_ERR_RESET if fail to reset MAC
8058 * E1000_SUCCESS at any other case.
8059 *
8060 ***************************************************************************/
8061 static int32_t
8062 e1000_get_phy_cfg_done(struct e1000_hw *hw)
8063 {
8064 int32_t timeout = PHY_CFG_TIMEOUT;
8065 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
8066
8067 DEBUGFUNC("e1000_get_phy_cfg_done");
8068
8069 switch (hw->mac_type) {
8070 default:
8071 mdelay(10);
8072 break;
8073 case e1000_80003es2lan:
8074 /* Separate *_CFG_DONE_* bit for each port */
8075 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
8076 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
8077 /* Fall Through */
8078 case e1000_82571:
8079 case e1000_82572:
8080 while (timeout) {
8081 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
8082 break;
8083 else
8084 msleep(1);
8085 timeout--;
8086 }
8087 if (!timeout) {
8088 DEBUGOUT("MNG configuration cycle has not completed.\n");
8089 return -E1000_ERR_RESET;
8090 }
8091 break;
8092 }
8093
8094 return E1000_SUCCESS;
8095 }
8096
8097 /***************************************************************************
8098 *
8099 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
8100 * adapter or Eeprom access.
8101 *
8102 * hw: Struct containing variables accessed by shared code
8103 *
8104 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
8105 * E1000_SUCCESS at any other case.
8106 *
8107 ***************************************************************************/
8108 static int32_t
8109 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
8110 {
8111 int32_t timeout;
8112 uint32_t swsm;
8113
8114 DEBUGFUNC("e1000_get_hw_eeprom_semaphore");
8115
8116 if (!hw->eeprom_semaphore_present)
8117 return E1000_SUCCESS;
8118
8119 if (hw->mac_type == e1000_80003es2lan) {
8120 /* Get the SW semaphore. */
8121 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
8122 return -E1000_ERR_EEPROM;
8123 }
8124
8125 /* Get the FW semaphore. */
8126 timeout = hw->eeprom.word_size + 1;
8127 while (timeout) {
8128 swsm = E1000_READ_REG(hw, SWSM);
8129 swsm |= E1000_SWSM_SWESMBI;
8130 E1000_WRITE_REG(hw, SWSM, swsm);
8131 /* if we managed to set the bit we got the semaphore. */
8132 swsm = E1000_READ_REG(hw, SWSM);
8133 if (swsm & E1000_SWSM_SWESMBI)
8134 break;
8135
8136 udelay(50);
8137 timeout--;
8138 }
8139
8140 if (!timeout) {
8141 /* Release semaphores */
8142 e1000_put_hw_eeprom_semaphore(hw);
8143 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n");
8144 return -E1000_ERR_EEPROM;
8145 }
8146
8147 return E1000_SUCCESS;
8148 }
8149
8150 /***************************************************************************
8151 * This function clears HW semaphore bits.
8152 *
8153 * hw: Struct containing variables accessed by shared code
8154 *
8155 * returns: - None.
8156 *
8157 ***************************************************************************/
8158 static void
8159 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
8160 {
8161 uint32_t swsm;
8162
8163 DEBUGFUNC("e1000_put_hw_eeprom_semaphore");
8164
8165 if (!hw->eeprom_semaphore_present)
8166 return;
8167
8168 swsm = E1000_READ_REG(hw, SWSM);
8169 if (hw->mac_type == e1000_80003es2lan) {
8170 /* Release both semaphores. */
8171 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
8172 } else
8173 swsm &= ~(E1000_SWSM_SWESMBI);
8174 E1000_WRITE_REG(hw, SWSM, swsm);
8175 }
8176
8177 /***************************************************************************
8178 *
8179 * Obtaining software semaphore bit (SMBI) before resetting PHY.
8180 *
8181 * hw: Struct containing variables accessed by shared code
8182 *
8183 * returns: - E1000_ERR_RESET if fail to obtain semaphore.
8184 * E1000_SUCCESS at any other case.
8185 *
8186 ***************************************************************************/
8187 static int32_t
8188 e1000_get_software_semaphore(struct e1000_hw *hw)
8189 {
8190 int32_t timeout = hw->eeprom.word_size + 1;
8191 uint32_t swsm;
8192
8193 DEBUGFUNC("e1000_get_software_semaphore");
8194
8195 if (hw->mac_type != e1000_80003es2lan) {
8196 return E1000_SUCCESS;
8197 }
8198
8199 while (timeout) {
8200 swsm = E1000_READ_REG(hw, SWSM);
8201 /* If SMBI bit cleared, it is now set and we hold the semaphore */
8202 if (!(swsm & E1000_SWSM_SMBI))
8203 break;
8204 mdelay(1);
8205 timeout--;
8206 }
8207
8208 if (!timeout) {
8209 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
8210 return -E1000_ERR_RESET;
8211 }
8212
8213 return E1000_SUCCESS;
8214 }
8215
8216 /***************************************************************************
8217 *
8218 * Release semaphore bit (SMBI).
8219 *
8220 * hw: Struct containing variables accessed by shared code
8221 *
8222 ***************************************************************************/
8223 static void
8224 e1000_release_software_semaphore(struct e1000_hw *hw)
8225 {
8226 uint32_t swsm;
8227
8228 DEBUGFUNC("e1000_release_software_semaphore");
8229
8230 if (hw->mac_type != e1000_80003es2lan) {
8231 return;
8232 }
8233
8234 swsm = E1000_READ_REG(hw, SWSM);
8235 /* Release the SW semaphores.*/
8236 swsm &= ~E1000_SWSM_SMBI;
8237 E1000_WRITE_REG(hw, SWSM, swsm);
8238 }
8239
8240 /******************************************************************************
8241 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
8242 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
8243 * the caller to figure out how to deal with it.
8244 *
8245 * hw - Struct containing variables accessed by shared code
8246 *
8247 * returns: - E1000_BLK_PHY_RESET
8248 * E1000_SUCCESS
8249 *
8250 *****************************************************************************/
8251 int32_t
8252 e1000_check_phy_reset_block(struct e1000_hw *hw)
8253 {
8254 uint32_t manc = 0;
8255 uint32_t fwsm = 0;
8256
8257 if (hw->mac_type == e1000_ich8lan) {
8258 fwsm = E1000_READ_REG(hw, FWSM);
8259 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
8260 : E1000_BLK_PHY_RESET;
8261 }
8262
8263 if (hw->mac_type > e1000_82547_rev_2)
8264 manc = E1000_READ_REG(hw, MANC);
8265 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
8266 E1000_BLK_PHY_RESET : E1000_SUCCESS;
8267 }
8268
8269 static uint8_t
8270 e1000_arc_subsystem_valid(struct e1000_hw *hw)
8271 {
8272 uint32_t fwsm;
8273
8274 /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC
8275 * may not be provided a DMA clock when no manageability features are
8276 * enabled. We do not want to perform any reads/writes to these registers
8277 * if this is the case. We read FWSM to determine the manageability mode.
8278 */
8279 switch (hw->mac_type) {
8280 case e1000_82571:
8281 case e1000_82572:
8282 case e1000_82573:
8283 case e1000_80003es2lan:
8284 fwsm = E1000_READ_REG(hw, FWSM);
8285 if ((fwsm & E1000_FWSM_MODE_MASK) != 0)
8286 return TRUE;
8287 break;
8288 case e1000_ich8lan:
8289 return TRUE;
8290 default:
8291 break;
8292 }
8293 return FALSE;
8294 }
8295
8296
8297 /******************************************************************************
8298 * Configure PCI-Ex no-snoop
8299 *
8300 * hw - Struct containing variables accessed by shared code.
8301 * no_snoop - Bitmap of no-snoop events.
8302 *
8303 * returns: E1000_SUCCESS
8304 *
8305 *****************************************************************************/
8306 static int32_t
8307 e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop)
8308 {
8309 uint32_t gcr_reg = 0;
8310
8311 DEBUGFUNC("e1000_set_pci_ex_no_snoop");
8312
8313 if (hw->bus_type == e1000_bus_type_unknown)
8314 e1000_get_bus_info(hw);
8315
8316 if (hw->bus_type != e1000_bus_type_pci_express)
8317 return E1000_SUCCESS;
8318
8319 if (no_snoop) {
8320 gcr_reg = E1000_READ_REG(hw, GCR);
8321 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL);
8322 gcr_reg |= no_snoop;
8323 E1000_WRITE_REG(hw, GCR, gcr_reg);
8324 }
8325 if (hw->mac_type == e1000_ich8lan) {
8326 uint32_t ctrl_ext;
8327
8328 E1000_WRITE_REG(hw, GCR, PCI_EX_82566_SNOOP_ALL);
8329
8330 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
8331 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
8332 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
8333 }
8334
8335 return E1000_SUCCESS;
8336 }
8337
8338 /***************************************************************************
8339 *
8340 * Get software semaphore FLAG bit (SWFLAG).
8341 * SWFLAG is used to synchronize the access to all shared resource between
8342 * SW, FW and HW.
8343 *
8344 * hw: Struct containing variables accessed by shared code
8345 *
8346 ***************************************************************************/
8347 static int32_t
8348 e1000_get_software_flag(struct e1000_hw *hw)
8349 {
8350 int32_t timeout = PHY_CFG_TIMEOUT;
8351 uint32_t extcnf_ctrl;
8352
8353 DEBUGFUNC("e1000_get_software_flag");
8354
8355 if (hw->mac_type == e1000_ich8lan) {
8356 while (timeout) {
8357 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8358 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
8359 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8360
8361 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8362 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
8363 break;
8364 mdelay(1);
8365 timeout--;
8366 }
8367
8368 if (!timeout) {
8369 DEBUGOUT("FW or HW locks the resource too long.\n");
8370 return -E1000_ERR_CONFIG;
8371 }
8372 }
8373
8374 return E1000_SUCCESS;
8375 }
8376
8377 /***************************************************************************
8378 *
8379 * Release software semaphore FLAG bit (SWFLAG).
8380 * SWFLAG is used to synchronize the access to all shared resource between
8381 * SW, FW and HW.
8382 *
8383 * hw: Struct containing variables accessed by shared code
8384 *
8385 ***************************************************************************/
8386 static void
8387 e1000_release_software_flag(struct e1000_hw *hw)
8388 {
8389 uint32_t extcnf_ctrl;
8390
8391 DEBUGFUNC("e1000_release_software_flag");
8392
8393 if (hw->mac_type == e1000_ich8lan) {
8394 extcnf_ctrl= E1000_READ_REG(hw, EXTCNF_CTRL);
8395 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
8396 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8397 }
8398
8399 return;
8400 }
8401
8402 /******************************************************************************
8403 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access
8404 * register.
8405 *
8406 * hw - Struct containing variables accessed by shared code
8407 * offset - offset of word in the EEPROM to read
8408 * data - word read from the EEPROM
8409 * words - number of words to read
8410 *****************************************************************************/
8411 static int32_t
8412 e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
8413 uint16_t *data)
8414 {
8415 int32_t error = E1000_SUCCESS;
8416 uint32_t flash_bank = 0;
8417 uint32_t act_offset = 0;
8418 uint32_t bank_offset = 0;
8419 uint16_t word = 0;
8420 uint16_t i = 0;
8421
8422 /* We need to know which is the valid flash bank. In the event
8423 * that we didn't allocate eeprom_shadow_ram, we may not be
8424 * managing flash_bank. So it cannot be trusted and needs
8425 * to be updated with each read.
8426 */
8427 /* Value of bit 22 corresponds to the flash bank we're on. */
8428 flash_bank = (E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL) ? 1 : 0;
8429
8430 /* Adjust offset appropriately if we're on bank 1 - adjust for word size */
8431 bank_offset = flash_bank * (hw->flash_bank_size * 2);
8432
8433 error = e1000_get_software_flag(hw);
8434 if (error != E1000_SUCCESS)
8435 return error;
8436
8437 for (i = 0; i < words; i++) {
8438 if (hw->eeprom_shadow_ram != NULL &&
8439 hw->eeprom_shadow_ram[offset+i].modified == TRUE) {
8440 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word;
8441 } else {
8442 /* The NVM part needs a byte offset, hence * 2 */
8443 act_offset = bank_offset + ((offset + i) * 2);
8444 error = e1000_read_ich8_word(hw, act_offset, &word);
8445 if (error != E1000_SUCCESS)
8446 break;
8447 data[i] = word;
8448 }
8449 }
8450
8451 e1000_release_software_flag(hw);
8452
8453 return error;
8454 }
8455
8456 /******************************************************************************
8457 * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access
8458 * register. Actually, writes are written to the shadow ram cache in the hw
8459 * structure hw->e1000_shadow_ram. e1000_commit_shadow_ram flushes this to
8460 * the NVM, which occurs when the NVM checksum is updated.
8461 *
8462 * hw - Struct containing variables accessed by shared code
8463 * offset - offset of word in the EEPROM to write
8464 * words - number of words to write
8465 * data - words to write to the EEPROM
8466 *****************************************************************************/
8467 static int32_t
8468 e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
8469 uint16_t *data)
8470 {
8471 uint32_t i = 0;
8472 int32_t error = E1000_SUCCESS;
8473
8474 error = e1000_get_software_flag(hw);
8475 if (error != E1000_SUCCESS)
8476 return error;
8477
8478 /* A driver can write to the NVM only if it has eeprom_shadow_ram
8479 * allocated. Subsequent reads to the modified words are read from
8480 * this cached structure as well. Writes will only go into this
8481 * cached structure unless it's followed by a call to
8482 * e1000_update_eeprom_checksum() where it will commit the changes
8483 * and clear the "modified" field.
8484 */
8485 if (hw->eeprom_shadow_ram != NULL) {
8486 for (i = 0; i < words; i++) {
8487 if ((offset + i) < E1000_SHADOW_RAM_WORDS) {
8488 hw->eeprom_shadow_ram[offset+i].modified = TRUE;
8489 hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i];
8490 } else {
8491 error = -E1000_ERR_EEPROM;
8492 break;
8493 }
8494 }
8495 } else {
8496 /* Drivers have the option to not allocate eeprom_shadow_ram as long
8497 * as they don't perform any NVM writes. An attempt in doing so
8498 * will result in this error.
8499 */
8500 error = -E1000_ERR_EEPROM;
8501 }
8502
8503 e1000_release_software_flag(hw);
8504
8505 return error;
8506 }
8507
8508 /******************************************************************************
8509 * This function does initial flash setup so that a new read/write/erase cycle
8510 * can be started.
8511 *
8512 * hw - The pointer to the hw structure
8513 ****************************************************************************/
8514 static int32_t
8515 e1000_ich8_cycle_init(struct e1000_hw *hw)
8516 {
8517 union ich8_hws_flash_status hsfsts;
8518 int32_t error = E1000_ERR_EEPROM;
8519 int32_t i = 0;
8520
8521 DEBUGFUNC("e1000_ich8_cycle_init");
8522
8523 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8524
8525 /* May be check the Flash Des Valid bit in Hw status */
8526 if (hsfsts.hsf_status.fldesvalid == 0) {
8527 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.");
8528 return error;
8529 }
8530
8531 /* Clear FCERR in Hw status by writing 1 */
8532 /* Clear DAEL in Hw status by writing a 1 */
8533 hsfsts.hsf_status.flcerr = 1;
8534 hsfsts.hsf_status.dael = 1;
8535
8536 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
8537
8538 /* Either we should have a hardware SPI cycle in progress bit to check
8539 * against, in order to start a new cycle or FDONE bit should be changed
8540 * in the hardware so that it is 1 after harware reset, which can then be
8541 * used as an indication whether a cycle is in progress or has been
8542 * completed .. we should also have some software semaphore mechanism to
8543 * guard FDONE or the cycle in progress bit so that two threads access to
8544 * those bits can be sequentiallized or a way so that 2 threads dont
8545 * start the cycle at the same time */
8546
8547 if (hsfsts.hsf_status.flcinprog == 0) {
8548 /* There is no cycle running at present, so we can start a cycle */
8549 /* Begin by setting Flash Cycle Done. */
8550 hsfsts.hsf_status.flcdone = 1;
8551 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
8552 error = E1000_SUCCESS;
8553 } else {
8554 /* otherwise poll for sometime so the current cycle has a chance
8555 * to end before giving up. */
8556 for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) {
8557 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8558 if (hsfsts.hsf_status.flcinprog == 0) {
8559 error = E1000_SUCCESS;
8560 break;
8561 }
8562 udelay(1);
8563 }
8564 if (error == E1000_SUCCESS) {
8565 /* Successful in waiting for previous cycle to timeout,
8566 * now set the Flash Cycle Done. */
8567 hsfsts.hsf_status.flcdone = 1;
8568 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
8569 } else {
8570 DEBUGOUT("Flash controller busy, cannot get access");
8571 }
8572 }
8573 return error;
8574 }
8575
8576 /******************************************************************************
8577 * This function starts a flash cycle and waits for its completion
8578 *
8579 * hw - The pointer to the hw structure
8580 ****************************************************************************/
8581 static int32_t
8582 e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout)
8583 {
8584 union ich8_hws_flash_ctrl hsflctl;
8585 union ich8_hws_flash_status hsfsts;
8586 int32_t error = E1000_ERR_EEPROM;
8587 uint32_t i = 0;
8588
8589 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
8590 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8591 hsflctl.hsf_ctrl.flcgo = 1;
8592 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8593
8594 /* wait till FDONE bit is set to 1 */
8595 do {
8596 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8597 if (hsfsts.hsf_status.flcdone == 1)
8598 break;
8599 udelay(1);
8600 i++;
8601 } while (i < timeout);
8602 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) {
8603 error = E1000_SUCCESS;
8604 }
8605 return error;
8606 }
8607
8608 /******************************************************************************
8609 * Reads a byte or word from the NVM using the ICH8 flash access registers.
8610 *
8611 * hw - The pointer to the hw structure
8612 * index - The index of the byte or word to read.
8613 * size - Size of data to read, 1=byte 2=word
8614 * data - Pointer to the word to store the value read.
8615 *****************************************************************************/
8616 static int32_t
8617 e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index,
8618 uint32_t size, uint16_t* data)
8619 {
8620 union ich8_hws_flash_status hsfsts;
8621 union ich8_hws_flash_ctrl hsflctl;
8622 uint32_t flash_linear_address;
8623 uint32_t flash_data = 0;
8624 int32_t error = -E1000_ERR_EEPROM;
8625 int32_t count = 0;
8626
8627 DEBUGFUNC("e1000_read_ich8_data");
8628
8629 if (size < 1 || size > 2 || data == 0x0 ||
8630 index > ICH_FLASH_LINEAR_ADDR_MASK)
8631 return error;
8632
8633 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
8634 hw->flash_base_addr;
8635
8636 do {
8637 udelay(1);
8638 /* Steps */
8639 error = e1000_ich8_cycle_init(hw);
8640 if (error != E1000_SUCCESS)
8641 break;
8642
8643 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8644 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8645 hsflctl.hsf_ctrl.fldbcount = size - 1;
8646 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
8647 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8648
8649 /* Write the last 24 bits of index into Flash Linear address field in
8650 * Flash Address */
8651 /* TODO: TBD maybe check the index against the size of flash */
8652
8653 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
8654
8655 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
8656
8657 /* Check if FCERR is set to 1, if set to 1, clear it and try the whole
8658 * sequence a few more times, else read in (shift in) the Flash Data0,
8659 * the order is least significant byte first msb to lsb */
8660 if (error == E1000_SUCCESS) {
8661 flash_data = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0);
8662 if (size == 1) {
8663 *data = (uint8_t)(flash_data & 0x000000FF);
8664 } else if (size == 2) {
8665 *data = (uint16_t)(flash_data & 0x0000FFFF);
8666 }
8667 break;
8668 } else {
8669 /* If we've gotten here, then things are probably completely hosed,
8670 * but if the error condition is detected, it won't hurt to give
8671 * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
8672 */
8673 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8674 if (hsfsts.hsf_status.flcerr == 1) {
8675 /* Repeat for some time before giving up. */
8676 continue;
8677 } else if (hsfsts.hsf_status.flcdone == 0) {
8678 DEBUGOUT("Timeout error - flash cycle did not complete.");
8679 break;
8680 }
8681 }
8682 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
8683
8684 return error;
8685 }
8686
8687 /******************************************************************************
8688 * Writes One /two bytes to the NVM using the ICH8 flash access registers.
8689 *
8690 * hw - The pointer to the hw structure
8691 * index - The index of the byte/word to read.
8692 * size - Size of data to read, 1=byte 2=word
8693 * data - The byte(s) to write to the NVM.
8694 *****************************************************************************/
8695 static int32_t
8696 e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size,
8697 uint16_t data)
8698 {
8699 union ich8_hws_flash_status hsfsts;
8700 union ich8_hws_flash_ctrl hsflctl;
8701 uint32_t flash_linear_address;
8702 uint32_t flash_data = 0;
8703 int32_t error = -E1000_ERR_EEPROM;
8704 int32_t count = 0;
8705
8706 DEBUGFUNC("e1000_write_ich8_data");
8707
8708 if (size < 1 || size > 2 || data > size * 0xff ||
8709 index > ICH_FLASH_LINEAR_ADDR_MASK)
8710 return error;
8711
8712 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
8713 hw->flash_base_addr;
8714
8715 do {
8716 udelay(1);
8717 /* Steps */
8718 error = e1000_ich8_cycle_init(hw);
8719 if (error != E1000_SUCCESS)
8720 break;
8721
8722 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8723 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8724 hsflctl.hsf_ctrl.fldbcount = size -1;
8725 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
8726 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8727
8728 /* Write the last 24 bits of index into Flash Linear address field in
8729 * Flash Address */
8730 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
8731
8732 if (size == 1)
8733 flash_data = (uint32_t)data & 0x00FF;
8734 else
8735 flash_data = (uint32_t)data;
8736
8737 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
8738
8739 /* check if FCERR is set to 1 , if set to 1, clear it and try the whole
8740 * sequence a few more times else done */
8741 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
8742 if (error == E1000_SUCCESS) {
8743 break;
8744 } else {
8745 /* If we're here, then things are most likely completely hosed,
8746 * but if the error condition is detected, it won't hurt to give
8747 * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
8748 */
8749 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8750 if (hsfsts.hsf_status.flcerr == 1) {
8751 /* Repeat for some time before giving up. */
8752 continue;
8753 } else if (hsfsts.hsf_status.flcdone == 0) {
8754 DEBUGOUT("Timeout error - flash cycle did not complete.");
8755 break;
8756 }
8757 }
8758 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
8759
8760 return error;
8761 }
8762
8763 /******************************************************************************
8764 * Reads a single byte from the NVM using the ICH8 flash access registers.
8765 *
8766 * hw - pointer to e1000_hw structure
8767 * index - The index of the byte to read.
8768 * data - Pointer to a byte to store the value read.
8769 *****************************************************************************/
8770 static int32_t
8771 e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t* data)
8772 {
8773 int32_t status = E1000_SUCCESS;
8774 uint16_t word = 0;
8775
8776 status = e1000_read_ich8_data(hw, index, 1, &word);
8777 if (status == E1000_SUCCESS) {
8778 *data = (uint8_t)word;
8779 }
8780
8781 return status;
8782 }
8783
8784 /******************************************************************************
8785 * Writes a single byte to the NVM using the ICH8 flash access registers.
8786 * Performs verification by reading back the value and then going through
8787 * a retry algorithm before giving up.
8788 *
8789 * hw - pointer to e1000_hw structure
8790 * index - The index of the byte to write.
8791 * byte - The byte to write to the NVM.
8792 *****************************************************************************/
8793 static int32_t
8794 e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte)
8795 {
8796 int32_t error = E1000_SUCCESS;
8797 int32_t program_retries = 0;
8798
8799 DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index);
8800
8801 error = e1000_write_ich8_byte(hw, index, byte);
8802
8803 if (error != E1000_SUCCESS) {
8804 for (program_retries = 0; program_retries < 100; program_retries++) {
8805 DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n", byte, index);
8806 error = e1000_write_ich8_byte(hw, index, byte);
8807 udelay(100);
8808 if (error == E1000_SUCCESS)
8809 break;
8810 }
8811 }
8812
8813 if (program_retries == 100)
8814 error = E1000_ERR_EEPROM;
8815
8816 return error;
8817 }
8818
8819 /******************************************************************************
8820 * Writes a single byte to the NVM using the ICH8 flash access registers.
8821 *
8822 * hw - pointer to e1000_hw structure
8823 * index - The index of the byte to read.
8824 * data - The byte to write to the NVM.
8825 *****************************************************************************/
8826 static int32_t
8827 e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t data)
8828 {
8829 int32_t status = E1000_SUCCESS;
8830 uint16_t word = (uint16_t)data;
8831
8832 status = e1000_write_ich8_data(hw, index, 1, word);
8833
8834 return status;
8835 }
8836
8837 /******************************************************************************
8838 * Reads a word from the NVM using the ICH8 flash access registers.
8839 *
8840 * hw - pointer to e1000_hw structure
8841 * index - The starting byte index of the word to read.
8842 * data - Pointer to a word to store the value read.
8843 *****************************************************************************/
8844 static int32_t
8845 e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data)
8846 {
8847 int32_t status = E1000_SUCCESS;
8848 status = e1000_read_ich8_data(hw, index, 2, data);
8849 return status;
8850 }
8851
8852 /******************************************************************************
8853 * Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0
8854 * based.
8855 *
8856 * hw - pointer to e1000_hw structure
8857 * bank - 0 for first bank, 1 for second bank
8858 *
8859 * Note that this function may actually erase as much as 8 or 64 KBytes. The
8860 * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the
8861 * bank size may be 4, 8 or 64 KBytes
8862 *****************************************************************************/
8863 int32_t
8864 e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank)
8865 {
8866 union ich8_hws_flash_status hsfsts;
8867 union ich8_hws_flash_ctrl hsflctl;
8868 uint32_t flash_linear_address;
8869 int32_t count = 0;
8870 int32_t error = E1000_ERR_EEPROM;
8871 int32_t iteration;
8872 int32_t sub_sector_size = 0;
8873 int32_t bank_size;
8874 int32_t j = 0;
8875 int32_t error_flag = 0;
8876
8877 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8878
8879 /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */
8880 /* 00: The Hw sector is 256 bytes, hence we need to erase 16
8881 * consecutive sectors. The start index for the nth Hw sector can be
8882 * calculated as bank * 4096 + n * 256
8883 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
8884 * The start index for the nth Hw sector can be calculated
8885 * as bank * 4096
8886 * 10: The HW sector is 8K bytes
8887 * 11: The Hw sector size is 64K bytes */
8888 if (hsfsts.hsf_status.berasesz == 0x0) {
8889 /* Hw sector size 256 */
8890 sub_sector_size = ICH_FLASH_SEG_SIZE_256;
8891 bank_size = ICH_FLASH_SECTOR_SIZE;
8892 iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256;
8893 } else if (hsfsts.hsf_status.berasesz == 0x1) {
8894 bank_size = ICH_FLASH_SEG_SIZE_4K;
8895 iteration = 1;
8896 } else if (hsfsts.hsf_status.berasesz == 0x3) {
8897 bank_size = ICH_FLASH_SEG_SIZE_64K;
8898 iteration = 1;
8899 } else {
8900 return error;
8901 }
8902
8903 for (j = 0; j < iteration ; j++) {
8904 do {
8905 count++;
8906 /* Steps */
8907 error = e1000_ich8_cycle_init(hw);
8908 if (error != E1000_SUCCESS) {
8909 error_flag = 1;
8910 break;
8911 }
8912
8913 /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash
8914 * Control */
8915 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8916 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
8917 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8918
8919 /* Write the last 24 bits of an index within the block into Flash
8920 * Linear address field in Flash Address. This probably needs to
8921 * be calculated here based off the on-chip erase sector size and
8922 * the software bank size (4, 8 or 64 KBytes) */
8923 flash_linear_address = bank * bank_size + j * sub_sector_size;
8924 flash_linear_address += hw->flash_base_addr;
8925 flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK;
8926
8927 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
8928
8929 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT);
8930 /* Check if FCERR is set to 1. If 1, clear it and try the whole
8931 * sequence a few more times else Done */
8932 if (error == E1000_SUCCESS) {
8933 break;
8934 } else {
8935 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8936 if (hsfsts.hsf_status.flcerr == 1) {
8937 /* repeat for some time before giving up */
8938 continue;
8939 } else if (hsfsts.hsf_status.flcdone == 0) {
8940 error_flag = 1;
8941 break;
8942 }
8943 }
8944 } while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag);
8945 if (error_flag == 1)
8946 break;
8947 }
8948 if (error_flag != 1)
8949 error = E1000_SUCCESS;
8950 return error;
8951 }
8952
8953 static int32_t
8954 e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
8955 uint32_t cnf_base_addr, uint32_t cnf_size)
8956 {
8957 uint32_t ret_val = E1000_SUCCESS;
8958 uint16_t word_addr, reg_data, reg_addr;
8959 uint16_t i;
8960
8961 /* cnf_base_addr is in DWORD */
8962 word_addr = (uint16_t)(cnf_base_addr << 1);
8963
8964 /* cnf_size is returned in size of dwords */
8965 for (i = 0; i < cnf_size; i++) {
8966 ret_val = e1000_read_eeprom(hw, (word_addr + i*2), 1, &reg_data);
8967 if (ret_val)
8968 return ret_val;
8969
8970 ret_val = e1000_read_eeprom(hw, (word_addr + i*2 + 1), 1, &reg_addr);
8971 if (ret_val)
8972 return ret_val;
8973
8974 ret_val = e1000_get_software_flag(hw);
8975 if (ret_val != E1000_SUCCESS)
8976 return ret_val;
8977
8978 ret_val = e1000_write_phy_reg_ex(hw, (uint32_t)reg_addr, reg_data);
8979
8980 e1000_release_software_flag(hw);
8981 }
8982
8983 return ret_val;
8984 }
8985
8986
8987 /******************************************************************************
8988 * This function initializes the PHY from the NVM on ICH8 platforms. This
8989 * is needed due to an issue where the NVM configuration is not properly
8990 * autoloaded after power transitions. Therefore, after each PHY reset, we
8991 * will load the configuration data out of the NVM manually.
8992 *
8993 * hw: Struct containing variables accessed by shared code
8994 *****************************************************************************/
8995 static int32_t
8996 e1000_init_lcd_from_nvm(struct e1000_hw *hw)
8997 {
8998 uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop;
8999
9000 if (hw->phy_type != e1000_phy_igp_3)
9001 return E1000_SUCCESS;
9002
9003 /* Check if SW needs configure the PHY */
9004 reg_data = E1000_READ_REG(hw, FEXTNVM);
9005 if (!(reg_data & FEXTNVM_SW_CONFIG))
9006 return E1000_SUCCESS;
9007
9008 /* Wait for basic configuration completes before proceeding*/
9009 loop = 0;
9010 do {
9011 reg_data = E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE;
9012 udelay(100);
9013 loop++;
9014 } while ((!reg_data) && (loop < 50));
9015
9016 /* Clear the Init Done bit for the next init event */
9017 reg_data = E1000_READ_REG(hw, STATUS);
9018 reg_data &= ~E1000_STATUS_LAN_INIT_DONE;
9019 E1000_WRITE_REG(hw, STATUS, reg_data);
9020
9021 /* Make sure HW does not configure LCD from PHY extended configuration
9022 before SW configuration */
9023 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
9024 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) {
9025 reg_data = E1000_READ_REG(hw, EXTCNF_SIZE);
9026 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH;
9027 cnf_size >>= 16;
9028 if (cnf_size) {
9029 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
9030 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER;
9031 /* cnf_base_addr is in DWORD */
9032 cnf_base_addr >>= 16;
9033
9034 /* Configure LCD from extended configuration region. */
9035 ret_val = e1000_init_lcd_from_nvm_config_region(hw, cnf_base_addr,
9036 cnf_size);
9037 if (ret_val)
9038 return ret_val;
9039 }
9040 }
9041
9042 return E1000_SUCCESS;
9043 }
9044
WRT350N Kernel Patches