?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
V4L/DVB (6006): tuner: move last_div to tuner-simple private data
[wrt350n-kernel.git] / drivers / media / video / pvrusb2 / pvrusb2-hdw.c
blob1311891e7ee3dd0d85acc751c0ad40362271e3c4
1 /*
2 *
3 * $Id$
4 *
5 * Copyright (C) 2005 Mike Isely <isely@pobox.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 */
21
22 #include <linux/errno.h>
23 #include <linux/string.h>
24 #include <linux/slab.h>
25 #include <linux/firmware.h>
26 #include <linux/videodev2.h>
27 #include <media/v4l2-common.h>
28 #include <asm/semaphore.h>
29 #include "pvrusb2.h"
30 #include "pvrusb2-std.h"
31 #include "pvrusb2-util.h"
32 #include "pvrusb2-hdw.h"
33 #include "pvrusb2-i2c-core.h"
34 #include "pvrusb2-tuner.h"
35 #include "pvrusb2-eeprom.h"
36 #include "pvrusb2-hdw-internal.h"
37 #include "pvrusb2-encoder.h"
38 #include "pvrusb2-debug.h"
39 #include "pvrusb2-fx2-cmd.h"
40
41 #define TV_MIN_FREQ 55250000L
42 #define TV_MAX_FREQ 850000000L
43
44 struct usb_device_id pvr2_device_table[] = {
45 [PVR2_HDW_TYPE_29XXX] = { USB_DEVICE(0x2040, 0x2900) },
46 [PVR2_HDW_TYPE_24XXX] = { USB_DEVICE(0x2040, 0x2400) },
47 { }
48 };
49
50 MODULE_DEVICE_TABLE(usb, pvr2_device_table);
51
52 static const char *pvr2_device_names[] = {
53 [PVR2_HDW_TYPE_29XXX] = "WinTV PVR USB2 Model Category 29xxxx",
54 [PVR2_HDW_TYPE_24XXX] = "WinTV PVR USB2 Model Category 24xxxx",
55 };
56
57 struct pvr2_string_table {
58 const char **lst;
59 unsigned int cnt;
60 };
61
62 // Names of other client modules to request for 24xxx model hardware
63 static const char *pvr2_client_24xxx[] = {
64 "cx25840",
65 "tuner",
66 "wm8775",
67 };
68
69 // Names of other client modules to request for 29xxx model hardware
70 static const char *pvr2_client_29xxx[] = {
71 "msp3400",
72 "saa7115",
73 "tuner",
74 };
75
76 static struct pvr2_string_table pvr2_client_lists[] = {
77 [PVR2_HDW_TYPE_29XXX] = {
78 pvr2_client_29xxx, ARRAY_SIZE(pvr2_client_29xxx)
79 },
80 [PVR2_HDW_TYPE_24XXX] = {
81 pvr2_client_24xxx, ARRAY_SIZE(pvr2_client_24xxx)
82 },
83 };
84
85 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
86 static DEFINE_MUTEX(pvr2_unit_mtx);
87
88 static int ctlchg = 0;
89 static int initusbreset = 1;
90 static int procreload = 0;
91 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
92 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
93 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
94 static int init_pause_msec = 0;
95
96 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
97 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
98 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
99 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
100 module_param(initusbreset, int, S_IRUGO|S_IWUSR);
101 MODULE_PARM_DESC(initusbreset, "Do USB reset device on probe");
102 module_param(procreload, int, S_IRUGO|S_IWUSR);
103 MODULE_PARM_DESC(procreload,
104 "Attempt init failure recovery with firmware reload");
105 module_param_array(tuner, int, NULL, 0444);
106 MODULE_PARM_DESC(tuner,"specify installed tuner type");
107 module_param_array(video_std, int, NULL, 0444);
108 MODULE_PARM_DESC(video_std,"specify initial video standard");
109 module_param_array(tolerance, int, NULL, 0444);
110 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
111
112 #define PVR2_CTL_WRITE_ENDPOINT 0x01
113 #define PVR2_CTL_READ_ENDPOINT 0x81
114
115 #define PVR2_GPIO_IN 0x9008
116 #define PVR2_GPIO_OUT 0x900c
117 #define PVR2_GPIO_DIR 0x9020
118
119 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
120
121 #define PVR2_FIRMWARE_ENDPOINT 0x02
122
123 /* size of a firmware chunk */
124 #define FIRMWARE_CHUNK_SIZE 0x2000
125
126 /* Define the list of additional controls we'll dynamically construct based
127 on query of the cx2341x module. */
128 struct pvr2_mpeg_ids {
129 const char *strid;
130 int id;
131 };
132 static const struct pvr2_mpeg_ids mpeg_ids[] = {
133 {
134 .strid = "audio_layer",
135 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
136 },{
137 .strid = "audio_bitrate",
138 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
139 },{
140 /* Already using audio_mode elsewhere :-( */
141 .strid = "mpeg_audio_mode",
142 .id = V4L2_CID_MPEG_AUDIO_MODE,
143 },{
144 .strid = "mpeg_audio_mode_extension",
145 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
146 },{
147 .strid = "audio_emphasis",
148 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
149 },{
150 .strid = "audio_crc",
151 .id = V4L2_CID_MPEG_AUDIO_CRC,
152 },{
153 .strid = "video_aspect",
154 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
155 },{
156 .strid = "video_b_frames",
157 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
158 },{
159 .strid = "video_gop_size",
160 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
161 },{
162 .strid = "video_gop_closure",
163 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
164 },{
165 .strid = "video_bitrate_mode",
166 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
167 },{
168 .strid = "video_bitrate",
169 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
170 },{
171 .strid = "video_bitrate_peak",
172 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
173 },{
174 .strid = "video_temporal_decimation",
175 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
176 },{
177 .strid = "stream_type",
178 .id = V4L2_CID_MPEG_STREAM_TYPE,
179 },{
180 .strid = "video_spatial_filter_mode",
181 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
182 },{
183 .strid = "video_spatial_filter",
184 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
185 },{
186 .strid = "video_luma_spatial_filter_type",
187 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
188 },{
189 .strid = "video_chroma_spatial_filter_type",
190 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
191 },{
192 .strid = "video_temporal_filter_mode",
193 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
194 },{
195 .strid = "video_temporal_filter",
196 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
197 },{
198 .strid = "video_median_filter_type",
199 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
200 },{
201 .strid = "video_luma_median_filter_top",
202 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
203 },{
204 .strid = "video_luma_median_filter_bottom",
205 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
206 },{
207 .strid = "video_chroma_median_filter_top",
208 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
209 },{
210 .strid = "video_chroma_median_filter_bottom",
211 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
212 }
213 };
214 #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
215
216
217 static const char *control_values_srate[] = {
218 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz",
219 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz",
220 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz",
221 };
222
223
224
225 static const char *control_values_input[] = {
226 [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/
227 [PVR2_CVAL_INPUT_RADIO] = "radio",
228 [PVR2_CVAL_INPUT_SVIDEO] = "s-video",
229 [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
230 };
231
232
233 static const char *control_values_audiomode[] = {
234 [V4L2_TUNER_MODE_MONO] = "Mono",
235 [V4L2_TUNER_MODE_STEREO] = "Stereo",
236 [V4L2_TUNER_MODE_LANG1] = "Lang1",
237 [V4L2_TUNER_MODE_LANG2] = "Lang2",
238 [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
239 };
240
241
242 static const char *control_values_hsm[] = {
243 [PVR2_CVAL_HSM_FAIL] = "Fail",
244 [PVR2_CVAL_HSM_HIGH] = "High",
245 [PVR2_CVAL_HSM_FULL] = "Full",
246 };
247
248
249 static const char *control_values_subsystem[] = {
250 [PVR2_SUBSYS_B_ENC_FIRMWARE] = "enc_firmware",
251 [PVR2_SUBSYS_B_ENC_CFG] = "enc_config",
252 [PVR2_SUBSYS_B_DIGITIZER_RUN] = "digitizer_run",
253 [PVR2_SUBSYS_B_USBSTREAM_RUN] = "usbstream_run",
254 [PVR2_SUBSYS_B_ENC_RUN] = "enc_run",
255 };
256
257 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
258 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
259 static int pvr2_hdw_commit_ctl_internal(struct pvr2_hdw *hdw);
260 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
261 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
262 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
263 static void pvr2_hdw_render_useless_unlocked(struct pvr2_hdw *hdw);
264 static void pvr2_hdw_subsys_bit_chg_no_lock(struct pvr2_hdw *hdw,
265 unsigned long msk,
266 unsigned long val);
267 static void pvr2_hdw_subsys_stream_bit_chg_no_lock(struct pvr2_hdw *hdw,
268 unsigned long msk,
269 unsigned long val);
270 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
271 unsigned int timeout,int probe_fl,
272 void *write_data,unsigned int write_len,
273 void *read_data,unsigned int read_len);
274
275 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
276 {
277 struct pvr2_hdw *hdw = cptr->hdw;
278 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
279 *vp = hdw->freqTable[hdw->freqProgSlot-1];
280 } else {
281 *vp = 0;
282 }
283 return 0;
284 }
285
286 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
287 {
288 struct pvr2_hdw *hdw = cptr->hdw;
289 unsigned int slotId = hdw->freqProgSlot;
290 if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
291 hdw->freqTable[slotId-1] = v;
292 /* Handle side effects correctly - if we're tuned to this
293 slot, then forgot the slot id relation since the stored
294 frequency has been changed. */
295 if (hdw->freqSelector) {
296 if (hdw->freqSlotRadio == slotId) {
297 hdw->freqSlotRadio = 0;
298 }
299 } else {
300 if (hdw->freqSlotTelevision == slotId) {
301 hdw->freqSlotTelevision = 0;
302 }
303 }
304 }
305 return 0;
306 }
307
308 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
309 {
310 *vp = cptr->hdw->freqProgSlot;
311 return 0;
312 }
313
314 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
315 {
316 struct pvr2_hdw *hdw = cptr->hdw;
317 if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
318 hdw->freqProgSlot = v;
319 }
320 return 0;
321 }
322
323 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
324 {
325 struct pvr2_hdw *hdw = cptr->hdw;
326 *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
327 return 0;
328 }
329
330 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
331 {
332 unsigned freq = 0;
333 struct pvr2_hdw *hdw = cptr->hdw;
334 if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
335 if (slotId > 0) {
336 freq = hdw->freqTable[slotId-1];
337 if (!freq) return 0;
338 pvr2_hdw_set_cur_freq(hdw,freq);
339 }
340 if (hdw->freqSelector) {
341 hdw->freqSlotRadio = slotId;
342 } else {
343 hdw->freqSlotTelevision = slotId;
344 }
345 return 0;
346 }
347
348 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
349 {
350 *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
351 return 0;
352 }
353
354 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
355 {
356 return cptr->hdw->freqDirty != 0;
357 }
358
359 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
360 {
361 cptr->hdw->freqDirty = 0;
362 }
363
364 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
365 {
366 pvr2_hdw_set_cur_freq(cptr->hdw,v);
367 return 0;
368 }
369
370 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
371 {
372 /* Actual maximum depends on the video standard in effect. */
373 if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
374 *vp = 480;
375 } else {
376 *vp = 576;
377 }
378 return 0;
379 }
380
381 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
382 {
383 /* Actual minimum depends on device type. */
384 if (cptr->hdw->hdw_type == PVR2_HDW_TYPE_24XXX) {
385 *vp = 75;
386 } else {
387 *vp = 17;
388 }
389 return 0;
390 }
391
392 static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
393 {
394 *vp = cptr->hdw->input_val;
395 return 0;
396 }
397
398 static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
399 {
400 struct pvr2_hdw *hdw = cptr->hdw;
401
402 if (hdw->input_val != v) {
403 hdw->input_val = v;
404 hdw->input_dirty = !0;
405 }
406
407 /* Handle side effects - if we switch to a mode that needs the RF
408 tuner, then select the right frequency choice as well and mark
409 it dirty. */
410 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
411 hdw->freqSelector = 0;
412 hdw->freqDirty = !0;
413 } else if (hdw->input_val == PVR2_CVAL_INPUT_TV) {
414 hdw->freqSelector = 1;
415 hdw->freqDirty = !0;
416 }
417 return 0;
418 }
419
420 static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
421 {
422 return cptr->hdw->input_dirty != 0;
423 }
424
425 static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
426 {
427 cptr->hdw->input_dirty = 0;
428 }
429
430
431 static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
432 {
433 unsigned long fv;
434 struct pvr2_hdw *hdw = cptr->hdw;
435 if (hdw->tuner_signal_stale) {
436 pvr2_i2c_core_status_poll(hdw);
437 }
438 fv = hdw->tuner_signal_info.rangehigh;
439 if (!fv) {
440 /* Safety fallback */
441 *vp = TV_MAX_FREQ;
442 return 0;
443 }
444 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
445 fv = (fv * 125) / 2;
446 } else {
447 fv = fv * 62500;
448 }
449 *vp = fv;
450 return 0;
451 }
452
453 static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
454 {
455 unsigned long fv;
456 struct pvr2_hdw *hdw = cptr->hdw;
457 if (hdw->tuner_signal_stale) {
458 pvr2_i2c_core_status_poll(hdw);
459 }
460 fv = hdw->tuner_signal_info.rangelow;
461 if (!fv) {
462 /* Safety fallback */
463 *vp = TV_MIN_FREQ;
464 return 0;
465 }
466 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
467 fv = (fv * 125) / 2;
468 } else {
469 fv = fv * 62500;
470 }
471 *vp = fv;
472 return 0;
473 }
474
475 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
476 {
477 return cptr->hdw->enc_stale != 0;
478 }
479
480 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
481 {
482 cptr->hdw->enc_stale = 0;
483 }
484
485 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
486 {
487 int ret;
488 struct v4l2_ext_controls cs;
489 struct v4l2_ext_control c1;
490 memset(&cs,0,sizeof(cs));
491 memset(&c1,0,sizeof(c1));
492 cs.controls = &c1;
493 cs.count = 1;
494 c1.id = cptr->info->v4l_id;
495 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state,&cs,
496 VIDIOC_G_EXT_CTRLS);
497 if (ret) return ret;
498 *vp = c1.value;
499 return 0;
500 }
501
502 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
503 {
504 int ret;
505 struct v4l2_ext_controls cs;
506 struct v4l2_ext_control c1;
507 memset(&cs,0,sizeof(cs));
508 memset(&c1,0,sizeof(c1));
509 cs.controls = &c1;
510 cs.count = 1;
511 c1.id = cptr->info->v4l_id;
512 c1.value = v;
513 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state,&cs,
514 VIDIOC_S_EXT_CTRLS);
515 if (ret) return ret;
516 cptr->hdw->enc_stale = !0;
517 return 0;
518 }
519
520 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
521 {
522 struct v4l2_queryctrl qctrl;
523 struct pvr2_ctl_info *info;
524 qctrl.id = cptr->info->v4l_id;
525 cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
526 /* Strip out the const so we can adjust a function pointer. It's
527 OK to do this here because we know this is a dynamically created
528 control, so the underlying storage for the info pointer is (a)
529 private to us, and (b) not in read-only storage. Either we do
530 this or we significantly complicate the underlying control
531 implementation. */
532 info = (struct pvr2_ctl_info *)(cptr->info);
533 if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
534 if (info->set_value) {
535 info->set_value = NULL;
536 }
537 } else {
538 if (!(info->set_value)) {
539 info->set_value = ctrl_cx2341x_set;
540 }
541 }
542 return qctrl.flags;
543 }
544
545 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
546 {
547 *vp = cptr->hdw->flag_streaming_enabled;
548 return 0;
549 }
550
551 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
552 {
553 int result = pvr2_hdw_is_hsm(cptr->hdw);
554 *vp = PVR2_CVAL_HSM_FULL;
555 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
556 if (result) *vp = PVR2_CVAL_HSM_HIGH;
557 return 0;
558 }
559
560 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
561 {
562 *vp = cptr->hdw->std_mask_avail;
563 return 0;
564 }
565
566 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
567 {
568 struct pvr2_hdw *hdw = cptr->hdw;
569 v4l2_std_id ns;
570 ns = hdw->std_mask_avail;
571 ns = (ns & ~m) | (v & m);
572 if (ns == hdw->std_mask_avail) return 0;
573 hdw->std_mask_avail = ns;
574 pvr2_hdw_internal_set_std_avail(hdw);
575 pvr2_hdw_internal_find_stdenum(hdw);
576 return 0;
577 }
578
579 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
580 char *bufPtr,unsigned int bufSize,
581 unsigned int *len)
582 {
583 *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
584 return 0;
585 }
586
587 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
588 const char *bufPtr,unsigned int bufSize,
589 int *mskp,int *valp)
590 {
591 int ret;
592 v4l2_std_id id;
593 ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
594 if (ret < 0) return ret;
595 if (mskp) *mskp = id;
596 if (valp) *valp = id;
597 return 0;
598 }
599
600 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
601 {
602 *vp = cptr->hdw->std_mask_cur;
603 return 0;
604 }
605
606 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
607 {
608 struct pvr2_hdw *hdw = cptr->hdw;
609 v4l2_std_id ns;
610 ns = hdw->std_mask_cur;
611 ns = (ns & ~m) | (v & m);
612 if (ns == hdw->std_mask_cur) return 0;
613 hdw->std_mask_cur = ns;
614 hdw->std_dirty = !0;
615 pvr2_hdw_internal_find_stdenum(hdw);
616 return 0;
617 }
618
619 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
620 {
621 return cptr->hdw->std_dirty != 0;
622 }
623
624 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
625 {
626 cptr->hdw->std_dirty = 0;
627 }
628
629 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
630 {
631 struct pvr2_hdw *hdw = cptr->hdw;
632 pvr2_i2c_core_status_poll(hdw);
633 *vp = hdw->tuner_signal_info.signal;
634 return 0;
635 }
636
637 static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
638 {
639 int val = 0;
640 unsigned int subchan;
641 struct pvr2_hdw *hdw = cptr->hdw;
642 pvr2_i2c_core_status_poll(hdw);
643 subchan = hdw->tuner_signal_info.rxsubchans;
644 if (subchan & V4L2_TUNER_SUB_MONO) {
645 val |= (1 << V4L2_TUNER_MODE_MONO);
646 }
647 if (subchan & V4L2_TUNER_SUB_STEREO) {
648 val |= (1 << V4L2_TUNER_MODE_STEREO);
649 }
650 if (subchan & V4L2_TUNER_SUB_LANG1) {
651 val |= (1 << V4L2_TUNER_MODE_LANG1);
652 }
653 if (subchan & V4L2_TUNER_SUB_LANG2) {
654 val |= (1 << V4L2_TUNER_MODE_LANG2);
655 }
656 *vp = val;
657 return 0;
658 }
659
660 static int ctrl_subsys_get(struct pvr2_ctrl *cptr,int *vp)
661 {
662 *vp = cptr->hdw->subsys_enabled_mask;
663 return 0;
664 }
665
666 static int ctrl_subsys_set(struct pvr2_ctrl *cptr,int m,int v)
667 {
668 pvr2_hdw_subsys_bit_chg_no_lock(cptr->hdw,m,v);
669 return 0;
670 }
671
672 static int ctrl_subsys_stream_get(struct pvr2_ctrl *cptr,int *vp)
673 {
674 *vp = cptr->hdw->subsys_stream_mask;
675 return 0;
676 }
677
678 static int ctrl_subsys_stream_set(struct pvr2_ctrl *cptr,int m,int v)
679 {
680 pvr2_hdw_subsys_stream_bit_chg_no_lock(cptr->hdw,m,v);
681 return 0;
682 }
683
684 static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
685 {
686 struct pvr2_hdw *hdw = cptr->hdw;
687 if (v < 0) return -EINVAL;
688 if (v > hdw->std_enum_cnt) return -EINVAL;
689 hdw->std_enum_cur = v;
690 if (!v) return 0;
691 v--;
692 if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
693 hdw->std_mask_cur = hdw->std_defs[v].id;
694 hdw->std_dirty = !0;
695 return 0;
696 }
697
698
699 static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
700 {
701 *vp = cptr->hdw->std_enum_cur;
702 return 0;
703 }
704
705
706 static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
707 {
708 return cptr->hdw->std_dirty != 0;
709 }
710
711
712 static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
713 {
714 cptr->hdw->std_dirty = 0;
715 }
716
717
718 #define DEFINT(vmin,vmax) \
719 .type = pvr2_ctl_int, \
720 .def.type_int.min_value = vmin, \
721 .def.type_int.max_value = vmax
722
723 #define DEFENUM(tab) \
724 .type = pvr2_ctl_enum, \
725 .def.type_enum.count = ARRAY_SIZE(tab), \
726 .def.type_enum.value_names = tab
727
728 #define DEFBOOL \
729 .type = pvr2_ctl_bool
730
731 #define DEFMASK(msk,tab) \
732 .type = pvr2_ctl_bitmask, \
733 .def.type_bitmask.valid_bits = msk, \
734 .def.type_bitmask.bit_names = tab
735
736 #define DEFREF(vname) \
737 .set_value = ctrl_set_##vname, \
738 .get_value = ctrl_get_##vname, \
739 .is_dirty = ctrl_isdirty_##vname, \
740 .clear_dirty = ctrl_cleardirty_##vname
741
742
743 #define VCREATE_FUNCS(vname) \
744 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
745 {*vp = cptr->hdw->vname##_val; return 0;} \
746 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
747 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
748 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
749 {return cptr->hdw->vname##_dirty != 0;} \
750 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
751 {cptr->hdw->vname##_dirty = 0;}
752
753 VCREATE_FUNCS(brightness)
754 VCREATE_FUNCS(contrast)
755 VCREATE_FUNCS(saturation)
756 VCREATE_FUNCS(hue)
757 VCREATE_FUNCS(volume)
758 VCREATE_FUNCS(balance)
759 VCREATE_FUNCS(bass)
760 VCREATE_FUNCS(treble)
761 VCREATE_FUNCS(mute)
762 VCREATE_FUNCS(audiomode)
763 VCREATE_FUNCS(res_hor)
764 VCREATE_FUNCS(res_ver)
765 VCREATE_FUNCS(srate)
766
767 /* Table definition of all controls which can be manipulated */
768 static const struct pvr2_ctl_info control_defs[] = {
769 {
770 .v4l_id = V4L2_CID_BRIGHTNESS,
771 .desc = "Brightness",
772 .name = "brightness",
773 .default_value = 128,
774 DEFREF(brightness),
775 DEFINT(0,255),
776 },{
777 .v4l_id = V4L2_CID_CONTRAST,
778 .desc = "Contrast",
779 .name = "contrast",
780 .default_value = 68,
781 DEFREF(contrast),
782 DEFINT(0,127),
783 },{
784 .v4l_id = V4L2_CID_SATURATION,
785 .desc = "Saturation",
786 .name = "saturation",
787 .default_value = 64,
788 DEFREF(saturation),
789 DEFINT(0,127),
790 },{
791 .v4l_id = V4L2_CID_HUE,
792 .desc = "Hue",
793 .name = "hue",
794 .default_value = 0,
795 DEFREF(hue),
796 DEFINT(-128,127),
797 },{
798 .v4l_id = V4L2_CID_AUDIO_VOLUME,
799 .desc = "Volume",
800 .name = "volume",
801 .default_value = 62000,
802 DEFREF(volume),
803 DEFINT(0,65535),
804 },{
805 .v4l_id = V4L2_CID_AUDIO_BALANCE,
806 .desc = "Balance",
807 .name = "balance",
808 .default_value = 0,
809 DEFREF(balance),
810 DEFINT(-32768,32767),
811 },{
812 .v4l_id = V4L2_CID_AUDIO_BASS,
813 .desc = "Bass",
814 .name = "bass",
815 .default_value = 0,
816 DEFREF(bass),
817 DEFINT(-32768,32767),
818 },{
819 .v4l_id = V4L2_CID_AUDIO_TREBLE,
820 .desc = "Treble",
821 .name = "treble",
822 .default_value = 0,
823 DEFREF(treble),
824 DEFINT(-32768,32767),
825 },{
826 .v4l_id = V4L2_CID_AUDIO_MUTE,
827 .desc = "Mute",
828 .name = "mute",
829 .default_value = 0,
830 DEFREF(mute),
831 DEFBOOL,
832 },{
833 .desc = "Video Source",
834 .name = "input",
835 .internal_id = PVR2_CID_INPUT,
836 .default_value = PVR2_CVAL_INPUT_TV,
837 DEFREF(input),
838 DEFENUM(control_values_input),
839 },{
840 .desc = "Audio Mode",
841 .name = "audio_mode",
842 .internal_id = PVR2_CID_AUDIOMODE,
843 .default_value = V4L2_TUNER_MODE_STEREO,
844 DEFREF(audiomode),
845 DEFENUM(control_values_audiomode),
846 },{
847 .desc = "Horizontal capture resolution",
848 .name = "resolution_hor",
849 .internal_id = PVR2_CID_HRES,
850 .default_value = 720,
851 DEFREF(res_hor),
852 DEFINT(19,720),
853 },{
854 .desc = "Vertical capture resolution",
855 .name = "resolution_ver",
856 .internal_id = PVR2_CID_VRES,
857 .default_value = 480,
858 DEFREF(res_ver),
859 DEFINT(17,576),
860 /* Hook in check for video standard and adjust maximum
861 depending on the standard. */
862 .get_max_value = ctrl_vres_max_get,
863 .get_min_value = ctrl_vres_min_get,
864 },{
865 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
866 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
867 .desc = "Audio Sampling Frequency",
868 .name = "srate",
869 DEFREF(srate),
870 DEFENUM(control_values_srate),
871 },{
872 .desc = "Tuner Frequency (Hz)",
873 .name = "frequency",
874 .internal_id = PVR2_CID_FREQUENCY,
875 .default_value = 0,
876 .set_value = ctrl_freq_set,
877 .get_value = ctrl_freq_get,
878 .is_dirty = ctrl_freq_is_dirty,
879 .clear_dirty = ctrl_freq_clear_dirty,
880 DEFINT(0,0),
881 /* Hook in check for input value (tv/radio) and adjust
882 max/min values accordingly */
883 .get_max_value = ctrl_freq_max_get,
884 .get_min_value = ctrl_freq_min_get,
885 },{
886 .desc = "Channel",
887 .name = "channel",
888 .set_value = ctrl_channel_set,
889 .get_value = ctrl_channel_get,
890 DEFINT(0,FREQTABLE_SIZE),
891 },{
892 .desc = "Channel Program Frequency",
893 .name = "freq_table_value",
894 .set_value = ctrl_channelfreq_set,
895 .get_value = ctrl_channelfreq_get,
896 DEFINT(0,0),
897 /* Hook in check for input value (tv/radio) and adjust
898 max/min values accordingly */
899 .get_max_value = ctrl_freq_max_get,
900 .get_min_value = ctrl_freq_min_get,
901 },{
902 .desc = "Channel Program ID",
903 .name = "freq_table_channel",
904 .set_value = ctrl_channelprog_set,
905 .get_value = ctrl_channelprog_get,
906 DEFINT(0,FREQTABLE_SIZE),
907 },{
908 .desc = "Streaming Enabled",
909 .name = "streaming_enabled",
910 .get_value = ctrl_streamingenabled_get,
911 DEFBOOL,
912 },{
913 .desc = "USB Speed",
914 .name = "usb_speed",
915 .get_value = ctrl_hsm_get,
916 DEFENUM(control_values_hsm),
917 },{
918 .desc = "Signal Present",
919 .name = "signal_present",
920 .get_value = ctrl_signal_get,
921 DEFINT(0,65535),
922 },{
923 .desc = "Audio Modes Present",
924 .name = "audio_modes_present",
925 .get_value = ctrl_audio_modes_present_get,
926 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
927 v4l. Nothing outside of this module cares about this,
928 but I reuse it in order to also reuse the
929 control_values_audiomode string table. */
930 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
931 (1 << V4L2_TUNER_MODE_STEREO)|
932 (1 << V4L2_TUNER_MODE_LANG1)|
933 (1 << V4L2_TUNER_MODE_LANG2)),
934 control_values_audiomode),
935 },{
936 .desc = "Video Standards Available Mask",
937 .name = "video_standard_mask_available",
938 .internal_id = PVR2_CID_STDAVAIL,
939 .skip_init = !0,
940 .get_value = ctrl_stdavail_get,
941 .set_value = ctrl_stdavail_set,
942 .val_to_sym = ctrl_std_val_to_sym,
943 .sym_to_val = ctrl_std_sym_to_val,
944 .type = pvr2_ctl_bitmask,
945 },{
946 .desc = "Video Standards In Use Mask",
947 .name = "video_standard_mask_active",
948 .internal_id = PVR2_CID_STDCUR,
949 .skip_init = !0,
950 .get_value = ctrl_stdcur_get,
951 .set_value = ctrl_stdcur_set,
952 .is_dirty = ctrl_stdcur_is_dirty,
953 .clear_dirty = ctrl_stdcur_clear_dirty,
954 .val_to_sym = ctrl_std_val_to_sym,
955 .sym_to_val = ctrl_std_sym_to_val,
956 .type = pvr2_ctl_bitmask,
957 },{
958 .desc = "Subsystem enabled mask",
959 .name = "debug_subsys_mask",
960 .skip_init = !0,
961 .get_value = ctrl_subsys_get,
962 .set_value = ctrl_subsys_set,
963 DEFMASK(PVR2_SUBSYS_ALL,control_values_subsystem),
964 },{
965 .desc = "Subsystem stream mask",
966 .name = "debug_subsys_stream_mask",
967 .skip_init = !0,
968 .get_value = ctrl_subsys_stream_get,
969 .set_value = ctrl_subsys_stream_set,
970 DEFMASK(PVR2_SUBSYS_ALL,control_values_subsystem),
971 },{
972 .desc = "Video Standard Name",
973 .name = "video_standard",
974 .internal_id = PVR2_CID_STDENUM,
975 .skip_init = !0,
976 .get_value = ctrl_stdenumcur_get,
977 .set_value = ctrl_stdenumcur_set,
978 .is_dirty = ctrl_stdenumcur_is_dirty,
979 .clear_dirty = ctrl_stdenumcur_clear_dirty,
980 .type = pvr2_ctl_enum,
981 }
982 };
983
984 #define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
985
986
987 const char *pvr2_config_get_name(enum pvr2_config cfg)
988 {
989 switch (cfg) {
990 case pvr2_config_empty: return "empty";
991 case pvr2_config_mpeg: return "mpeg";
992 case pvr2_config_vbi: return "vbi";
993 case pvr2_config_pcm: return "pcm";
994 case pvr2_config_rawvideo: return "raw video";
995 }
996 return "<unknown>";
997 }
998
999
1000 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1001 {
1002 return hdw->usb_dev;
1003 }
1004
1005
1006 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1007 {
1008 return hdw->serial_number;
1009 }
1010
1011
1012 const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1013 {
1014 return hdw->bus_info;
1015 }
1016
1017
1018 unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1019 {
1020 return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1021 }
1022
1023 /* Set the currently tuned frequency and account for all possible
1024 driver-core side effects of this action. */
1025 void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1026 {
1027 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1028 if (hdw->freqSelector) {
1029 /* Swing over to radio frequency selection */
1030 hdw->freqSelector = 0;
1031 hdw->freqDirty = !0;
1032 }
1033 if (hdw->freqValRadio != val) {
1034 hdw->freqValRadio = val;
1035 hdw->freqSlotRadio = 0;
1036 hdw->freqDirty = !0;
1037 }
1038 } else {
1039 if (!(hdw->freqSelector)) {
1040 /* Swing over to television frequency selection */
1041 hdw->freqSelector = 1;
1042 hdw->freqDirty = !0;
1043 }
1044 if (hdw->freqValTelevision != val) {
1045 hdw->freqValTelevision = val;
1046 hdw->freqSlotTelevision = 0;
1047 hdw->freqDirty = !0;
1048 }
1049 }
1050 }
1051
1052 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1053 {
1054 return hdw->unit_number;
1055 }
1056
1057
1058 /* Attempt to locate one of the given set of files. Messages are logged
1059 appropriate to what has been found. The return value will be 0 or
1060 greater on success (it will be the index of the file name found) and
1061 fw_entry will be filled in. Otherwise a negative error is returned on
1062 failure. If the return value is -ENOENT then no viable firmware file
1063 could be located. */
1064 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1065 const struct firmware **fw_entry,
1066 const char *fwtypename,
1067 unsigned int fwcount,
1068 const char *fwnames[])
1069 {
1070 unsigned int idx;
1071 int ret = -EINVAL;
1072 for (idx = 0; idx < fwcount; idx++) {
1073 ret = request_firmware(fw_entry,
1074 fwnames[idx],
1075 &hdw->usb_dev->dev);
1076 if (!ret) {
1077 trace_firmware("Located %s firmware: %s;"
1078 " uploading...",
1079 fwtypename,
1080 fwnames[idx]);
1081 return idx;
1082 }
1083 if (ret == -ENOENT) continue;
1084 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1085 "request_firmware fatal error with code=%d",ret);
1086 return ret;
1087 }
1088 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1089 "***WARNING***"
1090 " Device %s firmware"
1091 " seems to be missing.",
1092 fwtypename);
1093 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1094 "Did you install the pvrusb2 firmware files"
1095 " in their proper location?");
1096 if (fwcount == 1) {
1097 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1098 "request_firmware unable to locate %s file %s",
1099 fwtypename,fwnames[0]);
1100 } else {
1101 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1102 "request_firmware unable to locate"
1103 " one of the following %s files:",
1104 fwtypename);
1105 for (idx = 0; idx < fwcount; idx++) {
1106 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1107 "request_firmware: Failed to find %s",
1108 fwnames[idx]);
1109 }
1110 }
1111 return ret;
1112 }
1113
1114
1115 /*
1116 * pvr2_upload_firmware1().
1117 *
1118 * Send the 8051 firmware to the device. After the upload, arrange for
1119 * device to re-enumerate.
1120 *
1121 * NOTE : the pointer to the firmware data given by request_firmware()
1122 * is not suitable for an usb transaction.
1123 *
1124 */
1125 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1126 {
1127 const struct firmware *fw_entry = NULL;
1128 void *fw_ptr;
1129 unsigned int pipe;
1130 int ret;
1131 u16 address;
1132 static const char *fw_files_29xxx[] = {
1133 "v4l-pvrusb2-29xxx-01.fw",
1134 };
1135 static const char *fw_files_24xxx[] = {
1136 "v4l-pvrusb2-24xxx-01.fw",
1137 };
1138 static const struct pvr2_string_table fw_file_defs[] = {
1139 [PVR2_HDW_TYPE_29XXX] = {
1140 fw_files_29xxx, ARRAY_SIZE(fw_files_29xxx)
1141 },
1142 [PVR2_HDW_TYPE_24XXX] = {
1143 fw_files_24xxx, ARRAY_SIZE(fw_files_24xxx)
1144 },
1145 };
1146 hdw->fw1_state = FW1_STATE_FAILED; // default result
1147
1148 trace_firmware("pvr2_upload_firmware1");
1149
1150 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1151 fw_file_defs[hdw->hdw_type].cnt,
1152 fw_file_defs[hdw->hdw_type].lst);
1153 if (ret < 0) {
1154 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1155 return ret;
1156 }
1157
1158 usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
1159 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1160
1161 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1162
1163 if (fw_entry->size != 0x2000){
1164 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1165 release_firmware(fw_entry);
1166 return -ENOMEM;
1167 }
1168
1169 fw_ptr = kmalloc(0x800, GFP_KERNEL);
1170 if (fw_ptr == NULL){
1171 release_firmware(fw_entry);
1172 return -ENOMEM;
1173 }
1174
1175 /* We have to hold the CPU during firmware upload. */
1176 pvr2_hdw_cpureset_assert(hdw,1);
1177
1178 /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1179 chunk. */
1180
1181 ret = 0;
1182 for(address = 0; address < fw_entry->size; address += 0x800) {
1183 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1184 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1185 0, fw_ptr, 0x800, HZ);
1186 }
1187
1188 trace_firmware("Upload done, releasing device's CPU");
1189
1190 /* Now release the CPU. It will disconnect and reconnect later. */
1191 pvr2_hdw_cpureset_assert(hdw,0);
1192
1193 kfree(fw_ptr);
1194 release_firmware(fw_entry);
1195
1196 trace_firmware("Upload done (%d bytes sent)",ret);
1197
1198 /* We should have written 8192 bytes */
1199 if (ret == 8192) {
1200 hdw->fw1_state = FW1_STATE_RELOAD;
1201 return 0;
1202 }
1203
1204 return -EIO;
1205 }
1206
1207
1208 /*
1209 * pvr2_upload_firmware2()
1210 *
1211 * This uploads encoder firmware on endpoint 2.
1212 *
1213 */
1214
1215 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1216 {
1217 const struct firmware *fw_entry = NULL;
1218 void *fw_ptr;
1219 unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1220 int actual_length;
1221 int ret = 0;
1222 int fwidx;
1223 static const char *fw_files[] = {
1224 CX2341X_FIRM_ENC_FILENAME,
1225 };
1226
1227 trace_firmware("pvr2_upload_firmware2");
1228
1229 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1230 ARRAY_SIZE(fw_files), fw_files);
1231 if (ret < 0) return ret;
1232 fwidx = ret;
1233 ret = 0;
1234 /* Since we're about to completely reinitialize the encoder,
1235 invalidate our cached copy of its configuration state. Next
1236 time we configure the encoder, then we'll fully configure it. */
1237 hdw->enc_cur_valid = 0;
1238
1239 /* First prepare firmware loading */
1240 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1241 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1242 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1243 ret |= pvr2_hdw_cmd_deep_reset(hdw);
1244 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1245 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1246 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1247 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1248 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1249 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1250 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1251 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1252 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1253 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1254 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1255 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1256 LOCK_TAKE(hdw->ctl_lock); do {
1257 hdw->cmd_buffer[0] = FX2CMD_FWPOST1;
1258 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
1259 hdw->cmd_buffer[0] = FX2CMD_MEMSEL;
1260 hdw->cmd_buffer[1] = 0;
1261 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,2,NULL,0);
1262 } while (0); LOCK_GIVE(hdw->ctl_lock);
1263
1264 if (ret) {
1265 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1266 "firmware2 upload prep failed, ret=%d",ret);
1267 release_firmware(fw_entry);
1268 return ret;
1269 }
1270
1271 /* Now send firmware */
1272
1273 fw_len = fw_entry->size;
1274
1275 if (fw_len % sizeof(u32)) {
1276 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1277 "size of %s firmware"
1278 " must be a multiple of %zu bytes",
1279 fw_files[fwidx],sizeof(u32));
1280 release_firmware(fw_entry);
1281 return -1;
1282 }
1283
1284 fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1285 if (fw_ptr == NULL){
1286 release_firmware(fw_entry);
1287 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1288 "failed to allocate memory for firmware2 upload");
1289 return -ENOMEM;
1290 }
1291
1292 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1293
1294 fw_done = 0;
1295 for (fw_done = 0; fw_done < fw_len;) {
1296 bcnt = fw_len - fw_done;
1297 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1298 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1299 /* Usbsnoop log shows that we must swap bytes... */
1300 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1301 ((u32 *)fw_ptr)[icnt] =
1302 ___swab32(((u32 *)fw_ptr)[icnt]);
1303
1304 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1305 &actual_length, HZ);
1306 ret |= (actual_length != bcnt);
1307 if (ret) break;
1308 fw_done += bcnt;
1309 }
1310
1311 trace_firmware("upload of %s : %i / %i ",
1312 fw_files[fwidx],fw_done,fw_len);
1313
1314 kfree(fw_ptr);
1315 release_firmware(fw_entry);
1316
1317 if (ret) {
1318 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1319 "firmware2 upload transfer failure");
1320 return ret;
1321 }
1322
1323 /* Finish upload */
1324
1325 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1326 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1327 LOCK_TAKE(hdw->ctl_lock); do {
1328 hdw->cmd_buffer[0] = FX2CMD_MEMSEL;
1329 hdw->cmd_buffer[1] = 0;
1330 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,2,NULL,0);
1331 } while (0); LOCK_GIVE(hdw->ctl_lock);
1332
1333 if (ret) {
1334 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1335 "firmware2 upload post-proc failure");
1336 } else {
1337 hdw->subsys_enabled_mask |= (1<<PVR2_SUBSYS_B_ENC_FIRMWARE);
1338 }
1339 return ret;
1340 }
1341
1342
1343 #define FIRMWARE_RECOVERY_BITS \
1344 ((1<<PVR2_SUBSYS_B_ENC_CFG) | \
1345 (1<<PVR2_SUBSYS_B_ENC_RUN) | \
1346 (1<<PVR2_SUBSYS_B_ENC_FIRMWARE) | \
1347 (1<<PVR2_SUBSYS_B_USBSTREAM_RUN))
1348
1349 /*
1350
1351 This single function is key to pretty much everything. The pvrusb2
1352 device can logically be viewed as a series of subsystems which can be
1353 stopped / started or unconfigured / configured. To get things streaming,
1354 one must configure everything and start everything, but there may be
1355 various reasons over time to deconfigure something or stop something.
1356 This function handles all of this activity. Everything EVERYWHERE that
1357 must affect a subsystem eventually comes here to do the work.
1358
1359 The current state of all subsystems is represented by a single bit mask,
1360 known as subsys_enabled_mask. The bit positions are defined by the
1361 PVR2_SUBSYS_xxxx macros, with one subsystem per bit position. At any
1362 time the set of configured or active subsystems can be queried just by
1363 looking at that mask. To change bits in that mask, this function here
1364 must be called. The "msk" argument indicates which bit positions to
1365 change, and the "val" argument defines the new values for the positions
1366 defined by "msk".
1367
1368 There is a priority ordering of starting / stopping things, and for
1369 multiple requested changes, this function implements that ordering.
1370 (Thus we will act on a request to load encoder firmware before we
1371 configure the encoder.) In addition to priority ordering, there is a
1372 recovery strategy implemented here. If a particular step fails and we
1373 detect that failure, this function will clear the affected subsystem bits
1374 and restart. Thus we have a means for recovering from a dead encoder:
1375 Clear all bits that correspond to subsystems that we need to restart /
1376 reconfigure and start over.
1377
1378 */
1379 static void pvr2_hdw_subsys_bit_chg_no_lock(struct pvr2_hdw *hdw,
1380 unsigned long msk,
1381 unsigned long val)
1382 {
1383 unsigned long nmsk;
1384 unsigned long vmsk;
1385 int ret;
1386 unsigned int tryCount = 0;
1387
1388 if (!hdw->flag_ok) return;
1389
1390 msk &= PVR2_SUBSYS_ALL;
1391 nmsk = (hdw->subsys_enabled_mask & ~msk) | (val & msk);
1392 nmsk &= PVR2_SUBSYS_ALL;
1393
1394 for (;;) {
1395 tryCount++;
1396 if (!((nmsk ^ hdw->subsys_enabled_mask) &
1397 PVR2_SUBSYS_ALL)) break;
1398 if (tryCount > 4) {
1399 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1400 "Too many retries when configuring device;"
1401 " giving up");
1402 pvr2_hdw_render_useless(hdw);
1403 break;
1404 }
1405 if (tryCount > 1) {
1406 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1407 "Retrying device reconfiguration");
1408 }
1409 pvr2_trace(PVR2_TRACE_INIT,
1410 "subsys mask changing 0x%lx:0x%lx"
1411 " from 0x%lx to 0x%lx",
1412 msk,val,hdw->subsys_enabled_mask,nmsk);
1413
1414 vmsk = (nmsk ^ hdw->subsys_enabled_mask) &
1415 hdw->subsys_enabled_mask;
1416 if (vmsk) {
1417 if (vmsk & (1<<PVR2_SUBSYS_B_ENC_RUN)) {
1418 pvr2_trace(PVR2_TRACE_CTL,
1419 "/*---TRACE_CTL----*/"
1420 " pvr2_encoder_stop");
1421 ret = pvr2_encoder_stop(hdw);
1422 if (ret) {
1423 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1424 "Error recovery initiated");
1425 hdw->subsys_enabled_mask &=
1426 ~FIRMWARE_RECOVERY_BITS;
1427 continue;
1428 }
1429 }
1430 if (vmsk & (1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) {
1431 pvr2_trace(PVR2_TRACE_CTL,
1432 "/*---TRACE_CTL----*/"
1433 " pvr2_hdw_cmd_usbstream(0)");
1434 pvr2_hdw_cmd_usbstream(hdw,0);
1435 }
1436 if (vmsk & (1<<PVR2_SUBSYS_B_DIGITIZER_RUN)) {
1437 pvr2_trace(PVR2_TRACE_CTL,
1438 "/*---TRACE_CTL----*/"
1439 " decoder disable");
1440 if (hdw->decoder_ctrl) {
1441 hdw->decoder_ctrl->enable(
1442 hdw->decoder_ctrl->ctxt,0);
1443 } else {
1444 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1445 "WARNING:"
1446 " No decoder present");
1447 }
1448 hdw->subsys_enabled_mask &=
1449 ~(1<<PVR2_SUBSYS_B_DIGITIZER_RUN);
1450 }
1451 if (vmsk & PVR2_SUBSYS_CFG_ALL) {
1452 hdw->subsys_enabled_mask &=
1453 ~(vmsk & PVR2_SUBSYS_CFG_ALL);
1454 }
1455 }
1456 vmsk = (nmsk ^ hdw->subsys_enabled_mask) & nmsk;
1457 if (vmsk) {
1458 if (vmsk & (1<<PVR2_SUBSYS_B_ENC_FIRMWARE)) {
1459 pvr2_trace(PVR2_TRACE_CTL,
1460 "/*---TRACE_CTL----*/"
1461 " pvr2_upload_firmware2");
1462 ret = pvr2_upload_firmware2(hdw);
1463 if (ret) {
1464 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1465 "Failure uploading encoder"
1466 " firmware");
1467 pvr2_hdw_render_useless(hdw);
1468 break;
1469 }
1470 }
1471 if (vmsk & (1<<PVR2_SUBSYS_B_ENC_CFG)) {
1472 pvr2_trace(PVR2_TRACE_CTL,
1473 "/*---TRACE_CTL----*/"
1474 " pvr2_encoder_configure");
1475 ret = pvr2_encoder_configure(hdw);
1476 if (ret) {
1477 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1478 "Error recovery initiated");
1479 hdw->subsys_enabled_mask &=
1480 ~FIRMWARE_RECOVERY_BITS;
1481 continue;
1482 }
1483 }
1484 if (vmsk & (1<<PVR2_SUBSYS_B_DIGITIZER_RUN)) {
1485 pvr2_trace(PVR2_TRACE_CTL,
1486 "/*---TRACE_CTL----*/"
1487 " decoder enable");
1488 if (hdw->decoder_ctrl) {
1489 hdw->decoder_ctrl->enable(
1490 hdw->decoder_ctrl->ctxt,!0);
1491 } else {
1492 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1493 "WARNING:"
1494 " No decoder present");
1495 }
1496 hdw->subsys_enabled_mask |=
1497 (1<<PVR2_SUBSYS_B_DIGITIZER_RUN);
1498 }
1499 if (vmsk & (1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) {
1500 pvr2_trace(PVR2_TRACE_CTL,
1501 "/*---TRACE_CTL----*/"
1502 " pvr2_hdw_cmd_usbstream(1)");
1503 pvr2_hdw_cmd_usbstream(hdw,!0);
1504 }
1505 if (vmsk & (1<<PVR2_SUBSYS_B_ENC_RUN)) {
1506 pvr2_trace(PVR2_TRACE_CTL,
1507 "/*---TRACE_CTL----*/"
1508 " pvr2_encoder_start");
1509 ret = pvr2_encoder_start(hdw);
1510 if (ret) {
1511 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1512 "Error recovery initiated");
1513 hdw->subsys_enabled_mask &=
1514 ~FIRMWARE_RECOVERY_BITS;
1515 continue;
1516 }
1517 }
1518 }
1519 }
1520 }
1521
1522
1523 void pvr2_hdw_subsys_bit_chg(struct pvr2_hdw *hdw,
1524 unsigned long msk,unsigned long val)
1525 {
1526 LOCK_TAKE(hdw->big_lock); do {
1527 pvr2_hdw_subsys_bit_chg_no_lock(hdw,msk,val);
1528 } while (0); LOCK_GIVE(hdw->big_lock);
1529 }
1530
1531
1532 unsigned long pvr2_hdw_subsys_get(struct pvr2_hdw *hdw)
1533 {
1534 return hdw->subsys_enabled_mask;
1535 }
1536
1537
1538 unsigned long pvr2_hdw_subsys_stream_get(struct pvr2_hdw *hdw)
1539 {
1540 return hdw->subsys_stream_mask;
1541 }
1542
1543
1544 static void pvr2_hdw_subsys_stream_bit_chg_no_lock(struct pvr2_hdw *hdw,
1545 unsigned long msk,
1546 unsigned long val)
1547 {
1548 unsigned long val2;
1549 msk &= PVR2_SUBSYS_ALL;
1550 val2 = ((hdw->subsys_stream_mask & ~msk) | (val & msk));
1551 pvr2_trace(PVR2_TRACE_INIT,
1552 "stream mask changing 0x%lx:0x%lx from 0x%lx to 0x%lx",
1553 msk,val,hdw->subsys_stream_mask,val2);
1554 hdw->subsys_stream_mask = val2;
1555 }
1556
1557
1558 void pvr2_hdw_subsys_stream_bit_chg(struct pvr2_hdw *hdw,
1559 unsigned long msk,
1560 unsigned long val)
1561 {
1562 LOCK_TAKE(hdw->big_lock); do {
1563 pvr2_hdw_subsys_stream_bit_chg_no_lock(hdw,msk,val);
1564 } while (0); LOCK_GIVE(hdw->big_lock);
1565 }
1566
1567
1568 static int pvr2_hdw_set_streaming_no_lock(struct pvr2_hdw *hdw,int enableFl)
1569 {
1570 if ((!enableFl) == !(hdw->flag_streaming_enabled)) return 0;
1571 if (enableFl) {
1572 pvr2_trace(PVR2_TRACE_START_STOP,
1573 "/*--TRACE_STREAM--*/ enable");
1574 pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,~0);
1575 } else {
1576 pvr2_trace(PVR2_TRACE_START_STOP,
1577 "/*--TRACE_STREAM--*/ disable");
1578 pvr2_hdw_subsys_bit_chg_no_lock(hdw,hdw->subsys_stream_mask,0);
1579 }
1580 if (!hdw->flag_ok) return -EIO;
1581 hdw->flag_streaming_enabled = enableFl != 0;
1582 return 0;
1583 }
1584
1585
1586 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1587 {
1588 return hdw->flag_streaming_enabled != 0;
1589 }
1590
1591
1592 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1593 {
1594 int ret;
1595 LOCK_TAKE(hdw->big_lock); do {
1596 ret = pvr2_hdw_set_streaming_no_lock(hdw,enable_flag);
1597 } while (0); LOCK_GIVE(hdw->big_lock);
1598 return ret;
1599 }
1600
1601
1602 static int pvr2_hdw_set_stream_type_no_lock(struct pvr2_hdw *hdw,
1603 enum pvr2_config config)
1604 {
1605 unsigned long sm = hdw->subsys_enabled_mask;
1606 if (!hdw->flag_ok) return -EIO;
1607 pvr2_hdw_subsys_bit_chg_no_lock(hdw,hdw->subsys_stream_mask,0);
1608 hdw->config = config;
1609 pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,sm);
1610 return 0;
1611 }
1612
1613
1614 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1615 {
1616 int ret;
1617 if (!hdw->flag_ok) return -EIO;
1618 LOCK_TAKE(hdw->big_lock);
1619 ret = pvr2_hdw_set_stream_type_no_lock(hdw,config);
1620 LOCK_GIVE(hdw->big_lock);
1621 return ret;
1622 }
1623
1624
1625 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1626 {
1627 int unit_number = hdw->unit_number;
1628 int tp = -1;
1629 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1630 tp = tuner[unit_number];
1631 }
1632 if (tp < 0) return -EINVAL;
1633 hdw->tuner_type = tp;
1634 return 0;
1635 }
1636
1637
1638 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1639 {
1640 int unit_number = hdw->unit_number;
1641 int tp = 0;
1642 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1643 tp = video_std[unit_number];
1644 }
1645 return tp;
1646 }
1647
1648
1649 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1650 {
1651 int unit_number = hdw->unit_number;
1652 int tp = 0;
1653 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1654 tp = tolerance[unit_number];
1655 }
1656 return tp;
1657 }
1658
1659
1660 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1661 {
1662 /* Try a harmless request to fetch the eeprom's address over
1663 endpoint 1. See what happens. Only the full FX2 image can
1664 respond to this. If this probe fails then likely the FX2
1665 firmware needs be loaded. */
1666 int result;
1667 LOCK_TAKE(hdw->ctl_lock); do {
1668 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1669 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1670 hdw->cmd_buffer,1,
1671 hdw->cmd_buffer,1);
1672 if (result < 0) break;
1673 } while(0); LOCK_GIVE(hdw->ctl_lock);
1674 if (result) {
1675 pvr2_trace(PVR2_TRACE_INIT,
1676 "Probe of device endpoint 1 result status %d",
1677 result);
1678 } else {
1679 pvr2_trace(PVR2_TRACE_INIT,
1680 "Probe of device endpoint 1 succeeded");
1681 }
1682 return result == 0;
1683 }
1684
1685 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1686 {
1687 char buf[40];
1688 unsigned int bcnt;
1689 v4l2_std_id std1,std2;
1690
1691 std1 = get_default_standard(hdw);
1692
1693 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1694 pvr2_trace(PVR2_TRACE_INIT,
1695 "Supported video standard(s) reported by eeprom: %.*s",
1696 bcnt,buf);
1697
1698 hdw->std_mask_avail = hdw->std_mask_eeprom;
1699
1700 std2 = std1 & ~hdw->std_mask_avail;
1701 if (std2) {
1702 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1703 pvr2_trace(PVR2_TRACE_INIT,
1704 "Expanding supported video standards"
1705 " to include: %.*s",
1706 bcnt,buf);
1707 hdw->std_mask_avail |= std2;
1708 }
1709
1710 pvr2_hdw_internal_set_std_avail(hdw);
1711
1712 if (std1) {
1713 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1714 pvr2_trace(PVR2_TRACE_INIT,
1715 "Initial video standard forced to %.*s",
1716 bcnt,buf);
1717 hdw->std_mask_cur = std1;
1718 hdw->std_dirty = !0;
1719 pvr2_hdw_internal_find_stdenum(hdw);
1720 return;
1721 }
1722
1723 if (hdw->std_enum_cnt > 1) {
1724 // Autoselect the first listed standard
1725 hdw->std_enum_cur = 1;
1726 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1727 hdw->std_dirty = !0;
1728 pvr2_trace(PVR2_TRACE_INIT,
1729 "Initial video standard auto-selected to %s",
1730 hdw->std_defs[hdw->std_enum_cur-1].name);
1731 return;
1732 }
1733
1734 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1735 "Unable to select a viable initial video standard");
1736 }
1737
1738
1739 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
1740 {
1741 int ret;
1742 unsigned int idx;
1743 struct pvr2_ctrl *cptr;
1744 int reloadFl = 0;
1745 if (!reloadFl) {
1746 reloadFl = (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
1747 == 0);
1748 if (reloadFl) {
1749 pvr2_trace(PVR2_TRACE_INIT,
1750 "USB endpoint config looks strange"
1751 "; possibly firmware needs to be loaded");
1752 }
1753 }
1754 if (!reloadFl) {
1755 reloadFl = !pvr2_hdw_check_firmware(hdw);
1756 if (reloadFl) {
1757 pvr2_trace(PVR2_TRACE_INIT,
1758 "Check for FX2 firmware failed"
1759 "; possibly firmware needs to be loaded");
1760 }
1761 }
1762 if (reloadFl) {
1763 if (pvr2_upload_firmware1(hdw) != 0) {
1764 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1765 "Failure uploading firmware1");
1766 }
1767 return;
1768 }
1769 hdw->fw1_state = FW1_STATE_OK;
1770
1771 if (initusbreset) {
1772 pvr2_hdw_device_reset(hdw);
1773 }
1774 if (!pvr2_hdw_dev_ok(hdw)) return;
1775
1776 for (idx = 0; idx < pvr2_client_lists[hdw->hdw_type].cnt; idx++) {
1777 request_module(pvr2_client_lists[hdw->hdw_type].lst[idx]);
1778 }
1779
1780 pvr2_hdw_cmd_powerup(hdw);
1781 if (!pvr2_hdw_dev_ok(hdw)) return;
1782
1783 if (pvr2_upload_firmware2(hdw)){
1784 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"device unstable!!");
1785 pvr2_hdw_render_useless(hdw);
1786 return;
1787 }
1788
1789 // This step MUST happen after the earlier powerup step.
1790 pvr2_i2c_core_init(hdw);
1791 if (!pvr2_hdw_dev_ok(hdw)) return;
1792
1793 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1794 cptr = hdw->controls + idx;
1795 if (cptr->info->skip_init) continue;
1796 if (!cptr->info->set_value) continue;
1797 cptr->info->set_value(cptr,~0,cptr->info->default_value);
1798 }
1799
1800 /* Set up special default values for the television and radio
1801 frequencies here. It's not really important what these defaults
1802 are, but I set them to something usable in the Chicago area just
1803 to make driver testing a little easier. */
1804
1805 /* US Broadcast channel 7 (175.25 MHz) */
1806 hdw->freqValTelevision = 175250000L;
1807 /* 104.3 MHz, a usable FM station for my area */
1808 hdw->freqValRadio = 104300000L;
1809
1810 // Do not use pvr2_reset_ctl_endpoints() here. It is not
1811 // thread-safe against the normal pvr2_send_request() mechanism.
1812 // (We should make it thread safe).
1813
1814 ret = pvr2_hdw_get_eeprom_addr(hdw);
1815 if (!pvr2_hdw_dev_ok(hdw)) return;
1816 if (ret < 0) {
1817 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1818 "Unable to determine location of eeprom, skipping");
1819 } else {
1820 hdw->eeprom_addr = ret;
1821 pvr2_eeprom_analyze(hdw);
1822 if (!pvr2_hdw_dev_ok(hdw)) return;
1823 }
1824
1825 pvr2_hdw_setup_std(hdw);
1826
1827 if (!get_default_tuner_type(hdw)) {
1828 pvr2_trace(PVR2_TRACE_INIT,
1829 "pvr2_hdw_setup: Tuner type overridden to %d",
1830 hdw->tuner_type);
1831 }
1832
1833 hdw->tuner_updated = !0;
1834 pvr2_i2c_core_check_stale(hdw);
1835 hdw->tuner_updated = 0;
1836
1837 if (!pvr2_hdw_dev_ok(hdw)) return;
1838
1839 pvr2_hdw_commit_ctl_internal(hdw);
1840 if (!pvr2_hdw_dev_ok(hdw)) return;
1841
1842 hdw->vid_stream = pvr2_stream_create();
1843 if (!pvr2_hdw_dev_ok(hdw)) return;
1844 pvr2_trace(PVR2_TRACE_INIT,
1845 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
1846 if (hdw->vid_stream) {
1847 idx = get_default_error_tolerance(hdw);
1848 if (idx) {
1849 pvr2_trace(PVR2_TRACE_INIT,
1850 "pvr2_hdw_setup: video stream %p"
1851 " setting tolerance %u",
1852 hdw->vid_stream,idx);
1853 }
1854 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
1855 PVR2_VID_ENDPOINT,idx);
1856 }
1857
1858 if (!pvr2_hdw_dev_ok(hdw)) return;
1859
1860 /* Make sure everything is up to date */
1861 pvr2_i2c_core_sync(hdw);
1862
1863 if (!pvr2_hdw_dev_ok(hdw)) return;
1864
1865 hdw->flag_init_ok = !0;
1866 }
1867
1868
1869 int pvr2_hdw_setup(struct pvr2_hdw *hdw)
1870 {
1871 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
1872 LOCK_TAKE(hdw->big_lock); do {
1873 pvr2_hdw_setup_low(hdw);
1874 pvr2_trace(PVR2_TRACE_INIT,
1875 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
1876 hdw,hdw->flag_ok,hdw->flag_init_ok);
1877 if (pvr2_hdw_dev_ok(hdw)) {
1878 if (pvr2_hdw_init_ok(hdw)) {
1879 pvr2_trace(
1880 PVR2_TRACE_INFO,
1881 "Device initialization"
1882 " completed successfully.");
1883 break;
1884 }
1885 if (hdw->fw1_state == FW1_STATE_RELOAD) {
1886 pvr2_trace(
1887 PVR2_TRACE_INFO,
1888 "Device microcontroller firmware"
1889 " (re)loaded; it should now reset"
1890 " and reconnect.");
1891 break;
1892 }
1893 pvr2_trace(
1894 PVR2_TRACE_ERROR_LEGS,
1895 "Device initialization was not successful.");
1896 if (hdw->fw1_state == FW1_STATE_MISSING) {
1897 pvr2_trace(
1898 PVR2_TRACE_ERROR_LEGS,
1899 "Giving up since device"
1900 " microcontroller firmware"
1901 " appears to be missing.");
1902 break;
1903 }
1904 }
1905 if (procreload) {
1906 pvr2_trace(
1907 PVR2_TRACE_ERROR_LEGS,
1908 "Attempting pvrusb2 recovery by reloading"
1909 " primary firmware.");
1910 pvr2_trace(
1911 PVR2_TRACE_ERROR_LEGS,
1912 "If this works, device should disconnect"
1913 " and reconnect in a sane state.");
1914 hdw->fw1_state = FW1_STATE_UNKNOWN;
1915 pvr2_upload_firmware1(hdw);
1916 } else {
1917 pvr2_trace(
1918 PVR2_TRACE_ERROR_LEGS,
1919 "***WARNING*** pvrusb2 device hardware"
1920 " appears to be jammed"
1921 " and I can't clear it.");
1922 pvr2_trace(
1923 PVR2_TRACE_ERROR_LEGS,
1924 "You might need to power cycle"
1925 " the pvrusb2 device"
1926 " in order to recover.");
1927 }
1928 } while (0); LOCK_GIVE(hdw->big_lock);
1929 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
1930 return hdw->flag_init_ok;
1931 }
1932
1933
1934 /* Create and return a structure for interacting with the underlying
1935 hardware */
1936 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
1937 const struct usb_device_id *devid)
1938 {
1939 unsigned int idx,cnt1,cnt2;
1940 struct pvr2_hdw *hdw;
1941 unsigned int hdw_type;
1942 int valid_std_mask;
1943 struct pvr2_ctrl *cptr;
1944 __u8 ifnum;
1945 struct v4l2_queryctrl qctrl;
1946 struct pvr2_ctl_info *ciptr;
1947
1948 hdw_type = devid - pvr2_device_table;
1949 if (hdw_type >= ARRAY_SIZE(pvr2_device_names)) {
1950 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1951 "Bogus device type of %u reported",hdw_type);
1952 return NULL;
1953 }
1954
1955 hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
1956 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
1957 hdw,pvr2_device_names[hdw_type]);
1958 if (!hdw) goto fail;
1959 hdw->tuner_signal_stale = !0;
1960 cx2341x_fill_defaults(&hdw->enc_ctl_state);
1961
1962 hdw->control_cnt = CTRLDEF_COUNT;
1963 hdw->control_cnt += MPEGDEF_COUNT;
1964 hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
1965 GFP_KERNEL);
1966 if (!hdw->controls) goto fail;
1967 hdw->hdw_type = hdw_type;
1968 for (idx = 0; idx < hdw->control_cnt; idx++) {
1969 cptr = hdw->controls + idx;
1970 cptr->hdw = hdw;
1971 }
1972 for (idx = 0; idx < 32; idx++) {
1973 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
1974 }
1975 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1976 cptr = hdw->controls + idx;
1977 cptr->info = control_defs+idx;
1978 }
1979 /* Define and configure additional controls from cx2341x module. */
1980 hdw->mpeg_ctrl_info = kzalloc(
1981 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
1982 if (!hdw->mpeg_ctrl_info) goto fail;
1983 for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
1984 cptr = hdw->controls + idx + CTRLDEF_COUNT;
1985 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
1986 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
1987 ciptr->name = mpeg_ids[idx].strid;
1988 ciptr->v4l_id = mpeg_ids[idx].id;
1989 ciptr->skip_init = !0;
1990 ciptr->get_value = ctrl_cx2341x_get;
1991 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
1992 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
1993 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
1994 qctrl.id = ciptr->v4l_id;
1995 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
1996 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
1997 ciptr->set_value = ctrl_cx2341x_set;
1998 }
1999 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2000 PVR2_CTLD_INFO_DESC_SIZE);
2001 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2002 ciptr->default_value = qctrl.default_value;
2003 switch (qctrl.type) {
2004 default:
2005 case V4L2_CTRL_TYPE_INTEGER:
2006 ciptr->type = pvr2_ctl_int;
2007 ciptr->def.type_int.min_value = qctrl.minimum;
2008 ciptr->def.type_int.max_value = qctrl.maximum;
2009 break;
2010 case V4L2_CTRL_TYPE_BOOLEAN:
2011 ciptr->type = pvr2_ctl_bool;
2012 break;
2013 case V4L2_CTRL_TYPE_MENU:
2014 ciptr->type = pvr2_ctl_enum;
2015 ciptr->def.type_enum.value_names =
2016 cx2341x_ctrl_get_menu(ciptr->v4l_id);
2017 for (cnt1 = 0;
2018 ciptr->def.type_enum.value_names[cnt1] != NULL;
2019 cnt1++) { }
2020 ciptr->def.type_enum.count = cnt1;
2021 break;
2022 }
2023 cptr->info = ciptr;
2024 }
2025
2026 // Initialize video standard enum dynamic control
2027 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2028 if (cptr) {
2029 memcpy(&hdw->std_info_enum,cptr->info,
2030 sizeof(hdw->std_info_enum));
2031 cptr->info = &hdw->std_info_enum;
2032
2033 }
2034 // Initialize control data regarding video standard masks
2035 valid_std_mask = pvr2_std_get_usable();
2036 for (idx = 0; idx < 32; idx++) {
2037 if (!(valid_std_mask & (1 << idx))) continue;
2038 cnt1 = pvr2_std_id_to_str(
2039 hdw->std_mask_names[idx],
2040 sizeof(hdw->std_mask_names[idx])-1,
2041 1 << idx);
2042 hdw->std_mask_names[idx][cnt1] = 0;
2043 }
2044 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2045 if (cptr) {
2046 memcpy(&hdw->std_info_avail,cptr->info,
2047 sizeof(hdw->std_info_avail));
2048 cptr->info = &hdw->std_info_avail;
2049 hdw->std_info_avail.def.type_bitmask.bit_names =
2050 hdw->std_mask_ptrs;
2051 hdw->std_info_avail.def.type_bitmask.valid_bits =
2052 valid_std_mask;
2053 }
2054 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2055 if (cptr) {
2056 memcpy(&hdw->std_info_cur,cptr->info,
2057 sizeof(hdw->std_info_cur));
2058 cptr->info = &hdw->std_info_cur;
2059 hdw->std_info_cur.def.type_bitmask.bit_names =
2060 hdw->std_mask_ptrs;
2061 hdw->std_info_avail.def.type_bitmask.valid_bits =
2062 valid_std_mask;
2063 }
2064
2065 hdw->eeprom_addr = -1;
2066 hdw->unit_number = -1;
2067 hdw->v4l_minor_number_video = -1;
2068 hdw->v4l_minor_number_vbi = -1;
2069 hdw->v4l_minor_number_radio = -1;
2070 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2071 if (!hdw->ctl_write_buffer) goto fail;
2072 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2073 if (!hdw->ctl_read_buffer) goto fail;
2074 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2075 if (!hdw->ctl_write_urb) goto fail;
2076 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2077 if (!hdw->ctl_read_urb) goto fail;
2078
2079 mutex_lock(&pvr2_unit_mtx); do {
2080 for (idx = 0; idx < PVR_NUM; idx++) {
2081 if (unit_pointers[idx]) continue;
2082 hdw->unit_number = idx;
2083 unit_pointers[idx] = hdw;
2084 break;
2085 }
2086 } while (0); mutex_unlock(&pvr2_unit_mtx);
2087
2088 cnt1 = 0;
2089 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2090 cnt1 += cnt2;
2091 if (hdw->unit_number >= 0) {
2092 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2093 ('a' + hdw->unit_number));
2094 cnt1 += cnt2;
2095 }
2096 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2097 hdw->name[cnt1] = 0;
2098
2099 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2100 hdw->unit_number,hdw->name);
2101
2102 hdw->tuner_type = -1;
2103 hdw->flag_ok = !0;
2104 /* Initialize the mask of subsystems that we will shut down when we
2105 stop streaming. */
2106 hdw->subsys_stream_mask = PVR2_SUBSYS_RUN_ALL;
2107 hdw->subsys_stream_mask |= (1<<PVR2_SUBSYS_B_ENC_CFG);
2108
2109 pvr2_trace(PVR2_TRACE_INIT,"subsys_stream_mask: 0x%lx",
2110 hdw->subsys_stream_mask);
2111
2112 hdw->usb_intf = intf;
2113 hdw->usb_dev = interface_to_usbdev(intf);
2114
2115 scnprintf(hdw->bus_info,sizeof(hdw->bus_info),
2116 "usb %s address %d",
2117 hdw->usb_dev->dev.bus_id,
2118 hdw->usb_dev->devnum);
2119
2120 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2121 usb_set_interface(hdw->usb_dev,ifnum,0);
2122
2123 mutex_init(&hdw->ctl_lock_mutex);
2124 mutex_init(&hdw->big_lock_mutex);
2125
2126 return hdw;
2127 fail:
2128 if (hdw) {
2129 usb_free_urb(hdw->ctl_read_urb);
2130 usb_free_urb(hdw->ctl_write_urb);
2131 kfree(hdw->ctl_read_buffer);
2132 kfree(hdw->ctl_write_buffer);
2133 kfree(hdw->controls);
2134 kfree(hdw->mpeg_ctrl_info);
2135 kfree(hdw);
2136 }
2137 return NULL;
2138 }
2139
2140
2141 /* Remove _all_ associations between this driver and the underlying USB
2142 layer. */
2143 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2144 {
2145 if (hdw->flag_disconnected) return;
2146 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2147 if (hdw->ctl_read_urb) {
2148 usb_kill_urb(hdw->ctl_read_urb);
2149 usb_free_urb(hdw->ctl_read_urb);
2150 hdw->ctl_read_urb = NULL;
2151 }
2152 if (hdw->ctl_write_urb) {
2153 usb_kill_urb(hdw->ctl_write_urb);
2154 usb_free_urb(hdw->ctl_write_urb);
2155 hdw->ctl_write_urb = NULL;
2156 }
2157 if (hdw->ctl_read_buffer) {
2158 kfree(hdw->ctl_read_buffer);
2159 hdw->ctl_read_buffer = NULL;
2160 }
2161 if (hdw->ctl_write_buffer) {
2162 kfree(hdw->ctl_write_buffer);
2163 hdw->ctl_write_buffer = NULL;
2164 }
2165 pvr2_hdw_render_useless_unlocked(hdw);
2166 hdw->flag_disconnected = !0;
2167 hdw->usb_dev = NULL;
2168 hdw->usb_intf = NULL;
2169 }
2170
2171
2172 /* Destroy hardware interaction structure */
2173 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2174 {
2175 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2176 if (hdw->fw_buffer) {
2177 kfree(hdw->fw_buffer);
2178 hdw->fw_buffer = NULL;
2179 }
2180 if (hdw->vid_stream) {
2181 pvr2_stream_destroy(hdw->vid_stream);
2182 hdw->vid_stream = NULL;
2183 }
2184 if (hdw->decoder_ctrl) {
2185 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
2186 }
2187 pvr2_i2c_core_done(hdw);
2188 pvr2_hdw_remove_usb_stuff(hdw);
2189 mutex_lock(&pvr2_unit_mtx); do {
2190 if ((hdw->unit_number >= 0) &&
2191 (hdw->unit_number < PVR_NUM) &&
2192 (unit_pointers[hdw->unit_number] == hdw)) {
2193 unit_pointers[hdw->unit_number] = NULL;
2194 }
2195 } while (0); mutex_unlock(&pvr2_unit_mtx);
2196 kfree(hdw->controls);
2197 kfree(hdw->mpeg_ctrl_info);
2198 kfree(hdw->std_defs);
2199 kfree(hdw->std_enum_names);
2200 kfree(hdw);
2201 }
2202
2203
2204 int pvr2_hdw_init_ok(struct pvr2_hdw *hdw)
2205 {
2206 return hdw->flag_init_ok;
2207 }
2208
2209
2210 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2211 {
2212 return (hdw && hdw->flag_ok);
2213 }
2214
2215
2216 /* Called when hardware has been unplugged */
2217 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2218 {
2219 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2220 LOCK_TAKE(hdw->big_lock);
2221 LOCK_TAKE(hdw->ctl_lock);
2222 pvr2_hdw_remove_usb_stuff(hdw);
2223 LOCK_GIVE(hdw->ctl_lock);
2224 LOCK_GIVE(hdw->big_lock);
2225 }
2226
2227
2228 // Attempt to autoselect an appropriate value for std_enum_cur given
2229 // whatever is currently in std_mask_cur
2230 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
2231 {
2232 unsigned int idx;
2233 for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2234 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2235 hdw->std_enum_cur = idx;
2236 return;
2237 }
2238 }
2239 hdw->std_enum_cur = 0;
2240 }
2241
2242
2243 // Calculate correct set of enumerated standards based on currently known
2244 // set of available standards bits.
2245 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
2246 {
2247 struct v4l2_standard *newstd;
2248 unsigned int std_cnt;
2249 unsigned int idx;
2250
2251 newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2252
2253 if (hdw->std_defs) {
2254 kfree(hdw->std_defs);
2255 hdw->std_defs = NULL;
2256 }
2257 hdw->std_enum_cnt = 0;
2258 if (hdw->std_enum_names) {
2259 kfree(hdw->std_enum_names);
2260 hdw->std_enum_names = NULL;
2261 }
2262
2263 if (!std_cnt) {
2264 pvr2_trace(
2265 PVR2_TRACE_ERROR_LEGS,
2266 "WARNING: Failed to identify any viable standards");
2267 }
2268 hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2269 hdw->std_enum_names[0] = "none";
2270 for (idx = 0; idx < std_cnt; idx++) {
2271 hdw->std_enum_names[idx+1] =
2272 newstd[idx].name;
2273 }
2274 // Set up the dynamic control for this standard
2275 hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2276 hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2277 hdw->std_defs = newstd;
2278 hdw->std_enum_cnt = std_cnt+1;
2279 hdw->std_enum_cur = 0;
2280 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2281 }
2282
2283
2284 int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2285 struct v4l2_standard *std,
2286 unsigned int idx)
2287 {
2288 int ret = -EINVAL;
2289 if (!idx) return ret;
2290 LOCK_TAKE(hdw->big_lock); do {
2291 if (idx >= hdw->std_enum_cnt) break;
2292 idx--;
2293 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2294 ret = 0;
2295 } while (0); LOCK_GIVE(hdw->big_lock);
2296 return ret;
2297 }
2298
2299
2300 /* Get the number of defined controls */
2301 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2302 {
2303 return hdw->control_cnt;
2304 }
2305
2306
2307 /* Retrieve a control handle given its index (0..count-1) */
2308 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2309 unsigned int idx)
2310 {
2311 if (idx >= hdw->control_cnt) return NULL;
2312 return hdw->controls + idx;
2313 }
2314
2315
2316 /* Retrieve a control handle given its index (0..count-1) */
2317 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2318 unsigned int ctl_id)
2319 {
2320 struct pvr2_ctrl *cptr;
2321 unsigned int idx;
2322 int i;
2323
2324 /* This could be made a lot more efficient, but for now... */
2325 for (idx = 0; idx < hdw->control_cnt; idx++) {
2326 cptr = hdw->controls + idx;
2327 i = cptr->info->internal_id;
2328 if (i && (i == ctl_id)) return cptr;
2329 }
2330 return NULL;
2331 }
2332
2333
2334 /* Given a V4L ID, retrieve the control structure associated with it. */
2335 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2336 {
2337 struct pvr2_ctrl *cptr;
2338 unsigned int idx;
2339 int i;
2340
2341 /* This could be made a lot more efficient, but for now... */
2342 for (idx = 0; idx < hdw->control_cnt; idx++) {
2343 cptr = hdw->controls + idx;
2344 i = cptr->info->v4l_id;
2345 if (i && (i == ctl_id)) return cptr;
2346 }
2347 return NULL;
2348 }
2349
2350
2351 /* Given a V4L ID for its immediate predecessor, retrieve the control
2352 structure associated with it. */
2353 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2354 unsigned int ctl_id)
2355 {
2356 struct pvr2_ctrl *cptr,*cp2;
2357 unsigned int idx;
2358 int i;
2359
2360 /* This could be made a lot more efficient, but for now... */
2361 cp2 = NULL;
2362 for (idx = 0; idx < hdw->control_cnt; idx++) {
2363 cptr = hdw->controls + idx;
2364 i = cptr->info->v4l_id;
2365 if (!i) continue;
2366 if (i <= ctl_id) continue;
2367 if (cp2 && (cp2->info->v4l_id < i)) continue;
2368 cp2 = cptr;
2369 }
2370 return cp2;
2371 return NULL;
2372 }
2373
2374
2375 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2376 {
2377 switch (tp) {
2378 case pvr2_ctl_int: return "integer";
2379 case pvr2_ctl_enum: return "enum";
2380 case pvr2_ctl_bool: return "boolean";
2381 case pvr2_ctl_bitmask: return "bitmask";
2382 }
2383 return "";
2384 }
2385
2386
2387 /* Commit all control changes made up to this point. Subsystems can be
2388 indirectly affected by these changes. For a given set of things being
2389 committed, we'll clear the affected subsystem bits and then once we're
2390 done committing everything we'll make a request to restore the subsystem
2391 state(s) back to their previous value before this function was called.
2392 Thus we can automatically reconfigure affected pieces of the driver as
2393 controls are changed. */
2394 static int pvr2_hdw_commit_ctl_internal(struct pvr2_hdw *hdw)
2395 {
2396 unsigned long saved_subsys_mask = hdw->subsys_enabled_mask;
2397 unsigned long stale_subsys_mask = 0;
2398 unsigned int idx;
2399 struct pvr2_ctrl *cptr;
2400 int value;
2401 int commit_flag = 0;
2402 char buf[100];
2403 unsigned int bcnt,ccnt;
2404
2405 for (idx = 0; idx < hdw->control_cnt; idx++) {
2406 cptr = hdw->controls + idx;
2407 if (cptr->info->is_dirty == 0) continue;
2408 if (!cptr->info->is_dirty(cptr)) continue;
2409 commit_flag = !0;
2410
2411 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
2412 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2413 cptr->info->name);
2414 value = 0;
2415 cptr->info->get_value(cptr,&value);
2416 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2417 buf+bcnt,
2418 sizeof(buf)-bcnt,&ccnt);
2419 bcnt += ccnt;
2420 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2421 get_ctrl_typename(cptr->info->type));
2422 pvr2_trace(PVR2_TRACE_CTL,
2423 "/*--TRACE_COMMIT--*/ %.*s",
2424 bcnt,buf);
2425 }
2426
2427 if (!commit_flag) {
2428 /* Nothing has changed */
2429 return 0;
2430 }
2431
2432 /* When video standard changes, reset the hres and vres values -
2433 but if the user has pending changes there, then let the changes
2434 take priority. */
2435 if (hdw->std_dirty) {
2436 /* Rewrite the vertical resolution to be appropriate to the
2437 video standard that has been selected. */
2438 int nvres;
2439 if (hdw->std_mask_cur & V4L2_STD_525_60) {
2440 nvres = 480;
2441 } else {
2442 nvres = 576;
2443 }
2444 if (nvres != hdw->res_ver_val) {
2445 hdw->res_ver_val = nvres;
2446 hdw->res_ver_dirty = !0;
2447 }
2448 }
2449
2450 if (hdw->std_dirty ||
2451 hdw->enc_stale ||
2452 hdw->srate_dirty ||
2453 hdw->res_ver_dirty ||
2454 hdw->res_hor_dirty ||
2455 0) {
2456 /* If any of this changes, then the encoder needs to be
2457 reconfigured, and we need to reset the stream. */
2458 stale_subsys_mask |= (1<<PVR2_SUBSYS_B_ENC_CFG);
2459 }
2460
2461 if (hdw->input_dirty) {
2462 /* pk: If input changes to or from radio, then the encoder
2463 needs to be restarted (for ENC_MUTE_VIDEO to work) */
2464 stale_subsys_mask |= (1<<PVR2_SUBSYS_B_ENC_RUN);
2465 }
2466
2467
2468 if (hdw->srate_dirty) {
2469 /* Write new sample rate into control structure since
2470 * the master copy is stale. We must track srate
2471 * separate from the mpeg control structure because
2472 * other logic also uses this value. */
2473 struct v4l2_ext_controls cs;
2474 struct v4l2_ext_control c1;
2475 memset(&cs,0,sizeof(cs));
2476 memset(&c1,0,sizeof(c1));
2477 cs.controls = &c1;
2478 cs.count = 1;
2479 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
2480 c1.value = hdw->srate_val;
2481 cx2341x_ext_ctrls(&hdw->enc_ctl_state,&cs,VIDIOC_S_EXT_CTRLS);
2482 }
2483
2484 /* Scan i2c core at this point - before we clear all the dirty
2485 bits. Various parts of the i2c core will notice dirty bits as
2486 appropriate and arrange to broadcast or directly send updates to
2487 the client drivers in order to keep everything in sync */
2488 pvr2_i2c_core_check_stale(hdw);
2489
2490 for (idx = 0; idx < hdw->control_cnt; idx++) {
2491 cptr = hdw->controls + idx;
2492 if (!cptr->info->clear_dirty) continue;
2493 cptr->info->clear_dirty(cptr);
2494 }
2495
2496 /* Now execute i2c core update */
2497 pvr2_i2c_core_sync(hdw);
2498
2499 pvr2_hdw_subsys_bit_chg_no_lock(hdw,stale_subsys_mask,0);
2500 pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,saved_subsys_mask);
2501
2502 return 0;
2503 }
2504
2505
2506 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
2507 {
2508 LOCK_TAKE(hdw->big_lock); do {
2509 pvr2_hdw_commit_ctl_internal(hdw);
2510 } while (0); LOCK_GIVE(hdw->big_lock);
2511 return 0;
2512 }
2513
2514
2515 void pvr2_hdw_poll(struct pvr2_hdw *hdw)
2516 {
2517 LOCK_TAKE(hdw->big_lock); do {
2518 pvr2_i2c_core_sync(hdw);
2519 } while (0); LOCK_GIVE(hdw->big_lock);
2520 }
2521
2522
2523 void pvr2_hdw_setup_poll_trigger(struct pvr2_hdw *hdw,
2524 void (*func)(void *),
2525 void *data)
2526 {
2527 LOCK_TAKE(hdw->big_lock); do {
2528 hdw->poll_trigger_func = func;
2529 hdw->poll_trigger_data = data;
2530 } while (0); LOCK_GIVE(hdw->big_lock);
2531 }
2532
2533
2534 void pvr2_hdw_poll_trigger_unlocked(struct pvr2_hdw *hdw)
2535 {
2536 if (hdw->poll_trigger_func) {
2537 hdw->poll_trigger_func(hdw->poll_trigger_data);
2538 }
2539 }
2540
2541 /* Return name for this driver instance */
2542 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
2543 {
2544 return hdw->name;
2545 }
2546
2547
2548 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
2549 {
2550 int result;
2551 LOCK_TAKE(hdw->ctl_lock); do {
2552 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
2553 result = pvr2_send_request(hdw,
2554 hdw->cmd_buffer,1,
2555 hdw->cmd_buffer,1);
2556 if (result < 0) break;
2557 result = (hdw->cmd_buffer[0] != 0);
2558 } while(0); LOCK_GIVE(hdw->ctl_lock);
2559 return result;
2560 }
2561
2562
2563 /* Execute poll of tuner status */
2564 void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
2565 {
2566 LOCK_TAKE(hdw->big_lock); do {
2567 pvr2_i2c_core_status_poll(hdw);
2568 } while (0); LOCK_GIVE(hdw->big_lock);
2569 }
2570
2571
2572 /* Return information about the tuner */
2573 int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
2574 {
2575 LOCK_TAKE(hdw->big_lock); do {
2576 if (hdw->tuner_signal_stale) {
2577 pvr2_i2c_core_status_poll(hdw);
2578 }
2579 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
2580 } while (0); LOCK_GIVE(hdw->big_lock);
2581 return 0;
2582 }
2583
2584
2585 /* Get handle to video output stream */
2586 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
2587 {
2588 return hp->vid_stream;
2589 }
2590
2591
2592 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
2593 {
2594 int nr = pvr2_hdw_get_unit_number(hdw);
2595 LOCK_TAKE(hdw->big_lock); do {
2596 hdw->log_requested = !0;
2597 printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr);
2598 pvr2_i2c_core_check_stale(hdw);
2599 hdw->log_requested = 0;
2600 pvr2_i2c_core_sync(hdw);
2601 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
2602 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
2603 printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr);
2604 } while (0); LOCK_GIVE(hdw->big_lock);
2605 }
2606
2607 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw, int enable_flag)
2608 {
2609 int ret;
2610 u16 address;
2611 unsigned int pipe;
2612 LOCK_TAKE(hdw->big_lock); do {
2613 if ((hdw->fw_buffer == 0) == !enable_flag) break;
2614
2615 if (!enable_flag) {
2616 pvr2_trace(PVR2_TRACE_FIRMWARE,
2617 "Cleaning up after CPU firmware fetch");
2618 kfree(hdw->fw_buffer);
2619 hdw->fw_buffer = NULL;
2620 hdw->fw_size = 0;
2621 /* Now release the CPU. It will disconnect and
2622 reconnect later. */
2623 pvr2_hdw_cpureset_assert(hdw,0);
2624 break;
2625 }
2626
2627 pvr2_trace(PVR2_TRACE_FIRMWARE,
2628 "Preparing to suck out CPU firmware");
2629 hdw->fw_size = 0x2000;
2630 hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
2631 if (!hdw->fw_buffer) {
2632 hdw->fw_size = 0;
2633 break;
2634 }
2635
2636 /* We have to hold the CPU during firmware upload. */
2637 pvr2_hdw_cpureset_assert(hdw,1);
2638
2639 /* download the firmware from address 0000-1fff in 2048
2640 (=0x800) bytes chunk. */
2641
2642 pvr2_trace(PVR2_TRACE_FIRMWARE,"Grabbing CPU firmware");
2643 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
2644 for(address = 0; address < hdw->fw_size; address += 0x800) {
2645 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0xc0,
2646 address,0,
2647 hdw->fw_buffer+address,0x800,HZ);
2648 if (ret < 0) break;
2649 }
2650
2651 pvr2_trace(PVR2_TRACE_FIRMWARE,"Done grabbing CPU firmware");
2652
2653 } while (0); LOCK_GIVE(hdw->big_lock);
2654 }
2655
2656
2657 /* Return true if we're in a mode for retrieval CPU firmware */
2658 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
2659 {
2660 return hdw->fw_buffer != 0;
2661 }
2662
2663
2664 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
2665 char *buf,unsigned int cnt)
2666 {
2667 int ret = -EINVAL;
2668 LOCK_TAKE(hdw->big_lock); do {
2669 if (!buf) break;
2670 if (!cnt) break;
2671
2672 if (!hdw->fw_buffer) {
2673 ret = -EIO;
2674 break;
2675 }
2676
2677 if (offs >= hdw->fw_size) {
2678 pvr2_trace(PVR2_TRACE_FIRMWARE,
2679 "Read firmware data offs=%d EOF",
2680 offs);
2681 ret = 0;
2682 break;
2683 }
2684
2685 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
2686
2687 memcpy(buf,hdw->fw_buffer+offs,cnt);
2688
2689 pvr2_trace(PVR2_TRACE_FIRMWARE,
2690 "Read firmware data offs=%d cnt=%d",
2691 offs,cnt);
2692 ret = cnt;
2693 } while (0); LOCK_GIVE(hdw->big_lock);
2694
2695 return ret;
2696 }
2697
2698
2699 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
2700 enum pvr2_v4l_type index)
2701 {
2702 switch (index) {
2703 case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
2704 case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
2705 case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
2706 default: return -1;
2707 }
2708 }
2709
2710
2711 /* Store a v4l minor device number */
2712 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
2713 enum pvr2_v4l_type index,int v)
2714 {
2715 switch (index) {
2716 case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
2717 case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
2718 case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
2719 default: break;
2720 }
2721 }
2722
2723
2724 static void pvr2_ctl_write_complete(struct urb *urb)
2725 {
2726 struct pvr2_hdw *hdw = urb->context;
2727 hdw->ctl_write_pend_flag = 0;
2728 if (hdw->ctl_read_pend_flag) return;
2729 complete(&hdw->ctl_done);
2730 }
2731
2732
2733 static void pvr2_ctl_read_complete(struct urb *urb)
2734 {
2735 struct pvr2_hdw *hdw = urb->context;
2736 hdw->ctl_read_pend_flag = 0;
2737 if (hdw->ctl_write_pend_flag) return;
2738 complete(&hdw->ctl_done);
2739 }
2740
2741
2742 static void pvr2_ctl_timeout(unsigned long data)
2743 {
2744 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
2745 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2746 hdw->ctl_timeout_flag = !0;
2747 if (hdw->ctl_write_pend_flag)
2748 usb_unlink_urb(hdw->ctl_write_urb);
2749 if (hdw->ctl_read_pend_flag)
2750 usb_unlink_urb(hdw->ctl_read_urb);
2751 }
2752 }
2753
2754
2755 /* Issue a command and get a response from the device. This extended
2756 version includes a probe flag (which if set means that device errors
2757 should not be logged or treated as fatal) and a timeout in jiffies.
2758 This can be used to non-lethally probe the health of endpoint 1. */
2759 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
2760 unsigned int timeout,int probe_fl,
2761 void *write_data,unsigned int write_len,
2762 void *read_data,unsigned int read_len)
2763 {
2764 unsigned int idx;
2765 int status = 0;
2766 struct timer_list timer;
2767 if (!hdw->ctl_lock_held) {
2768 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2769 "Attempted to execute control transfer"
2770 " without lock!!");
2771 return -EDEADLK;
2772 }
2773 if ((!hdw->flag_ok) && !probe_fl) {
2774 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2775 "Attempted to execute control transfer"
2776 " when device not ok");
2777 return -EIO;
2778 }
2779 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
2780 if (!probe_fl) {
2781 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2782 "Attempted to execute control transfer"
2783 " when USB is disconnected");
2784 }
2785 return -ENOTTY;
2786 }
2787
2788 /* Ensure that we have sane parameters */
2789 if (!write_data) write_len = 0;
2790 if (!read_data) read_len = 0;
2791 if (write_len > PVR2_CTL_BUFFSIZE) {
2792 pvr2_trace(
2793 PVR2_TRACE_ERROR_LEGS,
2794 "Attempted to execute %d byte"
2795 " control-write transfer (limit=%d)",
2796 write_len,PVR2_CTL_BUFFSIZE);
2797 return -EINVAL;
2798 }
2799 if (read_len > PVR2_CTL_BUFFSIZE) {
2800 pvr2_trace(
2801 PVR2_TRACE_ERROR_LEGS,
2802 "Attempted to execute %d byte"
2803 " control-read transfer (limit=%d)",
2804 write_len,PVR2_CTL_BUFFSIZE);
2805 return -EINVAL;
2806 }
2807 if ((!write_len) && (!read_len)) {
2808 pvr2_trace(
2809 PVR2_TRACE_ERROR_LEGS,
2810 "Attempted to execute null control transfer?");
2811 return -EINVAL;
2812 }
2813
2814
2815 hdw->cmd_debug_state = 1;
2816 if (write_len) {
2817 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
2818 } else {
2819 hdw->cmd_debug_code = 0;
2820 }
2821 hdw->cmd_debug_write_len = write_len;
2822 hdw->cmd_debug_read_len = read_len;
2823
2824 /* Initialize common stuff */
2825 init_completion(&hdw->ctl_done);
2826 hdw->ctl_timeout_flag = 0;
2827 hdw->ctl_write_pend_flag = 0;
2828 hdw->ctl_read_pend_flag = 0;
2829 init_timer(&timer);
2830 timer.expires = jiffies + timeout;
2831 timer.data = (unsigned long)hdw;
2832 timer.function = pvr2_ctl_timeout;
2833
2834 if (write_len) {
2835 hdw->cmd_debug_state = 2;
2836 /* Transfer write data to internal buffer */
2837 for (idx = 0; idx < write_len; idx++) {
2838 hdw->ctl_write_buffer[idx] =
2839 ((unsigned char *)write_data)[idx];
2840 }
2841 /* Initiate a write request */
2842 usb_fill_bulk_urb(hdw->ctl_write_urb,
2843 hdw->usb_dev,
2844 usb_sndbulkpipe(hdw->usb_dev,
2845 PVR2_CTL_WRITE_ENDPOINT),
2846 hdw->ctl_write_buffer,
2847 write_len,
2848 pvr2_ctl_write_complete,
2849 hdw);
2850 hdw->ctl_write_urb->actual_length = 0;
2851 hdw->ctl_write_pend_flag = !0;
2852 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
2853 if (status < 0) {
2854 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2855 "Failed to submit write-control"
2856 " URB status=%d",status);
2857 hdw->ctl_write_pend_flag = 0;
2858 goto done;
2859 }
2860 }
2861
2862 if (read_len) {
2863 hdw->cmd_debug_state = 3;
2864 memset(hdw->ctl_read_buffer,0x43,read_len);
2865 /* Initiate a read request */
2866 usb_fill_bulk_urb(hdw->ctl_read_urb,
2867 hdw->usb_dev,
2868 usb_rcvbulkpipe(hdw->usb_dev,
2869 PVR2_CTL_READ_ENDPOINT),
2870 hdw->ctl_read_buffer,
2871 read_len,
2872 pvr2_ctl_read_complete,
2873 hdw);
2874 hdw->ctl_read_urb->actual_length = 0;
2875 hdw->ctl_read_pend_flag = !0;
2876 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
2877 if (status < 0) {
2878 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2879 "Failed to submit read-control"
2880 " URB status=%d",status);
2881 hdw->ctl_read_pend_flag = 0;
2882 goto done;
2883 }
2884 }
2885
2886 /* Start timer */
2887 add_timer(&timer);
2888
2889 /* Now wait for all I/O to complete */
2890 hdw->cmd_debug_state = 4;
2891 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2892 wait_for_completion(&hdw->ctl_done);
2893 }
2894 hdw->cmd_debug_state = 5;
2895
2896 /* Stop timer */
2897 del_timer_sync(&timer);
2898
2899 hdw->cmd_debug_state = 6;
2900 status = 0;
2901
2902 if (hdw->ctl_timeout_flag) {
2903 status = -ETIMEDOUT;
2904 if (!probe_fl) {
2905 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2906 "Timed out control-write");
2907 }
2908 goto done;
2909 }
2910
2911 if (write_len) {
2912 /* Validate results of write request */
2913 if ((hdw->ctl_write_urb->status != 0) &&
2914 (hdw->ctl_write_urb->status != -ENOENT) &&
2915 (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
2916 (hdw->ctl_write_urb->status != -ECONNRESET)) {
2917 /* USB subsystem is reporting some kind of failure
2918 on the write */
2919 status = hdw->ctl_write_urb->status;
2920 if (!probe_fl) {
2921 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2922 "control-write URB failure,"
2923 " status=%d",
2924 status);
2925 }
2926 goto done;
2927 }
2928 if (hdw->ctl_write_urb->actual_length < write_len) {
2929 /* Failed to write enough data */
2930 status = -EIO;
2931 if (!probe_fl) {
2932 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2933 "control-write URB short,"
2934 " expected=%d got=%d",
2935 write_len,
2936 hdw->ctl_write_urb->actual_length);
2937 }
2938 goto done;
2939 }
2940 }
2941 if (read_len) {
2942 /* Validate results of read request */
2943 if ((hdw->ctl_read_urb->status != 0) &&
2944 (hdw->ctl_read_urb->status != -ENOENT) &&
2945 (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
2946 (hdw->ctl_read_urb->status != -ECONNRESET)) {
2947 /* USB subsystem is reporting some kind of failure
2948 on the read */
2949 status = hdw->ctl_read_urb->status;
2950 if (!probe_fl) {
2951 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2952 "control-read URB failure,"
2953 " status=%d",
2954 status);
2955 }
2956 goto done;
2957 }
2958 if (hdw->ctl_read_urb->actual_length < read_len) {
2959 /* Failed to read enough data */
2960 status = -EIO;
2961 if (!probe_fl) {
2962 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2963 "control-read URB short,"
2964 " expected=%d got=%d",
2965 read_len,
2966 hdw->ctl_read_urb->actual_length);
2967 }
2968 goto done;
2969 }
2970 /* Transfer retrieved data out from internal buffer */
2971 for (idx = 0; idx < read_len; idx++) {
2972 ((unsigned char *)read_data)[idx] =
2973 hdw->ctl_read_buffer[idx];
2974 }
2975 }
2976
2977 done:
2978
2979 hdw->cmd_debug_state = 0;
2980 if ((status < 0) && (!probe_fl)) {
2981 pvr2_hdw_render_useless_unlocked(hdw);
2982 }
2983 return status;
2984 }
2985
2986
2987 int pvr2_send_request(struct pvr2_hdw *hdw,
2988 void *write_data,unsigned int write_len,
2989 void *read_data,unsigned int read_len)
2990 {
2991 return pvr2_send_request_ex(hdw,HZ*4,0,
2992 write_data,write_len,
2993 read_data,read_len);
2994 }
2995
2996 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
2997 {
2998 int ret;
2999
3000 LOCK_TAKE(hdw->ctl_lock);
3001
3002 hdw->cmd_buffer[0] = FX2CMD_REG_WRITE; /* write register prefix */
3003 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3004 hdw->cmd_buffer[5] = 0;
3005 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3006 hdw->cmd_buffer[7] = reg & 0xff;
3007
3008
3009 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3010
3011 LOCK_GIVE(hdw->ctl_lock);
3012
3013 return ret;
3014 }
3015
3016
3017 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
3018 {
3019 int ret = 0;
3020
3021 LOCK_TAKE(hdw->ctl_lock);
3022
3023 hdw->cmd_buffer[0] = FX2CMD_REG_READ; /* read register prefix */
3024 hdw->cmd_buffer[1] = 0;
3025 hdw->cmd_buffer[2] = 0;
3026 hdw->cmd_buffer[3] = 0;
3027 hdw->cmd_buffer[4] = 0;
3028 hdw->cmd_buffer[5] = 0;
3029 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3030 hdw->cmd_buffer[7] = reg & 0xff;
3031
3032 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3033 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3034
3035 LOCK_GIVE(hdw->ctl_lock);
3036
3037 return ret;
3038 }
3039
3040
3041 static void pvr2_hdw_render_useless_unlocked(struct pvr2_hdw *hdw)
3042 {
3043 if (!hdw->flag_ok) return;
3044 pvr2_trace(PVR2_TRACE_INIT,"render_useless");
3045 hdw->flag_ok = 0;
3046 if (hdw->vid_stream) {
3047 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
3048 }
3049 hdw->flag_streaming_enabled = 0;
3050 hdw->subsys_enabled_mask = 0;
3051 }
3052
3053
3054 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
3055 {
3056 LOCK_TAKE(hdw->ctl_lock);
3057 pvr2_hdw_render_useless_unlocked(hdw);
3058 LOCK_GIVE(hdw->ctl_lock);
3059 }
3060
3061
3062 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
3063 {
3064 int ret;
3065 pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
3066 ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
3067 if (ret == 1) {
3068 ret = usb_reset_device(hdw->usb_dev);
3069 usb_unlock_device(hdw->usb_dev);
3070 } else {
3071 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3072 "Failed to lock USB device ret=%d",ret);
3073 }
3074 if (init_pause_msec) {
3075 pvr2_trace(PVR2_TRACE_INFO,
3076 "Waiting %u msec for hardware to settle",
3077 init_pause_msec);
3078 msleep(init_pause_msec);
3079 }
3080
3081 }
3082
3083
3084 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
3085 {
3086 char da[1];
3087 unsigned int pipe;
3088 int ret;
3089
3090 if (!hdw->usb_dev) return;
3091
3092 pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
3093
3094 da[0] = val ? 0x01 : 0x00;
3095
3096 /* Write the CPUCS register on the 8051. The lsb of the register
3097 is the reset bit; a 1 asserts reset while a 0 clears it. */
3098 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
3099 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
3100 if (ret < 0) {
3101 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3102 "cpureset_assert(%d) error=%d",val,ret);
3103 pvr2_hdw_render_useless(hdw);
3104 }
3105 }
3106
3107
3108 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
3109 {
3110 int status;
3111 LOCK_TAKE(hdw->ctl_lock); do {
3112 pvr2_trace(PVR2_TRACE_INIT,"Requesting uproc hard reset");
3113 hdw->flag_ok = !0;
3114 hdw->cmd_buffer[0] = FX2CMD_DEEP_RESET;
3115 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
3116 } while (0); LOCK_GIVE(hdw->ctl_lock);
3117 return status;
3118 }
3119
3120
3121 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
3122 {
3123 int status;
3124 LOCK_TAKE(hdw->ctl_lock); do {
3125 pvr2_trace(PVR2_TRACE_INIT,"Requesting powerup");
3126 hdw->cmd_buffer[0] = FX2CMD_POWER_ON;
3127 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
3128 } while (0); LOCK_GIVE(hdw->ctl_lock);
3129 return status;
3130 }
3131
3132
3133 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
3134 {
3135 if (!hdw->decoder_ctrl) {
3136 pvr2_trace(PVR2_TRACE_INIT,
3137 "Unable to reset decoder: nothing attached");
3138 return -ENOTTY;
3139 }
3140
3141 if (!hdw->decoder_ctrl->force_reset) {
3142 pvr2_trace(PVR2_TRACE_INIT,
3143 "Unable to reset decoder: not implemented");
3144 return -ENOTTY;
3145 }
3146
3147 pvr2_trace(PVR2_TRACE_INIT,
3148 "Requesting decoder reset");
3149 hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
3150 return 0;
3151 }
3152
3153
3154 /* Stop / start video stream transport */
3155 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
3156 {
3157 int status;
3158 LOCK_TAKE(hdw->ctl_lock); do {
3159 hdw->cmd_buffer[0] =
3160 (runFl ? FX2CMD_STREAMING_ON : FX2CMD_STREAMING_OFF);
3161 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
3162 } while (0); LOCK_GIVE(hdw->ctl_lock);
3163 if (!status) {
3164 hdw->subsys_enabled_mask =
3165 ((hdw->subsys_enabled_mask &
3166 ~(1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) |
3167 (runFl ? (1<<PVR2_SUBSYS_B_USBSTREAM_RUN) : 0));
3168 }
3169 return status;
3170 }
3171
3172
3173 void pvr2_hdw_get_debug_info(const struct pvr2_hdw *hdw,
3174 struct pvr2_hdw_debug_info *ptr)
3175 {
3176 ptr->big_lock_held = hdw->big_lock_held;
3177 ptr->ctl_lock_held = hdw->ctl_lock_held;
3178 ptr->flag_ok = hdw->flag_ok;
3179 ptr->flag_disconnected = hdw->flag_disconnected;
3180 ptr->flag_init_ok = hdw->flag_init_ok;
3181 ptr->flag_streaming_enabled = hdw->flag_streaming_enabled;
3182 ptr->subsys_flags = hdw->subsys_enabled_mask;
3183 ptr->cmd_debug_state = hdw->cmd_debug_state;
3184 ptr->cmd_code = hdw->cmd_debug_code;
3185 ptr->cmd_debug_write_len = hdw->cmd_debug_write_len;
3186 ptr->cmd_debug_read_len = hdw->cmd_debug_read_len;
3187 ptr->cmd_debug_timeout = hdw->ctl_timeout_flag;
3188 ptr->cmd_debug_write_pend = hdw->ctl_write_pend_flag;
3189 ptr->cmd_debug_read_pend = hdw->ctl_read_pend_flag;
3190 ptr->cmd_debug_rstatus = hdw->ctl_read_urb->status;
3191 ptr->cmd_debug_wstatus = hdw->ctl_read_urb->status;
3192 }
3193
3194
3195 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
3196 {
3197 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
3198 }
3199
3200
3201 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
3202 {
3203 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
3204 }
3205
3206
3207 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
3208 {
3209 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
3210 }
3211
3212
3213 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
3214 {
3215 u32 cval,nval;
3216 int ret;
3217 if (~msk) {
3218 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
3219 if (ret) return ret;
3220 nval = (cval & ~msk) | (val & msk);
3221 pvr2_trace(PVR2_TRACE_GPIO,
3222 "GPIO direction changing 0x%x:0x%x"
3223 " from 0x%x to 0x%x",
3224 msk,val,cval,nval);
3225 } else {
3226 nval = val;
3227 pvr2_trace(PVR2_TRACE_GPIO,
3228 "GPIO direction changing to 0x%x",nval);
3229 }
3230 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
3231 }
3232
3233
3234 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
3235 {
3236 u32 cval,nval;
3237 int ret;
3238 if (~msk) {
3239 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
3240 if (ret) return ret;
3241 nval = (cval & ~msk) | (val & msk);
3242 pvr2_trace(PVR2_TRACE_GPIO,
3243 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
3244 msk,val,cval,nval);
3245 } else {
3246 nval = val;
3247 pvr2_trace(PVR2_TRACE_GPIO,
3248 "GPIO output changing to 0x%x",nval);
3249 }
3250 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
3251 }
3252
3253
3254 /* Find I2C address of eeprom */
3255 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
3256 {
3257 int result;
3258 LOCK_TAKE(hdw->ctl_lock); do {
3259 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
3260 result = pvr2_send_request(hdw,
3261 hdw->cmd_buffer,1,
3262 hdw->cmd_buffer,1);
3263 if (result < 0) break;
3264 result = hdw->cmd_buffer[0];
3265 } while(0); LOCK_GIVE(hdw->ctl_lock);
3266 return result;
3267 }
3268
3269
3270 int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
3271 u32 match_type, u32 match_chip, u64 reg_id,
3272 int setFl,u64 *val_ptr)
3273 {
3274 #ifdef CONFIG_VIDEO_ADV_DEBUG
3275 struct list_head *item;
3276 struct pvr2_i2c_client *cp;
3277 struct v4l2_register req;
3278 int stat = 0;
3279 int okFl = 0;
3280
3281 if (!capable(CAP_SYS_ADMIN)) return -EPERM;
3282
3283 req.match_type = match_type;
3284 req.match_chip = match_chip;
3285 req.reg = reg_id;
3286 if (setFl) req.val = *val_ptr;
3287 mutex_lock(&hdw->i2c_list_lock); do {
3288 list_for_each(item,&hdw->i2c_clients) {
3289 cp = list_entry(item,struct pvr2_i2c_client,list);
3290 if (!v4l2_chip_match_i2c_client(
3291 cp->client,
3292 req.match_type, req.match_chip)) {
3293 continue;
3294 }
3295 stat = pvr2_i2c_client_cmd(
3296 cp,(setFl ? VIDIOC_DBG_S_REGISTER :
3297 VIDIOC_DBG_G_REGISTER),&req);
3298 if (!setFl) *val_ptr = req.val;
3299 okFl = !0;
3300 break;
3301 }
3302 } while (0); mutex_unlock(&hdw->i2c_list_lock);
3303 if (okFl) {
3304 return stat;
3305 }
3306 return -EINVAL;
3307 #else
3308 return -ENOSYS;
3309 #endif
3310 }
3311
3312
3313 /*
3314 Stuff for Emacs to see, in order to encourage consistent editing style:
3315 *** Local Variables: ***
3316 *** mode: c ***
3317 *** fill-column: 75 ***
3318 *** tab-width: 8 ***
3319 *** c-basic-offset: 8 ***
3320 *** End: ***
3321 */
WRT350N Kernel Patches