| blob | 789b6fd79d881fe3a4827d7958f90efd3850b17d |
1 /*
2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Low-level exception handlers and MMU support
7 * rewritten by Paul Mackerras.
8 * Copyright (C) 1996 Paul Mackerras.
9 * MPC8xx modifications by Dan Malek
10 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
11 *
12 * This file contains low-level support and setup for PowerPC 8xx
13 * embedded processors, including trap and interrupt dispatch.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
19 *
20 */
22 #include <asm/processor.h>
23 #include <asm/page.h>
24 #include <asm/mmu.h>
25 #include <asm/cache.h>
26 #include <asm/pgtable.h>
27 #include <asm/cputable.h>
28 #include <asm/thread_info.h>
29 #include <asm/ppc_asm.h>
30 #include <asm/asm-offsets.h>
32 /* Macro to make the code more readable. */
33 #ifdef CONFIG_8xx_CPU6
34 #define DO_8xx_CPU6(val, reg) \
35 li reg, val; \
36 stw reg, 12(r0); \
37 lwz reg, 12(r0);
38 #else
39 #define DO_8xx_CPU6(val, reg)
40 #endif
41 .text
42 .globl _stext
43 _stext:
44 .text
45 .globl _start
46 _start:
48 /* MPC8xx
49 * This port was done on an MBX board with an 860. Right now I only
50 * support an ELF compressed (zImage) boot from EPPC-Bug because the
51 * code there loads up some registers before calling us:
52 * r3: ptr to board info data
53 * r4: initrd_start or if no initrd then 0
54 * r5: initrd_end - unused if r4 is 0
55 * r6: Start of command line string
56 * r7: End of command line string
57 *
58 * I decided to use conditional compilation instead of checking PVR and
59 * adding more processor specific branches around code I don't need.
60 * Since this is an embedded processor, I also appreciate any memory
61 * savings I can get.
62 *
63 * The MPC8xx does not have any BATs, but it supports large page sizes.
64 * We first initialize the MMU to support 8M byte pages, then load one
65 * entry into each of the instruction and data TLBs to map the first
66 * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to
67 * the "internal" processor registers before MMU_init is called.
68 *
69 * The TLB code currently contains a major hack. Since I use the condition
70 * code register, I have to save and restore it. I am out of registers, so
71 * I just store it in memory location 0 (the TLB handlers are not reentrant).
72 * To avoid making any decisions, I need to use the "segment" valid bit
73 * in the first level table, but that would require many changes to the
74 * Linux page directory/table functions that I don't want to do right now.
75 *
76 * I used to use SPRG2 for a temporary register in the TLB handler, but it
77 * has since been put to other uses. I now use a hack to save a register
78 * and the CCR at memory location 0.....Someday I'll fix this.....
79 * -- Dan
80 */
81 .globl __start
82 __start:
83 mr r31,r3 /* save parameters */
84 mr r30,r4
85 mr r29,r5
86 mr r28,r6
87 mr r27,r7
89 /* We have to turn on the MMU right away so we get cache modes
90 * set correctly.
91 */
92 bl initial_mmu
94 /* We now have the lower 8 Meg mapped into TLB entries, and the caches
95 * ready to work.
96 */
98 turn_on_mmu:
99 mfmsr r0
100 ori r0,r0,MSR_DR|MSR_IR
101 mtspr SPRN_SRR1,r0
102 lis r0,start_here@h
103 ori r0,r0,start_here@l
104 mtspr SPRN_SRR0,r0
105 SYNC
106 rfi /* enables MMU */
108 /*
109 * Exception entry code. This code runs with address translation
110 * turned off, i.e. using physical addresses.
111 * We assume sprg3 has the physical address of the current
112 * task's thread_struct.
113 */
114 #define EXCEPTION_PROLOG \
115 mtspr SPRN_SPRG0,r10; \
116 mtspr SPRN_SPRG1,r11; \
117 mfcr r10; \
118 EXCEPTION_PROLOG_1; \
119 EXCEPTION_PROLOG_2
121 #define EXCEPTION_PROLOG_1 \
122 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
123 andi. r11,r11,MSR_PR; \
124 tophys(r11,r1); /* use tophys(r1) if kernel */ \
125 beq 1f; \
126 mfspr r11,SPRN_SPRG3; \
127 lwz r11,THREAD_INFO-THREAD(r11); \
128 addi r11,r11,THREAD_SIZE; \
129 tophys(r11,r11); \
130 1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
133 #define EXCEPTION_PROLOG_2 \
134 CLR_TOP32(r11); \
135 stw r10,_CCR(r11); /* save registers */ \
136 stw r12,GPR12(r11); \
137 stw r9,GPR9(r11); \
138 mfspr r10,SPRN_SPRG0; \
139 stw r10,GPR10(r11); \
140 mfspr r12,SPRN_SPRG1; \
141 stw r12,GPR11(r11); \
142 mflr r10; \
143 stw r10,_LINK(r11); \
144 mfspr r12,SPRN_SRR0; \
145 mfspr r9,SPRN_SRR1; \
146 stw r1,GPR1(r11); \
147 stw r1,0(r11); \
148 tovirt(r1,r11); /* set new kernel sp */ \
149 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
150 MTMSRD(r10); /* (except for mach check in rtas) */ \
151 stw r0,GPR0(r11); \
152 SAVE_4GPRS(3, r11); \
153 SAVE_2GPRS(7, r11)
155 /*
156 * Note: code which follows this uses cr0.eq (set if from kernel),
157 * r11, r12 (SRR0), and r9 (SRR1).
158 *
159 * Note2: once we have set r1 we are in a position to take exceptions
160 * again, and we could thus set MSR:RI at that point.
161 */
163 /*
164 * Exception vectors.
165 */
166 #define EXCEPTION(n, label, hdlr, xfer) \
167 . = n; \
168 label: \
169 EXCEPTION_PROLOG; \
170 addi r3,r1,STACK_FRAME_OVERHEAD; \
171 xfer(n, hdlr)
173 #define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
174 li r10,trap; \
175 stw r10,TRAP(r11); \
176 li r10,MSR_KERNEL; \
177 copyee(r10, r9); \
178 bl tfer; \
179 i##n: \
180 .long hdlr; \
181 .long ret
183 #define COPY_EE(d, s) rlwimi d,s,0,16,16
184 #define NOCOPY(d, s)
186 #define EXC_XFER_STD(n, hdlr) \
187 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
188 ret_from_except_full)
190 #define EXC_XFER_LITE(n, hdlr) \
191 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
192 ret_from_except)
194 #define EXC_XFER_EE(n, hdlr) \
195 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
196 ret_from_except_full)
198 #define EXC_XFER_EE_LITE(n, hdlr) \
199 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
200 ret_from_except)
202 /* System reset */
203 EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
205 /* Machine check */
206 . = 0x200
207 MachineCheck:
208 EXCEPTION_PROLOG
209 mfspr r4,SPRN_DAR
210 stw r4,_DAR(r11)
211 mfspr r5,SPRN_DSISR
212 stw r5,_DSISR(r11)
213 addi r3,r1,STACK_FRAME_OVERHEAD
214 EXC_XFER_STD(0x200, machine_check_exception)
216 /* Data access exception.
217 * This is "never generated" by the MPC8xx. We jump to it for other
218 * translation errors.
219 */
220 . = 0x300
221 DataAccess:
222 EXCEPTION_PROLOG
223 mfspr r10,SPRN_DSISR
224 stw r10,_DSISR(r11)
225 mr r5,r10
226 mfspr r4,SPRN_DAR
227 EXC_XFER_EE_LITE(0x300, handle_page_fault)
229 /* Instruction access exception.
230 * This is "never generated" by the MPC8xx. We jump to it for other
231 * translation errors.
232 */
233 . = 0x400
234 InstructionAccess:
235 EXCEPTION_PROLOG
236 mr r4,r12
237 mr r5,r9
238 EXC_XFER_EE_LITE(0x400, handle_page_fault)
240 /* External interrupt */
241 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
243 /* Alignment exception */
244 . = 0x600
245 Alignment:
246 EXCEPTION_PROLOG
247 mfspr r4,SPRN_DAR
248 stw r4,_DAR(r11)
249 mfspr r5,SPRN_DSISR
250 stw r5,_DSISR(r11)
251 addi r3,r1,STACK_FRAME_OVERHEAD
252 EXC_XFER_EE(0x600, alignment_exception)
254 /* Program check exception */
255 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
257 /* No FPU on MPC8xx. This exception is not supposed to happen.
258 */
259 EXCEPTION(0x800, FPUnavailable, unknown_exception, EXC_XFER_STD)
261 /* Decrementer */
262 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
264 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE)
265 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE)
267 /* System call */
268 . = 0xc00
269 SystemCall:
270 EXCEPTION_PROLOG
271 EXC_XFER_EE_LITE(0xc00, DoSyscall)
273 /* Single step - not used on 601 */
274 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
275 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE)
276 EXCEPTION(0xf00, Trap_0f, unknown_exception, EXC_XFER_EE)
278 /* On the MPC8xx, this is a software emulation interrupt. It occurs
279 * for all unimplemented and illegal instructions.
280 */
281 EXCEPTION(0x1000, SoftEmu, SoftwareEmulation, EXC_XFER_STD)
283 . = 0x1100
284 /*
285 * For the MPC8xx, this is a software tablewalk to load the instruction
286 * TLB. It is modelled after the example in the Motorola manual. The task
287 * switch loads the M_TWB register with the pointer to the first level table.
288 * If we discover there is no second level table (value is zero) or if there
289 * is an invalid pte, we load that into the TLB, which causes another fault
290 * into the TLB Error interrupt where we can handle such problems.
291 * We have to use the MD_xxx registers for the tablewalk because the
292 * equivalent MI_xxx registers only perform the attribute functions.
293 */
294 InstructionTLBMiss:
295 #ifdef CONFIG_8xx_CPU6
296 stw r3, 8(r0)
297 #endif
298 DO_8xx_CPU6(0x3f80, r3)
299 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */
300 mfcr r10
301 stw r10, 0(r0)
302 stw r11, 4(r0)
303 mfspr r10, SPRN_SRR0 /* Get effective address of fault */
304 DO_8xx_CPU6(0x3780, r3)
305 mtspr SPRN_MD_EPN, r10 /* Have to use MD_EPN for walk, MI_EPN can't */
306 mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */
308 /* If we are faulting a kernel address, we have to use the
309 * kernel page tables.
310 */
311 andi. r11, r10, 0x0800 /* Address >= 0x80000000 */
312 beq 3f
313 lis r11, swapper_pg_dir@h
314 ori r11, r11, swapper_pg_dir@l
315 rlwimi r10, r11, 0, 2, 19
316 3:
317 lwz r11, 0(r10) /* Get the level 1 entry */
318 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
319 beq 2f /* If zero, don't try to find a pte */
321 /* We have a pte table, so load the MI_TWC with the attributes
322 * for this "segment."
323 */
324 ori r11,r11,1 /* Set valid bit */
325 DO_8xx_CPU6(0x2b80, r3)
326 mtspr SPRN_MI_TWC, r11 /* Set segment attributes */
327 DO_8xx_CPU6(0x3b80, r3)
328 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
329 mfspr r11, SPRN_MD_TWC /* ....and get the pte address */
330 lwz r10, 0(r11) /* Get the pte */
332 <<<<<<< HEAD:arch/ppc/kernel/head_8xx.S
333 =======
334 #ifdef CONFIG_SWAP
335 /* do not set the _PAGE_ACCESSED bit of a non-present page */
336 andi. r11, r10, _PAGE_PRESENT
337 beq 4f
338 ori r10, r10, _PAGE_ACCESSED
339 mfspr r11, SPRN_MD_TWC /* get the pte address again */
340 stw r10, 0(r11)
341 4:
342 #else
343 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/ppc/kernel/head_8xx.S
344 ori r10, r10, _PAGE_ACCESSED
345 stw r10, 0(r11)
346 <<<<<<< HEAD:arch/ppc/kernel/head_8xx.S
347 =======
348 #endif
349 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/ppc/kernel/head_8xx.S
351 /* The Linux PTE won't go exactly into the MMU TLB.
352 * Software indicator bits 21, 22 and 28 must be clear.
353 * Software indicator bits 24, 25, 26, and 27 must be
354 * set. All other Linux PTE bits control the behavior
355 * of the MMU.
356 */
357 2: li r11, 0x00f0
358 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
359 DO_8xx_CPU6(0x2d80, r3)
360 mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
362 mfspr r10, SPRN_M_TW /* Restore registers */
363 lwz r11, 0(r0)
364 mtcr r11
365 lwz r11, 4(r0)
366 #ifdef CONFIG_8xx_CPU6
367 lwz r3, 8(r0)
368 #endif
369 rfi
371 . = 0x1200
372 DataStoreTLBMiss:
373 stw r3, 8(r0)
374 DO_8xx_CPU6(0x3f80, r3)
375 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */
376 mfcr r10
377 stw r10, 0(r0)
378 stw r11, 4(r0)
379 mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */
381 /* If we are faulting a kernel address, we have to use the
382 * kernel page tables.
383 */
384 andi. r11, r10, 0x0800
385 beq 3f
386 lis r11, swapper_pg_dir@h
387 ori r11, r11, swapper_pg_dir@l
388 rlwimi r10, r11, 0, 2, 19
389 stw r12, 16(r0)
390 b LoadLargeDTLB
391 3:
392 lwz r11, 0(r10) /* Get the level 1 entry */
393 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
394 beq 2f /* If zero, don't try to find a pte */
396 /* We have a pte table, so load fetch the pte from the table.
397 */
398 ori r11, r11, 1 /* Set valid bit in physical L2 page */
399 DO_8xx_CPU6(0x3b80, r3)
400 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
401 mfspr r10, SPRN_MD_TWC /* ....and get the pte address */
402 lwz r10, 0(r10) /* Get the pte */
404 /* Insert the Guarded flag into the TWC from the Linux PTE.
405 * It is bit 27 of both the Linux PTE and the TWC (at least
406 * I got that right :-). It will be better when we can put
407 * this into the Linux pgd/pmd and load it in the operation
408 * above.
409 */
410 rlwimi r11, r10, 0, 27, 27
411 DO_8xx_CPU6(0x3b80, r3)
412 mtspr SPRN_MD_TWC, r11
414 <<<<<<< HEAD:arch/ppc/kernel/head_8xx.S
415 mfspr r11, SPRN_MD_TWC /* get the pte address again */
416 =======
417 #ifdef CONFIG_SWAP
418 /* do not set the _PAGE_ACCESSED bit of a non-present page */
419 andi. r11, r10, _PAGE_PRESENT
420 beq 4f
421 ori r10, r10, _PAGE_ACCESSED
422 4:
423 /* and update pte in table */
424 #else
425 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/ppc/kernel/head_8xx.S
426 ori r10, r10, _PAGE_ACCESSED
427 <<<<<<< HEAD:arch/ppc/kernel/head_8xx.S
428 =======
429 #endif
430 mfspr r11, SPRN_MD_TWC /* get the pte address again */
431 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/ppc/kernel/head_8xx.S
432 stw r10, 0(r11)
434 /* The Linux PTE won't go exactly into the MMU TLB.
435 * Software indicator bits 21, 22 and 28 must be clear.
436 * Software indicator bits 24, 25, 26, and 27 must be
437 * set. All other Linux PTE bits control the behavior
438 * of the MMU.
439 */
440 2: li r11, 0x00f0
441 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
442 DO_8xx_CPU6(0x3d80, r3)
443 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
445 mfspr r10, SPRN_M_TW /* Restore registers */
446 lwz r11, 0(r0)
447 mtcr r11
448 lwz r11, 4(r0)
449 lwz r3, 8(r0)
450 rfi
452 /* This is an instruction TLB error on the MPC8xx. This could be due
453 * to many reasons, such as executing guarded memory or illegal instruction
454 * addresses. There is nothing to do but handle a big time error fault.
455 */
456 . = 0x1300
457 InstructionTLBError:
458 b InstructionAccess
460 LoadLargeDTLB:
461 li r12, 0
462 lwz r11, 0(r10) /* Get the level 1 entry */
463 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
464 beq 3f /* If zero, don't try to find a pte */
466 /* We have a pte table, so load fetch the pte from the table.
467 */
468 ori r11, r11, 1 /* Set valid bit in physical L2 page */
469 DO_8xx_CPU6(0x3b80, r3)
470 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
471 mfspr r10, SPRN_MD_TWC /* ....and get the pte address */
472 lwz r10, 0(r10) /* Get the pte */
474 /* Insert the Guarded flag into the TWC from the Linux PTE.
475 * It is bit 27 of both the Linux PTE and the TWC (at least
476 * I got that right :-). It will be better when we can put
477 * this into the Linux pgd/pmd and load it in the operation
478 * above.
479 */
480 rlwimi r11, r10, 0, 27, 27
482 rlwimi r12, r10, 0, 0, 9 /* extract phys. addr */
483 mfspr r3, SPRN_MD_EPN
484 rlwinm r3, r3, 0, 0, 9 /* extract virtual address */
485 tophys(r3, r3)
486 cmpw r3, r12 /* only use 8M page if it is a direct
487 kernel mapping */
488 bne 1f
489 ori r11, r11, MD_PS8MEG
490 li r12, 1
491 b 2f
492 1:
493 li r12, 0 /* can't use 8MB TLB, so zero r12. */
494 2:
495 DO_8xx_CPU6(0x3b80, r3)
496 mtspr SPRN_MD_TWC, r11
498 /* The Linux PTE won't go exactly into the MMU TLB.
499 * Software indicator bits 21, 22 and 28 must be clear.
500 * Software indicator bits 24, 25, 26, and 27 must be
501 * set. All other Linux PTE bits control the behavior
502 * of the MMU.
503 */
504 3: li r11, 0x00f0
505 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
506 cmpwi r12, 1
507 bne 4f
508 ori r10, r10, 0x8
510 mfspr r12, SPRN_MD_EPN
511 lis r3, 0xff80 /* 10-19 must be clear for 8MB TLB */
512 ori r3, r3, 0x0fff
513 and r12, r3, r12
514 DO_8xx_CPU6(0x3780, r3)
515 mtspr SPRN_MD_EPN, r12
517 lis r3, 0xff80 /* 10-19 must be clear for 8MB TLB */
518 ori r3, r3, 0x0fff
519 and r10, r3, r10
520 4:
521 DO_8xx_CPU6(0x3d80, r3)
522 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
524 mfspr r10, SPRN_M_TW /* Restore registers */
525 lwz r11, 0(r0)
526 mtcr r11
527 lwz r11, 4(r0)
529 lwz r12, 16(r0)
530 lwz r3, 8(r0)
531 rfi
533 /* This is the data TLB error on the MPC8xx. This could be due to
534 * many reasons, including a dirty update to a pte. We can catch that
535 * one here, but anything else is an error. First, we track down the
536 * Linux pte. If it is valid, write access is allowed, but the
537 * page dirty bit is not set, we will set it and reload the TLB. For
538 * any other case, we bail out to a higher level function that can
539 * handle it.
540 */
541 . = 0x1400
542 DataTLBError:
543 #ifdef CONFIG_8xx_CPU6
544 stw r3, 8(r0)
545 #endif
546 DO_8xx_CPU6(0x3f80, r3)
547 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */
548 mfcr r10
549 stw r10, 0(r0)
550 stw r11, 4(r0)
552 /* First, make sure this was a store operation.
553 */
554 mfspr r10, SPRN_DSISR
555 andis. r11, r10, 0x0200 /* If set, indicates store op */
556 beq 2f
558 /* The EA of a data TLB miss is automatically stored in the MD_EPN
559 * register. The EA of a data TLB error is automatically stored in
560 * the DAR, but not the MD_EPN register. We must copy the 20 most
561 * significant bits of the EA from the DAR to MD_EPN before we
562 * start walking the page tables. We also need to copy the CASID
563 * value from the M_CASID register.
564 * Addendum: The EA of a data TLB error is _supposed_ to be stored
565 * in DAR, but it seems that this doesn't happen in some cases, such
566 * as when the error is due to a dcbi instruction to a page with a
567 * TLB that doesn't have the changed bit set. In such cases, there
568 * does not appear to be any way to recover the EA of the error
569 * since it is neither in DAR nor MD_EPN. As a workaround, the
570 * _PAGE_HWWRITE bit is set for all kernel data pages when the PTEs
571 * are initialized in mapin_ram(). This will avoid the problem,
572 * assuming we only use the dcbi instruction on kernel addresses.
573 */
574 mfspr r10, SPRN_DAR
575 rlwinm r11, r10, 0, 0, 19
576 ori r11, r11, MD_EVALID
577 mfspr r10, SPRN_M_CASID
578 rlwimi r11, r10, 0, 28, 31
579 DO_8xx_CPU6(0x3780, r3)
580 mtspr SPRN_MD_EPN, r11
582 mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */
584 /* If we are faulting a kernel address, we have to use the
585 * kernel page tables.
586 */
587 andi. r11, r10, 0x0800
588 beq 3f
589 lis r11, swapper_pg_dir@h
590 ori r11, r11, swapper_pg_dir@l
591 rlwimi r10, r11, 0, 2, 19
592 3:
593 lwz r11, 0(r10) /* Get the level 1 entry */
594 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
595 beq 2f /* If zero, bail */
597 /* We have a pte table, so fetch the pte from the table.
598 */
599 ori r11, r11, 1 /* Set valid bit in physical L2 page */
600 DO_8xx_CPU6(0x3b80, r3)
601 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
602 mfspr r11, SPRN_MD_TWC /* ....and get the pte address */
603 lwz r10, 0(r11) /* Get the pte */
605 andi. r11, r10, _PAGE_RW /* Is it writeable? */
606 beq 2f /* Bail out if not */
608 /* Update 'changed', among others.
609 */
610 <<<<<<< HEAD:arch/ppc/kernel/head_8xx.S
611 =======
612 #ifdef CONFIG_SWAP
613 ori r10, r10, _PAGE_DIRTY|_PAGE_HWWRITE
614 /* do not set the _PAGE_ACCESSED bit of a non-present page */
615 andi. r11, r10, _PAGE_PRESENT
616 beq 4f
617 ori r10, r10, _PAGE_ACCESSED
618 4:
619 #else
620 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/ppc/kernel/head_8xx.S
621 ori r10, r10, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
622 <<<<<<< HEAD:arch/ppc/kernel/head_8xx.S
623 =======
624 #endif
625 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/ppc/kernel/head_8xx.S
626 mfspr r11, SPRN_MD_TWC /* Get pte address again */
627 stw r10, 0(r11) /* and update pte in table */
629 /* The Linux PTE won't go exactly into the MMU TLB.
630 * Software indicator bits 21, 22 and 28 must be clear.
631 * Software indicator bits 24, 25, 26, and 27 must be
632 * set. All other Linux PTE bits control the behavior
633 * of the MMU.
634 */
635 li r11, 0x00f0
636 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
637 DO_8xx_CPU6(0x3d80, r3)
638 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
640 mfspr r10, SPRN_M_TW /* Restore registers */
641 lwz r11, 0(r0)
642 mtcr r11
643 lwz r11, 4(r0)
644 #ifdef CONFIG_8xx_CPU6
645 lwz r3, 8(r0)
646 #endif
647 rfi
648 2:
649 mfspr r10, SPRN_M_TW /* Restore registers */
650 lwz r11, 0(r0)
651 mtcr r11
652 lwz r11, 4(r0)
653 #ifdef CONFIG_8xx_CPU6
654 lwz r3, 8(r0)
655 #endif
656 b DataAccess
658 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
659 EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE)
660 EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE)
661 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
662 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
663 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE)
664 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE)
666 /* On the MPC8xx, these next four traps are used for development
667 * support of breakpoints and such. Someday I will get around to
668 * using them.
669 */
670 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE)
671 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
672 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE)
673 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE)
675 . = 0x2000
677 .globl giveup_fpu
678 giveup_fpu:
679 blr
681 /*
682 * This is where the main kernel code starts.
683 */
684 start_here:
685 /* ptr to current */
686 lis r2,init_task@h
687 ori r2,r2,init_task@l
689 /* ptr to phys current thread */
690 tophys(r4,r2)
691 addi r4,r4,THREAD /* init task's THREAD */
692 mtspr SPRN_SPRG3,r4
693 li r3,0
694 mtspr SPRN_SPRG2,r3 /* 0 => r1 has kernel sp */
696 /* stack */
697 lis r1,init_thread_union@ha
698 addi r1,r1,init_thread_union@l
699 li r0,0
700 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
702 bl early_init /* We have to do this with MMU on */
704 /*
705 * Decide what sort of machine this is and initialize the MMU.
706 */
707 mr r3,r31
708 mr r4,r30
709 mr r5,r29
710 mr r6,r28
711 mr r7,r27
712 bl machine_init
713 bl MMU_init
715 /*
716 * Go back to running unmapped so we can load up new values
717 * and change to using our exception vectors.
718 * On the 8xx, all we have to do is invalidate the TLB to clear
719 * the old 8M byte TLB mappings and load the page table base register.
720 */
721 /* The right way to do this would be to track it down through
722 * init's THREAD like the context switch code does, but this is
723 * easier......until someone changes init's static structures.
724 */
725 lis r6, swapper_pg_dir@h
726 ori r6, r6, swapper_pg_dir@l
727 tophys(r6,r6)
728 #ifdef CONFIG_8xx_CPU6
729 lis r4, cpu6_errata_word@h
730 ori r4, r4, cpu6_errata_word@l
731 li r3, 0x3980
732 stw r3, 12(r4)
733 lwz r3, 12(r4)
734 #endif
735 mtspr SPRN_M_TWB, r6
736 lis r4,2f@h
737 ori r4,r4,2f@l
738 tophys(r4,r4)
739 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
740 mtspr SPRN_SRR0,r4
741 mtspr SPRN_SRR1,r3
742 rfi
743 /* Load up the kernel context */
744 2:
745 SYNC /* Force all PTE updates to finish */
746 tlbia /* Clear all TLB entries */
747 sync /* wait for tlbia/tlbie to finish */
748 TLBSYNC /* ... on all CPUs */
750 /* set up the PTE pointers for the Abatron bdiGDB.
751 */
752 tovirt(r6,r6)
753 lis r5, abatron_pteptrs@h
754 ori r5, r5, abatron_pteptrs@l
755 stw r5, 0xf0(r0) /* Must match your Abatron config file */
756 tophys(r5,r5)
757 stw r6, 0(r5)
759 /* Now turn on the MMU for real! */
760 li r4,MSR_KERNEL
761 lis r3,start_kernel@h
762 ori r3,r3,start_kernel@l
763 mtspr SPRN_SRR0,r3
764 mtspr SPRN_SRR1,r4
765 rfi /* enable MMU and jump to start_kernel */
767 /* Set up the initial MMU state so we can do the first level of
768 * kernel initialization. This maps the first 8 MBytes of memory 1:1
769 * virtual to physical. Also, set the cache mode since that is defined
770 * by TLB entries and perform any additional mapping (like of the IMMR).
771 * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel,
772 * 24 Mbytes of data, and the 8M IMMR space. Anything not covered by
773 * these mappings is mapped by page tables.
774 */
775 initial_mmu:
776 tlbia /* Invalidate all TLB entries */
777 #ifdef CONFIG_PIN_TLB
778 lis r8, MI_RSV4I@h
779 ori r8, r8, 0x1c00
780 #else
781 li r8, 0
782 #endif
783 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */
785 #ifdef CONFIG_PIN_TLB
786 lis r10, (MD_RSV4I | MD_RESETVAL)@h
787 ori r10, r10, 0x1c00
788 mr r8, r10
789 #else
790 lis r10, MD_RESETVAL@h
791 #endif
792 #ifndef CONFIG_8xx_COPYBACK
793 oris r10, r10, MD_WTDEF@h
794 #endif
795 mtspr SPRN_MD_CTR, r10 /* Set data TLB control */
797 /* Now map the lower 8 Meg into the TLBs. For this quick hack,
798 * we can load the instruction and data TLB registers with the
799 * same values.
800 */
801 lis r8, KERNELBASE@h /* Create vaddr for TLB */
802 ori r8, r8, MI_EVALID /* Mark it valid */
803 mtspr SPRN_MI_EPN, r8
804 mtspr SPRN_MD_EPN, r8
805 li r8, MI_PS8MEG /* Set 8M byte page */
806 ori r8, r8, MI_SVALID /* Make it valid */
807 mtspr SPRN_MI_TWC, r8
808 mtspr SPRN_MD_TWC, r8
809 li r8, MI_BOOTINIT /* Create RPN for address 0 */
810 mtspr SPRN_MI_RPN, r8 /* Store TLB entry */
811 mtspr SPRN_MD_RPN, r8
812 lis r8, MI_Kp@h /* Set the protection mode */
813 mtspr SPRN_MI_AP, r8
814 mtspr SPRN_MD_AP, r8
816 /* Map another 8 MByte at the IMMR to get the processor
817 * internal registers (among other things).
818 */
819 #ifdef CONFIG_PIN_TLB
820 addi r10, r10, 0x0100
821 mtspr SPRN_MD_CTR, r10
822 #endif
823 mfspr r9, 638 /* Get current IMMR */
824 andis. r9, r9, 0xff80 /* Get 8Mbyte boundary */
826 mr r8, r9 /* Create vaddr for TLB */
827 ori r8, r8, MD_EVALID /* Mark it valid */
828 mtspr SPRN_MD_EPN, r8
829 li r8, MD_PS8MEG /* Set 8M byte page */
830 ori r8, r8, MD_SVALID /* Make it valid */
831 mtspr SPRN_MD_TWC, r8
832 mr r8, r9 /* Create paddr for TLB */
833 ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
834 mtspr SPRN_MD_RPN, r8
836 #ifdef CONFIG_PIN_TLB
837 /* Map two more 8M kernel data pages.
838 */
839 addi r10, r10, 0x0100
840 mtspr SPRN_MD_CTR, r10
842 lis r8, KERNELBASE@h /* Create vaddr for TLB */
843 addis r8, r8, 0x0080 /* Add 8M */
844 ori r8, r8, MI_EVALID /* Mark it valid */
845 mtspr SPRN_MD_EPN, r8
846 li r9, MI_PS8MEG /* Set 8M byte page */
847 ori r9, r9, MI_SVALID /* Make it valid */
848 mtspr SPRN_MD_TWC, r9
849 li r11, MI_BOOTINIT /* Create RPN for address 0 */
850 addis r11, r11, 0x0080 /* Add 8M */
851 mtspr SPRN_MD_RPN, r11
853 addi r10, r10, 0x0100
854 mtspr SPRN_MD_CTR, r10
856 addis r8, r8, 0x0080 /* Add 8M */
857 mtspr SPRN_MD_EPN, r8
858 mtspr SPRN_MD_TWC, r9
859 addis r11, r11, 0x0080 /* Add 8M */
860 mtspr SPRN_MD_RPN, r11
861 #endif
863 /* Since the cache is enabled according to the information we
864 * just loaded into the TLB, invalidate and enable the caches here.
865 * We should probably check/set other modes....later.
866 */
867 lis r8, IDC_INVALL@h
868 mtspr SPRN_IC_CST, r8
869 mtspr SPRN_DC_CST, r8
870 lis r8, IDC_ENABLE@h
871 mtspr SPRN_IC_CST, r8
872 #ifdef CONFIG_8xx_COPYBACK
873 mtspr SPRN_DC_CST, r8
874 #else
875 /* For a debug option, I left this here to easily enable
876 * the write through cache mode
877 */
878 lis r8, DC_SFWT@h
879 mtspr SPRN_DC_CST, r8
880 lis r8, IDC_ENABLE@h
881 mtspr SPRN_DC_CST, r8
882 #endif
883 blr
886 /*
887 * Set up to use a given MMU context.
888 * r3 is context number, r4 is PGD pointer.
889 *
890 * We place the physical address of the new task page directory loaded
891 * into the MMU base register, and set the ASID compare register with
892 * the new "context."
893 */
894 _GLOBAL(set_context)
896 #ifdef CONFIG_BDI_SWITCH
897 /* Context switch the PTE pointer for the Abatron BDI2000.
898 * The PGDIR is passed as second argument.
899 */
900 lis r5, KERNELBASE@h
901 lwz r5, 0xf0(r5)
902 stw r4, 0x4(r5)
903 #endif
905 #ifdef CONFIG_8xx_CPU6
906 lis r6, cpu6_errata_word@h
907 ori r6, r6, cpu6_errata_word@l
908 tophys (r4, r4)
909 li r7, 0x3980
910 stw r7, 12(r6)
911 lwz r7, 12(r6)
912 mtspr SPRN_M_TWB, r4 /* Update MMU base address */
913 li r7, 0x3380
914 stw r7, 12(r6)
915 lwz r7, 12(r6)
916 mtspr SPRN_M_CASID, r3 /* Update context */
917 #else
918 mtspr SPRN_M_CASID,r3 /* Update context */
919 tophys (r4, r4)
920 mtspr SPRN_M_TWB, r4 /* and pgd */
921 #endif
922 SYNC
923 blr
925 #ifdef CONFIG_8xx_CPU6
926 /* It's here because it is unique to the 8xx.
927 * It is important we get called with interrupts disabled. I used to
928 * do that, but it appears that all code that calls this already had
929 * interrupt disabled.
930 */
931 .globl set_dec_cpu6
932 set_dec_cpu6:
933 lis r7, cpu6_errata_word@h
934 ori r7, r7, cpu6_errata_word@l
935 li r4, 0x2c00
936 stw r4, 8(r7)
937 lwz r4, 8(r7)
938 mtspr 22, r3 /* Update Decrementer */
939 SYNC
940 blr
941 #endif
943 /*
944 * We put a few things here that have to be page-aligned.
945 * This stuff goes at the beginning of the data segment,
946 * which is page-aligned.
947 */
948 .data
949 .globl sdata
950 sdata:
951 .globl empty_zero_page
952 empty_zero_page:
953 .space 4096
955 .globl swapper_pg_dir
956 swapper_pg_dir:
957 .space 4096
959 /*
960 * This space gets a copy of optional info passed to us by the bootstrap
961 * Used to pass parameters into the kernel like root=/dev/sda1, etc.
962 */
963 .globl cmd_line
964 cmd_line:
965 .space 512
967 /* Room for two PTE table poiners, usually the kernel and current user
968 * pointer to their respective root page table (pgdir).
969 */
970 abatron_pteptrs:
971 .space 8
973 #ifdef CONFIG_8xx_CPU6
974 .globl cpu6_errata_word
975 cpu6_errata_word:
976 .space 16
977 #endif