arch/sh/kernel/cpu/sh4a/setup-sh7780.c

   1 /*
   2  * SH7780 Setup
   3  *
   4  *  Copyright (C) 2006  Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/platform_device.h>
  11 #include <linux/init.h>
  12 #include <linux/serial.h>
  13 #include <linux/io.h>
  14 <<<<<<< HEAD:arch/sh/kernel/cpu/sh4a/setup-sh7780.c
  15 #include <asm/sci.h>
  16 =======
  17 #include <linux/serial_sci.h>
  18 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/sh/kernel/cpu/sh4a/setup-sh7780.c
  19
  20 static struct resource rtc_resources[] = {
  21         [0] = {
  22                 .start  = 0xffe80000,
  23                 .end    = 0xffe80000 + 0x58 - 1,
  24                 .flags  = IORESOURCE_IO,
  25         },
  26         [1] = {
  27                 /* Period IRQ */
  28                 .start  = 21,
  29                 .flags  = IORESOURCE_IRQ,
  30         },
  31         [2] = {
  32                 /* Carry IRQ */
  33                 .start  = 22,
  34                 .flags  = IORESOURCE_IRQ,
  35         },
  36         [3] = {
  37                 /* Alarm IRQ */
  38                 .start  = 20,
  39                 .flags  = IORESOURCE_IRQ,
  40         },
  41 };
  42
  43 static struct platform_device rtc_device = {
  44         .name           = "sh-rtc",
  45         .id             = -1,
  46         .num_resources  = ARRAY_SIZE(rtc_resources),
  47         .resource       = rtc_resources,
  48 };
  49
  50 static struct plat_sci_port sci_platform_data[] = {
  51         {
  52                 .mapbase        = 0xffe00000,
  53                 .flags          = UPF_BOOT_AUTOCONF,
  54                 .type           = PORT_SCIF,
  55                 .irqs           = { 40, 41, 43, 42 },
  56         }, {
  57                 .mapbase        = 0xffe10000,
  58                 .flags          = UPF_BOOT_AUTOCONF,
  59                 .type           = PORT_SCIF,
  60                 .irqs           = { 76, 77, 79, 78 },
  61         }, {
  62                 .flags = 0,
  63         }
  64 };
  65
  66 static struct platform_device sci_device = {
  67         .name           = "sh-sci",
  68         .id             = -1,
  69         .dev            = {
  70                 .platform_data  = sci_platform_data,
  71         },
  72 };
  73
  74 static struct platform_device *sh7780_devices[] __initdata = {
  75         &rtc_device,
  76         &sci_device,
  77 };
  78
  79 static int __init sh7780_devices_setup(void)
  80 {
  81         return platform_add_devices(sh7780_devices,
  82                                     ARRAY_SIZE(sh7780_devices));
  83 }
  84 __initcall(sh7780_devices_setup);
  85
  86 enum {
  87         UNUSED = 0,
  88
  89         /* interrupt sources */
  90
  91         IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
  92         IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
  93         IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
  94         IRL_HHLL, IRL_HHLH, IRL_HHHL,
  95
  96         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
  97         RTC_ATI, RTC_PRI, RTC_CUI,
  98         WDT,
  99         TMU0, TMU1, TMU2, TMU2_TICPI,
 100         HUDI,
 101         DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3, DMAC0_DMAE,
 102         SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
 103         DMAC0_DMINT4, DMAC0_DMINT5, DMAC1_DMINT6, DMAC1_DMINT7,
 104         CMT, HAC,
 105         PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD,
 106         PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0,
 107         SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
 108         SIOF, HSPI,
 109         MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY,
 110         DMAC1_DMINT8, DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11,
 111         TMU3, TMU4, TMU5,
 112         SSI,
 113         FLCTL_FLSTE, FLCTL_FLEND, FLCTL_FLTRQ0, FLCTL_FLTRQ1,
 114         GPIOI0, GPIOI1, GPIOI2, GPIOI3,
 115
 116         /* interrupt groups */
 117
 118         RTC, TMU012, DMAC0, SCIF0, DMAC45, DMAC1,
 119         PCIC5, SCIF1, MMCIF, TMU345, FLCTL, GPIO,
 120 };
 121
 122 static struct intc_vect vectors[] __initdata = {
 123         INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
 124         INTC_VECT(RTC_CUI, 0x4c0),
 125         INTC_VECT(WDT, 0x560),
 126         INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
 127         INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
 128         INTC_VECT(HUDI, 0x600),
 129         INTC_VECT(DMAC0_DMINT0, 0x640), INTC_VECT(DMAC0_DMINT1, 0x660),
 130         INTC_VECT(DMAC0_DMINT2, 0x680), INTC_VECT(DMAC0_DMINT3, 0x6a0),
 131         INTC_VECT(DMAC0_DMAE, 0x6c0),
 132         INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720),
 133         INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760),
 134         INTC_VECT(DMAC0_DMINT4, 0x780), INTC_VECT(DMAC0_DMINT5, 0x7a0),
 135         INTC_VECT(DMAC1_DMINT6, 0x7c0), INTC_VECT(DMAC1_DMINT7, 0x7e0),
 136         INTC_VECT(CMT, 0x900), INTC_VECT(HAC, 0x980),
 137         INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
 138         INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
 139         INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIERR, 0xaa0),
 140         INTC_VECT(PCIPWD3, 0xac0), INTC_VECT(PCIPWD2, 0xae0),
 141         INTC_VECT(PCIPWD1, 0xb00), INTC_VECT(PCIPWD0, 0xb20),
 142         INTC_VECT(SCIF1_ERI, 0xb80), INTC_VECT(SCIF1_RXI, 0xba0),
 143         INTC_VECT(SCIF1_BRI, 0xbc0), INTC_VECT(SCIF1_TXI, 0xbe0),
 144         INTC_VECT(SIOF, 0xc00), INTC_VECT(HSPI, 0xc80),
 145         INTC_VECT(MMCIF_FSTAT, 0xd00), INTC_VECT(MMCIF_TRAN, 0xd20),
 146         INTC_VECT(MMCIF_ERR, 0xd40), INTC_VECT(MMCIF_FRDY, 0xd60),
 147         INTC_VECT(DMAC1_DMINT8, 0xd80), INTC_VECT(DMAC1_DMINT9, 0xda0),
 148         INTC_VECT(DMAC1_DMINT10, 0xdc0), INTC_VECT(DMAC1_DMINT11, 0xde0),
 149         INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
 150         INTC_VECT(TMU5, 0xe40),
 151         INTC_VECT(SSI, 0xe80),
 152         INTC_VECT(FLCTL_FLSTE, 0xf00), INTC_VECT(FLCTL_FLEND, 0xf20),
 153         INTC_VECT(FLCTL_FLTRQ0, 0xf40), INTC_VECT(FLCTL_FLTRQ1, 0xf60),
 154         INTC_VECT(GPIOI0, 0xf80), INTC_VECT(GPIOI1, 0xfa0),
 155         INTC_VECT(GPIOI2, 0xfc0), INTC_VECT(GPIOI3, 0xfe0),
 156 };
 157
 158 static struct intc_group groups[] __initdata = {
 159         INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
 160         INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
 161         INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
 162                    DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
 163         INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
 164         INTC_GROUP(DMAC1, DMAC1_DMINT6, DMAC1_DMINT7, DMAC1_DMINT8,
 165                    DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11),
 166         INTC_GROUP(PCIC5, PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0),
 167         INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
 168         INTC_GROUP(MMCIF, MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY),
 169         INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
 170         INTC_GROUP(FLCTL, FLCTL_FLSTE, FLCTL_FLEND,
 171                    FLCTL_FLTRQ0, FLCTL_FLTRQ1),
 172         INTC_GROUP(GPIO, GPIOI0, GPIOI1, GPIOI2, GPIOI3),
 173 };
 174
 175 static struct intc_mask_reg mask_registers[] __initdata = {
 176         { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
 177           { 0, 0, 0, 0, 0, 0, GPIO, FLCTL,
 178             SSI, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
 179             PCIINTA, PCISERR, HAC, CMT, 0, 0, DMAC1, DMAC0,
 180             HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
 181 };
 182
 183 static struct intc_prio_reg prio_registers[] __initdata = {
 184         { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
 185                                                  TMU2, TMU2_TICPI } },
 186         { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
 187         { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
 188         { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI, DMAC0, DMAC1 } },
 189         { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT, HAC,
 190                                                  PCISERR, PCIINTA, } },
 191         { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC,
 192                                                  PCIINTD, PCIC5 } },
 193         { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF, HSPI, MMCIF, SSI } },
 194         { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { FLCTL, GPIO } },
 195 };
 196
 197 static DECLARE_INTC_DESC(intc_desc, "sh7780", vectors, groups,
 198                          mask_registers, prio_registers, NULL);
 199
 200 /* Support for external interrupt pins in IRQ mode */
 201
 202 static struct intc_vect irq_vectors[] __initdata = {
 203         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
 204         INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
 205         INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
 206         INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
 207 };
 208
 209 static struct intc_mask_reg irq_mask_registers[] __initdata = {
 210         { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
 211           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 212 };
 213
 214 static struct intc_prio_reg irq_prio_registers[] __initdata = {
 215         { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
 216                                                IRQ4, IRQ5, IRQ6, IRQ7 } },
 217 };
 218
 219 static struct intc_sense_reg irq_sense_registers[] __initdata = {
 220         { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
 221                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
 222 };
 223
 224 static DECLARE_INTC_DESC(intc_irq_desc, "sh7780-irq", irq_vectors,
 225                          NULL, irq_mask_registers, irq_prio_registers,
 226                          irq_sense_registers);
 227
 228 /* External interrupt pins in IRL mode */
 229
 230 static struct intc_vect irl_vectors[] __initdata = {
 231         INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
 232         INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
 233         INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
 234         INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
 235         INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
 236         INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
 237         INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
 238         INTC_VECT(IRL_HHHL, 0x3c0),
 239 };
 240
 241 static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
 242         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 243           { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 244             IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 245             IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 246             IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
 247 };
 248
 249 static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
 250         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 251           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 252             IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 253             IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 254             IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 255             IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
 256 };
 257
 258 static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654", irl_vectors,
 259                          NULL, irl7654_mask_registers, NULL, NULL);
 260
 261 static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
 262                          NULL, irl3210_mask_registers, NULL, NULL);
 263
 264 #define INTC_ICR0       0xffd00000
 265 #define INTC_INTMSK0    0xffd00044
 266 #define INTC_INTMSK1    0xffd00048
 267 #define INTC_INTMSK2    0xffd40080
 268 #define INTC_INTMSKCLR1 0xffd00068
 269 #define INTC_INTMSKCLR2 0xffd40084
 270
 271 void __init plat_irq_setup(void)
 272 {
 273         /* disable IRQ7-0 */
 274         ctrl_outl(0xff000000, INTC_INTMSK0);
 275
 276         /* disable IRL3-0 + IRL7-4 */
 277         ctrl_outl(0xc0000000, INTC_INTMSK1);
 278         ctrl_outl(0xfffefffe, INTC_INTMSK2);
 279
 280         /* select IRL mode for IRL3-0 + IRL7-4 */
 281         ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 282
 283         /* disable holding function, ie enable "SH-4 Mode" */
 284         ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0);
 285
 286         register_intc_controller(&intc_desc);
 287 }
 288
 289 void __init plat_irq_setup_pins(int mode)
 290 {
 291         switch (mode) {
 292         case IRQ_MODE_IRQ:
 293                 /* select IRQ mode for IRL3-0 + IRL7-4 */
 294                 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
 295                 register_intc_controller(&intc_irq_desc);
 296                 break;
 297         case IRQ_MODE_IRL7654:
 298                 /* enable IRL7-4 but don't provide any masking */
 299                 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
 300                 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
 301                 break;
 302         case IRQ_MODE_IRL3210:
 303                 /* enable IRL0-3 but don't provide any masking */
 304                 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
 305                 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
 306                 break;
 307         case IRQ_MODE_IRL7654_MASK:
 308                 /* enable IRL7-4 and mask using cpu intc controller */
 309                 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
 310                 register_intc_controller(&intc_irl7654_desc);
 311                 break;
 312         case IRQ_MODE_IRL3210_MASK:
 313                 /* enable IRL0-3 and mask using cpu intc controller */
 314                 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
 315                 register_intc_controller(&intc_irl3210_desc);
 316                 break;
 317         default:
 318                 BUG();
 319         }
 320 }