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Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / drivers / ata / sata_svw.c
bloba9bf21f4b15048607f53bfbec62ff4e22defdab0
1 /*
2 * sata_svw.c - ServerWorks / Apple K2 SATA
3 *
4 * Maintained by: Benjamin Herrenschmidt <benh@kernel.crashing.org> and
5 * Jeff Garzik <jgarzik@pobox.com>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
10 *
11 * Bits from Jeff Garzik, Copyright RedHat, Inc.
12 *
13 * This driver probably works with non-Apple versions of the
14 * Broadcom chipset...
15 *
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License as published by
19 * the Free Software Foundation; either version 2, or (at your option)
20 * any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; see the file COPYING. If not, write to
29 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
30 *
31 *
32 * libata documentation is available via 'make {ps|pdf}docs',
33 * as Documentation/DocBook/libata.*
34 *
35 * Hardware documentation available under NDA.
36 *
37 */
38
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/pci.h>
42 #include <linux/init.h>
43 #include <linux/blkdev.h>
44 #include <linux/delay.h>
45 #include <linux/interrupt.h>
46 #include <linux/device.h>
47 #include <scsi/scsi_host.h>
48 <<<<<<< HEAD:drivers/ata/sata_svw.c
49 =======
50 #include <scsi/scsi_cmnd.h>
51 #include <scsi/scsi.h>
52 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ata/sata_svw.c
53 #include <linux/libata.h>
54
55 #ifdef CONFIG_PPC_OF
56 #include <asm/prom.h>
57 #include <asm/pci-bridge.h>
58 #endif /* CONFIG_PPC_OF */
59
60 #define DRV_NAME "sata_svw"
61 #define DRV_VERSION "2.3"
62
63 enum {
64 /* ap->flags bits */
65 K2_FLAG_SATA_8_PORTS = (1 << 24),
66 K2_FLAG_NO_ATAPI_DMA = (1 << 25),
67 <<<<<<< HEAD:drivers/ata/sata_svw.c
68 =======
69 K2_FLAG_BAR_POS_3 = (1 << 26),
70 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ata/sata_svw.c
71
72 /* Taskfile registers offsets */
73 K2_SATA_TF_CMD_OFFSET = 0x00,
74 K2_SATA_TF_DATA_OFFSET = 0x00,
75 K2_SATA_TF_ERROR_OFFSET = 0x04,
76 K2_SATA_TF_NSECT_OFFSET = 0x08,
77 K2_SATA_TF_LBAL_OFFSET = 0x0c,
78 K2_SATA_TF_LBAM_OFFSET = 0x10,
79 K2_SATA_TF_LBAH_OFFSET = 0x14,
80 K2_SATA_TF_DEVICE_OFFSET = 0x18,
81 K2_SATA_TF_CMDSTAT_OFFSET = 0x1c,
82 K2_SATA_TF_CTL_OFFSET = 0x20,
83
84 /* DMA base */
85 K2_SATA_DMA_CMD_OFFSET = 0x30,
86
87 /* SCRs base */
88 K2_SATA_SCR_STATUS_OFFSET = 0x40,
89 K2_SATA_SCR_ERROR_OFFSET = 0x44,
90 K2_SATA_SCR_CONTROL_OFFSET = 0x48,
91
92 /* Others */
93 K2_SATA_SICR1_OFFSET = 0x80,
94 K2_SATA_SICR2_OFFSET = 0x84,
95 K2_SATA_SIM_OFFSET = 0x88,
96
97 /* Port stride */
98 K2_SATA_PORT_OFFSET = 0x100,
99
100 <<<<<<< HEAD:drivers/ata/sata_svw.c
101 board_svw4 = 0,
102 board_svw8 = 1,
103 =======
104 chip_svw4 = 0,
105 chip_svw8 = 1,
106 chip_svw42 = 2, /* bar 3 */
107 chip_svw43 = 3, /* bar 5 */
108 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ata/sata_svw.c
109 };
110
111 static u8 k2_stat_check_status(struct ata_port *ap);
112
113
114 static int k2_sata_check_atapi_dma(struct ata_queued_cmd *qc)
115 {
116 <<<<<<< HEAD:drivers/ata/sata_svw.c
117 =======
118 u8 cmnd = qc->scsicmd->cmnd[0];
119
120 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ata/sata_svw.c
121 if (qc->ap->flags & K2_FLAG_NO_ATAPI_DMA)
122 return -1; /* ATAPI DMA not supported */
123 <<<<<<< HEAD:drivers/ata/sata_svw.c
124 =======
125 else {
126 switch (cmnd) {
127 case READ_10:
128 case READ_12:
129 case READ_16:
130 case WRITE_10:
131 case WRITE_12:
132 case WRITE_16:
133 return 0;
134
135 default:
136 return -1;
137 }
138 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ata/sata_svw.c
139
140 <<<<<<< HEAD:drivers/ata/sata_svw.c
141 return 0;
142 =======
143 }
144 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ata/sata_svw.c
145 }
146
147 static int k2_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
148 {
149 if (sc_reg > SCR_CONTROL)
150 return -EINVAL;
151 *val = readl(ap->ioaddr.scr_addr + (sc_reg * 4));
152 return 0;
153 }
154
155
156 static int k2_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
157 {
158 if (sc_reg > SCR_CONTROL)
159 return -EINVAL;
160 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
161 return 0;
162 }
163
164
165 static void k2_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
166 {
167 struct ata_ioports *ioaddr = &ap->ioaddr;
168 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
169
170 if (tf->ctl != ap->last_ctl) {
171 writeb(tf->ctl, ioaddr->ctl_addr);
172 ap->last_ctl = tf->ctl;
173 ata_wait_idle(ap);
174 }
175 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
176 writew(tf->feature | (((u16)tf->hob_feature) << 8),
177 ioaddr->feature_addr);
178 writew(tf->nsect | (((u16)tf->hob_nsect) << 8),
179 ioaddr->nsect_addr);
180 writew(tf->lbal | (((u16)tf->hob_lbal) << 8),
181 ioaddr->lbal_addr);
182 writew(tf->lbam | (((u16)tf->hob_lbam) << 8),
183 ioaddr->lbam_addr);
184 writew(tf->lbah | (((u16)tf->hob_lbah) << 8),
185 ioaddr->lbah_addr);
186 } else if (is_addr) {
187 writew(tf->feature, ioaddr->feature_addr);
188 writew(tf->nsect, ioaddr->nsect_addr);
189 writew(tf->lbal, ioaddr->lbal_addr);
190 writew(tf->lbam, ioaddr->lbam_addr);
191 writew(tf->lbah, ioaddr->lbah_addr);
192 }
193
194 if (tf->flags & ATA_TFLAG_DEVICE)
195 writeb(tf->device, ioaddr->device_addr);
196
197 ata_wait_idle(ap);
198 }
199
200
201 static void k2_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
202 {
203 struct ata_ioports *ioaddr = &ap->ioaddr;
204 u16 nsect, lbal, lbam, lbah, feature;
205
206 tf->command = k2_stat_check_status(ap);
207 tf->device = readw(ioaddr->device_addr);
208 feature = readw(ioaddr->error_addr);
209 nsect = readw(ioaddr->nsect_addr);
210 lbal = readw(ioaddr->lbal_addr);
211 lbam = readw(ioaddr->lbam_addr);
212 lbah = readw(ioaddr->lbah_addr);
213
214 tf->feature = feature;
215 tf->nsect = nsect;
216 tf->lbal = lbal;
217 tf->lbam = lbam;
218 tf->lbah = lbah;
219
220 if (tf->flags & ATA_TFLAG_LBA48) {
221 tf->hob_feature = feature >> 8;
222 tf->hob_nsect = nsect >> 8;
223 tf->hob_lbal = lbal >> 8;
224 tf->hob_lbam = lbam >> 8;
225 tf->hob_lbah = lbah >> 8;
226 }
227 }
228
229 /**
230 * k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO)
231 * @qc: Info associated with this ATA transaction.
232 *
233 * LOCKING:
234 * spin_lock_irqsave(host lock)
235 */
236
237 static void k2_bmdma_setup_mmio(struct ata_queued_cmd *qc)
238 {
239 struct ata_port *ap = qc->ap;
240 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
241 u8 dmactl;
242 void __iomem *mmio = ap->ioaddr.bmdma_addr;
243
244 /* load PRD table addr. */
245 mb(); /* make sure PRD table writes are visible to controller */
246 writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS);
247
248 /* specify data direction, triple-check start bit is clear */
249 dmactl = readb(mmio + ATA_DMA_CMD);
250 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
251 if (!rw)
252 dmactl |= ATA_DMA_WR;
253 writeb(dmactl, mmio + ATA_DMA_CMD);
254
255 /* issue r/w command if this is not a ATA DMA command*/
256 if (qc->tf.protocol != ATA_PROT_DMA)
257 ap->ops->exec_command(ap, &qc->tf);
258 }
259
260 /**
261 * k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO)
262 * @qc: Info associated with this ATA transaction.
263 *
264 * LOCKING:
265 * spin_lock_irqsave(host lock)
266 */
267
268 static void k2_bmdma_start_mmio(struct ata_queued_cmd *qc)
269 {
270 struct ata_port *ap = qc->ap;
271 void __iomem *mmio = ap->ioaddr.bmdma_addr;
272 u8 dmactl;
273
274 /* start host DMA transaction */
275 dmactl = readb(mmio + ATA_DMA_CMD);
276 writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
277 /* There is a race condition in certain SATA controllers that can
278 be seen when the r/w command is given to the controller before the
279 host DMA is started. On a Read command, the controller would initiate
280 the command to the drive even before it sees the DMA start. When there
281 are very fast drives connected to the controller, or when the data request
282 hits in the drive cache, there is the possibility that the drive returns a part
283 or all of the requested data to the controller before the DMA start is issued.
284 In this case, the controller would become confused as to what to do with the data.
285 In the worst case when all the data is returned back to the controller, the
286 controller could hang. In other cases it could return partial data returning
287 in data corruption. This problem has been seen in PPC systems and can also appear
288 on an system with very fast disks, where the SATA controller is sitting behind a
289 number of bridges, and hence there is significant latency between the r/w command
290 and the start command. */
291 /* issue r/w command if the access is to ATA*/
292 if (qc->tf.protocol == ATA_PROT_DMA)
293 ap->ops->exec_command(ap, &qc->tf);
294 }
295
296
297 static u8 k2_stat_check_status(struct ata_port *ap)
298 {
299 return readl(ap->ioaddr.status_addr);
300 }
301
302 #ifdef CONFIG_PPC_OF
303 /*
304 * k2_sata_proc_info
305 * inout : decides on the direction of the dataflow and the meaning of the
306 * variables
307 * buffer: If inout==FALSE data is being written to it else read from it
308 * *start: If inout==FALSE start of the valid data in the buffer
309 * offset: If inout==FALSE offset from the beginning of the imaginary file
310 * from which we start writing into the buffer
311 * length: If inout==FALSE max number of bytes to be written into the buffer
312 * else number of bytes in the buffer
313 */
314 static int k2_sata_proc_info(struct Scsi_Host *shost, char *page, char **start,
315 off_t offset, int count, int inout)
316 {
317 struct ata_port *ap;
318 struct device_node *np;
319 int len, index;
320
321 /* Find the ata_port */
322 ap = ata_shost_to_port(shost);
323 if (ap == NULL)
324 return 0;
325
326 /* Find the OF node for the PCI device proper */
327 np = pci_device_to_OF_node(to_pci_dev(ap->host->dev));
328 if (np == NULL)
329 return 0;
330
331 /* Match it to a port node */
332 index = (ap == ap->host->ports[0]) ? 0 : 1;
333 for (np = np->child; np != NULL; np = np->sibling) {
334 const u32 *reg = of_get_property(np, "reg", NULL);
335 if (!reg)
336 continue;
337 if (index == *reg)
338 break;
339 }
340 if (np == NULL)
341 return 0;
342
343 len = sprintf(page, "devspec: %s\n", np->full_name);
344
345 return len;
346 }
347 #endif /* CONFIG_PPC_OF */
348
349
350 static struct scsi_host_template k2_sata_sht = {
351 .module = THIS_MODULE,
352 .name = DRV_NAME,
353 .ioctl = ata_scsi_ioctl,
354 .queuecommand = ata_scsi_queuecmd,
355 .can_queue = ATA_DEF_QUEUE,
356 .this_id = ATA_SHT_THIS_ID,
357 .sg_tablesize = LIBATA_MAX_PRD,
358 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
359 .emulated = ATA_SHT_EMULATED,
360 .use_clustering = ATA_SHT_USE_CLUSTERING,
361 .proc_name = DRV_NAME,
362 .dma_boundary = ATA_DMA_BOUNDARY,
363 .slave_configure = ata_scsi_slave_config,
364 .slave_destroy = ata_scsi_slave_destroy,
365 #ifdef CONFIG_PPC_OF
366 .proc_info = k2_sata_proc_info,
367 #endif
368 .bios_param = ata_std_bios_param,
369 };
370
371
372 static const struct ata_port_operations k2_sata_ops = {
373 .tf_load = k2_sata_tf_load,
374 .tf_read = k2_sata_tf_read,
375 .check_status = k2_stat_check_status,
376 .exec_command = ata_exec_command,
377 .dev_select = ata_std_dev_select,
378 .check_atapi_dma = k2_sata_check_atapi_dma,
379 .bmdma_setup = k2_bmdma_setup_mmio,
380 .bmdma_start = k2_bmdma_start_mmio,
381 .bmdma_stop = ata_bmdma_stop,
382 .bmdma_status = ata_bmdma_status,
383 .qc_prep = ata_qc_prep,
384 .qc_issue = ata_qc_issue_prot,
385 .data_xfer = ata_data_xfer,
386 .freeze = ata_bmdma_freeze,
387 .thaw = ata_bmdma_thaw,
388 .error_handler = ata_bmdma_error_handler,
389 .post_internal_cmd = ata_bmdma_post_internal_cmd,
390 .irq_clear = ata_bmdma_irq_clear,
391 .irq_on = ata_irq_on,
392 .scr_read = k2_sata_scr_read,
393 .scr_write = k2_sata_scr_write,
394 .port_start = ata_port_start,
395 };
396
397 static const struct ata_port_info k2_port_info[] = {
398 <<<<<<< HEAD:drivers/ata/sata_svw.c
399 /* board_svw4 */
400 =======
401 /* chip_svw4 */
402 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ata/sata_svw.c
403 {
404 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
405 ATA_FLAG_MMIO | K2_FLAG_NO_ATAPI_DMA,
406 .pio_mask = 0x1f,
407 .mwdma_mask = 0x07,
408 .udma_mask = ATA_UDMA6,
409 .port_ops = &k2_sata_ops,
410 },
411 <<<<<<< HEAD:drivers/ata/sata_svw.c
412 /* board_svw8 */
413 =======
414 /* chip_svw8 */
415 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ata/sata_svw.c
416 {
417 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
418 ATA_FLAG_MMIO | K2_FLAG_NO_ATAPI_DMA |
419 K2_FLAG_SATA_8_PORTS,
420 .pio_mask = 0x1f,
421 .mwdma_mask = 0x07,
422 .udma_mask = ATA_UDMA6,
423 .port_ops = &k2_sata_ops,
424 },
425 <<<<<<< HEAD:drivers/ata/sata_svw.c
426 =======
427 /* chip_svw42 */
428 {
429 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
430 ATA_FLAG_MMIO | K2_FLAG_BAR_POS_3,
431 .pio_mask = 0x1f,
432 .mwdma_mask = 0x07,
433 .udma_mask = ATA_UDMA6,
434 .port_ops = &k2_sata_ops,
435 },
436 /* chip_svw43 */
437 {
438 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
439 ATA_FLAG_MMIO,
440 .pio_mask = 0x1f,
441 .mwdma_mask = 0x07,
442 .udma_mask = ATA_UDMA6,
443 .port_ops = &k2_sata_ops,
444 },
445 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ata/sata_svw.c
446 };
447
448 static void k2_sata_setup_port(struct ata_ioports *port, void __iomem *base)
449 {
450 port->cmd_addr = base + K2_SATA_TF_CMD_OFFSET;
451 port->data_addr = base + K2_SATA_TF_DATA_OFFSET;
452 port->feature_addr =
453 port->error_addr = base + K2_SATA_TF_ERROR_OFFSET;
454 port->nsect_addr = base + K2_SATA_TF_NSECT_OFFSET;
455 port->lbal_addr = base + K2_SATA_TF_LBAL_OFFSET;
456 port->lbam_addr = base + K2_SATA_TF_LBAM_OFFSET;
457 port->lbah_addr = base + K2_SATA_TF_LBAH_OFFSET;
458 port->device_addr = base + K2_SATA_TF_DEVICE_OFFSET;
459 port->command_addr =
460 port->status_addr = base + K2_SATA_TF_CMDSTAT_OFFSET;
461 port->altstatus_addr =
462 port->ctl_addr = base + K2_SATA_TF_CTL_OFFSET;
463 port->bmdma_addr = base + K2_SATA_DMA_CMD_OFFSET;
464 port->scr_addr = base + K2_SATA_SCR_STATUS_OFFSET;
465 }
466
467
468 static int k2_sata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
469 {
470 static int printed_version;
471 const struct ata_port_info *ppi[] =
472 { &k2_port_info[ent->driver_data], NULL };
473 struct ata_host *host;
474 void __iomem *mmio_base;
475 <<<<<<< HEAD:drivers/ata/sata_svw.c
476 int n_ports, i, rc;
477 =======
478 int n_ports, i, rc, bar_pos;
479 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ata/sata_svw.c
480
481 if (!printed_version++)
482 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
483
484 /* allocate host */
485 n_ports = 4;
486 if (ppi[0]->flags & K2_FLAG_SATA_8_PORTS)
487 n_ports = 8;
488
489 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
490 if (!host)
491 return -ENOMEM;
492
493 <<<<<<< HEAD:drivers/ata/sata_svw.c
494 =======
495 bar_pos = 5;
496 if (ppi[0]->flags & K2_FLAG_BAR_POS_3)
497 bar_pos = 3;
498 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ata/sata_svw.c
499 /*
500 * If this driver happens to only be useful on Apple's K2, then
501 * we should check that here as it has a normal Serverworks ID
502 */
503 rc = pcim_enable_device(pdev);
504 if (rc)
505 return rc;
506
507 /*
508 * Check if we have resources mapped at all (second function may
509 * have been disabled by firmware)
510 */
511 <<<<<<< HEAD:drivers/ata/sata_svw.c
512 if (pci_resource_len(pdev, 5) == 0)
513 =======
514 if (pci_resource_len(pdev, bar_pos) == 0) {
515 /* In IDE mode we need to pin the device to ensure that
516 pcim_release does not clear the busmaster bit in config
517 space, clearing causes busmaster DMA to fail on
518 ports 3 & 4 */
519 pcim_pin_device(pdev);
520 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ata/sata_svw.c
521 return -ENODEV;
522 <<<<<<< HEAD:drivers/ata/sata_svw.c
523 =======
524 }
525 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ata/sata_svw.c
526
527 /* Request and iomap PCI regions */
528 <<<<<<< HEAD:drivers/ata/sata_svw.c
529 rc = pcim_iomap_regions(pdev, 1 << 5, DRV_NAME);
530 =======
531 rc = pcim_iomap_regions(pdev, 1 << bar_pos, DRV_NAME);
532 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ata/sata_svw.c
533 if (rc == -EBUSY)
534 pcim_pin_device(pdev);
535 if (rc)
536 return rc;
537 host->iomap = pcim_iomap_table(pdev);
538 <<<<<<< HEAD:drivers/ata/sata_svw.c
539 mmio_base = host->iomap[5];
540 =======
541 mmio_base = host->iomap[bar_pos];
542 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ata/sata_svw.c
543
544 /* different controllers have different number of ports - currently 4 or 8 */
545 /* All ports are on the same function. Multi-function device is no
546 * longer available. This should not be seen in any system. */
547 for (i = 0; i < host->n_ports; i++) {
548 struct ata_port *ap = host->ports[i];
549 unsigned int offset = i * K2_SATA_PORT_OFFSET;
550
551 k2_sata_setup_port(&ap->ioaddr, mmio_base + offset);
552
553 ata_port_pbar_desc(ap, 5, -1, "mmio");
554 ata_port_pbar_desc(ap, 5, offset, "port");
555 }
556
557 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
558 if (rc)
559 return rc;
560 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
561 if (rc)
562 return rc;
563
564 /* Clear a magic bit in SCR1 according to Darwin, those help
565 * some funky seagate drives (though so far, those were already
566 * set by the firmware on the machines I had access to)
567 */
568 writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000,
569 mmio_base + K2_SATA_SICR1_OFFSET);
570
571 /* Clear SATA error & interrupts we don't use */
572 writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET);
573 writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);
574
575 pci_set_master(pdev);
576 return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
577 &k2_sata_sht);
578 }
579
580 /* 0x240 is device ID for Apple K2 device
581 * 0x241 is device ID for Serverworks Frodo4
582 * 0x242 is device ID for Serverworks Frodo8
583 * 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA
584 * controller
585 * */
586 static const struct pci_device_id k2_sata_pci_tbl[] = {
587 <<<<<<< HEAD:drivers/ata/sata_svw.c
588 { PCI_VDEVICE(SERVERWORKS, 0x0240), board_svw4 },
589 { PCI_VDEVICE(SERVERWORKS, 0x0241), board_svw4 },
590 { PCI_VDEVICE(SERVERWORKS, 0x0242), board_svw8 },
591 { PCI_VDEVICE(SERVERWORKS, 0x024a), board_svw4 },
592 { PCI_VDEVICE(SERVERWORKS, 0x024b), board_svw4 },
593 =======
594 { PCI_VDEVICE(SERVERWORKS, 0x0240), chip_svw4 },
595 { PCI_VDEVICE(SERVERWORKS, 0x0241), chip_svw4 },
596 { PCI_VDEVICE(SERVERWORKS, 0x0242), chip_svw8 },
597 { PCI_VDEVICE(SERVERWORKS, 0x024a), chip_svw4 },
598 { PCI_VDEVICE(SERVERWORKS, 0x024b), chip_svw4 },
599 { PCI_VDEVICE(SERVERWORKS, 0x0410), chip_svw42 },
600 { PCI_VDEVICE(SERVERWORKS, 0x0411), chip_svw43 },
601 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ata/sata_svw.c
602
603 { }
604 };
605
606 static struct pci_driver k2_sata_pci_driver = {
607 .name = DRV_NAME,
608 .id_table = k2_sata_pci_tbl,
609 .probe = k2_sata_init_one,
610 .remove = ata_pci_remove_one,
611 };
612
613 static int __init k2_sata_init(void)
614 {
615 return pci_register_driver(&k2_sata_pci_driver);
616 }
617
618 static void __exit k2_sata_exit(void)
619 {
620 pci_unregister_driver(&k2_sata_pci_driver);
621 }
622
623 MODULE_AUTHOR("Benjamin Herrenschmidt");
624 MODULE_DESCRIPTION("low-level driver for K2 SATA controller");
625 MODULE_LICENSE("GPL");
626 MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl);
627 MODULE_VERSION(DRV_VERSION);
628
629 module_init(k2_sata_init);
630 module_exit(k2_sata_exit);
WRT350N Kernel Patches