x86: convert cpu_to_apicid to be a per cpu variable
[wrt350n-kernel.git] / arch / mips / cobalt / setup.c
blobd11bb1bc7b6b2dd12644f32dc0558a71907a4238
1 /*
2 * Setup pointers to hardware dependent routines.
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
8 * Copyright (C) 1996, 1997, 2004, 05 by Ralf Baechle (ralf@linux-mips.org)
9 * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv)
12 #include <linux/interrupt.h>
13 #include <linux/init.h>
14 #include <linux/pm.h>
16 #include <asm/bootinfo.h>
17 #include <asm/time.h>
18 #include <asm/i8253.h>
19 #include <asm/io.h>
20 #include <asm/reboot.h>
21 #include <asm/gt64120.h>
23 #include <cobalt.h>
24 #include <irq.h>
26 extern void cobalt_machine_restart(char *command);
27 extern void cobalt_machine_halt(void);
29 const char *get_system_type(void)
31 switch (cobalt_board_id) {
32 case COBALT_BRD_ID_QUBE1:
33 return "Cobalt Qube";
34 case COBALT_BRD_ID_RAQ1:
35 return "Cobalt RaQ";
36 case COBALT_BRD_ID_QUBE2:
37 return "Cobalt Qube2";
38 case COBALT_BRD_ID_RAQ2:
39 return "Cobalt RaQ2";
41 return "MIPS Cobalt";
44 void __init plat_timer_setup(struct irqaction *irq)
46 /* Load timer value for HZ (TCLK is 50MHz) */
47 GT_WRITE(GT_TC0_OFS, 50*1000*1000 / HZ);
49 /* Enable timer0 */
50 GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);
52 setup_irq(GT641XX_TIMER0_IRQ, irq);
56 * Cobalt doesn't have PS/2 keyboard/mouse interfaces,
57 * keyboard conntroller is never used.
58 * Also PCI-ISA bridge DMA contoroller is never used.
60 static struct resource cobalt_reserved_resources[] = {
61 { /* dma1 */
62 .start = 0x00,
63 .end = 0x1f,
64 .name = "reserved",
65 .flags = IORESOURCE_BUSY | IORESOURCE_IO,
67 { /* keyboard */
68 .start = 0x60,
69 .end = 0x6f,
70 .name = "reserved",
71 .flags = IORESOURCE_BUSY | IORESOURCE_IO,
73 { /* dma page reg */
74 .start = 0x80,
75 .end = 0x8f,
76 .name = "reserved",
77 .flags = IORESOURCE_BUSY | IORESOURCE_IO,
79 { /* dma2 */
80 .start = 0xc0,
81 .end = 0xdf,
82 .name = "reserved",
83 .flags = IORESOURCE_BUSY | IORESOURCE_IO,
87 void __init plat_time_init(void)
89 setup_pit_timer();
92 void __init plat_mem_setup(void)
94 int i;
96 _machine_restart = cobalt_machine_restart;
97 _machine_halt = cobalt_machine_halt;
98 pm_power_off = cobalt_machine_halt;
100 set_io_port_base(CKSEG1ADDR(GT_DEF_PCI0_IO_BASE));
102 /* I/O port resource must include LCD/buttons */
103 ioport_resource.end = 0x0fffffff;
105 /* These resources have been reserved by VIA SuperI/O chip. */
106 for (i = 0; i < ARRAY_SIZE(cobalt_reserved_resources); i++)
107 request_resource(&ioport_resource, cobalt_reserved_resources + i);
111 * Prom init. We read our one and only communication with the firmware.
112 * Grab the amount of installed memory.
113 * Better boot loaders (CoLo) pass a command line too :-)
116 void __init prom_init(void)
118 int narg, indx, posn, nchr;
119 unsigned long memsz;
120 char **argv;
122 memsz = fw_arg0 & 0x7fff0000;
123 narg = fw_arg0 & 0x0000ffff;
125 if (narg) {
126 arcs_cmdline[0] = '\0';
127 argv = (char **) fw_arg1;
128 posn = 0;
129 for (indx = 1; indx < narg; ++indx) {
130 nchr = strlen(argv[indx]);
131 if (posn + 1 + nchr + 1 > sizeof(arcs_cmdline))
132 break;
133 if (posn)
134 arcs_cmdline[posn++] = ' ';
135 strcpy(arcs_cmdline + posn, argv[indx]);
136 posn += nchr;
140 add_memory_region(0x0, memsz, BOOT_MEM_RAM);
143 void __init prom_free_prom_memory(void)
145 /* Nothing to do! */