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x86: i8259A: remove redundant irq_descinitialization
[wrt350n-kernel.git] / drivers / ata / pata_pdc202xx_old.c
blob3ed866723e0c3c3187ca8071e28857a3672b4412
1 /*
2 * pata_pdc202xx_old.c - Promise PDC202xx PATA for new ATA layer
3 * (C) 2005 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 * (C) 2007 Bartlomiej Zolnierkiewicz
6 *
7 * Based in part on linux/drivers/ide/pci/pdc202xx_old.c
8 *
9 * First cut with LBA48/ATAPI
10 *
11 * TODO:
12 * Channel interlock/reset on both required ?
13 */
14
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/pci.h>
18 #include <linux/init.h>
19 #include <linux/blkdev.h>
20 #include <linux/delay.h>
21 #include <scsi/scsi_host.h>
22 #include <linux/libata.h>
23
24 #define DRV_NAME "pata_pdc202xx_old"
25 #define DRV_VERSION "0.4.3"
26
27 static int pdc2026x_cable_detect(struct ata_port *ap)
28 {
29 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
30 u16 cis;
31
32 pci_read_config_word(pdev, 0x50, &cis);
33 if (cis & (1 << (10 + ap->port_no)))
34 return ATA_CBL_PATA40;
35 return ATA_CBL_PATA80;
36 }
37
38 /**
39 * pdc202xx_configure_piomode - set chip PIO timing
40 * @ap: ATA interface
41 * @adev: ATA device
42 * @pio: PIO mode
43 *
44 * Called to do the PIO mode setup. Our timing registers are shared
45 * so a configure_dmamode call will undo any work we do here and vice
46 * versa
47 */
48
49 static void pdc202xx_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio)
50 {
51 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
52 int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
53 static u16 pio_timing[5] = {
54 0x0913, 0x050C , 0x0308, 0x0206, 0x0104
55 };
56 u8 r_ap, r_bp;
57
58 pci_read_config_byte(pdev, port, &r_ap);
59 pci_read_config_byte(pdev, port + 1, &r_bp);
60 r_ap &= ~0x3F; /* Preserve ERRDY_EN, SYNC_IN */
61 r_bp &= ~0x1F;
62 r_ap |= (pio_timing[pio] >> 8);
63 r_bp |= (pio_timing[pio] & 0xFF);
64
65 if (ata_pio_need_iordy(adev))
66 r_ap |= 0x20; /* IORDY enable */
67 if (adev->class == ATA_DEV_ATA)
68 r_ap |= 0x10; /* FIFO enable */
69 pci_write_config_byte(pdev, port, r_ap);
70 pci_write_config_byte(pdev, port + 1, r_bp);
71 }
72
73 /**
74 * pdc202xx_set_piomode - set initial PIO mode data
75 * @ap: ATA interface
76 * @adev: ATA device
77 *
78 * Called to do the PIO mode setup. Our timing registers are shared
79 * but we want to set the PIO timing by default.
80 */
81
82 static void pdc202xx_set_piomode(struct ata_port *ap, struct ata_device *adev)
83 {
84 pdc202xx_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
85 }
86
87 /**
88 * pdc202xx_configure_dmamode - set DMA mode in chip
89 * @ap: ATA interface
90 * @adev: ATA device
91 *
92 * Load DMA cycle times into the chip ready for a DMA transfer
93 * to occur.
94 */
95
96 static void pdc202xx_set_dmamode(struct ata_port *ap, struct ata_device *adev)
97 {
98 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
99 int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
100 static u8 udma_timing[6][2] = {
101 { 0x60, 0x03 }, /* 33 Mhz Clock */
102 { 0x40, 0x02 },
103 { 0x20, 0x01 },
104 { 0x40, 0x02 }, /* 66 Mhz Clock */
105 { 0x20, 0x01 },
106 { 0x20, 0x01 }
107 };
108 static u8 mdma_timing[3][2] = {
109 { 0xe0, 0x0f },
110 { 0x60, 0x04 },
111 { 0x60, 0x03 },
112 };
113 u8 r_bp, r_cp;
114
115 pci_read_config_byte(pdev, port + 1, &r_bp);
116 pci_read_config_byte(pdev, port + 2, &r_cp);
117
118 r_bp &= ~0xE0;
119 r_cp &= ~0x0F;
120
121 if (adev->dma_mode >= XFER_UDMA_0) {
122 int speed = adev->dma_mode - XFER_UDMA_0;
123 r_bp |= udma_timing[speed][0];
124 r_cp |= udma_timing[speed][1];
125
126 } else {
127 int speed = adev->dma_mode - XFER_MW_DMA_0;
128 r_bp |= mdma_timing[speed][0];
129 r_cp |= mdma_timing[speed][1];
130 }
131 pci_write_config_byte(pdev, port + 1, r_bp);
132 pci_write_config_byte(pdev, port + 2, r_cp);
133
134 }
135
136 /**
137 * pdc2026x_bmdma_start - DMA engine begin
138 * @qc: ATA command
139 *
140 * In UDMA3 or higher we have to clock switch for the duration of the
141 * DMA transfer sequence.
142 *
143 * Note: The host lock held by the libata layer protects
144 * us from two channels both trying to set DMA bits at once
145 */
146
147 static void pdc2026x_bmdma_start(struct ata_queued_cmd *qc)
148 {
149 struct ata_port *ap = qc->ap;
150 struct ata_device *adev = qc->dev;
151 struct ata_taskfile *tf = &qc->tf;
152 int sel66 = ap->port_no ? 0x08: 0x02;
153
154 void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
155 void __iomem *clock = master + 0x11;
156 void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no);
157
158 u32 len;
159
160 /* Check we keep host level locking here */
161 if (adev->dma_mode >= XFER_UDMA_2)
162 iowrite8(ioread8(clock) | sel66, clock);
163 else
164 iowrite8(ioread8(clock) & ~sel66, clock);
165
166 /* The DMA clocks may have been trashed by a reset. FIXME: make conditional
167 and move to qc_issue ? */
168 pdc202xx_set_dmamode(ap, qc->dev);
169
170 /* Cases the state machine will not complete correctly without help */
171 if ((tf->flags & ATA_TFLAG_LBA48) || tf->protocol == ATAPI_PROT_DMA) {
172 len = qc->nbytes / 2;
173
174 if (tf->flags & ATA_TFLAG_WRITE)
175 len |= 0x06000000;
176 else
177 len |= 0x05000000;
178
179 iowrite32(len, atapi_reg);
180 }
181
182 /* Activate DMA */
183 ata_bmdma_start(qc);
184 }
185
186 /**
187 * pdc2026x_bmdma_end - DMA engine stop
188 * @qc: ATA command
189 *
190 * After a DMA completes we need to put the clock back to 33MHz for
191 * PIO timings.
192 *
193 * Note: The host lock held by the libata layer protects
194 * us from two channels both trying to set DMA bits at once
195 */
196
197 static void pdc2026x_bmdma_stop(struct ata_queued_cmd *qc)
198 {
199 struct ata_port *ap = qc->ap;
200 struct ata_device *adev = qc->dev;
201 struct ata_taskfile *tf = &qc->tf;
202
203 int sel66 = ap->port_no ? 0x08: 0x02;
204 /* The clock bits are in the same register for both channels */
205 void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
206 void __iomem *clock = master + 0x11;
207 void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no);
208
209 /* Cases the state machine will not complete correctly */
210 if (tf->protocol == ATAPI_PROT_DMA || (tf->flags & ATA_TFLAG_LBA48)) {
211 iowrite32(0, atapi_reg);
212 iowrite8(ioread8(clock) & ~sel66, clock);
213 }
214 /* Flip back to 33Mhz for PIO */
215 if (adev->dma_mode >= XFER_UDMA_2)
216 iowrite8(ioread8(clock) & ~sel66, clock);
217 ata_bmdma_stop(qc);
218 pdc202xx_set_piomode(ap, adev);
219 }
220
221 /**
222 * pdc2026x_dev_config - device setup hook
223 * @adev: newly found device
224 *
225 * Perform chip specific early setup. We need to lock the transfer
226 * sizes to 8bit to avoid making the state engine on the 2026x cards
227 * barf.
228 */
229
230 static void pdc2026x_dev_config(struct ata_device *adev)
231 {
232 adev->max_sectors = 256;
233 }
234
235 static int pdc2026x_port_start(struct ata_port *ap)
236 {
237 void __iomem *bmdma = ap->ioaddr.bmdma_addr;
238 if (bmdma) {
239 /* Enable burst mode */
240 u8 burst = ioread8(bmdma + 0x1f);
241 iowrite8(burst | 0x01, bmdma + 0x1f);
242 }
243 return ata_sff_port_start(ap);
244 }
245
246 /**
247 * pdc2026x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command
248 * @qc: Metadata associated with taskfile to check
249 *
250 * Just say no - not supported on older Promise.
251 *
252 * LOCKING:
253 * None (inherited from caller).
254 *
255 * RETURNS: 0 when ATAPI DMA can be used
256 * 1 otherwise
257 */
258
259 static int pdc2026x_check_atapi_dma(struct ata_queued_cmd *qc)
260 {
261 return 1;
262 }
263
264 static struct scsi_host_template pdc202xx_sht = {
265 .module = THIS_MODULE,
266 .name = DRV_NAME,
267 .ioctl = ata_scsi_ioctl,
268 .queuecommand = ata_scsi_queuecmd,
269 .can_queue = ATA_DEF_QUEUE,
270 .this_id = ATA_SHT_THIS_ID,
271 .sg_tablesize = LIBATA_MAX_PRD,
272 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
273 .emulated = ATA_SHT_EMULATED,
274 .use_clustering = ATA_SHT_USE_CLUSTERING,
275 .proc_name = DRV_NAME,
276 .dma_boundary = ATA_DMA_BOUNDARY,
277 .slave_configure = ata_scsi_slave_config,
278 .slave_destroy = ata_scsi_slave_destroy,
279 .bios_param = ata_std_bios_param,
280 };
281
282 static struct ata_port_operations pdc2024x_port_ops = {
283 .set_piomode = pdc202xx_set_piomode,
284 .set_dmamode = pdc202xx_set_dmamode,
285 .mode_filter = ata_pci_default_filter,
286 .tf_load = ata_tf_load,
287 .tf_read = ata_tf_read,
288 .check_status = ata_check_status,
289 .exec_command = ata_exec_command,
290 .dev_select = ata_std_dev_select,
291
292 .freeze = ata_bmdma_freeze,
293 .thaw = ata_bmdma_thaw,
294 .error_handler = ata_bmdma_error_handler,
295 .post_internal_cmd = ata_bmdma_post_internal_cmd,
296 .cable_detect = ata_cable_40wire,
297
298 .bmdma_setup = ata_bmdma_setup,
299 .bmdma_start = ata_bmdma_start,
300 .bmdma_stop = ata_bmdma_stop,
301 .bmdma_status = ata_bmdma_status,
302
303 .qc_prep = ata_qc_prep,
304 .qc_issue = ata_qc_issue_prot,
305 .data_xfer = ata_data_xfer,
306
307 .irq_handler = ata_interrupt,
308 .irq_clear = ata_bmdma_irq_clear,
309 .irq_on = ata_irq_on,
310
311 .port_start = ata_sff_port_start,
312 };
313
314 static struct ata_port_operations pdc2026x_port_ops = {
315 .set_piomode = pdc202xx_set_piomode,
316 .set_dmamode = pdc202xx_set_dmamode,
317 .mode_filter = ata_pci_default_filter,
318 .tf_load = ata_tf_load,
319 .tf_read = ata_tf_read,
320 .check_status = ata_check_status,
321 .exec_command = ata_exec_command,
322 .dev_select = ata_std_dev_select,
323 .dev_config = pdc2026x_dev_config,
324
325 .freeze = ata_bmdma_freeze,
326 .thaw = ata_bmdma_thaw,
327 .error_handler = ata_bmdma_error_handler,
328 .post_internal_cmd = ata_bmdma_post_internal_cmd,
329 .cable_detect = pdc2026x_cable_detect,
330
331 .check_atapi_dma= pdc2026x_check_atapi_dma,
332 .bmdma_setup = ata_bmdma_setup,
333 .bmdma_start = pdc2026x_bmdma_start,
334 .bmdma_stop = pdc2026x_bmdma_stop,
335 .bmdma_status = ata_bmdma_status,
336
337 .qc_prep = ata_qc_prep,
338 .qc_issue = ata_qc_issue_prot,
339 .data_xfer = ata_data_xfer,
340
341 .irq_handler = ata_interrupt,
342 .irq_clear = ata_bmdma_irq_clear,
343 .irq_on = ata_irq_on,
344
345 .port_start = pdc2026x_port_start,
346 };
347
348 static int pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
349 {
350 static const struct ata_port_info info[3] = {
351 {
352 .sht = &pdc202xx_sht,
353 .flags = ATA_FLAG_SLAVE_POSS,
354 .pio_mask = 0x1f,
355 .mwdma_mask = 0x07,
356 .udma_mask = ATA_UDMA2,
357 .port_ops = &pdc2024x_port_ops
358 },
359 {
360 .sht = &pdc202xx_sht,
361 .flags = ATA_FLAG_SLAVE_POSS,
362 .pio_mask = 0x1f,
363 .mwdma_mask = 0x07,
364 .udma_mask = ATA_UDMA4,
365 .port_ops = &pdc2026x_port_ops
366 },
367 {
368 .sht = &pdc202xx_sht,
369 .flags = ATA_FLAG_SLAVE_POSS,
370 .pio_mask = 0x1f,
371 .mwdma_mask = 0x07,
372 .udma_mask = ATA_UDMA5,
373 .port_ops = &pdc2026x_port_ops
374 }
375
376 };
377 const struct ata_port_info *ppi[] = { &info[id->driver_data], NULL };
378
379 if (dev->device == PCI_DEVICE_ID_PROMISE_20265) {
380 struct pci_dev *bridge = dev->bus->self;
381 /* Don't grab anything behind a Promise I2O RAID */
382 if (bridge && bridge->vendor == PCI_VENDOR_ID_INTEL) {
383 if (bridge->device == PCI_DEVICE_ID_INTEL_I960)
384 return -ENODEV;
385 if (bridge->device == PCI_DEVICE_ID_INTEL_I960RM)
386 return -ENODEV;
387 }
388 }
389 return ata_pci_init_one(dev, ppi);
390 }
391
392 static const struct pci_device_id pdc202xx[] = {
393 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
394 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
395 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
396 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
397 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },
398
399 { },
400 };
401
402 static struct pci_driver pdc202xx_pci_driver = {
403 .name = DRV_NAME,
404 .id_table = pdc202xx,
405 .probe = pdc202xx_init_one,
406 .remove = ata_pci_remove_one,
407 #ifdef CONFIG_PM
408 .suspend = ata_pci_device_suspend,
409 .resume = ata_pci_device_resume,
410 #endif
411 };
412
413 static int __init pdc202xx_init(void)
414 {
415 return pci_register_driver(&pdc202xx_pci_driver);
416 }
417
418 static void __exit pdc202xx_exit(void)
419 {
420 pci_unregister_driver(&pdc202xx_pci_driver);
421 }
422
423 MODULE_AUTHOR("Alan Cox");
424 MODULE_DESCRIPTION("low-level driver for Promise 2024x and 20262-20267");
425 MODULE_LICENSE("GPL");
426 MODULE_DEVICE_TABLE(pci, pdc202xx);
427 MODULE_VERSION(DRV_VERSION);
428
429 module_init(pdc202xx_init);
430 module_exit(pdc202xx_exit);
WRT350N Kernel Patches