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x86: i8259A: remove redundant irq_descinitialization
[wrt350n-kernel.git] / drivers / net / ns83820.c
blobb42c05f84be15d78d59600362f7e8f8f5e0837d0
1 #define VERSION "0.23"
2 /* ns83820.c by Benjamin LaHaise with contributions.
3 *
4 * Questions/comments/discussion to linux-ns83820@kvack.org.
5 *
6 * $Revision: 1.34.2.23 $
7 *
8 * Copyright 2001 Benjamin LaHaise.
9 * Copyright 2001, 2002 Red Hat.
10 *
11 * Mmmm, chocolate vanilla mocha...
12 *
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 *
28 *
29 * ChangeLog
30 * =========
31 * 20010414 0.1 - created
32 * 20010622 0.2 - basic rx and tx.
33 * 20010711 0.3 - added duplex and link state detection support.
34 * 20010713 0.4 - zero copy, no hangs.
35 * 0.5 - 64 bit dma support (davem will hate me for this)
36 * - disable jumbo frames to avoid tx hangs
37 * - work around tx deadlocks on my 1.02 card via
38 * fiddling with TXCFG
39 * 20010810 0.6 - use pci dma api for ringbuffers, work on ia64
40 * 20010816 0.7 - misc cleanups
41 * 20010826 0.8 - fix critical zero copy bugs
42 * 0.9 - internal experiment
43 * 20010827 0.10 - fix ia64 unaligned access.
44 * 20010906 0.11 - accept all packets with checksum errors as
45 * otherwise fragments get lost
46 * - fix >> 32 bugs
47 * 0.12 - add statistics counters
48 * - add allmulti/promisc support
49 * 20011009 0.13 - hotplug support, other smaller pci api cleanups
50 * 20011204 0.13a - optical transceiver support added
51 * by Michael Clark <michael@metaparadigm.com>
52 * 20011205 0.13b - call register_netdev earlier in initialization
53 * suppress duplicate link status messages
54 * 20011117 0.14 - ethtool GDRVINFO, GLINK support from jgarzik
55 * 20011204 0.15 get ppc (big endian) working
56 * 20011218 0.16 various cleanups
57 * 20020310 0.17 speedups
58 * 20020610 0.18 - actually use the pci dma api for highmem
59 * - remove pci latency register fiddling
60 * 0.19 - better bist support
61 * - add ihr and reset_phy parameters
62 * - gmii bus probing
63 * - fix missed txok introduced during performance
64 * tuning
65 * 0.20 - fix stupid RFEN thinko. i am such a smurf.
66 * 20040828 0.21 - add hardware vlan accleration
67 * by Neil Horman <nhorman@redhat.com>
68 * 20050406 0.22 - improved DAC ifdefs from Andi Kleen
69 * - removal of dead code from Adrian Bunk
70 * - fix half duplex collision behaviour
71 * Driver Overview
72 * ===============
73 *
74 * This driver was originally written for the National Semiconductor
75 * 83820 chip, a 10/100/1000 Mbps 64 bit PCI ethernet NIC. Hopefully
76 * this code will turn out to be a) clean, b) correct, and c) fast.
77 * With that in mind, I'm aiming to split the code up as much as
78 * reasonably possible. At present there are X major sections that
79 * break down into a) packet receive, b) packet transmit, c) link
80 * management, d) initialization and configuration. Where possible,
81 * these code paths are designed to run in parallel.
82 *
83 * This driver has been tested and found to work with the following
84 * cards (in no particular order):
85 *
86 * Cameo SOHO-GA2000T SOHO-GA2500T
87 * D-Link DGE-500T
88 * PureData PDP8023Z-TG
89 * SMC SMC9452TX SMC9462TX
90 * Netgear GA621
91 *
92 * Special thanks to SMC for providing hardware to test this driver on.
93 *
94 * Reports of success or failure would be greatly appreciated.
95 */
96 //#define dprintk printk
97 #define dprintk(x...) do { } while (0)
98
99 #include <linux/module.h>
100 #include <linux/moduleparam.h>
101 #include <linux/types.h>
102 #include <linux/pci.h>
103 #include <linux/dma-mapping.h>
104 #include <linux/netdevice.h>
105 #include <linux/etherdevice.h>
106 #include <linux/delay.h>
107 #include <linux/workqueue.h>
108 #include <linux/init.h>
109 #include <linux/ip.h> /* for iph */
110 #include <linux/in.h> /* for IPPROTO_... */
111 #include <linux/compiler.h>
112 #include <linux/prefetch.h>
113 #include <linux/ethtool.h>
114 #include <linux/timer.h>
115 #include <linux/if_vlan.h>
116 #include <linux/rtnetlink.h>
117 #include <linux/jiffies.h>
118
119 #include <asm/io.h>
120 #include <asm/uaccess.h>
121 #include <asm/system.h>
122
123 #define DRV_NAME "ns83820"
124
125 /* Global parameters. See module_param near the bottom. */
126 static int ihr = 2;
127 static int reset_phy = 0;
128 static int lnksts = 0; /* CFG_LNKSTS bit polarity */
129
130 /* Dprintk is used for more interesting debug events */
131 #undef Dprintk
132 #define Dprintk dprintk
133
134 /* tunables */
135 #define RX_BUF_SIZE 1500 /* 8192 */
136 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
137 #define NS83820_VLAN_ACCEL_SUPPORT
138 #endif
139
140 /* Must not exceed ~65000. */
141 #define NR_RX_DESC 64
142 #define NR_TX_DESC 128
143
144 /* not tunable */
145 #define REAL_RX_BUF_SIZE (RX_BUF_SIZE + 14) /* rx/tx mac addr + type */
146
147 #define MIN_TX_DESC_FREE 8
148
149 /* register defines */
150 #define CFGCS 0x04
151
152 #define CR_TXE 0x00000001
153 #define CR_TXD 0x00000002
154 /* Ramit : Here's a tip, don't do a RXD immediately followed by an RXE
155 * The Receive engine skips one descriptor and moves
156 * onto the next one!! */
157 #define CR_RXE 0x00000004
158 #define CR_RXD 0x00000008
159 #define CR_TXR 0x00000010
160 #define CR_RXR 0x00000020
161 #define CR_SWI 0x00000080
162 #define CR_RST 0x00000100
163
164 #define PTSCR_EEBIST_FAIL 0x00000001
165 #define PTSCR_EEBIST_EN 0x00000002
166 #define PTSCR_EELOAD_EN 0x00000004
167 #define PTSCR_RBIST_FAIL 0x000001b8
168 #define PTSCR_RBIST_DONE 0x00000200
169 #define PTSCR_RBIST_EN 0x00000400
170 #define PTSCR_RBIST_RST 0x00002000
171
172 #define MEAR_EEDI 0x00000001
173 #define MEAR_EEDO 0x00000002
174 #define MEAR_EECLK 0x00000004
175 #define MEAR_EESEL 0x00000008
176 #define MEAR_MDIO 0x00000010
177 #define MEAR_MDDIR 0x00000020
178 #define MEAR_MDC 0x00000040
179
180 #define ISR_TXDESC3 0x40000000
181 #define ISR_TXDESC2 0x20000000
182 #define ISR_TXDESC1 0x10000000
183 #define ISR_TXDESC0 0x08000000
184 #define ISR_RXDESC3 0x04000000
185 #define ISR_RXDESC2 0x02000000
186 #define ISR_RXDESC1 0x01000000
187 #define ISR_RXDESC0 0x00800000
188 #define ISR_TXRCMP 0x00400000
189 #define ISR_RXRCMP 0x00200000
190 #define ISR_DPERR 0x00100000
191 #define ISR_SSERR 0x00080000
192 #define ISR_RMABT 0x00040000
193 #define ISR_RTABT 0x00020000
194 #define ISR_RXSOVR 0x00010000
195 #define ISR_HIBINT 0x00008000
196 #define ISR_PHY 0x00004000
197 #define ISR_PME 0x00002000
198 #define ISR_SWI 0x00001000
199 #define ISR_MIB 0x00000800
200 #define ISR_TXURN 0x00000400
201 #define ISR_TXIDLE 0x00000200
202 #define ISR_TXERR 0x00000100
203 #define ISR_TXDESC 0x00000080
204 #define ISR_TXOK 0x00000040
205 #define ISR_RXORN 0x00000020
206 #define ISR_RXIDLE 0x00000010
207 #define ISR_RXEARLY 0x00000008
208 #define ISR_RXERR 0x00000004
209 #define ISR_RXDESC 0x00000002
210 #define ISR_RXOK 0x00000001
211
212 #define TXCFG_CSI 0x80000000
213 #define TXCFG_HBI 0x40000000
214 #define TXCFG_MLB 0x20000000
215 #define TXCFG_ATP 0x10000000
216 #define TXCFG_ECRETRY 0x00800000
217 #define TXCFG_BRST_DIS 0x00080000
218 #define TXCFG_MXDMA1024 0x00000000
219 #define TXCFG_MXDMA512 0x00700000
220 #define TXCFG_MXDMA256 0x00600000
221 #define TXCFG_MXDMA128 0x00500000
222 #define TXCFG_MXDMA64 0x00400000
223 #define TXCFG_MXDMA32 0x00300000
224 #define TXCFG_MXDMA16 0x00200000
225 #define TXCFG_MXDMA8 0x00100000
226
227 #define CFG_LNKSTS 0x80000000
228 #define CFG_SPDSTS 0x60000000
229 #define CFG_SPDSTS1 0x40000000
230 #define CFG_SPDSTS0 0x20000000
231 #define CFG_DUPSTS 0x10000000
232 #define CFG_TBI_EN 0x01000000
233 #define CFG_MODE_1000 0x00400000
234 /* Ramit : Dont' ever use AUTO_1000, it never works and is buggy.
235 * Read the Phy response and then configure the MAC accordingly */
236 #define CFG_AUTO_1000 0x00200000
237 #define CFG_PINT_CTL 0x001c0000
238 #define CFG_PINT_DUPSTS 0x00100000
239 #define CFG_PINT_LNKSTS 0x00080000
240 #define CFG_PINT_SPDSTS 0x00040000
241 #define CFG_TMRTEST 0x00020000
242 #define CFG_MRM_DIS 0x00010000
243 #define CFG_MWI_DIS 0x00008000
244 #define CFG_T64ADDR 0x00004000
245 #define CFG_PCI64_DET 0x00002000
246 #define CFG_DATA64_EN 0x00001000
247 #define CFG_M64ADDR 0x00000800
248 #define CFG_PHY_RST 0x00000400
249 #define CFG_PHY_DIS 0x00000200
250 #define CFG_EXTSTS_EN 0x00000100
251 #define CFG_REQALG 0x00000080
252 #define CFG_SB 0x00000040
253 #define CFG_POW 0x00000020
254 #define CFG_EXD 0x00000010
255 #define CFG_PESEL 0x00000008
256 #define CFG_BROM_DIS 0x00000004
257 #define CFG_EXT_125 0x00000002
258 #define CFG_BEM 0x00000001
259
260 #define EXTSTS_UDPPKT 0x00200000
261 #define EXTSTS_TCPPKT 0x00080000
262 #define EXTSTS_IPPKT 0x00020000
263 #define EXTSTS_VPKT 0x00010000
264 #define EXTSTS_VTG_MASK 0x0000ffff
265
266 #define SPDSTS_POLARITY (CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0))
267
268 #define MIBC_MIBS 0x00000008
269 #define MIBC_ACLR 0x00000004
270 #define MIBC_FRZ 0x00000002
271 #define MIBC_WRN 0x00000001
272
273 #define PCR_PSEN (1 << 31)
274 #define PCR_PS_MCAST (1 << 30)
275 #define PCR_PS_DA (1 << 29)
276 #define PCR_STHI_8 (3 << 23)
277 #define PCR_STLO_4 (1 << 23)
278 #define PCR_FFHI_8K (3 << 21)
279 #define PCR_FFLO_4K (1 << 21)
280 #define PCR_PAUSE_CNT 0xFFFE
281
282 #define RXCFG_AEP 0x80000000
283 #define RXCFG_ARP 0x40000000
284 #define RXCFG_STRIPCRC 0x20000000
285 #define RXCFG_RX_FD 0x10000000
286 #define RXCFG_ALP 0x08000000
287 #define RXCFG_AIRL 0x04000000
288 #define RXCFG_MXDMA512 0x00700000
289 #define RXCFG_DRTH 0x0000003e
290 #define RXCFG_DRTH0 0x00000002
291
292 #define RFCR_RFEN 0x80000000
293 #define RFCR_AAB 0x40000000
294 #define RFCR_AAM 0x20000000
295 #define RFCR_AAU 0x10000000
296 #define RFCR_APM 0x08000000
297 #define RFCR_APAT 0x07800000
298 #define RFCR_APAT3 0x04000000
299 #define RFCR_APAT2 0x02000000
300 #define RFCR_APAT1 0x01000000
301 #define RFCR_APAT0 0x00800000
302 #define RFCR_AARP 0x00400000
303 #define RFCR_MHEN 0x00200000
304 #define RFCR_UHEN 0x00100000
305 #define RFCR_ULM 0x00080000
306
307 #define VRCR_RUDPE 0x00000080
308 #define VRCR_RTCPE 0x00000040
309 #define VRCR_RIPE 0x00000020
310 #define VRCR_IPEN 0x00000010
311 #define VRCR_DUTF 0x00000008
312 #define VRCR_DVTF 0x00000004
313 #define VRCR_VTREN 0x00000002
314 #define VRCR_VTDEN 0x00000001
315
316 #define VTCR_PPCHK 0x00000008
317 #define VTCR_GCHK 0x00000004
318 #define VTCR_VPPTI 0x00000002
319 #define VTCR_VGTI 0x00000001
320
321 #define CR 0x00
322 #define CFG 0x04
323 #define MEAR 0x08
324 #define PTSCR 0x0c
325 #define ISR 0x10
326 #define IMR 0x14
327 #define IER 0x18
328 #define IHR 0x1c
329 #define TXDP 0x20
330 #define TXDP_HI 0x24
331 #define TXCFG 0x28
332 #define GPIOR 0x2c
333 #define RXDP 0x30
334 #define RXDP_HI 0x34
335 #define RXCFG 0x38
336 #define PQCR 0x3c
337 #define WCSR 0x40
338 #define PCR 0x44
339 #define RFCR 0x48
340 #define RFDR 0x4c
341
342 #define SRR 0x58
343
344 #define VRCR 0xbc
345 #define VTCR 0xc0
346 #define VDR 0xc4
347 #define CCSR 0xcc
348
349 #define TBICR 0xe0
350 #define TBISR 0xe4
351 #define TANAR 0xe8
352 #define TANLPAR 0xec
353 #define TANER 0xf0
354 #define TESR 0xf4
355
356 #define TBICR_MR_AN_ENABLE 0x00001000
357 #define TBICR_MR_RESTART_AN 0x00000200
358
359 #define TBISR_MR_LINK_STATUS 0x00000020
360 #define TBISR_MR_AN_COMPLETE 0x00000004
361
362 #define TANAR_PS2 0x00000100
363 #define TANAR_PS1 0x00000080
364 #define TANAR_HALF_DUP 0x00000040
365 #define TANAR_FULL_DUP 0x00000020
366
367 #define GPIOR_GP5_OE 0x00000200
368 #define GPIOR_GP4_OE 0x00000100
369 #define GPIOR_GP3_OE 0x00000080
370 #define GPIOR_GP2_OE 0x00000040
371 #define GPIOR_GP1_OE 0x00000020
372 #define GPIOR_GP3_OUT 0x00000004
373 #define GPIOR_GP1_OUT 0x00000001
374
375 #define LINK_AUTONEGOTIATE 0x01
376 #define LINK_DOWN 0x02
377 #define LINK_UP 0x04
378
379 #define HW_ADDR_LEN sizeof(dma_addr_t)
380 #define desc_addr_set(desc, addr) \
381 do { \
382 ((desc)[0] = cpu_to_le32(addr)); \
383 if (HW_ADDR_LEN == 8) \
384 (desc)[1] = cpu_to_le32(((u64)addr) >> 32); \
385 } while(0)
386 #define desc_addr_get(desc) \
387 (le32_to_cpu((desc)[0]) | \
388 (HW_ADDR_LEN == 8 ? ((dma_addr_t)le32_to_cpu((desc)[1]))<<32 : 0))
389
390 #define DESC_LINK 0
391 #define DESC_BUFPTR (DESC_LINK + HW_ADDR_LEN/4)
392 #define DESC_CMDSTS (DESC_BUFPTR + HW_ADDR_LEN/4)
393 #define DESC_EXTSTS (DESC_CMDSTS + 4/4)
394
395 #define CMDSTS_OWN 0x80000000
396 #define CMDSTS_MORE 0x40000000
397 #define CMDSTS_INTR 0x20000000
398 #define CMDSTS_ERR 0x10000000
399 #define CMDSTS_OK 0x08000000
400 #define CMDSTS_RUNT 0x00200000
401 #define CMDSTS_LEN_MASK 0x0000ffff
402
403 #define CMDSTS_DEST_MASK 0x01800000
404 #define CMDSTS_DEST_SELF 0x00800000
405 #define CMDSTS_DEST_MULTI 0x01000000
406
407 #define DESC_SIZE 8 /* Should be cache line sized */
408
409 struct rx_info {
410 spinlock_t lock;
411 int up;
412 long idle;
413
414 struct sk_buff *skbs[NR_RX_DESC];
415
416 __le32 *next_rx_desc;
417 u16 next_rx, next_empty;
418
419 __le32 *descs;
420 dma_addr_t phy_descs;
421 };
422
423
424 struct ns83820 {
425 struct net_device_stats stats;
426 u8 __iomem *base;
427
428 struct pci_dev *pci_dev;
429 struct net_device *ndev;
430
431 #ifdef NS83820_VLAN_ACCEL_SUPPORT
432 struct vlan_group *vlgrp;
433 #endif
434
435 struct rx_info rx_info;
436 struct tasklet_struct rx_tasklet;
437
438 unsigned ihr;
439 struct work_struct tq_refill;
440
441 /* protects everything below. irqsave when using. */
442 spinlock_t misc_lock;
443
444 u32 CFG_cache;
445
446 u32 MEAR_cache;
447 u32 IMR_cache;
448
449 unsigned linkstate;
450
451 spinlock_t tx_lock;
452
453 u16 tx_done_idx;
454 u16 tx_idx;
455 volatile u16 tx_free_idx; /* idx of free desc chain */
456 u16 tx_intr_idx;
457
458 atomic_t nr_tx_skbs;
459 struct sk_buff *tx_skbs[NR_TX_DESC];
460
461 char pad[16] __attribute__((aligned(16)));
462 __le32 *tx_descs;
463 dma_addr_t tx_phy_descs;
464
465 struct timer_list tx_watchdog;
466 };
467
468 static inline struct ns83820 *PRIV(struct net_device *dev)
469 {
470 return netdev_priv(dev);
471 }
472
473 #define __kick_rx(dev) writel(CR_RXE, dev->base + CR)
474
475 static inline void kick_rx(struct net_device *ndev)
476 {
477 struct ns83820 *dev = PRIV(ndev);
478 dprintk("kick_rx: maybe kicking\n");
479 if (test_and_clear_bit(0, &dev->rx_info.idle)) {
480 dprintk("actually kicking\n");
481 writel(dev->rx_info.phy_descs +
482 (4 * DESC_SIZE * dev->rx_info.next_rx),
483 dev->base + RXDP);
484 if (dev->rx_info.next_rx == dev->rx_info.next_empty)
485 printk(KERN_DEBUG "%s: uh-oh: next_rx == next_empty???\n",
486 ndev->name);
487 __kick_rx(dev);
488 }
489 }
490
491 //free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC
492 #define start_tx_okay(dev) \
493 (((NR_TX_DESC-2 + dev->tx_done_idx - dev->tx_free_idx) % NR_TX_DESC) > MIN_TX_DESC_FREE)
494
495
496 #ifdef NS83820_VLAN_ACCEL_SUPPORT
497 static void ns83820_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
498 {
499 struct ns83820 *dev = PRIV(ndev);
500
501 spin_lock_irq(&dev->misc_lock);
502 spin_lock(&dev->tx_lock);
503
504 dev->vlgrp = grp;
505
506 spin_unlock(&dev->tx_lock);
507 spin_unlock_irq(&dev->misc_lock);
508 }
509 #endif
510
511 /* Packet Receiver
512 *
513 * The hardware supports linked lists of receive descriptors for
514 * which ownership is transfered back and forth by means of an
515 * ownership bit. While the hardware does support the use of a
516 * ring for receive descriptors, we only make use of a chain in
517 * an attempt to reduce bus traffic under heavy load scenarios.
518 * This will also make bugs a bit more obvious. The current code
519 * only makes use of a single rx chain; I hope to implement
520 * priority based rx for version 1.0. Goal: even under overload
521 * conditions, still route realtime traffic with as low jitter as
522 * possible.
523 */
524 static inline void build_rx_desc(struct ns83820 *dev, __le32 *desc, dma_addr_t link, dma_addr_t buf, u32 cmdsts, u32 extsts)
525 {
526 desc_addr_set(desc + DESC_LINK, link);
527 desc_addr_set(desc + DESC_BUFPTR, buf);
528 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
529 mb();
530 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
531 }
532
533 #define nr_rx_empty(dev) ((NR_RX_DESC-2 + dev->rx_info.next_rx - dev->rx_info.next_empty) % NR_RX_DESC)
534 static inline int ns83820_add_rx_skb(struct ns83820 *dev, struct sk_buff *skb)
535 {
536 unsigned next_empty;
537 u32 cmdsts;
538 __le32 *sg;
539 dma_addr_t buf;
540
541 next_empty = dev->rx_info.next_empty;
542
543 /* don't overrun last rx marker */
544 if (unlikely(nr_rx_empty(dev) <= 2)) {
545 kfree_skb(skb);
546 return 1;
547 }
548
549 #if 0
550 dprintk("next_empty[%d] nr_used[%d] next_rx[%d]\n",
551 dev->rx_info.next_empty,
552 dev->rx_info.nr_used,
553 dev->rx_info.next_rx
554 );
555 #endif
556
557 sg = dev->rx_info.descs + (next_empty * DESC_SIZE);
558 BUG_ON(NULL != dev->rx_info.skbs[next_empty]);
559 dev->rx_info.skbs[next_empty] = skb;
560
561 dev->rx_info.next_empty = (next_empty + 1) % NR_RX_DESC;
562 cmdsts = REAL_RX_BUF_SIZE | CMDSTS_INTR;
563 buf = pci_map_single(dev->pci_dev, skb->data,
564 REAL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
565 build_rx_desc(dev, sg, 0, buf, cmdsts, 0);
566 /* update link of previous rx */
567 if (likely(next_empty != dev->rx_info.next_rx))
568 dev->rx_info.descs[((NR_RX_DESC + next_empty - 1) % NR_RX_DESC) * DESC_SIZE] = cpu_to_le32(dev->rx_info.phy_descs + (next_empty * DESC_SIZE * 4));
569
570 return 0;
571 }
572
573 static inline int rx_refill(struct net_device *ndev, gfp_t gfp)
574 {
575 struct ns83820 *dev = PRIV(ndev);
576 unsigned i;
577 unsigned long flags = 0;
578
579 if (unlikely(nr_rx_empty(dev) <= 2))
580 return 0;
581
582 dprintk("rx_refill(%p)\n", ndev);
583 if (gfp == GFP_ATOMIC)
584 spin_lock_irqsave(&dev->rx_info.lock, flags);
585 for (i=0; i<NR_RX_DESC; i++) {
586 struct sk_buff *skb;
587 long res;
588 /* extra 16 bytes for alignment */
589 skb = __dev_alloc_skb(REAL_RX_BUF_SIZE+16, gfp);
590 if (unlikely(!skb))
591 break;
592
593 res = (long)skb->data & 0xf;
594 res = 0x10 - res;
595 res &= 0xf;
596 skb_reserve(skb, res);
597
598 if (gfp != GFP_ATOMIC)
599 spin_lock_irqsave(&dev->rx_info.lock, flags);
600 res = ns83820_add_rx_skb(dev, skb);
601 if (gfp != GFP_ATOMIC)
602 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
603 if (res) {
604 i = 1;
605 break;
606 }
607 }
608 if (gfp == GFP_ATOMIC)
609 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
610
611 return i ? 0 : -ENOMEM;
612 }
613
614 static void rx_refill_atomic(struct net_device *ndev)
615 {
616 rx_refill(ndev, GFP_ATOMIC);
617 }
618
619 /* REFILL */
620 static inline void queue_refill(struct work_struct *work)
621 {
622 struct ns83820 *dev = container_of(work, struct ns83820, tq_refill);
623 struct net_device *ndev = dev->ndev;
624
625 rx_refill(ndev, GFP_KERNEL);
626 if (dev->rx_info.up)
627 kick_rx(ndev);
628 }
629
630 static inline void clear_rx_desc(struct ns83820 *dev, unsigned i)
631 {
632 build_rx_desc(dev, dev->rx_info.descs + (DESC_SIZE * i), 0, 0, CMDSTS_OWN, 0);
633 }
634
635 static void phy_intr(struct net_device *ndev)
636 {
637 struct ns83820 *dev = PRIV(ndev);
638 static const char *speeds[] = { "10", "100", "1000", "1000(?)", "1000F" };
639 u32 cfg, new_cfg;
640 u32 tbisr, tanar, tanlpar;
641 int speed, fullduplex, newlinkstate;
642
643 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
644
645 if (dev->CFG_cache & CFG_TBI_EN) {
646 /* we have an optical transceiver */
647 tbisr = readl(dev->base + TBISR);
648 tanar = readl(dev->base + TANAR);
649 tanlpar = readl(dev->base + TANLPAR);
650 dprintk("phy_intr: tbisr=%08x, tanar=%08x, tanlpar=%08x\n",
651 tbisr, tanar, tanlpar);
652
653 if ( (fullduplex = (tanlpar & TANAR_FULL_DUP)
654 && (tanar & TANAR_FULL_DUP)) ) {
655
656 /* both of us are full duplex */
657 writel(readl(dev->base + TXCFG)
658 | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP,
659 dev->base + TXCFG);
660 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
661 dev->base + RXCFG);
662 /* Light up full duplex LED */
663 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
664 dev->base + GPIOR);
665
666 } else if(((tanlpar & TANAR_HALF_DUP)
667 && (tanar & TANAR_HALF_DUP))
668 || ((tanlpar & TANAR_FULL_DUP)
669 && (tanar & TANAR_HALF_DUP))
670 || ((tanlpar & TANAR_HALF_DUP)
671 && (tanar & TANAR_FULL_DUP))) {
672
673 /* one or both of us are half duplex */
674 writel((readl(dev->base + TXCFG)
675 & ~(TXCFG_CSI | TXCFG_HBI)) | TXCFG_ATP,
676 dev->base + TXCFG);
677 writel(readl(dev->base + RXCFG) & ~RXCFG_RX_FD,
678 dev->base + RXCFG);
679 /* Turn off full duplex LED */
680 writel(readl(dev->base + GPIOR) & ~GPIOR_GP1_OUT,
681 dev->base + GPIOR);
682 }
683
684 speed = 4; /* 1000F */
685
686 } else {
687 /* we have a copper transceiver */
688 new_cfg = dev->CFG_cache & ~(CFG_SB | CFG_MODE_1000 | CFG_SPDSTS);
689
690 if (cfg & CFG_SPDSTS1)
691 new_cfg |= CFG_MODE_1000;
692 else
693 new_cfg &= ~CFG_MODE_1000;
694
695 speed = ((cfg / CFG_SPDSTS0) & 3);
696 fullduplex = (cfg & CFG_DUPSTS);
697
698 if (fullduplex) {
699 new_cfg |= CFG_SB;
700 writel(readl(dev->base + TXCFG)
701 | TXCFG_CSI | TXCFG_HBI,
702 dev->base + TXCFG);
703 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
704 dev->base + RXCFG);
705 } else {
706 writel(readl(dev->base + TXCFG)
707 & ~(TXCFG_CSI | TXCFG_HBI),
708 dev->base + TXCFG);
709 writel(readl(dev->base + RXCFG) & ~(RXCFG_RX_FD),
710 dev->base + RXCFG);
711 }
712
713 if ((cfg & CFG_LNKSTS) &&
714 ((new_cfg ^ dev->CFG_cache) != 0)) {
715 writel(new_cfg, dev->base + CFG);
716 dev->CFG_cache = new_cfg;
717 }
718
719 dev->CFG_cache &= ~CFG_SPDSTS;
720 dev->CFG_cache |= cfg & CFG_SPDSTS;
721 }
722
723 newlinkstate = (cfg & CFG_LNKSTS) ? LINK_UP : LINK_DOWN;
724
725 if (newlinkstate & LINK_UP
726 && dev->linkstate != newlinkstate) {
727 netif_start_queue(ndev);
728 netif_wake_queue(ndev);
729 printk(KERN_INFO "%s: link now %s mbps, %s duplex and up.\n",
730 ndev->name,
731 speeds[speed],
732 fullduplex ? "full" : "half");
733 } else if (newlinkstate & LINK_DOWN
734 && dev->linkstate != newlinkstate) {
735 netif_stop_queue(ndev);
736 printk(KERN_INFO "%s: link now down.\n", ndev->name);
737 }
738
739 dev->linkstate = newlinkstate;
740 }
741
742 static int ns83820_setup_rx(struct net_device *ndev)
743 {
744 struct ns83820 *dev = PRIV(ndev);
745 unsigned i;
746 int ret;
747
748 dprintk("ns83820_setup_rx(%p)\n", ndev);
749
750 dev->rx_info.idle = 1;
751 dev->rx_info.next_rx = 0;
752 dev->rx_info.next_rx_desc = dev->rx_info.descs;
753 dev->rx_info.next_empty = 0;
754
755 for (i=0; i<NR_RX_DESC; i++)
756 clear_rx_desc(dev, i);
757
758 writel(0, dev->base + RXDP_HI);
759 writel(dev->rx_info.phy_descs, dev->base + RXDP);
760
761 ret = rx_refill(ndev, GFP_KERNEL);
762 if (!ret) {
763 dprintk("starting receiver\n");
764 /* prevent the interrupt handler from stomping on us */
765 spin_lock_irq(&dev->rx_info.lock);
766
767 writel(0x0001, dev->base + CCSR);
768 writel(0, dev->base + RFCR);
769 writel(0x7fc00000, dev->base + RFCR);
770 writel(0xffc00000, dev->base + RFCR);
771
772 dev->rx_info.up = 1;
773
774 phy_intr(ndev);
775
776 /* Okay, let it rip */
777 spin_lock_irq(&dev->misc_lock);
778 dev->IMR_cache |= ISR_PHY;
779 dev->IMR_cache |= ISR_RXRCMP;
780 //dev->IMR_cache |= ISR_RXERR;
781 //dev->IMR_cache |= ISR_RXOK;
782 dev->IMR_cache |= ISR_RXORN;
783 dev->IMR_cache |= ISR_RXSOVR;
784 dev->IMR_cache |= ISR_RXDESC;
785 dev->IMR_cache |= ISR_RXIDLE;
786 dev->IMR_cache |= ISR_TXDESC;
787 dev->IMR_cache |= ISR_TXIDLE;
788
789 writel(dev->IMR_cache, dev->base + IMR);
790 writel(1, dev->base + IER);
791 spin_unlock(&dev->misc_lock);
792
793 kick_rx(ndev);
794
795 spin_unlock_irq(&dev->rx_info.lock);
796 }
797 return ret;
798 }
799
800 static void ns83820_cleanup_rx(struct ns83820 *dev)
801 {
802 unsigned i;
803 unsigned long flags;
804
805 dprintk("ns83820_cleanup_rx(%p)\n", dev);
806
807 /* disable receive interrupts */
808 spin_lock_irqsave(&dev->misc_lock, flags);
809 dev->IMR_cache &= ~(ISR_RXOK | ISR_RXDESC | ISR_RXERR | ISR_RXEARLY | ISR_RXIDLE);
810 writel(dev->IMR_cache, dev->base + IMR);
811 spin_unlock_irqrestore(&dev->misc_lock, flags);
812
813 /* synchronize with the interrupt handler and kill it */
814 dev->rx_info.up = 0;
815 synchronize_irq(dev->pci_dev->irq);
816
817 /* touch the pci bus... */
818 readl(dev->base + IMR);
819
820 /* assumes the transmitter is already disabled and reset */
821 writel(0, dev->base + RXDP_HI);
822 writel(0, dev->base + RXDP);
823
824 for (i=0; i<NR_RX_DESC; i++) {
825 struct sk_buff *skb = dev->rx_info.skbs[i];
826 dev->rx_info.skbs[i] = NULL;
827 clear_rx_desc(dev, i);
828 if (skb)
829 kfree_skb(skb);
830 }
831 }
832
833 static void ns83820_rx_kick(struct net_device *ndev)
834 {
835 struct ns83820 *dev = PRIV(ndev);
836 /*if (nr_rx_empty(dev) >= NR_RX_DESC/4)*/ {
837 if (dev->rx_info.up) {
838 rx_refill_atomic(ndev);
839 kick_rx(ndev);
840 }
841 }
842
843 if (dev->rx_info.up && nr_rx_empty(dev) > NR_RX_DESC*3/4)
844 schedule_work(&dev->tq_refill);
845 else
846 kick_rx(ndev);
847 if (dev->rx_info.idle)
848 printk(KERN_DEBUG "%s: BAD\n", ndev->name);
849 }
850
851 /* rx_irq
852 *
853 */
854 static void rx_irq(struct net_device *ndev)
855 {
856 struct ns83820 *dev = PRIV(ndev);
857 struct rx_info *info = &dev->rx_info;
858 unsigned next_rx;
859 int rx_rc, len;
860 u32 cmdsts;
861 __le32 *desc;
862 unsigned long flags;
863 int nr = 0;
864
865 dprintk("rx_irq(%p)\n", ndev);
866 dprintk("rxdp: %08x, descs: %08lx next_rx[%d]: %p next_empty[%d]: %p\n",
867 readl(dev->base + RXDP),
868 (long)(dev->rx_info.phy_descs),
869 (int)dev->rx_info.next_rx,
870 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_rx)),
871 (int)dev->rx_info.next_empty,
872 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_empty))
873 );
874
875 spin_lock_irqsave(&info->lock, flags);
876 if (!info->up)
877 goto out;
878
879 dprintk("walking descs\n");
880 next_rx = info->next_rx;
881 desc = info->next_rx_desc;
882 while ((CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) &&
883 (cmdsts != CMDSTS_OWN)) {
884 struct sk_buff *skb;
885 u32 extsts = le32_to_cpu(desc[DESC_EXTSTS]);
886 dma_addr_t bufptr = desc_addr_get(desc + DESC_BUFPTR);
887
888 dprintk("cmdsts: %08x\n", cmdsts);
889 dprintk("link: %08x\n", cpu_to_le32(desc[DESC_LINK]));
890 dprintk("extsts: %08x\n", extsts);
891
892 skb = info->skbs[next_rx];
893 info->skbs[next_rx] = NULL;
894 info->next_rx = (next_rx + 1) % NR_RX_DESC;
895
896 mb();
897 clear_rx_desc(dev, next_rx);
898
899 pci_unmap_single(dev->pci_dev, bufptr,
900 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
901 len = cmdsts & CMDSTS_LEN_MASK;
902 #ifdef NS83820_VLAN_ACCEL_SUPPORT
903 /* NH: As was mentioned below, this chip is kinda
904 * brain dead about vlan tag stripping. Frames
905 * that are 64 bytes with a vlan header appended
906 * like arp frames, or pings, are flagged as Runts
907 * when the tag is stripped and hardware. This
908 * also means that the OK bit in the descriptor
909 * is cleared when the frame comes in so we have
910 * to do a specific length check here to make sure
911 * the frame would have been ok, had we not stripped
912 * the tag.
913 */
914 if (likely((CMDSTS_OK & cmdsts) ||
915 ((cmdsts & CMDSTS_RUNT) && len >= 56))) {
916 #else
917 if (likely(CMDSTS_OK & cmdsts)) {
918 #endif
919 skb_put(skb, len);
920 if (unlikely(!skb))
921 goto netdev_mangle_me_harder_failed;
922 if (cmdsts & CMDSTS_DEST_MULTI)
923 dev->stats.multicast ++;
924 dev->stats.rx_packets ++;
925 dev->stats.rx_bytes += len;
926 if ((extsts & 0x002a0000) && !(extsts & 0x00540000)) {
927 skb->ip_summed = CHECKSUM_UNNECESSARY;
928 } else {
929 skb->ip_summed = CHECKSUM_NONE;
930 }
931 skb->protocol = eth_type_trans(skb, ndev);
932 #ifdef NS83820_VLAN_ACCEL_SUPPORT
933 if(extsts & EXTSTS_VPKT) {
934 unsigned short tag;
935 tag = ntohs(extsts & EXTSTS_VTG_MASK);
936 rx_rc = vlan_hwaccel_rx(skb,dev->vlgrp,tag);
937 } else {
938 rx_rc = netif_rx(skb);
939 }
940 #else
941 rx_rc = netif_rx(skb);
942 #endif
943 if (NET_RX_DROP == rx_rc) {
944 netdev_mangle_me_harder_failed:
945 dev->stats.rx_dropped ++;
946 }
947 } else {
948 kfree_skb(skb);
949 }
950
951 nr++;
952 next_rx = info->next_rx;
953 desc = info->descs + (DESC_SIZE * next_rx);
954 }
955 info->next_rx = next_rx;
956 info->next_rx_desc = info->descs + (DESC_SIZE * next_rx);
957
958 out:
959 if (0 && !nr) {
960 Dprintk("dazed: cmdsts_f: %08x\n", cmdsts);
961 }
962
963 spin_unlock_irqrestore(&info->lock, flags);
964 }
965
966 static void rx_action(unsigned long _dev)
967 {
968 struct net_device *ndev = (void *)_dev;
969 struct ns83820 *dev = PRIV(ndev);
970 rx_irq(ndev);
971 writel(ihr, dev->base + IHR);
972
973 spin_lock_irq(&dev->misc_lock);
974 dev->IMR_cache |= ISR_RXDESC;
975 writel(dev->IMR_cache, dev->base + IMR);
976 spin_unlock_irq(&dev->misc_lock);
977
978 rx_irq(ndev);
979 ns83820_rx_kick(ndev);
980 }
981
982 /* Packet Transmit code
983 */
984 static inline void kick_tx(struct ns83820 *dev)
985 {
986 dprintk("kick_tx(%p): tx_idx=%d free_idx=%d\n",
987 dev, dev->tx_idx, dev->tx_free_idx);
988 writel(CR_TXE, dev->base + CR);
989 }
990
991 /* No spinlock needed on the transmit irq path as the interrupt handler is
992 * serialized.
993 */
994 static void do_tx_done(struct net_device *ndev)
995 {
996 struct ns83820 *dev = PRIV(ndev);
997 u32 cmdsts, tx_done_idx;
998 __le32 *desc;
999
1000 dprintk("do_tx_done(%p)\n", ndev);
1001 tx_done_idx = dev->tx_done_idx;
1002 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1003
1004 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1005 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1006 while ((tx_done_idx != dev->tx_free_idx) &&
1007 !(CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) ) {
1008 struct sk_buff *skb;
1009 unsigned len;
1010 dma_addr_t addr;
1011
1012 if (cmdsts & CMDSTS_ERR)
1013 dev->stats.tx_errors ++;
1014 if (cmdsts & CMDSTS_OK)
1015 dev->stats.tx_packets ++;
1016 if (cmdsts & CMDSTS_OK)
1017 dev->stats.tx_bytes += cmdsts & 0xffff;
1018
1019 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1020 tx_done_idx, dev->tx_free_idx, cmdsts);
1021 skb = dev->tx_skbs[tx_done_idx];
1022 dev->tx_skbs[tx_done_idx] = NULL;
1023 dprintk("done(%p)\n", skb);
1024
1025 len = cmdsts & CMDSTS_LEN_MASK;
1026 addr = desc_addr_get(desc + DESC_BUFPTR);
1027 if (skb) {
1028 pci_unmap_single(dev->pci_dev,
1029 addr,
1030 len,
1031 PCI_DMA_TODEVICE);
1032 dev_kfree_skb_irq(skb);
1033 atomic_dec(&dev->nr_tx_skbs);
1034 } else
1035 pci_unmap_page(dev->pci_dev,
1036 addr,
1037 len,
1038 PCI_DMA_TODEVICE);
1039
1040 tx_done_idx = (tx_done_idx + 1) % NR_TX_DESC;
1041 dev->tx_done_idx = tx_done_idx;
1042 desc[DESC_CMDSTS] = cpu_to_le32(0);
1043 mb();
1044 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1045 }
1046
1047 /* Allow network stack to resume queueing packets after we've
1048 * finished transmitting at least 1/4 of the packets in the queue.
1049 */
1050 if (netif_queue_stopped(ndev) && start_tx_okay(dev)) {
1051 dprintk("start_queue(%p)\n", ndev);
1052 netif_start_queue(ndev);
1053 netif_wake_queue(ndev);
1054 }
1055 }
1056
1057 static void ns83820_cleanup_tx(struct ns83820 *dev)
1058 {
1059 unsigned i;
1060
1061 for (i=0; i<NR_TX_DESC; i++) {
1062 struct sk_buff *skb = dev->tx_skbs[i];
1063 dev->tx_skbs[i] = NULL;
1064 if (skb) {
1065 __le32 *desc = dev->tx_descs + (i * DESC_SIZE);
1066 pci_unmap_single(dev->pci_dev,
1067 desc_addr_get(desc + DESC_BUFPTR),
1068 le32_to_cpu(desc[DESC_CMDSTS]) & CMDSTS_LEN_MASK,
1069 PCI_DMA_TODEVICE);
1070 dev_kfree_skb_irq(skb);
1071 atomic_dec(&dev->nr_tx_skbs);
1072 }
1073 }
1074
1075 memset(dev->tx_descs, 0, NR_TX_DESC * DESC_SIZE * 4);
1076 }
1077
1078 /* transmit routine. This code relies on the network layer serializing
1079 * its calls in, but will run happily in parallel with the interrupt
1080 * handler. This code currently has provisions for fragmenting tx buffers
1081 * while trying to track down a bug in either the zero copy code or
1082 * the tx fifo (hence the MAX_FRAG_LEN).
1083 */
1084 static int ns83820_hard_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1085 {
1086 struct ns83820 *dev = PRIV(ndev);
1087 u32 free_idx, cmdsts, extsts;
1088 int nr_free, nr_frags;
1089 unsigned tx_done_idx, last_idx;
1090 dma_addr_t buf;
1091 unsigned len;
1092 skb_frag_t *frag;
1093 int stopped = 0;
1094 int do_intr = 0;
1095 volatile __le32 *first_desc;
1096
1097 dprintk("ns83820_hard_start_xmit\n");
1098
1099 nr_frags = skb_shinfo(skb)->nr_frags;
1100 again:
1101 if (unlikely(dev->CFG_cache & CFG_LNKSTS)) {
1102 netif_stop_queue(ndev);
1103 if (unlikely(dev->CFG_cache & CFG_LNKSTS))
1104 return 1;
1105 netif_start_queue(ndev);
1106 }
1107
1108 last_idx = free_idx = dev->tx_free_idx;
1109 tx_done_idx = dev->tx_done_idx;
1110 nr_free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC;
1111 nr_free -= 1;
1112 if (nr_free <= nr_frags) {
1113 dprintk("stop_queue - not enough(%p)\n", ndev);
1114 netif_stop_queue(ndev);
1115
1116 /* Check again: we may have raced with a tx done irq */
1117 if (dev->tx_done_idx != tx_done_idx) {
1118 dprintk("restart queue(%p)\n", ndev);
1119 netif_start_queue(ndev);
1120 goto again;
1121 }
1122 return 1;
1123 }
1124
1125 if (free_idx == dev->tx_intr_idx) {
1126 do_intr = 1;
1127 dev->tx_intr_idx = (dev->tx_intr_idx + NR_TX_DESC/4) % NR_TX_DESC;
1128 }
1129
1130 nr_free -= nr_frags;
1131 if (nr_free < MIN_TX_DESC_FREE) {
1132 dprintk("stop_queue - last entry(%p)\n", ndev);
1133 netif_stop_queue(ndev);
1134 stopped = 1;
1135 }
1136
1137 frag = skb_shinfo(skb)->frags;
1138 if (!nr_frags)
1139 frag = NULL;
1140 extsts = 0;
1141 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1142 extsts |= EXTSTS_IPPKT;
1143 if (IPPROTO_TCP == ip_hdr(skb)->protocol)
1144 extsts |= EXTSTS_TCPPKT;
1145 else if (IPPROTO_UDP == ip_hdr(skb)->protocol)
1146 extsts |= EXTSTS_UDPPKT;
1147 }
1148
1149 #ifdef NS83820_VLAN_ACCEL_SUPPORT
1150 if(vlan_tx_tag_present(skb)) {
1151 /* fetch the vlan tag info out of the
1152 * ancilliary data if the vlan code
1153 * is using hw vlan acceleration
1154 */
1155 short tag = vlan_tx_tag_get(skb);
1156 extsts |= (EXTSTS_VPKT | htons(tag));
1157 }
1158 #endif
1159
1160 len = skb->len;
1161 if (nr_frags)
1162 len -= skb->data_len;
1163 buf = pci_map_single(dev->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
1164
1165 first_desc = dev->tx_descs + (free_idx * DESC_SIZE);
1166
1167 for (;;) {
1168 volatile __le32 *desc = dev->tx_descs + (free_idx * DESC_SIZE);
1169
1170 dprintk("frag[%3u]: %4u @ 0x%08Lx\n", free_idx, len,
1171 (unsigned long long)buf);
1172 last_idx = free_idx;
1173 free_idx = (free_idx + 1) % NR_TX_DESC;
1174 desc[DESC_LINK] = cpu_to_le32(dev->tx_phy_descs + (free_idx * DESC_SIZE * 4));
1175 desc_addr_set(desc + DESC_BUFPTR, buf);
1176 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
1177
1178 cmdsts = ((nr_frags) ? CMDSTS_MORE : do_intr ? CMDSTS_INTR : 0);
1179 cmdsts |= (desc == first_desc) ? 0 : CMDSTS_OWN;
1180 cmdsts |= len;
1181 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
1182
1183 if (!nr_frags)
1184 break;
1185
1186 buf = pci_map_page(dev->pci_dev, frag->page,
1187 frag->page_offset,
1188 frag->size, PCI_DMA_TODEVICE);
1189 dprintk("frag: buf=%08Lx page=%08lx offset=%08lx\n",
1190 (long long)buf, (long) page_to_pfn(frag->page),
1191 frag->page_offset);
1192 len = frag->size;
1193 frag++;
1194 nr_frags--;
1195 }
1196 dprintk("done pkt\n");
1197
1198 spin_lock_irq(&dev->tx_lock);
1199 dev->tx_skbs[last_idx] = skb;
1200 first_desc[DESC_CMDSTS] |= cpu_to_le32(CMDSTS_OWN);
1201 dev->tx_free_idx = free_idx;
1202 atomic_inc(&dev->nr_tx_skbs);
1203 spin_unlock_irq(&dev->tx_lock);
1204
1205 kick_tx(dev);
1206
1207 /* Check again: we may have raced with a tx done irq */
1208 if (stopped && (dev->tx_done_idx != tx_done_idx) && start_tx_okay(dev))
1209 netif_start_queue(ndev);
1210
1211 /* set the transmit start time to catch transmit timeouts */
1212 ndev->trans_start = jiffies;
1213 return 0;
1214 }
1215
1216 static void ns83820_update_stats(struct ns83820 *dev)
1217 {
1218 u8 __iomem *base = dev->base;
1219
1220 /* the DP83820 will freeze counters, so we need to read all of them */
1221 dev->stats.rx_errors += readl(base + 0x60) & 0xffff;
1222 dev->stats.rx_crc_errors += readl(base + 0x64) & 0xffff;
1223 dev->stats.rx_missed_errors += readl(base + 0x68) & 0xffff;
1224 dev->stats.rx_frame_errors += readl(base + 0x6c) & 0xffff;
1225 /*dev->stats.rx_symbol_errors +=*/ readl(base + 0x70);
1226 dev->stats.rx_length_errors += readl(base + 0x74) & 0xffff;
1227 dev->stats.rx_length_errors += readl(base + 0x78) & 0xffff;
1228 /*dev->stats.rx_badopcode_errors += */ readl(base + 0x7c);
1229 /*dev->stats.rx_pause_count += */ readl(base + 0x80);
1230 /*dev->stats.tx_pause_count += */ readl(base + 0x84);
1231 dev->stats.tx_carrier_errors += readl(base + 0x88) & 0xff;
1232 }
1233
1234 static struct net_device_stats *ns83820_get_stats(struct net_device *ndev)
1235 {
1236 struct ns83820 *dev = PRIV(ndev);
1237
1238 /* somewhat overkill */
1239 spin_lock_irq(&dev->misc_lock);
1240 ns83820_update_stats(dev);
1241 spin_unlock_irq(&dev->misc_lock);
1242
1243 return &dev->stats;
1244 }
1245
1246 /* Let ethtool retrieve info */
1247 static int ns83820_get_settings(struct net_device *ndev,
1248 struct ethtool_cmd *cmd)
1249 {
1250 struct ns83820 *dev = PRIV(ndev);
1251 u32 cfg, tanar, tbicr;
1252 int have_optical = 0;
1253 int fullduplex = 0;
1254
1255 /*
1256 * Here's the list of available ethtool commands from other drivers:
1257 * cmd->advertising =
1258 * cmd->speed =
1259 * cmd->duplex =
1260 * cmd->port = 0;
1261 * cmd->phy_address =
1262 * cmd->transceiver = 0;
1263 * cmd->autoneg =
1264 * cmd->maxtxpkt = 0;
1265 * cmd->maxrxpkt = 0;
1266 */
1267
1268 /* read current configuration */
1269 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1270 tanar = readl(dev->base + TANAR);
1271 tbicr = readl(dev->base + TBICR);
1272
1273 if (dev->CFG_cache & CFG_TBI_EN) {
1274 /* we have an optical interface */
1275 have_optical = 1;
1276 fullduplex = (cfg & CFG_DUPSTS) ? 1 : 0;
1277
1278 } else {
1279 /* We have copper */
1280 fullduplex = (cfg & CFG_DUPSTS) ? 1 : 0;
1281 }
1282
1283 cmd->supported = SUPPORTED_Autoneg;
1284
1285 /* we have optical interface */
1286 if (dev->CFG_cache & CFG_TBI_EN) {
1287 cmd->supported |= SUPPORTED_1000baseT_Half |
1288 SUPPORTED_1000baseT_Full |
1289 SUPPORTED_FIBRE;
1290 cmd->port = PORT_FIBRE;
1291 } /* TODO: else copper related support */
1292
1293 cmd->duplex = fullduplex ? DUPLEX_FULL : DUPLEX_HALF;
1294 switch (cfg / CFG_SPDSTS0 & 3) {
1295 case 2:
1296 cmd->speed = SPEED_1000;
1297 break;
1298 case 1:
1299 cmd->speed = SPEED_100;
1300 break;
1301 default:
1302 cmd->speed = SPEED_10;
1303 break;
1304 }
1305 cmd->autoneg = (tbicr & TBICR_MR_AN_ENABLE) ? 1: 0;
1306 return 0;
1307 }
1308
1309 /* Let ethool change settings*/
1310 static int ns83820_set_settings(struct net_device *ndev,
1311 struct ethtool_cmd *cmd)
1312 {
1313 struct ns83820 *dev = PRIV(ndev);
1314 u32 cfg, tanar;
1315 int have_optical = 0;
1316 int fullduplex = 0;
1317
1318 /* read current configuration */
1319 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1320 tanar = readl(dev->base + TANAR);
1321
1322 if (dev->CFG_cache & CFG_TBI_EN) {
1323 /* we have optical */
1324 have_optical = 1;
1325 fullduplex = (tanar & TANAR_FULL_DUP);
1326
1327 } else {
1328 /* we have copper */
1329 fullduplex = cfg & CFG_DUPSTS;
1330 }
1331
1332 spin_lock_irq(&dev->misc_lock);
1333 spin_lock(&dev->tx_lock);
1334
1335 /* Set duplex */
1336 if (cmd->duplex != fullduplex) {
1337 if (have_optical) {
1338 /*set full duplex*/
1339 if (cmd->duplex == DUPLEX_FULL) {
1340 /* force full duplex */
1341 writel(readl(dev->base + TXCFG)
1342 | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP,
1343 dev->base + TXCFG);
1344 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
1345 dev->base + RXCFG);
1346 /* Light up full duplex LED */
1347 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
1348 dev->base + GPIOR);
1349 } else {
1350 /*TODO: set half duplex */
1351 }
1352
1353 } else {
1354 /*we have copper*/
1355 /* TODO: Set duplex for copper cards */
1356 }
1357 printk(KERN_INFO "%s: Duplex set via ethtool\n",
1358 ndev->name);
1359 }
1360
1361 /* Set autonegotiation */
1362 if (1) {
1363 if (cmd->autoneg == AUTONEG_ENABLE) {
1364 /* restart auto negotiation */
1365 writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
1366 dev->base + TBICR);
1367 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
1368 dev->linkstate = LINK_AUTONEGOTIATE;
1369
1370 printk(KERN_INFO "%s: autoneg enabled via ethtool\n",
1371 ndev->name);
1372 } else {
1373 /* disable auto negotiation */
1374 writel(0x00000000, dev->base + TBICR);
1375 }
1376
1377 printk(KERN_INFO "%s: autoneg %s via ethtool\n", ndev->name,
1378 cmd->autoneg ? "ENABLED" : "DISABLED");
1379 }
1380
1381 phy_intr(ndev);
1382 spin_unlock(&dev->tx_lock);
1383 spin_unlock_irq(&dev->misc_lock);
1384
1385 return 0;
1386 }
1387 /* end ethtool get/set support -df */
1388
1389 static void ns83820_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo *info)
1390 {
1391 struct ns83820 *dev = PRIV(ndev);
1392 strcpy(info->driver, "ns83820");
1393 strcpy(info->version, VERSION);
1394 strcpy(info->bus_info, pci_name(dev->pci_dev));
1395 }
1396
1397 static u32 ns83820_get_link(struct net_device *ndev)
1398 {
1399 struct ns83820 *dev = PRIV(ndev);
1400 u32 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1401 return cfg & CFG_LNKSTS ? 1 : 0;
1402 }
1403
1404 static const struct ethtool_ops ops = {
1405 .get_settings = ns83820_get_settings,
1406 .set_settings = ns83820_set_settings,
1407 .get_drvinfo = ns83820_get_drvinfo,
1408 .get_link = ns83820_get_link
1409 };
1410
1411 /* this function is called in irq context from the ISR */
1412 static void ns83820_mib_isr(struct ns83820 *dev)
1413 {
1414 unsigned long flags;
1415 spin_lock_irqsave(&dev->misc_lock, flags);
1416 ns83820_update_stats(dev);
1417 spin_unlock_irqrestore(&dev->misc_lock, flags);
1418 }
1419
1420 static void ns83820_do_isr(struct net_device *ndev, u32 isr);
1421 static irqreturn_t ns83820_irq(int foo, void *data)
1422 {
1423 struct net_device *ndev = data;
1424 struct ns83820 *dev = PRIV(ndev);
1425 u32 isr;
1426 dprintk("ns83820_irq(%p)\n", ndev);
1427
1428 dev->ihr = 0;
1429
1430 isr = readl(dev->base + ISR);
1431 dprintk("irq: %08x\n", isr);
1432 ns83820_do_isr(ndev, isr);
1433 return IRQ_HANDLED;
1434 }
1435
1436 static void ns83820_do_isr(struct net_device *ndev, u32 isr)
1437 {
1438 struct ns83820 *dev = PRIV(ndev);
1439 unsigned long flags;
1440
1441 #ifdef DEBUG
1442 if (isr & ~(ISR_PHY | ISR_RXDESC | ISR_RXEARLY | ISR_RXOK | ISR_RXERR | ISR_TXIDLE | ISR_TXOK | ISR_TXDESC))
1443 Dprintk("odd isr? 0x%08x\n", isr);
1444 #endif
1445
1446 if (ISR_RXIDLE & isr) {
1447 dev->rx_info.idle = 1;
1448 Dprintk("oh dear, we are idle\n");
1449 ns83820_rx_kick(ndev);
1450 }
1451
1452 if ((ISR_RXDESC | ISR_RXOK) & isr) {
1453 prefetch(dev->rx_info.next_rx_desc);
1454
1455 spin_lock_irqsave(&dev->misc_lock, flags);
1456 dev->IMR_cache &= ~(ISR_RXDESC | ISR_RXOK);
1457 writel(dev->IMR_cache, dev->base + IMR);
1458 spin_unlock_irqrestore(&dev->misc_lock, flags);
1459
1460 tasklet_schedule(&dev->rx_tasklet);
1461 //rx_irq(ndev);
1462 //writel(4, dev->base + IHR);
1463 }
1464
1465 if ((ISR_RXIDLE | ISR_RXORN | ISR_RXDESC | ISR_RXOK | ISR_RXERR) & isr)
1466 ns83820_rx_kick(ndev);
1467
1468 if (unlikely(ISR_RXSOVR & isr)) {
1469 //printk("overrun: rxsovr\n");
1470 dev->stats.rx_fifo_errors ++;
1471 }
1472
1473 if (unlikely(ISR_RXORN & isr)) {
1474 //printk("overrun: rxorn\n");
1475 dev->stats.rx_fifo_errors ++;
1476 }
1477
1478 if ((ISR_RXRCMP & isr) && dev->rx_info.up)
1479 writel(CR_RXE, dev->base + CR);
1480
1481 if (ISR_TXIDLE & isr) {
1482 u32 txdp;
1483 txdp = readl(dev->base + TXDP);
1484 dprintk("txdp: %08x\n", txdp);
1485 txdp -= dev->tx_phy_descs;
1486 dev->tx_idx = txdp / (DESC_SIZE * 4);
1487 if (dev->tx_idx >= NR_TX_DESC) {
1488 printk(KERN_ALERT "%s: BUG -- txdp out of range\n", ndev->name);
1489 dev->tx_idx = 0;
1490 }
1491 /* The may have been a race between a pci originated read
1492 * and the descriptor update from the cpu. Just in case,
1493 * kick the transmitter if the hardware thinks it is on a
1494 * different descriptor than we are.
1495 */
1496 if (dev->tx_idx != dev->tx_free_idx)
1497 kick_tx(dev);
1498 }
1499
1500 /* Defer tx ring processing until more than a minimum amount of
1501 * work has accumulated
1502 */
1503 if ((ISR_TXDESC | ISR_TXIDLE | ISR_TXOK | ISR_TXERR) & isr) {
1504 spin_lock_irqsave(&dev->tx_lock, flags);
1505 do_tx_done(ndev);
1506 spin_unlock_irqrestore(&dev->tx_lock, flags);
1507
1508 /* Disable TxOk if there are no outstanding tx packets.
1509 */
1510 if ((dev->tx_done_idx == dev->tx_free_idx) &&
1511 (dev->IMR_cache & ISR_TXOK)) {
1512 spin_lock_irqsave(&dev->misc_lock, flags);
1513 dev->IMR_cache &= ~ISR_TXOK;
1514 writel(dev->IMR_cache, dev->base + IMR);
1515 spin_unlock_irqrestore(&dev->misc_lock, flags);
1516 }
1517 }
1518
1519 /* The TxIdle interrupt can come in before the transmit has
1520 * completed. Normally we reap packets off of the combination
1521 * of TxDesc and TxIdle and leave TxOk disabled (since it
1522 * occurs on every packet), but when no further irqs of this
1523 * nature are expected, we must enable TxOk.
1524 */
1525 if ((ISR_TXIDLE & isr) && (dev->tx_done_idx != dev->tx_free_idx)) {
1526 spin_lock_irqsave(&dev->misc_lock, flags);
1527 dev->IMR_cache |= ISR_TXOK;
1528 writel(dev->IMR_cache, dev->base + IMR);
1529 spin_unlock_irqrestore(&dev->misc_lock, flags);
1530 }
1531
1532 /* MIB interrupt: one of the statistics counters is about to overflow */
1533 if (unlikely(ISR_MIB & isr))
1534 ns83820_mib_isr(dev);
1535
1536 /* PHY: Link up/down/negotiation state change */
1537 if (unlikely(ISR_PHY & isr))
1538 phy_intr(ndev);
1539
1540 #if 0 /* Still working on the interrupt mitigation strategy */
1541 if (dev->ihr)
1542 writel(dev->ihr, dev->base + IHR);
1543 #endif
1544 }
1545
1546 static void ns83820_do_reset(struct ns83820 *dev, u32 which)
1547 {
1548 Dprintk("resetting chip...\n");
1549 writel(which, dev->base + CR);
1550 do {
1551 schedule();
1552 } while (readl(dev->base + CR) & which);
1553 Dprintk("okay!\n");
1554 }
1555
1556 static int ns83820_stop(struct net_device *ndev)
1557 {
1558 struct ns83820 *dev = PRIV(ndev);
1559
1560 /* FIXME: protect against interrupt handler? */
1561 del_timer_sync(&dev->tx_watchdog);
1562
1563 /* disable interrupts */
1564 writel(0, dev->base + IMR);
1565 writel(0, dev->base + IER);
1566 readl(dev->base + IER);
1567
1568 dev->rx_info.up = 0;
1569 synchronize_irq(dev->pci_dev->irq);
1570
1571 ns83820_do_reset(dev, CR_RST);
1572
1573 synchronize_irq(dev->pci_dev->irq);
1574
1575 spin_lock_irq(&dev->misc_lock);
1576 dev->IMR_cache &= ~(ISR_TXURN | ISR_TXIDLE | ISR_TXERR | ISR_TXDESC | ISR_TXOK);
1577 spin_unlock_irq(&dev->misc_lock);
1578
1579 ns83820_cleanup_rx(dev);
1580 ns83820_cleanup_tx(dev);
1581
1582 return 0;
1583 }
1584
1585 static void ns83820_tx_timeout(struct net_device *ndev)
1586 {
1587 struct ns83820 *dev = PRIV(ndev);
1588 u32 tx_done_idx;
1589 __le32 *desc;
1590 unsigned long flags;
1591
1592 spin_lock_irqsave(&dev->tx_lock, flags);
1593
1594 tx_done_idx = dev->tx_done_idx;
1595 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1596
1597 printk(KERN_INFO "%s: tx_timeout: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1598 ndev->name,
1599 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1600
1601 #if defined(DEBUG)
1602 {
1603 u32 isr;
1604 isr = readl(dev->base + ISR);
1605 printk("irq: %08x imr: %08x\n", isr, dev->IMR_cache);
1606 ns83820_do_isr(ndev, isr);
1607 }
1608 #endif
1609
1610 do_tx_done(ndev);
1611
1612 tx_done_idx = dev->tx_done_idx;
1613 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1614
1615 printk(KERN_INFO "%s: after: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1616 ndev->name,
1617 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1618
1619 spin_unlock_irqrestore(&dev->tx_lock, flags);
1620 }
1621
1622 static void ns83820_tx_watch(unsigned long data)
1623 {
1624 struct net_device *ndev = (void *)data;
1625 struct ns83820 *dev = PRIV(ndev);
1626
1627 #if defined(DEBUG)
1628 printk("ns83820_tx_watch: %u %u %d\n",
1629 dev->tx_done_idx, dev->tx_free_idx, atomic_read(&dev->nr_tx_skbs)
1630 );
1631 #endif
1632
1633 if (time_after(jiffies, ndev->trans_start + 1*HZ) &&
1634 dev->tx_done_idx != dev->tx_free_idx) {
1635 printk(KERN_DEBUG "%s: ns83820_tx_watch: %u %u %d\n",
1636 ndev->name,
1637 dev->tx_done_idx, dev->tx_free_idx,
1638 atomic_read(&dev->nr_tx_skbs));
1639 ns83820_tx_timeout(ndev);
1640 }
1641
1642 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1643 }
1644
1645 static int ns83820_open(struct net_device *ndev)
1646 {
1647 struct ns83820 *dev = PRIV(ndev);
1648 unsigned i;
1649 u32 desc;
1650 int ret;
1651
1652 dprintk("ns83820_open\n");
1653
1654 writel(0, dev->base + PQCR);
1655
1656 ret = ns83820_setup_rx(ndev);
1657 if (ret)
1658 goto failed;
1659
1660 memset(dev->tx_descs, 0, 4 * NR_TX_DESC * DESC_SIZE);
1661 for (i=0; i<NR_TX_DESC; i++) {
1662 dev->tx_descs[(i * DESC_SIZE) + DESC_LINK]
1663 = cpu_to_le32(
1664 dev->tx_phy_descs
1665 + ((i+1) % NR_TX_DESC) * DESC_SIZE * 4);
1666 }
1667
1668 dev->tx_idx = 0;
1669 dev->tx_done_idx = 0;
1670 desc = dev->tx_phy_descs;
1671 writel(0, dev->base + TXDP_HI);
1672 writel(desc, dev->base + TXDP);
1673
1674 init_timer(&dev->tx_watchdog);
1675 dev->tx_watchdog.data = (unsigned long)ndev;
1676 dev->tx_watchdog.function = ns83820_tx_watch;
1677 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1678
1679 netif_start_queue(ndev); /* FIXME: wait for phy to come up */
1680
1681 return 0;
1682
1683 failed:
1684 ns83820_stop(ndev);
1685 return ret;
1686 }
1687
1688 static void ns83820_getmac(struct ns83820 *dev, u8 *mac)
1689 {
1690 unsigned i;
1691 for (i=0; i<3; i++) {
1692 u32 data;
1693
1694 /* Read from the perfect match memory: this is loaded by
1695 * the chip from the EEPROM via the EELOAD self test.
1696 */
1697 writel(i*2, dev->base + RFCR);
1698 data = readl(dev->base + RFDR);
1699
1700 *mac++ = data;
1701 *mac++ = data >> 8;
1702 }
1703 }
1704
1705 static int ns83820_change_mtu(struct net_device *ndev, int new_mtu)
1706 {
1707 if (new_mtu > RX_BUF_SIZE)
1708 return -EINVAL;
1709 ndev->mtu = new_mtu;
1710 return 0;
1711 }
1712
1713 static void ns83820_set_multicast(struct net_device *ndev)
1714 {
1715 struct ns83820 *dev = PRIV(ndev);
1716 u8 __iomem *rfcr = dev->base + RFCR;
1717 u32 and_mask = 0xffffffff;
1718 u32 or_mask = 0;
1719 u32 val;
1720
1721 if (ndev->flags & IFF_PROMISC)
1722 or_mask |= RFCR_AAU | RFCR_AAM;
1723 else
1724 and_mask &= ~(RFCR_AAU | RFCR_AAM);
1725
1726 if (ndev->flags & IFF_ALLMULTI || ndev->mc_count)
1727 or_mask |= RFCR_AAM;
1728 else
1729 and_mask &= ~RFCR_AAM;
1730
1731 spin_lock_irq(&dev->misc_lock);
1732 val = (readl(rfcr) & and_mask) | or_mask;
1733 /* Ramit : RFCR Write Fix doc says RFEN must be 0 modify other bits */
1734 writel(val & ~RFCR_RFEN, rfcr);
1735 writel(val, rfcr);
1736 spin_unlock_irq(&dev->misc_lock);
1737 }
1738
1739 static void ns83820_run_bist(struct net_device *ndev, const char *name, u32 enable, u32 done, u32 fail)
1740 {
1741 struct ns83820 *dev = PRIV(ndev);
1742 int timed_out = 0;
1743 unsigned long start;
1744 u32 status;
1745 int loops = 0;
1746
1747 dprintk("%s: start %s\n", ndev->name, name);
1748
1749 start = jiffies;
1750
1751 writel(enable, dev->base + PTSCR);
1752 for (;;) {
1753 loops++;
1754 status = readl(dev->base + PTSCR);
1755 if (!(status & enable))
1756 break;
1757 if (status & done)
1758 break;
1759 if (status & fail)
1760 break;
1761 if (time_after_eq(jiffies, start + HZ)) {
1762 timed_out = 1;
1763 break;
1764 }
1765 schedule_timeout_uninterruptible(1);
1766 }
1767
1768 if (status & fail)
1769 printk(KERN_INFO "%s: %s failed! (0x%08x & 0x%08x)\n",
1770 ndev->name, name, status, fail);
1771 else if (timed_out)
1772 printk(KERN_INFO "%s: run_bist %s timed out! (%08x)\n",
1773 ndev->name, name, status);
1774
1775 dprintk("%s: done %s in %d loops\n", ndev->name, name, loops);
1776 }
1777
1778 #ifdef PHY_CODE_IS_FINISHED
1779 static void ns83820_mii_write_bit(struct ns83820 *dev, int bit)
1780 {
1781 /* drive MDC low */
1782 dev->MEAR_cache &= ~MEAR_MDC;
1783 writel(dev->MEAR_cache, dev->base + MEAR);
1784 readl(dev->base + MEAR);
1785
1786 /* enable output, set bit */
1787 dev->MEAR_cache |= MEAR_MDDIR;
1788 if (bit)
1789 dev->MEAR_cache |= MEAR_MDIO;
1790 else
1791 dev->MEAR_cache &= ~MEAR_MDIO;
1792
1793 /* set the output bit */
1794 writel(dev->MEAR_cache, dev->base + MEAR);
1795 readl(dev->base + MEAR);
1796
1797 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1798 udelay(1);
1799
1800 /* drive MDC high causing the data bit to be latched */
1801 dev->MEAR_cache |= MEAR_MDC;
1802 writel(dev->MEAR_cache, dev->base + MEAR);
1803 readl(dev->base + MEAR);
1804
1805 /* Wait again... */
1806 udelay(1);
1807 }
1808
1809 static int ns83820_mii_read_bit(struct ns83820 *dev)
1810 {
1811 int bit;
1812
1813 /* drive MDC low, disable output */
1814 dev->MEAR_cache &= ~MEAR_MDC;
1815 dev->MEAR_cache &= ~MEAR_MDDIR;
1816 writel(dev->MEAR_cache, dev->base + MEAR);
1817 readl(dev->base + MEAR);
1818
1819 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1820 udelay(1);
1821
1822 /* drive MDC high causing the data bit to be latched */
1823 bit = (readl(dev->base + MEAR) & MEAR_MDIO) ? 1 : 0;
1824 dev->MEAR_cache |= MEAR_MDC;
1825 writel(dev->MEAR_cache, dev->base + MEAR);
1826
1827 /* Wait again... */
1828 udelay(1);
1829
1830 return bit;
1831 }
1832
1833 static unsigned ns83820_mii_read_reg(struct ns83820 *dev, unsigned phy, unsigned reg)
1834 {
1835 unsigned data = 0;
1836 int i;
1837
1838 /* read some garbage so that we eventually sync up */
1839 for (i=0; i<64; i++)
1840 ns83820_mii_read_bit(dev);
1841
1842 ns83820_mii_write_bit(dev, 0); /* start */
1843 ns83820_mii_write_bit(dev, 1);
1844 ns83820_mii_write_bit(dev, 1); /* opcode read */
1845 ns83820_mii_write_bit(dev, 0);
1846
1847 /* write out the phy address: 5 bits, msb first */
1848 for (i=0; i<5; i++)
1849 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1850
1851 /* write out the register address, 5 bits, msb first */
1852 for (i=0; i<5; i++)
1853 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1854
1855 ns83820_mii_read_bit(dev); /* turn around cycles */
1856 ns83820_mii_read_bit(dev);
1857
1858 /* read in the register data, 16 bits msb first */
1859 for (i=0; i<16; i++) {
1860 data <<= 1;
1861 data |= ns83820_mii_read_bit(dev);
1862 }
1863
1864 return data;
1865 }
1866
1867 static unsigned ns83820_mii_write_reg(struct ns83820 *dev, unsigned phy, unsigned reg, unsigned data)
1868 {
1869 int i;
1870
1871 /* read some garbage so that we eventually sync up */
1872 for (i=0; i<64; i++)
1873 ns83820_mii_read_bit(dev);
1874
1875 ns83820_mii_write_bit(dev, 0); /* start */
1876 ns83820_mii_write_bit(dev, 1);
1877 ns83820_mii_write_bit(dev, 0); /* opcode read */
1878 ns83820_mii_write_bit(dev, 1);
1879
1880 /* write out the phy address: 5 bits, msb first */
1881 for (i=0; i<5; i++)
1882 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1883
1884 /* write out the register address, 5 bits, msb first */
1885 for (i=0; i<5; i++)
1886 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1887
1888 ns83820_mii_read_bit(dev); /* turn around cycles */
1889 ns83820_mii_read_bit(dev);
1890
1891 /* read in the register data, 16 bits msb first */
1892 for (i=0; i<16; i++)
1893 ns83820_mii_write_bit(dev, (data >> (15 - i)) & 1);
1894
1895 return data;
1896 }
1897
1898 static void ns83820_probe_phy(struct net_device *ndev)
1899 {
1900 struct ns83820 *dev = PRIV(ndev);
1901 static int first;
1902 int i;
1903 #define MII_PHYIDR1 0x02
1904 #define MII_PHYIDR2 0x03
1905
1906 #if 0
1907 if (!first) {
1908 unsigned tmp;
1909 ns83820_mii_read_reg(dev, 1, 0x09);
1910 ns83820_mii_write_reg(dev, 1, 0x10, 0x0d3e);
1911
1912 tmp = ns83820_mii_read_reg(dev, 1, 0x00);
1913 ns83820_mii_write_reg(dev, 1, 0x00, tmp | 0x8000);
1914 udelay(1300);
1915 ns83820_mii_read_reg(dev, 1, 0x09);
1916 }
1917 #endif
1918 first = 1;
1919
1920 for (i=1; i<2; i++) {
1921 int j;
1922 unsigned a, b;
1923 a = ns83820_mii_read_reg(dev, i, MII_PHYIDR1);
1924 b = ns83820_mii_read_reg(dev, i, MII_PHYIDR2);
1925
1926 //printk("%s: phy %d: 0x%04x 0x%04x\n",
1927 // ndev->name, i, a, b);
1928
1929 for (j=0; j<0x16; j+=4) {
1930 dprintk("%s: [0x%02x] %04x %04x %04x %04x\n",
1931 ndev->name, j,
1932 ns83820_mii_read_reg(dev, i, 0 + j),
1933 ns83820_mii_read_reg(dev, i, 1 + j),
1934 ns83820_mii_read_reg(dev, i, 2 + j),
1935 ns83820_mii_read_reg(dev, i, 3 + j)
1936 );
1937 }
1938 }
1939 {
1940 unsigned a, b;
1941 /* read firmware version: memory addr is 0x8402 and 0x8403 */
1942 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1943 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1944 a = ns83820_mii_read_reg(dev, 1, 0x1d);
1945
1946 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1947 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1948 b = ns83820_mii_read_reg(dev, 1, 0x1d);
1949 dprintk("version: 0x%04x 0x%04x\n", a, b);
1950 }
1951 }
1952 #endif
1953
1954 static int __devinit ns83820_init_one(struct pci_dev *pci_dev, const struct pci_device_id *id)
1955 {
1956 struct net_device *ndev;
1957 struct ns83820 *dev;
1958 long addr;
1959 int err;
1960 int using_dac = 0;
1961 DECLARE_MAC_BUF(mac);
1962
1963 /* See if we can set the dma mask early on; failure is fatal. */
1964 if (sizeof(dma_addr_t) == 8 &&
1965 !pci_set_dma_mask(pci_dev, DMA_64BIT_MASK)) {
1966 using_dac = 1;
1967 } else if (!pci_set_dma_mask(pci_dev, DMA_32BIT_MASK)) {
1968 using_dac = 0;
1969 } else {
1970 dev_warn(&pci_dev->dev, "pci_set_dma_mask failed!\n");
1971 return -ENODEV;
1972 }
1973
1974 ndev = alloc_etherdev(sizeof(struct ns83820));
1975 dev = PRIV(ndev);
1976
1977 err = -ENOMEM;
1978 if (!dev)
1979 goto out;
1980
1981 dev->ndev = ndev;
1982
1983 spin_lock_init(&dev->rx_info.lock);
1984 spin_lock_init(&dev->tx_lock);
1985 spin_lock_init(&dev->misc_lock);
1986 dev->pci_dev = pci_dev;
1987
1988 SET_NETDEV_DEV(ndev, &pci_dev->dev);
1989
1990 INIT_WORK(&dev->tq_refill, queue_refill);
1991 tasklet_init(&dev->rx_tasklet, rx_action, (unsigned long)ndev);
1992
1993 err = pci_enable_device(pci_dev);
1994 if (err) {
1995 dev_info(&pci_dev->dev, "pci_enable_dev failed: %d\n", err);
1996 goto out_free;
1997 }
1998
1999 pci_set_master(pci_dev);
2000 addr = pci_resource_start(pci_dev, 1);
2001 dev->base = ioremap_nocache(addr, PAGE_SIZE);
2002 dev->tx_descs = pci_alloc_consistent(pci_dev,
2003 4 * DESC_SIZE * NR_TX_DESC, &dev->tx_phy_descs);
2004 dev->rx_info.descs = pci_alloc_consistent(pci_dev,
2005 4 * DESC_SIZE * NR_RX_DESC, &dev->rx_info.phy_descs);
2006 err = -ENOMEM;
2007 if (!dev->base || !dev->tx_descs || !dev->rx_info.descs)
2008 goto out_disable;
2009
2010 dprintk("%p: %08lx %p: %08lx\n",
2011 dev->tx_descs, (long)dev->tx_phy_descs,
2012 dev->rx_info.descs, (long)dev->rx_info.phy_descs);
2013
2014 /* disable interrupts */
2015 writel(0, dev->base + IMR);
2016 writel(0, dev->base + IER);
2017 readl(dev->base + IER);
2018
2019 dev->IMR_cache = 0;
2020
2021 err = request_irq(pci_dev->irq, ns83820_irq, IRQF_SHARED,
2022 DRV_NAME, ndev);
2023 if (err) {
2024 dev_info(&pci_dev->dev, "unable to register irq %d, err %d\n",
2025 pci_dev->irq, err);
2026 goto out_disable;
2027 }
2028
2029 /*
2030 * FIXME: we are holding rtnl_lock() over obscenely long area only
2031 * because some of the setup code uses dev->name. It's Wrong(tm) -
2032 * we should be using driver-specific names for all that stuff.
2033 * For now that will do, but we really need to come back and kill
2034 * most of the dev_alloc_name() users later.
2035 */
2036 rtnl_lock();
2037 err = dev_alloc_name(ndev, ndev->name);
2038 if (err < 0) {
2039 dev_info(&pci_dev->dev, "unable to get netdev name: %d\n", err);
2040 goto out_free_irq;
2041 }
2042
2043 printk("%s: ns83820.c: 0x22c: %08x, subsystem: %04x:%04x\n",
2044 ndev->name, le32_to_cpu(readl(dev->base + 0x22c)),
2045 pci_dev->subsystem_vendor, pci_dev->subsystem_device);
2046
2047 ndev->open = ns83820_open;
2048 ndev->stop = ns83820_stop;
2049 ndev->hard_start_xmit = ns83820_hard_start_xmit;
2050 ndev->get_stats = ns83820_get_stats;
2051 ndev->change_mtu = ns83820_change_mtu;
2052 ndev->set_multicast_list = ns83820_set_multicast;
2053 SET_ETHTOOL_OPS(ndev, &ops);
2054 ndev->tx_timeout = ns83820_tx_timeout;
2055 ndev->watchdog_timeo = 5 * HZ;
2056 pci_set_drvdata(pci_dev, ndev);
2057
2058 ns83820_do_reset(dev, CR_RST);
2059
2060 /* Must reset the ram bist before running it */
2061 writel(PTSCR_RBIST_RST, dev->base + PTSCR);
2062 ns83820_run_bist(ndev, "sram bist", PTSCR_RBIST_EN,
2063 PTSCR_RBIST_DONE, PTSCR_RBIST_FAIL);
2064 ns83820_run_bist(ndev, "eeprom bist", PTSCR_EEBIST_EN, 0,
2065 PTSCR_EEBIST_FAIL);
2066 ns83820_run_bist(ndev, "eeprom load", PTSCR_EELOAD_EN, 0, 0);
2067
2068 /* I love config registers */
2069 dev->CFG_cache = readl(dev->base + CFG);
2070
2071 if ((dev->CFG_cache & CFG_PCI64_DET)) {
2072 printk(KERN_INFO "%s: detected 64 bit PCI data bus.\n",
2073 ndev->name);
2074 /*dev->CFG_cache |= CFG_DATA64_EN;*/
2075 if (!(dev->CFG_cache & CFG_DATA64_EN))
2076 printk(KERN_INFO "%s: EEPROM did not enable 64 bit bus. Disabled.\n",
2077 ndev->name);
2078 } else
2079 dev->CFG_cache &= ~(CFG_DATA64_EN);
2080
2081 dev->CFG_cache &= (CFG_TBI_EN | CFG_MRM_DIS | CFG_MWI_DIS |
2082 CFG_T64ADDR | CFG_DATA64_EN | CFG_EXT_125 |
2083 CFG_M64ADDR);
2084 dev->CFG_cache |= CFG_PINT_DUPSTS | CFG_PINT_LNKSTS | CFG_PINT_SPDSTS |
2085 CFG_EXTSTS_EN | CFG_EXD | CFG_PESEL;
2086 dev->CFG_cache |= CFG_REQALG;
2087 dev->CFG_cache |= CFG_POW;
2088 dev->CFG_cache |= CFG_TMRTEST;
2089
2090 /* When compiled with 64 bit addressing, we must always enable
2091 * the 64 bit descriptor format.
2092 */
2093 if (sizeof(dma_addr_t) == 8)
2094 dev->CFG_cache |= CFG_M64ADDR;
2095 if (using_dac)
2096 dev->CFG_cache |= CFG_T64ADDR;
2097
2098 /* Big endian mode does not seem to do what the docs suggest */
2099 dev->CFG_cache &= ~CFG_BEM;
2100
2101 /* setup optical transceiver if we have one */
2102 if (dev->CFG_cache & CFG_TBI_EN) {
2103 printk(KERN_INFO "%s: enabling optical transceiver\n",
2104 ndev->name);
2105 writel(readl(dev->base + GPIOR) | 0x3e8, dev->base + GPIOR);
2106
2107 /* setup auto negotiation feature advertisement */
2108 writel(readl(dev->base + TANAR)
2109 | TANAR_HALF_DUP | TANAR_FULL_DUP,
2110 dev->base + TANAR);
2111
2112 /* start auto negotiation */
2113 writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
2114 dev->base + TBICR);
2115 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
2116 dev->linkstate = LINK_AUTONEGOTIATE;
2117
2118 dev->CFG_cache |= CFG_MODE_1000;
2119 }
2120
2121 writel(dev->CFG_cache, dev->base + CFG);
2122 dprintk("CFG: %08x\n", dev->CFG_cache);
2123
2124 if (reset_phy) {
2125 printk(KERN_INFO "%s: resetting phy\n", ndev->name);
2126 writel(dev->CFG_cache | CFG_PHY_RST, dev->base + CFG);
2127 msleep(10);
2128 writel(dev->CFG_cache, dev->base + CFG);
2129 }
2130
2131 #if 0 /* Huh? This sets the PCI latency register. Should be done via
2132 * the PCI layer. FIXME.
2133 */
2134 if (readl(dev->base + SRR))
2135 writel(readl(dev->base+0x20c) | 0xfe00, dev->base + 0x20c);
2136 #endif
2137
2138 /* Note! The DMA burst size interacts with packet
2139 * transmission, such that the largest packet that
2140 * can be transmitted is 8192 - FLTH - burst size.
2141 * If only the transmit fifo was larger...
2142 */
2143 /* Ramit : 1024 DMA is not a good idea, it ends up banging
2144 * some DELL and COMPAQ SMP systems */
2145 writel(TXCFG_CSI | TXCFG_HBI | TXCFG_ATP | TXCFG_MXDMA512
2146 | ((1600 / 32) * 0x100),
2147 dev->base + TXCFG);
2148
2149 /* Flush the interrupt holdoff timer */
2150 writel(0x000, dev->base + IHR);
2151 writel(0x100, dev->base + IHR);
2152 writel(0x000, dev->base + IHR);
2153
2154 /* Set Rx to full duplex, don't accept runt, errored, long or length
2155 * range errored packets. Use 512 byte DMA.
2156 */
2157 /* Ramit : 1024 DMA is not a good idea, it ends up banging
2158 * some DELL and COMPAQ SMP systems
2159 * Turn on ALP, only we are accpeting Jumbo Packets */
2160 writel(RXCFG_AEP | RXCFG_ARP | RXCFG_AIRL | RXCFG_RX_FD
2161 | RXCFG_STRIPCRC
2162 //| RXCFG_ALP
2163 | (RXCFG_MXDMA512) | 0, dev->base + RXCFG);
2164
2165 /* Disable priority queueing */
2166 writel(0, dev->base + PQCR);
2167
2168 /* Enable IP checksum validation and detetion of VLAN headers.
2169 * Note: do not set the reject options as at least the 0x102
2170 * revision of the chip does not properly accept IP fragments
2171 * at least for UDP.
2172 */
2173 /* Ramit : Be sure to turn on RXCFG_ARP if VLAN's are enabled, since
2174 * the MAC it calculates the packetsize AFTER stripping the VLAN
2175 * header, and if a VLAN Tagged packet of 64 bytes is received (like
2176 * a ping with a VLAN header) then the card, strips the 4 byte VLAN
2177 * tag and then checks the packet size, so if RXCFG_ARP is not enabled,
2178 * it discrards it!. These guys......
2179 * also turn on tag stripping if hardware acceleration is enabled
2180 */
2181 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2182 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN|VRCR_VTREN)
2183 #else
2184 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN)
2185 #endif
2186 writel(VRCR_INIT_VALUE, dev->base + VRCR);
2187
2188 /* Enable per-packet TCP/UDP/IP checksumming
2189 * and per packet vlan tag insertion if
2190 * vlan hardware acceleration is enabled
2191 */
2192 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2193 #define VTCR_INIT_VALUE (VTCR_PPCHK|VTCR_VPPTI)
2194 #else
2195 #define VTCR_INIT_VALUE VTCR_PPCHK
2196 #endif
2197 writel(VTCR_INIT_VALUE, dev->base + VTCR);
2198
2199 /* Ramit : Enable async and sync pause frames */
2200 /* writel(0, dev->base + PCR); */
2201 writel((PCR_PS_MCAST | PCR_PS_DA | PCR_PSEN | PCR_FFLO_4K |
2202 PCR_FFHI_8K | PCR_STLO_4 | PCR_STHI_8 | PCR_PAUSE_CNT),
2203 dev->base + PCR);
2204
2205 /* Disable Wake On Lan */
2206 writel(0, dev->base + WCSR);
2207
2208 ns83820_getmac(dev, ndev->dev_addr);
2209
2210 /* Yes, we support dumb IP checksum on transmit */
2211 ndev->features |= NETIF_F_SG;
2212 ndev->features |= NETIF_F_IP_CSUM;
2213
2214 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2215 /* We also support hardware vlan acceleration */
2216 ndev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2217 ndev->vlan_rx_register = ns83820_vlan_rx_register;
2218 #endif
2219
2220 if (using_dac) {
2221 printk(KERN_INFO "%s: using 64 bit addressing.\n",
2222 ndev->name);
2223 ndev->features |= NETIF_F_HIGHDMA;
2224 }
2225
2226 printk(KERN_INFO "%s: ns83820 v" VERSION ": DP83820 v%u.%u: %s io=0x%08lx irq=%d f=%s\n",
2227 ndev->name,
2228 (unsigned)readl(dev->base + SRR) >> 8,
2229 (unsigned)readl(dev->base + SRR) & 0xff,
2230 print_mac(mac, ndev->dev_addr),
2231 addr, pci_dev->irq,
2232 (ndev->features & NETIF_F_HIGHDMA) ? "h,sg" : "sg"
2233 );
2234
2235 #ifdef PHY_CODE_IS_FINISHED
2236 ns83820_probe_phy(ndev);
2237 #endif
2238
2239 err = register_netdevice(ndev);
2240 if (err) {
2241 printk(KERN_INFO "ns83820: unable to register netdev: %d\n", err);
2242 goto out_cleanup;
2243 }
2244 rtnl_unlock();
2245
2246 return 0;
2247
2248 out_cleanup:
2249 writel(0, dev->base + IMR); /* paranoia */
2250 writel(0, dev->base + IER);
2251 readl(dev->base + IER);
2252 out_free_irq:
2253 rtnl_unlock();
2254 free_irq(pci_dev->irq, ndev);
2255 out_disable:
2256 if (dev->base)
2257 iounmap(dev->base);
2258 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_TX_DESC, dev->tx_descs, dev->tx_phy_descs);
2259 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_RX_DESC, dev->rx_info.descs, dev->rx_info.phy_descs);
2260 pci_disable_device(pci_dev);
2261 out_free:
2262 free_netdev(ndev);
2263 pci_set_drvdata(pci_dev, NULL);
2264 out:
2265 return err;
2266 }
2267
2268 static void __devexit ns83820_remove_one(struct pci_dev *pci_dev)
2269 {
2270 struct net_device *ndev = pci_get_drvdata(pci_dev);
2271 struct ns83820 *dev = PRIV(ndev); /* ok even if NULL */
2272
2273 if (!ndev) /* paranoia */
2274 return;
2275
2276 writel(0, dev->base + IMR); /* paranoia */
2277 writel(0, dev->base + IER);
2278 readl(dev->base + IER);
2279
2280 unregister_netdev(ndev);
2281 free_irq(dev->pci_dev->irq, ndev);
2282 iounmap(dev->base);
2283 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_TX_DESC,
2284 dev->tx_descs, dev->tx_phy_descs);
2285 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_RX_DESC,
2286 dev->rx_info.descs, dev->rx_info.phy_descs);
2287 pci_disable_device(dev->pci_dev);
2288 free_netdev(ndev);
2289 pci_set_drvdata(pci_dev, NULL);
2290 }
2291
2292 static struct pci_device_id ns83820_pci_tbl[] = {
2293 { 0x100b, 0x0022, PCI_ANY_ID, PCI_ANY_ID, 0, .driver_data = 0, },
2294 { 0, },
2295 };
2296
2297 static struct pci_driver driver = {
2298 .name = "ns83820",
2299 .id_table = ns83820_pci_tbl,
2300 .probe = ns83820_init_one,
2301 .remove = __devexit_p(ns83820_remove_one),
2302 #if 0 /* FIXME: implement */
2303 .suspend = ,
2304 .resume = ,
2305 #endif
2306 };
2307
2308
2309 static int __init ns83820_init(void)
2310 {
2311 printk(KERN_INFO "ns83820.c: National Semiconductor DP83820 10/100/1000 driver.\n");
2312 return pci_register_driver(&driver);
2313 }
2314
2315 static void __exit ns83820_exit(void)
2316 {
2317 pci_unregister_driver(&driver);
2318 }
2319
2320 MODULE_AUTHOR("Benjamin LaHaise <bcrl@kvack.org>");
2321 MODULE_DESCRIPTION("National Semiconductor DP83820 10/100/1000 driver");
2322 MODULE_LICENSE("GPL");
2323
2324 MODULE_DEVICE_TABLE(pci, ns83820_pci_tbl);
2325
2326 module_param(lnksts, int, 0);
2327 MODULE_PARM_DESC(lnksts, "Polarity of LNKSTS bit");
2328
2329 module_param(ihr, int, 0);
2330 MODULE_PARM_DESC(ihr, "Time in 100 us increments to delay interrupts (range 0-127)");
2331
2332 module_param(reset_phy, int, 0);
2333 MODULE_PARM_DESC(reset_phy, "Set to 1 to reset the PHY on startup");
2334
2335 module_init(ns83820_init);
2336 module_exit(ns83820_exit);
WRT350N Kernel Patches