include/asm-arm/arch-lh7a40x/registers.h

   1 /* include/asm-arm/arch-lh7a40x/registers.h
   2  *
   3  *  Copyright (C) 2004 Coastal Environmental Systems
   4  *  Copyright (C) 2004 Logic Product Development
   5  *
   6  *  This program is free software; you can redistribute it and/or
   7  *  modify it under the terms of the GNU General Public License
   8  *  version 2 as published by the Free Software Foundation.
   9  *
  10  */
  11
  12 #include <asm/arch/constants.h>
  13
  14 #ifndef __ASM_ARCH_REGISTERS_H
  15 #define __ASM_ARCH_REGISTERS_H
  16
  17
  18         /* Physical register base addresses */
  19
  20 #define AC97C_PHYS      (0x80000000)    /* AC97 Controller */
  21 #define MMC_PHYS        (0x80000100)    /* Multimedia Card Controller */
  22 #define USB_PHYS        (0x80000200)    /* USB Client */
  23 #define SCI_PHYS        (0x80000300)    /* Secure Card Interface */
  24 #define CSC_PHYS        (0x80000400)    /* Clock/State Controller  */
  25 #define INTC_PHYS       (0x80000500)    /* Interrupt Controller */
  26 #define UART1_PHYS      (0x80000600)    /* UART1 Controller */
  27 #define SIR_PHYS        (0x80000600)    /* IR Controller, same are UART1 */
  28 #define UART2_PHYS      (0x80000700)    /* UART2 Controller */
  29 #define UART3_PHYS      (0x80000800)    /* UART3 Controller */
  30 #define DCDC_PHYS       (0x80000900)    /* DC to DC Controller */
  31 #define ACI_PHYS        (0x80000a00)    /* Audio Codec Interface */
  32 #define SSP_PHYS        (0x80000b00)    /* Synchronous ... */
  33 #define TIMER_PHYS      (0x80000c00)    /* Timer Controller */
  34 #define RTC_PHYS        (0x80000d00)    /* Real-time Clock */
  35 #define GPIO_PHYS       (0x80000e00)    /* General Purpose IO */
  36 #define BMI_PHYS        (0x80000f00)    /* Battery Monitor Interface */
  37 #define HRTFTC_PHYS     (0x80001000)    /* High-res TFT Controller (LH7A400) */
  38 #define ALI_PHYS        (0x80001000)    /* Advanced LCD Interface (LH7A404) */
  39 #define WDT_PHYS        (0x80001400)    /* Watchdog Timer */
  40 #define SMC_PHYS        (0x80002000)    /* Static Memory Controller */
  41 #define SDRC_PHYS       (0x80002400)    /* SDRAM Controller */
  42 #define DMAC_PHYS       (0x80002800)    /* DMA Controller */
  43 #define CLCDC_PHYS      (0x80003000)    /* Color LCD Controller */
  44
  45         /* Physical registers of the LH7A404 */
  46
  47 #define ADC_PHYS        (0x80001300)    /* A/D & Touchscreen Controller */
  48 #define VIC1_PHYS       (0x80008000)    /* Vectored Interrupt Controller 1 */
  49 #define USBH_PHYS       (0x80009000)    /* USB OHCI host controller */
  50 #define VIC2_PHYS       (0x8000a000)    /* Vectored Interrupt Controller 2 */
  51
  52 /*#define KBD_PHYS      (0x80000e00) */
  53 /*#define LCDICP_PHYS   (0x80001000) */
  54
  55
  56         /* Clock/State Controller register */
  57
  58 #define CSC_PWRSR       __REG(CSC_PHYS + 0x00) /* Reset register & ID */
  59 #define CSC_PWRCNT      __REG(CSC_PHYS + 0x04) /* Power control */
  60 #define CSC_CLKSET      __REG(CSC_PHYS + 0x20) /* Clock speed control */
  61 #define CSC_USBDRESET   __REG(CSC_PHYS + 0x4c) /* USB Device resets */
  62
  63 #define CSC_PWRCNT_USBH_EN      (1<<28) /* USB Host power enable */
  64 #define CSC_PWRCNT_DMAC_M2M1_EN (1<<27)
  65 #define CSC_PWRCNT_DMAC_M2M0_EN (1<<26)
  66 #define CSC_PWRCNT_DMAC_M2P8_EN (1<<25)
  67 #define CSC_PWRCNT_DMAC_M2P9_EN (1<<24)
  68 #define CSC_PWRCNT_DMAC_M2P6_EN (1<<23)
  69 #define CSC_PWRCNT_DMAC_M2P7_EN (1<<22)
  70 #define CSC_PWRCNT_DMAC_M2P4_EN (1<<21)
  71 #define CSC_PWRCNT_DMAC_M2P5_EN (1<<20)
  72 #define CSC_PWRCNT_DMAC_M2P2_EN (1<<19)
  73 #define CSC_PWRCNT_DMAC_M2P3_EN (1<<18)
  74 #define CSC_PWRCNT_DMAC_M2P0_EN (1<<17)
  75 #define CSC_PWRCNT_DMAC_M2P1_EN (1<<16)
  76
  77 #define CSC_PWRSR_CHIPMAN_SHIFT (24)
  78 #define CSC_PWRSR_CHIPMAN_MASK  (0xff)
  79 #define CSC_PWRSR_CHIPID_SHIFT  (16)
  80 #define CSC_PWRSR_CHIPID_MASK   (0xff)
  81
  82 #define CSC_USBDRESET_APBRESETREG       (1<<1)
  83 #define CSC_USBDRESET_IORESETREG        (1<<0)
  84
  85         /* Interrupt Controller registers */
  86
  87 #define INTC_INTSR      __REG(INTC_PHYS + 0x00) /* Status */
  88 #define INTC_INTRSR     __REG(INTC_PHYS + 0x04) /* Raw Status */
  89 #define INTC_INTENS     __REG(INTC_PHYS + 0x08) /* Enable Set */
  90 #define INTC_INTENC     __REG(INTC_PHYS + 0x0c) /* Enable Clear */
  91
  92
  93         /* Vectored Interrupted Controller registers */
  94
  95 #define VIC1_IRQSTATUS  __REG(VIC1_PHYS + 0x00)
  96 #define VIC1_FIQSTATUS  __REG(VIC1_PHYS + 0x04)
  97 #define VIC1_RAWINTR    __REG(VIC1_PHYS + 0x08)
  98 #define VIC1_INTSEL     __REG(VIC1_PHYS + 0x0c)
  99 #define VIC1_INTEN      __REG(VIC1_PHYS + 0x10)
 100 #define VIC1_INTENCLR   __REG(VIC1_PHYS + 0x14)
 101 #define VIC1_SOFTINT    __REG(VIC1_PHYS + 0x18)
 102 #define VIC1_SOFTINTCLR __REG(VIC1_PHYS + 0x1c)
 103 #define VIC1_PROTECT    __REG(VIC1_PHYS + 0x20)
 104 #define VIC1_VECTADDR   __REG(VIC1_PHYS + 0x30)
 105 #define VIC1_NVADDR     __REG(VIC1_PHYS + 0x34)
 106 #define VIC1_VAD0       __REG(VIC1_PHYS + 0x100)
 107 #define VIC1_VECTCNTL0  __REG(VIC1_PHYS + 0x200)
 108 #define VIC2_IRQSTATUS  __REG(VIC2_PHYS + 0x00)
 109 #define VIC2_FIQSTATUS  __REG(VIC2_PHYS + 0x04)
 110 #define VIC2_RAWINTR    __REG(VIC2_PHYS + 0x08)
 111 #define VIC2_INTSEL     __REG(VIC2_PHYS + 0x0c)
 112 #define VIC2_INTEN      __REG(VIC2_PHYS + 0x10)
 113 #define VIC2_INTENCLR   __REG(VIC2_PHYS + 0x14)
 114 #define VIC2_SOFTINT    __REG(VIC2_PHYS + 0x18)
 115 #define VIC2_SOFTINTCLR __REG(VIC2_PHYS + 0x1c)
 116 #define VIC2_PROTECT    __REG(VIC2_PHYS + 0x20)
 117 #define VIC2_VECTADDR   __REG(VIC2_PHYS + 0x30)
 118 #define VIC2_NVADDR     __REG(VIC2_PHYS + 0x34)
 119 #define VIC2_VAD0       __REG(VIC2_PHYS + 0x100)
 120 #define VIC2_VECTCNTL0  __REG(VIC2_PHYS + 0x200)
 121
 122 #define VIC_CNTL_ENABLE (0x20)
 123
 124         /* USB Host registers (Open HCI compatible) */
 125
 126 #define USBH_CMDSTATUS  __REG(USBH_PHYS + 0x08)
 127
 128
 129         /* GPIO registers */
 130
 131 #define GPIO_INTTYPE1   __REG(GPIO_PHYS + 0x4c) /* Interrupt Type 1 (Edge) */
 132 #define GPIO_INTTYPE2   __REG(GPIO_PHYS + 0x50) /* Interrupt Type 2 */
 133 #define GPIO_GPIOFEOI   __REG(GPIO_PHYS + 0x54) /* GPIO End-of-Interrupt */
 134 #define GPIO_GPIOINTEN  __REG(GPIO_PHYS + 0x58) /* GPIO Interrupt Enable */
 135 #define GPIO_INTSTATUS  __REG(GPIO_PHYS + 0x5c) /* GPIO Interrupt Status */
 136 #define GPIO_PINMUX     __REG(GPIO_PHYS + 0x2c)
 137 #define GPIO_PADD       __REG(GPIO_PHYS + 0x10)
 138 #define GPIO_PAD        __REG(GPIO_PHYS + 0x00)
 139 #define GPIO_PCD        __REG(GPIO_PHYS + 0x08)
 140 #define GPIO_PCDD       __REG(GPIO_PHYS + 0x18)
 141 #define GPIO_PEDD       __REG(GPIO_PHYS + 0x24)
 142 #define GPIO_PED        __REG(GPIO_PHYS + 0x20)
 143
 144
 145         /* Static Memory Controller registers */
 146
 147 #define SMC_BCR0        __REG(SMC_PHYS + 0x00)  /* Bank 0 Configuration */
 148 #define SMC_BCR1        __REG(SMC_PHYS + 0x04)  /* Bank 1 Configuration */
 149 #define SMC_BCR2        __REG(SMC_PHYS + 0x08)  /* Bank 2 Configuration */
 150 #define SMC_BCR3        __REG(SMC_PHYS + 0x0C)  /* Bank 3 Configuration */
 151 #define SMC_BCR6        __REG(SMC_PHYS + 0x18)  /* Bank 6 Configuration */
 152 #define SMC_BCR7        __REG(SMC_PHYS + 0x1c)  /* Bank 7 Configuration */
 153
 154
 155 #ifdef CONFIG_MACH_KEV7A400
 156 # define CPLD_RD_OPT_DIP_SW     __REG16(CPLD_PHYS + 0x00) /* Read Option SW */
 157 # define CPLD_WR_IO_BRD_CTL     __REG16(CPLD_PHYS + 0x00) /* Write Control */
 158 # define CPLD_RD_PB_KEYS        __REG16(CPLD_PHYS + 0x02) /* Read Btn Keys */
 159 # define CPLD_LATCHED_INTS      __REG16(CPLD_PHYS + 0x04) /* Read INTR stat. */
 160 # define CPLD_CL_INT            __REG16(CPLD_PHYS + 0x04) /* Clear INTR stat */
 161 # define CPLD_BOOT_MMC_STATUS   __REG16(CPLD_PHYS + 0x06) /* R/O */
 162 # define CPLD_RD_KPD_ROW_SENSE  __REG16(CPLD_PHYS + 0x08)
 163 # define CPLD_WR_PB_INT_MASK    __REG16(CPLD_PHYS + 0x08)
 164 # define CPLD_RD_BRD_DISP_SW    __REG16(CPLD_PHYS + 0x0a)
 165 # define CPLD_WR_EXT_INT_MASK   __REG16(CPLD_PHYS + 0x0a)
 166 # define CPLD_LCD_PWR_CNTL      __REG16(CPLD_PHYS + 0x0c)
 167 # define CPLD_SEVEN_SEG         __REG16(CPLD_PHYS + 0x0e) /* 7 seg. LED mask */
 168
 169 #endif
 170
 171 #if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
 172
 173 # define CPLD_CONTROL           __REG16(CPLD02_PHYS)
 174 # define CPLD_SPI_DATA          __REG16(CPLD06_PHYS)
 175 # define CPLD_SPI_CONTROL       __REG16(CPLD08_PHYS)
 176 # define CPLD_SPI_EEPROM        __REG16(CPLD0A_PHYS)
 177 # define CPLD_INTERRUPTS        __REG16(CPLD0C_PHYS) /* IRQ mask/status */
 178 # define CPLD_BOOT_MODE         __REG16(CPLD0E_PHYS)
 179 # define CPLD_FLASH             __REG16(CPLD10_PHYS)
 180 # define CPLD_POWER_MGMT        __REG16(CPLD12_PHYS)
 181 # define CPLD_REVISION          __REG16(CPLD14_PHYS)
 182 # define CPLD_GPIO_EXT          __REG16(CPLD16_PHYS)
 183 # define CPLD_GPIO_DATA         __REG16(CPLD18_PHYS)
 184 # define CPLD_GPIO_DIR          __REG16(CPLD1A_PHYS)
 185
 186 #endif
 187
 188         /* Timer registers */
 189
 190 #define TIMER_LOAD1     __REG(TIMER_PHYS + 0x00) /* Timer 1 initial value */
 191 #define TIMER_VALUE1    __REG(TIMER_PHYS + 0x04) /* Timer 1 current value */
 192 #define TIMER_CONTROL1  __REG(TIMER_PHYS + 0x08) /* Timer 1 control word */
 193 #define TIMER_EOI1      __REG(TIMER_PHYS + 0x0c) /* Timer 1 interrupt clear */
 194
 195 #define TIMER_LOAD2     __REG(TIMER_PHYS + 0x20) /* Timer 2 initial value */
 196 #define TIMER_VALUE2    __REG(TIMER_PHYS + 0x24) /* Timer 2 current value */
 197 #define TIMER_CONTROL2  __REG(TIMER_PHYS + 0x28) /* Timer 2 control word */
 198 #define TIMER_EOI2      __REG(TIMER_PHYS + 0x2c) /* Timer 2 interrupt clear */
 199
 200 #define TIMER_BUZZCON   __REG(TIMER_PHYS + 0x40) /* Buzzer configuration */
 201
 202 #define TIMER_LOAD3     __REG(TIMER_PHYS + 0x80) /* Timer 3 initial value */
 203 #define TIMER_VALUE3    __REG(TIMER_PHYS + 0x84) /* Timer 3 current value */
 204 #define TIMER_CONTROL3  __REG(TIMER_PHYS + 0x88) /* Timer 3 control word */
 205 #define TIMER_EOI3      __REG(TIMER_PHYS + 0x8c) /* Timer 3 interrupt clear */
 206
 207 #define TIMER_C_ENABLE          (1<<7)
 208 #define TIMER_C_PERIODIC        (1<<6)
 209 #define TIMER_C_FREERUNNING     (0)
 210 #define TIMER_C_2KHZ            (0x00)          /* 1.986 kHz */
 211 #define TIMER_C_508KHZ          (0x08)
 212
 213         /* GPIO registers */
 214
 215 #define GPIO_PFDD               __REG(GPIO_PHYS + 0x34) /* PF direction */
 216 #define GPIO_INTTYPE1           __REG(GPIO_PHYS + 0x4c) /* IRQ edge or lvl  */
 217 #define GPIO_INTTYPE2           __REG(GPIO_PHYS + 0x50) /* IRQ activ hi/lo */
 218 #define GPIO_GPIOFEOI           __REG(GPIO_PHYS + 0x54) /* GPIOF end of IRQ */
 219 #define GPIO_GPIOFINTEN         __REG(GPIO_PHYS + 0x58) /* GPIOF IRQ enable */
 220 #define GPIO_INTSTATUS          __REG(GPIO_PHYS + 0x5c) /* GPIOF IRQ latch */
 221 #define GPIO_RAWINTSTATUS       __REG(GPIO_PHYS + 0x60) /* GPIOF IRQ raw */
 222
 223
 224 #endif  /* _ASM_ARCH_REGISTERS_H */