x86: i8259A: remove redundant irq_descinitialization
[wrt350n-kernel.git] / include / asm-mips / smtc.h
blobff3e8936b493d8b7137ab991fe84fd9e1bdebc19
1 #ifndef _ASM_SMTC_MT_H
2 #define _ASM_SMTC_MT_H
4 /*
5 * Definitions for SMTC multitasking on MIPS MT cores
6 */
8 #include <asm/mips_mt.h>
11 * System-wide SMTC status information
14 extern unsigned int smtc_status;
16 #define SMTC_TLB_SHARED 0x00000001
17 #define SMTC_MTC_ACTIVE 0x00000002
20 * TLB/ASID Management information
23 #define MAX_SMTC_TLBS 2
24 #define MAX_SMTC_ASIDS 256
25 #if NR_CPUS <= 8
26 typedef char asiduse;
27 #else
28 #if NR_CPUS <= 16
29 typedef short asiduse;
30 #else
31 typedef long asiduse;
32 #endif
33 #endif
35 extern asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS];
37 struct mm_struct;
38 struct task_struct;
40 void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu);
42 void smtc_flush_tlb_asid(unsigned long asid);
43 extern int mipsmt_build_cpu_map(int startslot);
44 extern void mipsmt_prepare_cpus(void);
45 extern void smtc_smp_finish(void);
46 extern void smtc_boot_secondary(int cpu, struct task_struct *t);
49 * Sharing the TLB between multiple VPEs means that the
50 * "random" index selection function is not allowed to
51 * select the current value of the Index register. To
52 * avoid additional TLB pressure, the Index registers
53 * are "parked" with an non-Valid value.
56 #define PARKED_INDEX ((unsigned int)0x80000000)
59 * Define low-level interrupt mask for IPIs, if necessary.
60 * By default, use SW interrupt 1, which requires no external
61 * hardware support, but which works only for single-core
62 * MIPS MT systems.
64 #ifndef MIPS_CPU_IPI_IRQ
65 #define MIPS_CPU_IPI_IRQ 1
66 #endif
68 #endif /* _ASM_SMTC_MT_H */