include/asm-x86/pgtable_32.h

   1 #ifndef _I386_PGTABLE_H
   2 #define _I386_PGTABLE_H
   3
   4
   5 /*
   6  * The Linux memory management assumes a three-level page table setup. On
   7  * the i386, we use that, but "fold" the mid level into the top-level page
   8  * table, so that we physically have the same two-level page table as the
   9  * i386 mmu expects.
  10  *
  11  * This file contains the functions and defines necessary to modify and use
  12  * the i386 page table tree.
  13  */
  14 #ifndef __ASSEMBLY__
  15 #include <asm/processor.h>
  16 #include <asm/fixmap.h>
  17 #include <linux/threads.h>
  18 #include <asm/paravirt.h>
  19
  20 #include <linux/bitops.h>
  21 #include <linux/slab.h>
  22 #include <linux/list.h>
  23 #include <linux/spinlock.h>
  24
  25 struct mm_struct;
  26 struct vm_area_struct;
  27
  28 extern pgd_t swapper_pg_dir[1024];
  29 extern struct kmem_cache *pmd_cache;
  30 void check_pgt_cache(void);
  31
  32 static inline void pgtable_cache_init(void) {}
  33 void paging_init(void);
  34
  35
  36 /*
  37  * The Linux x86 paging architecture is 'compile-time dual-mode', it
  38  * implements both the traditional 2-level x86 page tables and the
  39  * newer 3-level PAE-mode page tables.
  40  */
  41 #ifdef CONFIG_X86_PAE
  42 # include <asm/pgtable-3level-defs.h>
  43 # define PMD_SIZE       (1UL << PMD_SHIFT)
  44 # define PMD_MASK       (~(PMD_SIZE-1))
  45 #else
  46 # include <asm/pgtable-2level-defs.h>
  47 #endif
  48
  49 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
  50 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
  51
  52 #define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
  53 #define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS)
  54
  55 /* Just any arbitrary offset to the start of the vmalloc VM area: the
  56  * current 8MB value just means that there will be a 8MB "hole" after the
  57  * physical memory until the kernel virtual memory starts.  That means that
  58  * any out-of-bounds memory accesses will hopefully be caught.
  59  * The vmalloc() routines leaves a hole of 4kB between each vmalloced
  60  * area for the same reason. ;)
  61  */
  62 #define VMALLOC_OFFSET  (8*1024*1024)
  63 #define VMALLOC_START   (((unsigned long) high_memory + \
  64                         2*VMALLOC_OFFSET-1) & ~(VMALLOC_OFFSET-1))
  65 #ifdef CONFIG_X86_PAE
  66 #define LAST_PKMAP 512
  67 #else
  68 #define LAST_PKMAP 1024
  69 #endif
  70
  71 #define PKMAP_BASE ((FIXADDR_BOOT_START - PAGE_SIZE*(LAST_PKMAP + 1)) & PMD_MASK)
  72
  73 #ifdef CONFIG_HIGHMEM
  74 # define VMALLOC_END    (PKMAP_BASE-2*PAGE_SIZE)
  75 #else
  76 # define VMALLOC_END    (FIXADDR_START-2*PAGE_SIZE)
  77 #endif
  78
  79 /*
  80  * Define this if things work differently on an i386 and an i486:
  81  * it will (on an i486) warn about kernel memory accesses that are
  82  * done without a 'access_ok(VERIFY_WRITE,..)'
  83  */
  84 #undef TEST_ACCESS_OK
  85
  86 /* The boot page tables (all created as a single array) */
  87 extern unsigned long pg0[];
  88
  89 #define pte_present(x)  ((x).pte_low & (_PAGE_PRESENT | _PAGE_PROTNONE))
  90
  91 /* To avoid harmful races, pmd_none(x) should check only the lower when PAE */
  92 #define pmd_none(x)     (!(unsigned long)pmd_val(x))
  93 #define pmd_present(x)  (pmd_val(x) & _PAGE_PRESENT)
  94 #define pmd_bad(x)      ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_USER)) != _KERNPG_TABLE)
  95
  96
  97 #define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
  98
  99 #ifdef CONFIG_X86_PAE
 100 # include <asm/pgtable-3level.h>
 101 #else
 102 # include <asm/pgtable-2level.h>
 103 #endif
 104
 105 /*
 106  * clone_pgd_range(pgd_t *dst, pgd_t *src, int count);
 107  *
 108  *  dst - pointer to pgd range anwhere on a pgd page
 109  *  src - ""
 110  *  count - the number of pgds to copy.
 111  *
 112  * dst and src can be on the same page, but the range must not overlap,
 113  * and must not cross a page boundary.
 114  */
 115 static inline void clone_pgd_range(pgd_t *dst, pgd_t *src, int count)
 116 {
 117        memcpy(dst, src, count * sizeof(pgd_t));
 118 }
 119
 120 /*
 121  * Macro to mark a page protection value as "uncacheable".  On processors which do not support
 122  * it, this is a no-op.
 123  */
 124 #define pgprot_noncached(prot)  ((boot_cpu_data.x86 > 3)                                          \
 125                                  ? (__pgprot(pgprot_val(prot) | _PAGE_PCD | _PAGE_PWT)) : (prot))
 126
 127 /*
 128  * Conversion functions: convert a page and protection to a page entry,
 129  * and a page entry and page directory to the page they refer to.
 130  */
 131
 132 #define mk_pte(page, pgprot)    pfn_pte(page_to_pfn(page), (pgprot))
 133
 134 /*
 135  * the pgd page can be thought of an array like this: pgd_t[PTRS_PER_PGD]
 136  *
 137  * this macro returns the index of the entry in the pgd page which would
 138  * control the given virtual address
 139  */
 140 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
 141 #define pgd_index_k(addr) pgd_index(addr)
 142
 143 /*
 144  * pgd_offset() returns a (pgd_t *)
 145  * pgd_index() is used get the offset into the pgd page's array of pgd_t's;
 146  */
 147 #define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
 148
 149 /*
 150  * a shortcut which implies the use of the kernel's pgd, instead
 151  * of a process's
 152  */
 153 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
 154
 155 static inline int pud_large(pud_t pud) { return 0; }
 156
 157 /*
 158  * the pmd page can be thought of an array like this: pmd_t[PTRS_PER_PMD]
 159  *
 160  * this macro returns the index of the entry in the pmd page which would
 161  * control the given virtual address
 162  */
 163 #define pmd_index(address) \
 164                 (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
 165
 166 /*
 167  * the pte page can be thought of an array like this: pte_t[PTRS_PER_PTE]
 168  *
 169  * this macro returns the index of the entry in the pte page which would
 170  * control the given virtual address
 171  */
 172 #define pte_index(address) \
 173                 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
 174 #define pte_offset_kernel(dir, address) \
 175         ((pte_t *) pmd_page_vaddr(*(dir)) +  pte_index(address))
 176
 177 #define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
 178
 179 #define pmd_page_vaddr(pmd) \
 180                 ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
 181
 182 #if defined(CONFIG_HIGHPTE)
 183 #define pte_offset_map(dir, address) \
 184         ((pte_t *)kmap_atomic_pte(pmd_page(*(dir)),KM_PTE0) + pte_index(address))
 185 #define pte_offset_map_nested(dir, address) \
 186         ((pte_t *)kmap_atomic_pte(pmd_page(*(dir)),KM_PTE1) + pte_index(address))
 187 #define pte_unmap(pte) kunmap_atomic(pte, KM_PTE0)
 188 #define pte_unmap_nested(pte) kunmap_atomic(pte, KM_PTE1)
 189 #else
 190 #define pte_offset_map(dir, address) \
 191         ((pte_t *)page_address(pmd_page(*(dir))) + pte_index(address))
 192 #define pte_offset_map_nested(dir, address) pte_offset_map(dir, address)
 193 #define pte_unmap(pte) do { } while (0)
 194 #define pte_unmap_nested(pte) do { } while (0)
 195 #endif
 196
 197 /* Clear a kernel PTE and flush it from the TLB */
 198 #define kpte_clear_flush(ptep, vaddr)                                   \
 199 do {                                                                    \
 200         pte_clear(&init_mm, vaddr, ptep);                               \
 201         __flush_tlb_one(vaddr);                                         \
 202 } while (0)
 203
 204 /*
 205  * The i386 doesn't have any external MMU info: the kernel page
 206  * tables contain all the necessary information.
 207  */
 208 #define update_mmu_cache(vma,address,pte) do { } while (0)
 209
 210 void native_pagetable_setup_start(pgd_t *base);
 211 void native_pagetable_setup_done(pgd_t *base);
 212
 213 #ifndef CONFIG_PARAVIRT
 214 static inline void paravirt_pagetable_setup_start(pgd_t *base)
 215 {
 216         native_pagetable_setup_start(base);
 217 }
 218
 219 static inline void paravirt_pagetable_setup_done(pgd_t *base)
 220 {
 221         native_pagetable_setup_done(base);
 222 }
 223 #endif  /* !CONFIG_PARAVIRT */
 224
 225 #endif /* !__ASSEMBLY__ */
 226
 227 /*
 228  * kern_addr_valid() is (1) for FLATMEM and (0) for
 229  * SPARSEMEM and DISCONTIGMEM
 230  */
 231 #ifdef CONFIG_FLATMEM
 232 #define kern_addr_valid(addr)   (1)
 233 #else
 234 #define kern_addr_valid(kaddr)  (0)
 235 #endif
 236
 237 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
 238                 remap_pfn_range(vma, vaddr, pfn, size, prot)
 239
 240 #endif /* _I386_PGTABLE_H */