arch/sh/kernel/cpu/sh2a/setup-sh7206.c

   1 /*
   2  * SH7206 Setup
   3  *
   4  *  Copyright (C) 2006  Yoshinori Sato
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/platform_device.h>
  11 #include <linux/init.h>
  12 #include <linux/serial.h>
  13 <<<<<<< HEAD:arch/sh/kernel/cpu/sh2a/setup-sh7206.c
  14 #include <asm/sci.h>
  15 =======
  16 #include <linux/serial_sci.h>
  17 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/sh/kernel/cpu/sh2a/setup-sh7206.c
  18
  19 enum {
  20         UNUSED = 0,
  21
  22         /* interrupt sources */
  23         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
  24         PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
  25         ADC_ADI0, ADC_ADI1,
  26         DMAC0_DEI, DMAC0_HEI, DMAC1_DEI, DMAC1_HEI,
  27         DMAC2_DEI, DMAC2_HEI, DMAC3_DEI, DMAC3_HEI,
  28         DMAC4_DEI, DMAC4_HEI, DMAC5_DEI, DMAC5_HEI,
  29         DMAC6_DEI, DMAC6_HEI, DMAC7_DEI, DMAC7_HEI,
  30         CMT0, CMT1, BSC, WDT,
  31         MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D,
  32         MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F,
  33         MTU2_TGI1A, MTU2_TGI1B, MTU2_TCI1V, MTU2_TCI1U,
  34         MTU2_TGI2A, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U,
  35         MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D, MTU2_TCI3V,
  36         MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D, MTU2_TCI4V,
  37         MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W,
  38         POE2_OEI1, POE2_OEI2,
  39         MTU2S_TGI3A, MTU2S_TGI3B, MTU2S_TGI3C, MTU2S_TGI3D, MTU2S_TCI3V,
  40         MTU2S_TGI4A, MTU2S_TGI4B, MTU2S_TGI4C, MTU2S_TGI4D, MTU2S_TCI4V,
  41         MTU2S_TGI5U, MTU2S_TGI5V, MTU2S_TGI5W,
  42         POE2_OEI3,
  43         IIC3_STPI, IIC3_NAKI, IIC3_RXI, IIC3_TXI, IIC3_TEI,
  44         SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
  45         SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
  46         SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI,
  47         SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI,
  48
  49         /* interrupt groups */
  50         PINT, DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
  51         MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
  52         MTU3_ABCD, MTU4_ABCD, MTU5, POE2_12, MTU3S_ABCD, MTU4S_ABCD, MTU5S,
  53         IIC3, SCIF0, SCIF1, SCIF2, SCIF3,
  54 };
  55
  56 static struct intc_vect vectors[] __initdata = {
  57         INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
  58         INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
  59         INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
  60         INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
  61         INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
  62         INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
  63         INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
  64         INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
  65         INTC_IRQ(ADC_ADI0, 92), INTC_IRQ(ADC_ADI1, 96),
  66         INTC_IRQ(DMAC0_DEI, 108), INTC_IRQ(DMAC0_HEI, 109),
  67         INTC_IRQ(DMAC1_DEI, 112), INTC_IRQ(DMAC1_HEI, 113),
  68         INTC_IRQ(DMAC2_DEI, 116), INTC_IRQ(DMAC2_HEI, 117),
  69         INTC_IRQ(DMAC3_DEI, 120), INTC_IRQ(DMAC3_HEI, 121),
  70         INTC_IRQ(DMAC4_DEI, 124), INTC_IRQ(DMAC4_HEI, 125),
  71         INTC_IRQ(DMAC5_DEI, 128), INTC_IRQ(DMAC5_HEI, 129),
  72         INTC_IRQ(DMAC6_DEI, 132), INTC_IRQ(DMAC6_HEI, 133),
  73         INTC_IRQ(DMAC7_DEI, 136), INTC_IRQ(DMAC7_HEI, 137),
  74         INTC_IRQ(CMT0, 140), INTC_IRQ(CMT1, 144),
  75         INTC_IRQ(BSC, 148), INTC_IRQ(WDT, 152),
  76         INTC_IRQ(MTU2_TGI0A, 156), INTC_IRQ(MTU2_TGI0B, 157),
  77         INTC_IRQ(MTU2_TGI0C, 158), INTC_IRQ(MTU2_TGI0D, 159),
  78         INTC_IRQ(MTU2_TCI0V, 160),
  79         INTC_IRQ(MTU2_TGI0E, 161), INTC_IRQ(MTU2_TGI0F, 162),
  80         INTC_IRQ(MTU2_TGI1A, 164), INTC_IRQ(MTU2_TGI1B, 165),
  81         INTC_IRQ(MTU2_TCI1V, 168), INTC_IRQ(MTU2_TCI1U, 169),
  82         INTC_IRQ(MTU2_TGI2A, 172), INTC_IRQ(MTU2_TGI2B, 173),
  83         INTC_IRQ(MTU2_TCI2V, 176), INTC_IRQ(MTU2_TCI2U, 177),
  84         INTC_IRQ(MTU2_TGI3A, 180), INTC_IRQ(MTU2_TGI3B, 181),
  85         INTC_IRQ(MTU2_TGI3C, 182), INTC_IRQ(MTU2_TGI3D, 183),
  86         INTC_IRQ(MTU2_TCI3V, 184),
  87         INTC_IRQ(MTU2_TGI4A, 188), INTC_IRQ(MTU2_TGI4B, 189),
  88         INTC_IRQ(MTU2_TGI4C, 190), INTC_IRQ(MTU2_TGI4D, 191),
  89         INTC_IRQ(MTU2_TCI4V, 192),
  90         INTC_IRQ(MTU2_TGI5U, 196), INTC_IRQ(MTU2_TGI5V, 197),
  91         INTC_IRQ(MTU2_TGI5W, 198),
  92         INTC_IRQ(POE2_OEI1, 200), INTC_IRQ(POE2_OEI2, 201),
  93         INTC_IRQ(MTU2S_TGI3A, 204), INTC_IRQ(MTU2S_TGI3B, 205),
  94         INTC_IRQ(MTU2S_TGI3C, 206), INTC_IRQ(MTU2S_TGI3D, 207),
  95         INTC_IRQ(MTU2S_TCI3V, 208),
  96         INTC_IRQ(MTU2S_TGI4A, 212), INTC_IRQ(MTU2S_TGI4B, 213),
  97         INTC_IRQ(MTU2S_TGI4C, 214), INTC_IRQ(MTU2S_TGI4D, 215),
  98         INTC_IRQ(MTU2S_TCI4V, 216),
  99         INTC_IRQ(MTU2S_TGI5U, 220), INTC_IRQ(MTU2S_TGI5V, 221),
 100         INTC_IRQ(MTU2S_TGI5W, 222),
 101         INTC_IRQ(POE2_OEI3, 224),
 102         INTC_IRQ(IIC3_STPI, 228), INTC_IRQ(IIC3_NAKI, 229),
 103         INTC_IRQ(IIC3_RXI, 230), INTC_IRQ(IIC3_TXI, 231),
 104         INTC_IRQ(IIC3_TEI, 232),
 105         INTC_IRQ(SCIF0_BRI, 240), INTC_IRQ(SCIF0_ERI, 241),
 106         INTC_IRQ(SCIF0_RXI, 242), INTC_IRQ(SCIF0_TXI, 243),
 107         INTC_IRQ(SCIF1_BRI, 244), INTC_IRQ(SCIF1_ERI, 245),
 108         INTC_IRQ(SCIF1_RXI, 246), INTC_IRQ(SCIF1_TXI, 247),
 109         INTC_IRQ(SCIF2_BRI, 248), INTC_IRQ(SCIF2_ERI, 249),
 110         INTC_IRQ(SCIF2_RXI, 250), INTC_IRQ(SCIF2_TXI, 251),
 111         INTC_IRQ(SCIF3_BRI, 252), INTC_IRQ(SCIF3_ERI, 253),
 112         INTC_IRQ(SCIF3_RXI, 254), INTC_IRQ(SCIF3_TXI, 255),
 113 };
 114
 115 static struct intc_group groups[] __initdata = {
 116         INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
 117                    PINT4, PINT5, PINT6, PINT7),
 118         INTC_GROUP(DMAC0, DMAC0_DEI, DMAC0_HEI),
 119         INTC_GROUP(DMAC1, DMAC1_DEI, DMAC1_HEI),
 120         INTC_GROUP(DMAC2, DMAC2_DEI, DMAC2_HEI),
 121         INTC_GROUP(DMAC3, DMAC3_DEI, DMAC3_HEI),
 122         INTC_GROUP(DMAC4, DMAC4_DEI, DMAC4_HEI),
 123         INTC_GROUP(DMAC5, DMAC5_DEI, DMAC5_HEI),
 124         INTC_GROUP(DMAC6, DMAC6_DEI, DMAC6_HEI),
 125         INTC_GROUP(DMAC7, DMAC7_DEI, DMAC7_HEI),
 126         INTC_GROUP(MTU0_ABCD, MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D),
 127         INTC_GROUP(MTU0_VEF, MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F),
 128         INTC_GROUP(MTU1_AB, MTU2_TGI1A, MTU2_TGI1B),
 129         INTC_GROUP(MTU1_VU, MTU2_TCI1V, MTU2_TCI1U),
 130         INTC_GROUP(MTU2_AB, MTU2_TGI2A, MTU2_TGI2B),
 131         INTC_GROUP(MTU2_VU, MTU2_TCI2V, MTU2_TCI2U),
 132         INTC_GROUP(MTU3_ABCD, MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D),
 133         INTC_GROUP(MTU4_ABCD, MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D),
 134         INTC_GROUP(MTU5, MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W),
 135         INTC_GROUP(POE2_12, POE2_OEI1, POE2_OEI2),
 136         INTC_GROUP(MTU3S_ABCD, MTU2S_TGI3A, MTU2S_TGI3B,
 137                    MTU2S_TGI3C, MTU2S_TGI3D),
 138         INTC_GROUP(MTU4S_ABCD, MTU2S_TGI4A, MTU2S_TGI4B,
 139                    MTU2S_TGI4C, MTU2S_TGI4D),
 140         INTC_GROUP(MTU5S, MTU2S_TGI5U, MTU2S_TGI5V, MTU2S_TGI5W),
 141         INTC_GROUP(IIC3, IIC3_STPI, IIC3_NAKI, IIC3_RXI, IIC3_TXI, IIC3_TEI),
 142         INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
 143         INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
 144         INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
 145         INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI),
 146 };
 147
 148 static struct intc_prio_reg prio_registers[] __initdata = {
 149         { 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
 150         { 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
 151         { 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, ADC_ADI0, ADC_ADI1 } },
 152         { 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
 153         { 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } },
 154         { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { CMT0, CMT1, BSC, WDT } },
 155         { 0xfffe0c06, 0, 16, 4, /* IPR09 */ { MTU0_ABCD, MTU0_VEF,
 156                                               MTU1_AB, MTU1_VU } },
 157         { 0xfffe0c08, 0, 16, 4, /* IPR10 */ { MTU2_AB, MTU2_VU,
 158                                               MTU3_ABCD, MTU2_TCI3V } },
 159         { 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { MTU4_ABCD, MTU2_TCI4V,
 160                                               MTU5, POE2_12 } },
 161         { 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { MTU3S_ABCD, MTU2S_TCI3V,
 162                                               MTU4S_ABCD, MTU2S_TCI4V } },
 163         { 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { MTU5S, POE2_OEI3, IIC3, 0 } },
 164         { 0xfffe0c10, 0, 16, 4, /* IPR14 */ { SCIF0, SCIF1, SCIF2, SCIF3 } },
 165 };
 166
 167 static struct intc_mask_reg mask_registers[] __initdata = {
 168         { 0xfffe0808, 0, 16, /* PINTER */
 169           { 0, 0, 0, 0, 0, 0, 0, 0,
 170             PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
 171 };
 172
 173 static DECLARE_INTC_DESC(intc_desc, "sh7206", vectors, groups,
 174                          mask_registers, prio_registers, NULL);
 175
 176 static struct plat_sci_port sci_platform_data[] = {
 177         {
 178                 .mapbase        = 0xfffe8000,
 179                 .flags          = UPF_BOOT_AUTOCONF,
 180                 .type           = PORT_SCIF,
 181                 .irqs           =  { 241, 242, 243, 240 },
 182         }, {
 183                 .mapbase        = 0xfffe8800,
 184                 .flags          = UPF_BOOT_AUTOCONF,
 185                 .type           = PORT_SCIF,
 186                 .irqs           =  { 245, 246, 247, 244 },
 187         }, {
 188                 .mapbase        = 0xfffe9000,
 189                 .flags          = UPF_BOOT_AUTOCONF,
 190                 .type           = PORT_SCIF,
 191                 .irqs           =  { 249, 250, 251, 248 },
 192         }, {
 193                 .mapbase        = 0xfffe9800,
 194                 .flags          = UPF_BOOT_AUTOCONF,
 195                 .type           = PORT_SCIF,
 196                 .irqs           =  { 253, 254, 255, 252 },
 197         }, {
 198                 .flags = 0,
 199         }
 200 };
 201
 202 static struct platform_device sci_device = {
 203         .name           = "sh-sci",
 204         .id             = -1,
 205         .dev            = {
 206                 .platform_data  = sci_platform_data,
 207         },
 208 };
 209
 210 static struct platform_device *sh7206_devices[] __initdata = {
 211         &sci_device,
 212 };
 213
 214 static int __init sh7206_devices_setup(void)
 215 {
 216         return platform_add_devices(sh7206_devices,
 217                                     ARRAY_SIZE(sh7206_devices));
 218 }
 219 __initcall(sh7206_devices_setup);
 220
 221 void __init plat_irq_setup(void)
 222 {
 223         register_intc_controller(&intc_desc);
 224 }