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Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / drivers / i2c / busses / i2c-pxa.c
blob652054dba72aeb762835b72356b925b0af7d3caf
1 /*
2 * i2c_adap_pxa.c
3 *
4 * I2C adapter for the PXA I2C bus access.
5 *
6 * Copyright (C) 2002 Intrinsyc Software Inc.
7 * Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * History:
14 * Apr 2002: Initial version [CS]
15 * Jun 2002: Properly seperated algo/adap [FB]
16 * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
17 * Jan 2003: added limited signal handling [Kai-Uwe Bloem]
18 * Sep 2004: Major rework to ensure efficient bus handling [RMK]
19 * Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood]
20 * Feb 2005: Rework slave mode handling [RMK]
21 */
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/i2c.h>
25 #include <linux/i2c-id.h>
26 #include <linux/init.h>
27 #include <linux/time.h>
28 #include <linux/sched.h>
29 #include <linux/delay.h>
30 #include <linux/errno.h>
31 #include <linux/interrupt.h>
32 #include <linux/i2c-pxa.h>
33 #include <linux/platform_device.h>
34 #include <linux/err.h>
35 #include <linux/clk.h>
36
37 #include <asm/hardware.h>
38 #include <asm/irq.h>
39 #include <asm/io.h>
40 #include <asm/arch/i2c.h>
41 #include <asm/arch/pxa-regs.h>
42
43 struct pxa_i2c {
44 spinlock_t lock;
45 wait_queue_head_t wait;
46 struct i2c_msg *msg;
47 unsigned int msg_num;
48 unsigned int msg_idx;
49 unsigned int msg_ptr;
50 unsigned int slave_addr;
51
52 struct i2c_adapter adap;
53 struct clk *clk;
54 #ifdef CONFIG_I2C_PXA_SLAVE
55 struct i2c_slave_client *slave;
56 #endif
57
58 unsigned int irqlogidx;
59 u32 isrlog[32];
60 u32 icrlog[32];
61
62 void __iomem *reg_base;
63
64 unsigned long iobase;
65 unsigned long iosize;
66
67 int irq;
68 int use_pio;
69 };
70
71 #define _IBMR(i2c) ((i2c)->reg_base + 0)
72 #define _IDBR(i2c) ((i2c)->reg_base + 8)
73 #define _ICR(i2c) ((i2c)->reg_base + 0x10)
74 #define _ISR(i2c) ((i2c)->reg_base + 0x18)
75 #define _ISAR(i2c) ((i2c)->reg_base + 0x20)
76
77 /*
78 * I2C Slave mode address
79 */
80 #define I2C_PXA_SLAVE_ADDR 0x1
81
82 #ifdef DEBUG
83
84 struct bits {
85 u32 mask;
86 const char *set;
87 const char *unset;
88 };
89 #define PXA_BIT(m, s, u) { .mask = m, .set = s, .unset = u }
90
91 static inline void
92 decode_bits(const char *prefix, const struct bits *bits, int num, u32 val)
93 {
94 printk("%s %08x: ", prefix, val);
95 while (num--) {
96 const char *str = val & bits->mask ? bits->set : bits->unset;
97 if (str)
98 printk("%s ", str);
99 bits++;
100 }
101 }
102
103 static const struct bits isr_bits[] = {
104 PXA_BIT(ISR_RWM, "RX", "TX"),
105 PXA_BIT(ISR_ACKNAK, "NAK", "ACK"),
106 PXA_BIT(ISR_UB, "Bsy", "Rdy"),
107 PXA_BIT(ISR_IBB, "BusBsy", "BusRdy"),
108 PXA_BIT(ISR_SSD, "SlaveStop", NULL),
109 PXA_BIT(ISR_ALD, "ALD", NULL),
110 PXA_BIT(ISR_ITE, "TxEmpty", NULL),
111 PXA_BIT(ISR_IRF, "RxFull", NULL),
112 PXA_BIT(ISR_GCAD, "GenCall", NULL),
113 PXA_BIT(ISR_SAD, "SlaveAddr", NULL),
114 PXA_BIT(ISR_BED, "BusErr", NULL),
115 };
116
117 static void decode_ISR(unsigned int val)
118 {
119 decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val);
120 printk("\n");
121 }
122
123 static const struct bits icr_bits[] = {
124 PXA_BIT(ICR_START, "START", NULL),
125 PXA_BIT(ICR_STOP, "STOP", NULL),
126 PXA_BIT(ICR_ACKNAK, "ACKNAK", NULL),
127 PXA_BIT(ICR_TB, "TB", NULL),
128 PXA_BIT(ICR_MA, "MA", NULL),
129 PXA_BIT(ICR_SCLE, "SCLE", "scle"),
130 PXA_BIT(ICR_IUE, "IUE", "iue"),
131 PXA_BIT(ICR_GCD, "GCD", NULL),
132 PXA_BIT(ICR_ITEIE, "ITEIE", NULL),
133 PXA_BIT(ICR_IRFIE, "IRFIE", NULL),
134 PXA_BIT(ICR_BEIE, "BEIE", NULL),
135 PXA_BIT(ICR_SSDIE, "SSDIE", NULL),
136 PXA_BIT(ICR_ALDIE, "ALDIE", NULL),
137 PXA_BIT(ICR_SADIE, "SADIE", NULL),
138 PXA_BIT(ICR_UR, "UR", "ur"),
139 };
140
141 <<<<<<< HEAD:drivers/i2c/busses/i2c-pxa.c
142 =======
143 #ifdef CONFIG_I2C_PXA_SLAVE
144 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/i2c/busses/i2c-pxa.c
145 static void decode_ICR(unsigned int val)
146 {
147 decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val);
148 printk("\n");
149 }
150 <<<<<<< HEAD:drivers/i2c/busses/i2c-pxa.c
151 =======
152 #endif
153 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/i2c/busses/i2c-pxa.c
154
155 static unsigned int i2c_debug = DEBUG;
156
157 static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
158 {
159 dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno,
160 readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
161 }
162
163 #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __FUNCTION__)
164 #else
165 #define i2c_debug 0
166
167 #define show_state(i2c) do { } while (0)
168 #define decode_ISR(val) do { } while (0)
169 #define decode_ICR(val) do { } while (0)
170 #endif
171
172 #define eedbg(lvl, x...) do { if ((lvl) < 1) { printk(KERN_DEBUG "" x); } } while(0)
173
174 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
175 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id);
176
177 static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
178 {
179 unsigned int i;
180 printk("i2c: error: %s\n", why);
181 printk("i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n",
182 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
183 printk("i2c: ICR: %08x ISR: %08x\n"
184 "i2c: log: ", readl(_ICR(i2c)), readl(_ISR(i2c)));
185 for (i = 0; i < i2c->irqlogidx; i++)
186 printk("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]);
187 printk("\n");
188 }
189
190 static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
191 {
192 return !(readl(_ICR(i2c)) & ICR_SCLE);
193 }
194
195 static void i2c_pxa_abort(struct pxa_i2c *i2c)
196 {
197 unsigned long timeout = jiffies + HZ/4;
198
199 if (i2c_pxa_is_slavemode(i2c)) {
200 dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__);
201 return;
202 }
203
204 while (time_before(jiffies, timeout) && (readl(_IBMR(i2c)) & 0x1) == 0) {
205 unsigned long icr = readl(_ICR(i2c));
206
207 icr &= ~ICR_START;
208 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB;
209
210 writel(icr, _ICR(i2c));
211
212 show_state(i2c);
213
214 msleep(1);
215 }
216
217 writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP),
218 _ICR(i2c));
219 }
220
221 static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
222 {
223 int timeout = DEF_TIMEOUT;
224
225 while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
226 if ((readl(_ISR(i2c)) & ISR_SAD) != 0)
227 timeout += 4;
228
229 msleep(2);
230 show_state(i2c);
231 }
232
233 if (timeout <= 0)
234 show_state(i2c);
235
236 return timeout <= 0 ? I2C_RETRY : 0;
237 }
238
239 static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
240 {
241 unsigned long timeout = jiffies + HZ*4;
242
243 while (time_before(jiffies, timeout)) {
244 if (i2c_debug > 1)
245 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
246 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
247
248 if (readl(_ISR(i2c)) & ISR_SAD) {
249 if (i2c_debug > 0)
250 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__);
251 goto out;
252 }
253
254 /* wait for unit and bus being not busy, and we also do a
255 * quick check of the i2c lines themselves to ensure they've
256 * gone high...
257 */
258 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 && readl(_IBMR(i2c)) == 3) {
259 if (i2c_debug > 0)
260 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
261 return 1;
262 }
263
264 msleep(1);
265 }
266
267 if (i2c_debug > 0)
268 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
269 out:
270 return 0;
271 }
272
273 static int i2c_pxa_set_master(struct pxa_i2c *i2c)
274 {
275 if (i2c_debug)
276 dev_dbg(&i2c->adap.dev, "setting to bus master\n");
277
278 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) {
279 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__);
280 if (!i2c_pxa_wait_master(i2c)) {
281 dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__);
282 return I2C_RETRY;
283 }
284 }
285
286 writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
287 return 0;
288 }
289
290 #ifdef CONFIG_I2C_PXA_SLAVE
291 static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
292 {
293 unsigned long timeout = jiffies + HZ*1;
294
295 /* wait for stop */
296
297 show_state(i2c);
298
299 while (time_before(jiffies, timeout)) {
300 if (i2c_debug > 1)
301 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
302 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
303
304 if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 ||
305 (readl(_ISR(i2c)) & ISR_SAD) != 0 ||
306 (readl(_ICR(i2c)) & ICR_SCLE) == 0) {
307 if (i2c_debug > 1)
308 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
309 return 1;
310 }
311
312 msleep(1);
313 }
314
315 if (i2c_debug > 0)
316 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
317 return 0;
318 }
319
320 /*
321 * clear the hold on the bus, and take of anything else
322 * that has been configured
323 */
324 static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
325 {
326 show_state(i2c);
327
328 if (errcode < 0) {
329 udelay(100); /* simple delay */
330 } else {
331 /* we need to wait for the stop condition to end */
332
333 /* if we where in stop, then clear... */
334 if (readl(_ICR(i2c)) & ICR_STOP) {
335 udelay(100);
336 writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c));
337 }
338
339 if (!i2c_pxa_wait_slave(i2c)) {
340 dev_err(&i2c->adap.dev, "%s: wait timedout\n",
341 __func__);
342 return;
343 }
344 }
345
346 writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c));
347 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
348
349 if (i2c_debug) {
350 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c)));
351 decode_ICR(readl(_ICR(i2c)));
352 }
353 }
354 #else
355 #define i2c_pxa_set_slave(i2c, err) do { } while (0)
356 #endif
357
358 static void i2c_pxa_reset(struct pxa_i2c *i2c)
359 {
360 pr_debug("Resetting I2C Controller Unit\n");
361
362 /* abort any transfer currently under way */
363 i2c_pxa_abort(i2c);
364
365 /* reset according to 9.8 */
366 writel(ICR_UR, _ICR(i2c));
367 writel(I2C_ISR_INIT, _ISR(i2c));
368 writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c));
369
370 writel(i2c->slave_addr, _ISAR(i2c));
371
372 /* set control register values */
373 writel(I2C_ICR_INIT, _ICR(i2c));
374
375 #ifdef CONFIG_I2C_PXA_SLAVE
376 dev_info(&i2c->adap.dev, "Enabling slave mode\n");
377 writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c));
378 #endif
379
380 i2c_pxa_set_slave(i2c, 0);
381
382 /* enable unit */
383 writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c));
384 udelay(100);
385 }
386
387
388 #ifdef CONFIG_I2C_PXA_SLAVE
389 /*
390 * PXA I2C Slave mode
391 */
392
393 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
394 {
395 if (isr & ISR_BED) {
396 /* what should we do here? */
397 } else {
398 int ret = 0;
399
400 if (i2c->slave != NULL)
401 ret = i2c->slave->read(i2c->slave->data);
402
403 writel(ret, _IDBR(i2c));
404 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); /* allow next byte */
405 }
406 }
407
408 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
409 {
410 unsigned int byte = readl(_IDBR(i2c));
411
412 if (i2c->slave != NULL)
413 i2c->slave->write(i2c->slave->data, byte);
414
415 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
416 }
417
418 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
419 {
420 int timeout;
421
422 if (i2c_debug > 0)
423 dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n",
424 (isr & ISR_RWM) ? 'r' : 't');
425
426 if (i2c->slave != NULL)
427 i2c->slave->event(i2c->slave->data,
428 (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE);
429
430 /*
431 * slave could interrupt in the middle of us generating a
432 * start condition... if this happens, we'd better back off
433 * and stop holding the poor thing up
434 */
435 writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
436 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
437
438 timeout = 0x10000;
439
440 while (1) {
441 if ((readl(_IBMR(i2c)) & 2) == 2)
442 break;
443
444 timeout--;
445
446 if (timeout <= 0) {
447 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
448 break;
449 }
450 }
451
452 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
453 }
454
455 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
456 {
457 if (i2c_debug > 2)
458 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n");
459
460 if (i2c->slave != NULL)
461 i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP);
462
463 if (i2c_debug > 2)
464 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n");
465
466 /*
467 * If we have a master-mode message waiting,
468 * kick it off now that the slave has completed.
469 */
470 if (i2c->msg)
471 i2c_pxa_master_complete(i2c, I2C_RETRY);
472 }
473 #else
474 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
475 {
476 if (isr & ISR_BED) {
477 /* what should we do here? */
478 } else {
479 writel(0, _IDBR(i2c));
480 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
481 }
482 }
483
484 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
485 {
486 writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
487 }
488
489 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
490 {
491 int timeout;
492
493 /*
494 * slave could interrupt in the middle of us generating a
495 * start condition... if this happens, we'd better back off
496 * and stop holding the poor thing up
497 */
498 writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
499 writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
500
501 timeout = 0x10000;
502
503 while (1) {
504 if ((readl(_IBMR(i2c)) & 2) == 2)
505 break;
506
507 timeout--;
508
509 if (timeout <= 0) {
510 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
511 break;
512 }
513 }
514
515 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
516 }
517
518 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
519 {
520 if (i2c->msg)
521 i2c_pxa_master_complete(i2c, I2C_RETRY);
522 }
523 #endif
524
525 /*
526 * PXA I2C Master mode
527 */
528
529 static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg)
530 {
531 unsigned int addr = (msg->addr & 0x7f) << 1;
532
533 if (msg->flags & I2C_M_RD)
534 addr |= 1;
535
536 return addr;
537 }
538
539 static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
540 {
541 u32 icr;
542
543 /*
544 * Step 1: target slave address into IDBR
545 */
546 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
547
548 /*
549 * Step 2: initiate the write.
550 */
551 icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
552 writel(icr | ICR_START | ICR_TB, _ICR(i2c));
553 }
554
555 static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c)
556 {
557 u32 icr;
558
559 /*
560 * Clear the STOP and ACK flags
561 */
562 icr = readl(_ICR(i2c));
563 icr &= ~(ICR_STOP | ICR_ACKNAK);
564 writel(icr, _ICR(i2c));
565 }
566
567 static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c)
568 {
569 /* make timeout the same as for interrupt based functions */
570 long timeout = 2 * DEF_TIMEOUT;
571
572 /*
573 * Wait for the bus to become free.
574 */
575 while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
576 udelay(1000);
577 show_state(i2c);
578 }
579
580 if (timeout <= 0) {
581 show_state(i2c);
582 dev_err(&i2c->adap.dev,
583 "i2c_pxa: timeout waiting for bus free\n");
584 return I2C_RETRY;
585 }
586
587 /*
588 * Set master mode.
589 */
590 writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
591
592 return 0;
593 }
594
595 static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c,
596 struct i2c_msg *msg, int num)
597 {
598 unsigned long timeout = 500000; /* 5 seconds */
599 int ret = 0;
600
601 ret = i2c_pxa_pio_set_master(i2c);
602 if (ret)
603 goto out;
604
605 i2c->msg = msg;
606 i2c->msg_num = num;
607 i2c->msg_idx = 0;
608 i2c->msg_ptr = 0;
609 i2c->irqlogidx = 0;
610
611 i2c_pxa_start_message(i2c);
612
613 while (timeout-- && i2c->msg_num > 0) {
614 i2c_pxa_handler(0, i2c);
615 udelay(10);
616 }
617
618 i2c_pxa_stop_message(i2c);
619
620 /*
621 * We place the return code in i2c->msg_idx.
622 */
623 ret = i2c->msg_idx;
624
625 out:
626 if (timeout == 0)
627 i2c_pxa_scream_blue_murder(i2c, "timeout");
628
629 return ret;
630 }
631
632 /*
633 * We are protected by the adapter bus mutex.
634 */
635 static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num)
636 {
637 long timeout;
638 int ret;
639
640 /*
641 * Wait for the bus to become free.
642 */
643 ret = i2c_pxa_wait_bus_not_busy(i2c);
644 if (ret) {
645 dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");
646 goto out;
647 }
648
649 /*
650 * Set master mode.
651 */
652 ret = i2c_pxa_set_master(i2c);
653 if (ret) {
654 dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);
655 goto out;
656 }
657
658 spin_lock_irq(&i2c->lock);
659
660 i2c->msg = msg;
661 i2c->msg_num = num;
662 i2c->msg_idx = 0;
663 i2c->msg_ptr = 0;
664 i2c->irqlogidx = 0;
665
666 i2c_pxa_start_message(i2c);
667
668 spin_unlock_irq(&i2c->lock);
669
670 /*
671 * The rest of the processing occurs in the interrupt handler.
672 */
673 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
674 i2c_pxa_stop_message(i2c);
675
676 /*
677 * We place the return code in i2c->msg_idx.
678 */
679 ret = i2c->msg_idx;
680
681 if (timeout == 0)
682 i2c_pxa_scream_blue_murder(i2c, "timeout");
683
684 out:
685 return ret;
686 }
687
688 static int i2c_pxa_pio_xfer(struct i2c_adapter *adap,
689 struct i2c_msg msgs[], int num)
690 {
691 struct pxa_i2c *i2c = adap->algo_data;
692 int ret, i;
693
694 /* If the I2C controller is disabled we need to reset it
695 (probably due to a suspend/resume destroying state). We do
696 this here as we can then avoid worrying about resuming the
697 controller before its users. */
698 if (!(readl(_ICR(i2c)) & ICR_IUE))
699 i2c_pxa_reset(i2c);
700
701 for (i = adap->retries; i >= 0; i--) {
702 ret = i2c_pxa_do_pio_xfer(i2c, msgs, num);
703 if (ret != I2C_RETRY)
704 goto out;
705
706 if (i2c_debug)
707 dev_dbg(&adap->dev, "Retrying transmission\n");
708 udelay(100);
709 }
710 i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
711 ret = -EREMOTEIO;
712 out:
713 i2c_pxa_set_slave(i2c, ret);
714 return ret;
715 }
716
717 /*
718 * i2c_pxa_master_complete - complete the message and wake up.
719 */
720 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret)
721 {
722 i2c->msg_ptr = 0;
723 i2c->msg = NULL;
724 i2c->msg_idx ++;
725 i2c->msg_num = 0;
726 if (ret)
727 i2c->msg_idx = ret;
728 if (!i2c->use_pio)
729 wake_up(&i2c->wait);
730 }
731
732 static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
733 {
734 u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
735
736 again:
737 /*
738 * If ISR_ALD is set, we lost arbitration.
739 */
740 if (isr & ISR_ALD) {
741 /*
742 * Do we need to do anything here? The PXA docs
743 * are vague about what happens.
744 */
745 i2c_pxa_scream_blue_murder(i2c, "ALD set");
746
747 /*
748 * We ignore this error. We seem to see spurious ALDs
749 * for seemingly no reason. If we handle them as I think
750 * they should, we end up causing an I2C error, which
751 * is painful for some systems.
752 */
753 return; /* ignore */
754 }
755
756 if (isr & ISR_BED) {
757 int ret = BUS_ERROR;
758
759 /*
760 * I2C bus error - either the device NAK'd us, or
761 * something more serious happened. If we were NAK'd
762 * on the initial address phase, we can retry.
763 */
764 if (isr & ISR_ACKNAK) {
765 if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)
766 ret = I2C_RETRY;
767 else
768 ret = XFER_NAKED;
769 }
770 i2c_pxa_master_complete(i2c, ret);
771 } else if (isr & ISR_RWM) {
772 /*
773 * Read mode. We have just sent the address byte, and
774 * now we must initiate the transfer.
775 */
776 if (i2c->msg_ptr == i2c->msg->len - 1 &&
777 i2c->msg_idx == i2c->msg_num - 1)
778 icr |= ICR_STOP | ICR_ACKNAK;
779
780 icr |= ICR_ALDIE | ICR_TB;
781 } else if (i2c->msg_ptr < i2c->msg->len) {
782 /*
783 * Write mode. Write the next data byte.
784 */
785 writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c));
786
787 icr |= ICR_ALDIE | ICR_TB;
788
789 /*
790 * If this is the last byte of the last message, send
791 * a STOP.
792 */
793 if (i2c->msg_ptr == i2c->msg->len &&
794 i2c->msg_idx == i2c->msg_num - 1)
795 icr |= ICR_STOP;
796 } else if (i2c->msg_idx < i2c->msg_num - 1) {
797 /*
798 * Next segment of the message.
799 */
800 i2c->msg_ptr = 0;
801 i2c->msg_idx ++;
802 i2c->msg++;
803
804 /*
805 * If we aren't doing a repeated start and address,
806 * go back and try to send the next byte. Note that
807 * we do not support switching the R/W direction here.
808 */
809 if (i2c->msg->flags & I2C_M_NOSTART)
810 goto again;
811
812 /*
813 * Write the next address.
814 */
815 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
816
817 /*
818 * And trigger a repeated start, and send the byte.
819 */
820 icr &= ~ICR_ALDIE;
821 icr |= ICR_START | ICR_TB;
822 } else {
823 if (i2c->msg->len == 0) {
824 /*
825 * Device probes have a message length of zero
826 * and need the bus to be reset before it can
827 * be used again.
828 */
829 i2c_pxa_reset(i2c);
830 }
831 i2c_pxa_master_complete(i2c, 0);
832 }
833
834 i2c->icrlog[i2c->irqlogidx-1] = icr;
835
836 writel(icr, _ICR(i2c));
837 show_state(i2c);
838 }
839
840 static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
841 {
842 u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
843
844 /*
845 * Read the byte.
846 */
847 i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c));
848
849 if (i2c->msg_ptr < i2c->msg->len) {
850 /*
851 * If this is the last byte of the last
852 * message, send a STOP.
853 */
854 if (i2c->msg_ptr == i2c->msg->len - 1)
855 icr |= ICR_STOP | ICR_ACKNAK;
856
857 icr |= ICR_ALDIE | ICR_TB;
858 } else {
859 i2c_pxa_master_complete(i2c, 0);
860 }
861
862 i2c->icrlog[i2c->irqlogidx-1] = icr;
863
864 writel(icr, _ICR(i2c));
865 }
866
867 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id)
868 {
869 struct pxa_i2c *i2c = dev_id;
870 u32 isr = readl(_ISR(i2c));
871
872 if (i2c_debug > 2 && 0) {
873 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
874 __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c)));
875 decode_ISR(isr);
876 }
877
878 if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog))
879 i2c->isrlog[i2c->irqlogidx++] = isr;
880
881 show_state(i2c);
882
883 /*
884 * Always clear all pending IRQs.
885 */
886 writel(isr & (ISR_SSD|ISR_ALD|ISR_ITE|ISR_IRF|ISR_SAD|ISR_BED), _ISR(i2c));
887
888 if (isr & ISR_SAD)
889 i2c_pxa_slave_start(i2c, isr);
890 if (isr & ISR_SSD)
891 i2c_pxa_slave_stop(i2c);
892
893 if (i2c_pxa_is_slavemode(i2c)) {
894 if (isr & ISR_ITE)
895 i2c_pxa_slave_txempty(i2c, isr);
896 if (isr & ISR_IRF)
897 i2c_pxa_slave_rxfull(i2c, isr);
898 } else if (i2c->msg) {
899 if (isr & ISR_ITE)
900 i2c_pxa_irq_txempty(i2c, isr);
901 if (isr & ISR_IRF)
902 i2c_pxa_irq_rxfull(i2c, isr);
903 } else {
904 i2c_pxa_scream_blue_murder(i2c, "spurious irq");
905 }
906
907 return IRQ_HANDLED;
908 }
909
910
911 static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
912 {
913 struct pxa_i2c *i2c = adap->algo_data;
914 int ret, i;
915
916 /* If the I2C controller is disabled we need to reset it (probably due
917 to a suspend/resume destroying state). We do this here as we can then
918 avoid worrying about resuming the controller before its users. */
919 if (!(readl(_ICR(i2c)) & ICR_IUE))
920 i2c_pxa_reset(i2c);
921
922 for (i = adap->retries; i >= 0; i--) {
923 ret = i2c_pxa_do_xfer(i2c, msgs, num);
924 if (ret != I2C_RETRY)
925 goto out;
926
927 if (i2c_debug)
928 dev_dbg(&adap->dev, "Retrying transmission\n");
929 udelay(100);
930 }
931 i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
932 ret = -EREMOTEIO;
933 out:
934 i2c_pxa_set_slave(i2c, ret);
935 return ret;
936 }
937
938 static u32 i2c_pxa_functionality(struct i2c_adapter *adap)
939 {
940 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
941 }
942
943 static const struct i2c_algorithm i2c_pxa_algorithm = {
944 .master_xfer = i2c_pxa_xfer,
945 .functionality = i2c_pxa_functionality,
946 };
947
948 static const struct i2c_algorithm i2c_pxa_pio_algorithm = {
949 .master_xfer = i2c_pxa_pio_xfer,
950 .functionality = i2c_pxa_functionality,
951 };
952
953 static void i2c_pxa_enable(struct platform_device *dev)
954 {
955 if (cpu_is_pxa27x()) {
956 switch (dev->id) {
957 case 0:
958 pxa_gpio_mode(GPIO117_I2CSCL_MD);
959 pxa_gpio_mode(GPIO118_I2CSDA_MD);
960 break;
961 case 1:
962 local_irq_disable();
963 PCFR |= PCFR_PI2CEN;
964 local_irq_enable();
965 break;
966 }
967 }
968 }
969
970 static void i2c_pxa_disable(struct platform_device *dev)
971 {
972 if (cpu_is_pxa27x() && dev->id == 1) {
973 local_irq_disable();
974 PCFR &= ~PCFR_PI2CEN;
975 local_irq_enable();
976 }
977 }
978
979 #define res_len(r) ((r)->end - (r)->start + 1)
980 static int i2c_pxa_probe(struct platform_device *dev)
981 {
982 struct pxa_i2c *i2c;
983 struct resource *res;
984 struct i2c_pxa_platform_data *plat = dev->dev.platform_data;
985 int ret;
986 int irq;
987
988 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
989 irq = platform_get_irq(dev, 0);
990 if (res == NULL || irq < 0)
991 return -ENODEV;
992
993 if (!request_mem_region(res->start, res_len(res), res->name))
994 return -ENOMEM;
995
996 i2c = kzalloc(sizeof(struct pxa_i2c), GFP_KERNEL);
997 if (!i2c) {
998 ret = -ENOMEM;
999 goto emalloc;
1000 }
1001
1002 i2c->adap.owner = THIS_MODULE;
1003 i2c->adap.retries = 5;
1004
1005 spin_lock_init(&i2c->lock);
1006 init_waitqueue_head(&i2c->wait);
1007
1008 <<<<<<< HEAD:drivers/i2c/busses/i2c-pxa.c
1009 sprintf(i2c->adap.name, "pxa_i2c-i2c.%u", dev->id);
1010 =======
1011 /*
1012 * If "dev->id" is negative we consider it as zero.
1013 * The reason to do so is to avoid sysfs names that only make
1014 * sense when there are multiple adapters.
1015 */
1016 i2c->adap.nr = dev->id != -1 ? dev->id : 0;
1017 snprintf(i2c->adap.name, sizeof(i2c->adap.name), "pxa_i2c-i2c.%u",
1018 i2c->adap.nr);
1019 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/i2c/busses/i2c-pxa.c
1020
1021 i2c->clk = clk_get(&dev->dev, "I2CCLK");
1022 if (IS_ERR(i2c->clk)) {
1023 ret = PTR_ERR(i2c->clk);
1024 goto eclk;
1025 }
1026
1027 i2c->reg_base = ioremap(res->start, res_len(res));
1028 if (!i2c->reg_base) {
1029 ret = -EIO;
1030 goto eremap;
1031 }
1032
1033 i2c->iobase = res->start;
1034 i2c->iosize = res_len(res);
1035
1036 i2c->irq = irq;
1037
1038 i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
1039
1040 #ifdef CONFIG_I2C_PXA_SLAVE
1041 if (plat) {
1042 i2c->slave_addr = plat->slave_addr;
1043 i2c->slave = plat->slave;
1044 }
1045 #endif
1046
1047 clk_enable(i2c->clk);
1048 i2c_pxa_enable(dev);
1049
1050 if (plat) {
1051 i2c->adap.class = plat->class;
1052 i2c->use_pio = plat->use_pio;
1053 }
1054
1055 if (i2c->use_pio) {
1056 i2c->adap.algo = &i2c_pxa_pio_algorithm;
1057 } else {
1058 i2c->adap.algo = &i2c_pxa_algorithm;
1059 ret = request_irq(irq, i2c_pxa_handler, IRQF_DISABLED,
1060 i2c->adap.name, i2c);
1061 if (ret)
1062 goto ereqirq;
1063 }
1064
1065 i2c_pxa_reset(i2c);
1066
1067 i2c->adap.algo_data = i2c;
1068 i2c->adap.dev.parent = &dev->dev;
1069
1070 <<<<<<< HEAD:drivers/i2c/busses/i2c-pxa.c
1071 /*
1072 * If "dev->id" is negative we consider it as zero.
1073 * The reason to do so is to avoid sysfs names that only make
1074 * sense when there are multiple adapters.
1075 */
1076 i2c->adap.nr = dev->id != -1 ? dev->id : 0;
1077
1078 =======
1079 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/i2c/busses/i2c-pxa.c
1080 ret = i2c_add_numbered_adapter(&i2c->adap);
1081 if (ret < 0) {
1082 printk(KERN_INFO "I2C: Failed to add bus\n");
1083 goto eadapt;
1084 }
1085
1086 platform_set_drvdata(dev, i2c);
1087
1088 #ifdef CONFIG_I2C_PXA_SLAVE
1089 printk(KERN_INFO "I2C: %s: PXA I2C adapter, slave address %d\n",
1090 i2c->adap.dev.bus_id, i2c->slave_addr);
1091 #else
1092 printk(KERN_INFO "I2C: %s: PXA I2C adapter\n",
1093 i2c->adap.dev.bus_id);
1094 #endif
1095 return 0;
1096
1097 eadapt:
1098 if (!i2c->use_pio)
1099 free_irq(irq, i2c);
1100 ereqirq:
1101 clk_disable(i2c->clk);
1102 i2c_pxa_disable(dev);
1103 <<<<<<< HEAD:drivers/i2c/busses/i2c-pxa.c
1104 =======
1105 iounmap(i2c->reg_base);
1106 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/i2c/busses/i2c-pxa.c
1107 eremap:
1108 clk_put(i2c->clk);
1109 eclk:
1110 kfree(i2c);
1111 emalloc:
1112 release_mem_region(res->start, res_len(res));
1113 return ret;
1114 }
1115
1116 <<<<<<< HEAD:drivers/i2c/busses/i2c-pxa.c
1117 static int i2c_pxa_remove(struct platform_device *dev)
1118 =======
1119 static int __exit i2c_pxa_remove(struct platform_device *dev)
1120 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/i2c/busses/i2c-pxa.c
1121 {
1122 struct pxa_i2c *i2c = platform_get_drvdata(dev);
1123
1124 platform_set_drvdata(dev, NULL);
1125
1126 i2c_del_adapter(&i2c->adap);
1127 if (!i2c->use_pio)
1128 free_irq(i2c->irq, i2c);
1129
1130 clk_disable(i2c->clk);
1131 clk_put(i2c->clk);
1132 i2c_pxa_disable(dev);
1133
1134 <<<<<<< HEAD:drivers/i2c/busses/i2c-pxa.c
1135 =======
1136 iounmap(i2c->reg_base);
1137 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/i2c/busses/i2c-pxa.c
1138 release_mem_region(i2c->iobase, i2c->iosize);
1139 kfree(i2c);
1140
1141 return 0;
1142 }
1143
1144 static struct platform_driver i2c_pxa_driver = {
1145 .probe = i2c_pxa_probe,
1146 <<<<<<< HEAD:drivers/i2c/busses/i2c-pxa.c
1147 .remove = i2c_pxa_remove,
1148 =======
1149 .remove = __exit_p(i2c_pxa_remove),
1150 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/i2c/busses/i2c-pxa.c
1151 .driver = {
1152 .name = "pxa2xx-i2c",
1153 <<<<<<< HEAD:drivers/i2c/busses/i2c-pxa.c
1154 =======
1155 .owner = THIS_MODULE,
1156 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/i2c/busses/i2c-pxa.c
1157 },
1158 };
1159
1160 static int __init i2c_adap_pxa_init(void)
1161 {
1162 return platform_driver_register(&i2c_pxa_driver);
1163 }
1164
1165 <<<<<<< HEAD:drivers/i2c/busses/i2c-pxa.c
1166 static void i2c_adap_pxa_exit(void)
1167 =======
1168 static void __exit i2c_adap_pxa_exit(void)
1169 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/i2c/busses/i2c-pxa.c
1170 {
1171 <<<<<<< HEAD:drivers/i2c/busses/i2c-pxa.c
1172 return platform_driver_unregister(&i2c_pxa_driver);
1173 =======
1174 platform_driver_unregister(&i2c_pxa_driver);
1175 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/i2c/busses/i2c-pxa.c
1176 }
1177
1178 MODULE_LICENSE("GPL");
1179
1180 module_init(i2c_adap_pxa_init);
1181 module_exit(i2c_adap_pxa_exit);
WRT350N Kernel Patches