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Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / drivers / net / s2io.c
blobc0af8b1c328383b6219d88e93b286c29743038d6
1 /************************************************************************
2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3 * Copyright(c) 2002-2007 Neterion Inc.
4
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 *
13 * Credits:
14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
21 * Francois Romieu : For pointing out all code part that were
22 * deprecated and also styling related comments.
23 * Grant Grundler : For helping me get rid of some Architecture
24 * dependent code.
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
26 *
27 * The module loadable parameters that are supported by the driver and a brief
28 * explaination of all the variables.
29 *
30 * rx_ring_num : This can be used to program the number of receive rings used
31 * in the driver.
32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
35 * values are 1, 2.
36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
38 * Tx descriptors that can be associated with each corresponding FIFO.
39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40 * 2(MSI_X). Default value is '2(MSI_X)'
41 * lro_enable: Specifies whether to enable Large Receive Offload (LRO) or not.
42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
45 * napi: This parameter used to enable/disable NAPI (polling Rx)
46 * Possible values '1' for enable and '0' for disable. Default is '1'
47 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
48 * Possible values '1' for enable and '0' for disable. Default is '0'
49 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
50 * Possible values '1' for enable , '0' for disable.
51 * Default is '2' - which means disable in promisc mode
52 * and enable in non-promiscuous mode.
53 ************************************************************************/
54
55 #include <linux/module.h>
56 #include <linux/types.h>
57 #include <linux/errno.h>
58 #include <linux/ioport.h>
59 #include <linux/pci.h>
60 #include <linux/dma-mapping.h>
61 #include <linux/kernel.h>
62 #include <linux/netdevice.h>
63 #include <linux/etherdevice.h>
64 #include <linux/skbuff.h>
65 #include <linux/init.h>
66 #include <linux/delay.h>
67 #include <linux/stddef.h>
68 #include <linux/ioctl.h>
69 #include <linux/timex.h>
70 #include <linux/ethtool.h>
71 #include <linux/workqueue.h>
72 #include <linux/if_vlan.h>
73 #include <linux/ip.h>
74 #include <linux/tcp.h>
75 #include <net/tcp.h>
76
77 #include <asm/system.h>
78 #include <asm/uaccess.h>
79 #include <asm/io.h>
80 #include <asm/div64.h>
81 #include <asm/irq.h>
82
83 /* local include */
84 #include "s2io.h"
85 #include "s2io-regs.h"
86
87 #define DRV_VERSION "2.0.26.15-2"
88
89 /* S2io Driver name & version. */
90 static char s2io_driver_name[] = "Neterion";
91 static char s2io_driver_version[] = DRV_VERSION;
92
93 static int rxd_size[2] = {32,48};
94 static int rxd_count[2] = {127,85};
95
96 static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
97 {
98 int ret;
99
100 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
101 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
102
103 return ret;
104 }
105
106 /*
107 * Cards with following subsystem_id have a link state indication
108 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
109 * macro below identifies these cards given the subsystem_id.
110 */
111 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
112 (dev_type == XFRAME_I_DEVICE) ? \
113 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
114 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
115
116 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
117 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
118 #define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
119 #define PANIC 1
120 #define LOW 2
121 static inline int rx_buffer_level(struct s2io_nic * sp, int rxb_size, int ring)
122 {
123 struct mac_info *mac_control;
124
125 mac_control = &sp->mac_control;
126 if (rxb_size <= rxd_count[sp->rxd_mode])
127 return PANIC;
128 else if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16)
129 return LOW;
130 return 0;
131 }
132
133 static inline int is_s2io_card_up(const struct s2io_nic * sp)
134 {
135 return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
136 }
137
138 /* Ethtool related variables and Macros. */
139 static char s2io_gstrings[][ETH_GSTRING_LEN] = {
140 "Register test\t(offline)",
141 "Eeprom test\t(offline)",
142 "Link test\t(online)",
143 "RLDRAM test\t(offline)",
144 "BIST Test\t(offline)"
145 };
146
147 static char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
148 {"tmac_frms"},
149 {"tmac_data_octets"},
150 {"tmac_drop_frms"},
151 {"tmac_mcst_frms"},
152 {"tmac_bcst_frms"},
153 {"tmac_pause_ctrl_frms"},
154 {"tmac_ttl_octets"},
155 {"tmac_ucst_frms"},
156 {"tmac_nucst_frms"},
157 {"tmac_any_err_frms"},
158 {"tmac_ttl_less_fb_octets"},
159 {"tmac_vld_ip_octets"},
160 {"tmac_vld_ip"},
161 {"tmac_drop_ip"},
162 {"tmac_icmp"},
163 {"tmac_rst_tcp"},
164 {"tmac_tcp"},
165 {"tmac_udp"},
166 {"rmac_vld_frms"},
167 {"rmac_data_octets"},
168 {"rmac_fcs_err_frms"},
169 {"rmac_drop_frms"},
170 {"rmac_vld_mcst_frms"},
171 {"rmac_vld_bcst_frms"},
172 {"rmac_in_rng_len_err_frms"},
173 {"rmac_out_rng_len_err_frms"},
174 {"rmac_long_frms"},
175 {"rmac_pause_ctrl_frms"},
176 {"rmac_unsup_ctrl_frms"},
177 {"rmac_ttl_octets"},
178 {"rmac_accepted_ucst_frms"},
179 {"rmac_accepted_nucst_frms"},
180 {"rmac_discarded_frms"},
181 {"rmac_drop_events"},
182 {"rmac_ttl_less_fb_octets"},
183 {"rmac_ttl_frms"},
184 {"rmac_usized_frms"},
185 {"rmac_osized_frms"},
186 {"rmac_frag_frms"},
187 {"rmac_jabber_frms"},
188 {"rmac_ttl_64_frms"},
189 {"rmac_ttl_65_127_frms"},
190 {"rmac_ttl_128_255_frms"},
191 {"rmac_ttl_256_511_frms"},
192 {"rmac_ttl_512_1023_frms"},
193 {"rmac_ttl_1024_1518_frms"},
194 {"rmac_ip"},
195 {"rmac_ip_octets"},
196 {"rmac_hdr_err_ip"},
197 {"rmac_drop_ip"},
198 {"rmac_icmp"},
199 {"rmac_tcp"},
200 {"rmac_udp"},
201 {"rmac_err_drp_udp"},
202 {"rmac_xgmii_err_sym"},
203 {"rmac_frms_q0"},
204 {"rmac_frms_q1"},
205 {"rmac_frms_q2"},
206 {"rmac_frms_q3"},
207 {"rmac_frms_q4"},
208 {"rmac_frms_q5"},
209 {"rmac_frms_q6"},
210 {"rmac_frms_q7"},
211 {"rmac_full_q0"},
212 {"rmac_full_q1"},
213 {"rmac_full_q2"},
214 {"rmac_full_q3"},
215 {"rmac_full_q4"},
216 {"rmac_full_q5"},
217 {"rmac_full_q6"},
218 {"rmac_full_q7"},
219 {"rmac_pause_cnt"},
220 {"rmac_xgmii_data_err_cnt"},
221 {"rmac_xgmii_ctrl_err_cnt"},
222 {"rmac_accepted_ip"},
223 {"rmac_err_tcp"},
224 {"rd_req_cnt"},
225 {"new_rd_req_cnt"},
226 {"new_rd_req_rtry_cnt"},
227 {"rd_rtry_cnt"},
228 {"wr_rtry_rd_ack_cnt"},
229 {"wr_req_cnt"},
230 {"new_wr_req_cnt"},
231 {"new_wr_req_rtry_cnt"},
232 {"wr_rtry_cnt"},
233 {"wr_disc_cnt"},
234 {"rd_rtry_wr_ack_cnt"},
235 {"txp_wr_cnt"},
236 {"txd_rd_cnt"},
237 {"txd_wr_cnt"},
238 {"rxd_rd_cnt"},
239 {"rxd_wr_cnt"},
240 {"txf_rd_cnt"},
241 {"rxf_wr_cnt"}
242 };
243
244 static char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
245 {"rmac_ttl_1519_4095_frms"},
246 {"rmac_ttl_4096_8191_frms"},
247 {"rmac_ttl_8192_max_frms"},
248 {"rmac_ttl_gt_max_frms"},
249 {"rmac_osized_alt_frms"},
250 {"rmac_jabber_alt_frms"},
251 {"rmac_gt_max_alt_frms"},
252 {"rmac_vlan_frms"},
253 {"rmac_len_discard"},
254 {"rmac_fcs_discard"},
255 {"rmac_pf_discard"},
256 {"rmac_da_discard"},
257 {"rmac_red_discard"},
258 {"rmac_rts_discard"},
259 {"rmac_ingm_full_discard"},
260 {"link_fault_cnt"}
261 };
262
263 static char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
264 {"\n DRIVER STATISTICS"},
265 {"single_bit_ecc_errs"},
266 {"double_bit_ecc_errs"},
267 {"parity_err_cnt"},
268 {"serious_err_cnt"},
269 {"soft_reset_cnt"},
270 {"fifo_full_cnt"},
271 {"ring_0_full_cnt"},
272 {"ring_1_full_cnt"},
273 {"ring_2_full_cnt"},
274 {"ring_3_full_cnt"},
275 {"ring_4_full_cnt"},
276 {"ring_5_full_cnt"},
277 {"ring_6_full_cnt"},
278 {"ring_7_full_cnt"},
279 {"alarm_transceiver_temp_high"},
280 {"alarm_transceiver_temp_low"},
281 {"alarm_laser_bias_current_high"},
282 {"alarm_laser_bias_current_low"},
283 {"alarm_laser_output_power_high"},
284 {"alarm_laser_output_power_low"},
285 {"warn_transceiver_temp_high"},
286 {"warn_transceiver_temp_low"},
287 {"warn_laser_bias_current_high"},
288 {"warn_laser_bias_current_low"},
289 {"warn_laser_output_power_high"},
290 {"warn_laser_output_power_low"},
291 {"lro_aggregated_pkts"},
292 {"lro_flush_both_count"},
293 {"lro_out_of_sequence_pkts"},
294 {"lro_flush_due_to_max_pkts"},
295 {"lro_avg_aggr_pkts"},
296 {"mem_alloc_fail_cnt"},
297 {"pci_map_fail_cnt"},
298 {"watchdog_timer_cnt"},
299 {"mem_allocated"},
300 {"mem_freed"},
301 {"link_up_cnt"},
302 {"link_down_cnt"},
303 {"link_up_time"},
304 {"link_down_time"},
305 {"tx_tcode_buf_abort_cnt"},
306 {"tx_tcode_desc_abort_cnt"},
307 {"tx_tcode_parity_err_cnt"},
308 {"tx_tcode_link_loss_cnt"},
309 {"tx_tcode_list_proc_err_cnt"},
310 {"rx_tcode_parity_err_cnt"},
311 {"rx_tcode_abort_cnt"},
312 {"rx_tcode_parity_abort_cnt"},
313 {"rx_tcode_rda_fail_cnt"},
314 {"rx_tcode_unkn_prot_cnt"},
315 {"rx_tcode_fcs_err_cnt"},
316 {"rx_tcode_buf_size_err_cnt"},
317 {"rx_tcode_rxd_corrupt_cnt"},
318 {"rx_tcode_unkn_err_cnt"},
319 {"tda_err_cnt"},
320 {"pfc_err_cnt"},
321 {"pcc_err_cnt"},
322 {"tti_err_cnt"},
323 {"tpa_err_cnt"},
324 {"sm_err_cnt"},
325 {"lso_err_cnt"},
326 {"mac_tmac_err_cnt"},
327 {"mac_rmac_err_cnt"},
328 {"xgxs_txgxs_err_cnt"},
329 {"xgxs_rxgxs_err_cnt"},
330 {"rc_err_cnt"},
331 {"prc_pcix_err_cnt"},
332 {"rpa_err_cnt"},
333 {"rda_err_cnt"},
334 {"rti_err_cnt"},
335 {"mc_err_cnt"}
336 };
337
338 #define S2IO_XENA_STAT_LEN ARRAY_SIZE(ethtool_xena_stats_keys)
339 #define S2IO_ENHANCED_STAT_LEN ARRAY_SIZE(ethtool_enhanced_stats_keys)
340 #define S2IO_DRIVER_STAT_LEN ARRAY_SIZE(ethtool_driver_stats_keys)
341
342 #define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN )
343 #define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN )
344
345 #define XFRAME_I_STAT_STRINGS_LEN ( XFRAME_I_STAT_LEN * ETH_GSTRING_LEN )
346 #define XFRAME_II_STAT_STRINGS_LEN ( XFRAME_II_STAT_LEN * ETH_GSTRING_LEN )
347
348 #define S2IO_TEST_LEN ARRAY_SIZE(s2io_gstrings)
349 #define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
350
351 #define S2IO_TIMER_CONF(timer, handle, arg, exp) \
352 init_timer(&timer); \
353 timer.function = handle; \
354 timer.data = (unsigned long) arg; \
355 mod_timer(&timer, (jiffies + exp)) \
356
357 /* copy mac addr to def_mac_addr array */
358 static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
359 {
360 sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
361 sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
362 sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
363 sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
364 sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
365 sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
366 }
367 /* Add the vlan */
368 static void s2io_vlan_rx_register(struct net_device *dev,
369 struct vlan_group *grp)
370 {
371 int i;
372 struct s2io_nic *nic = dev->priv;
373 unsigned long flags[MAX_TX_FIFOS];
374 struct mac_info *mac_control = &nic->mac_control;
375 struct config_param *config = &nic->config;
376
377 for (i = 0; i < config->tx_fifo_num; i++)
378 spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags[i]);
379
380 nic->vlgrp = grp;
381 for (i = config->tx_fifo_num - 1; i >= 0; i--)
382 spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock,
383 flags[i]);
384 }
385
386 /* A flag indicating whether 'RX_PA_CFG_STRIP_VLAN_TAG' bit is set or not */
387 static int vlan_strip_flag;
388
389 /*
390 * Constants to be programmed into the Xena's registers, to configure
391 * the XAUI.
392 */
393
394 #define END_SIGN 0x0
395 static const u64 herc_act_dtx_cfg[] = {
396 /* Set address */
397 0x8000051536750000ULL, 0x80000515367500E0ULL,
398 /* Write data */
399 0x8000051536750004ULL, 0x80000515367500E4ULL,
400 /* Set address */
401 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
402 /* Write data */
403 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
404 /* Set address */
405 0x801205150D440000ULL, 0x801205150D4400E0ULL,
406 /* Write data */
407 0x801205150D440004ULL, 0x801205150D4400E4ULL,
408 /* Set address */
409 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
410 /* Write data */
411 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
412 /* Done */
413 END_SIGN
414 };
415
416 static const u64 xena_dtx_cfg[] = {
417 /* Set address */
418 0x8000051500000000ULL, 0x80000515000000E0ULL,
419 /* Write data */
420 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
421 /* Set address */
422 0x8001051500000000ULL, 0x80010515000000E0ULL,
423 /* Write data */
424 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
425 /* Set address */
426 0x8002051500000000ULL, 0x80020515000000E0ULL,
427 /* Write data */
428 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
429 END_SIGN
430 };
431
432 /*
433 * Constants for Fixing the MacAddress problem seen mostly on
434 * Alpha machines.
435 */
436 static const u64 fix_mac[] = {
437 0x0060000000000000ULL, 0x0060600000000000ULL,
438 0x0040600000000000ULL, 0x0000600000000000ULL,
439 0x0020600000000000ULL, 0x0060600000000000ULL,
440 0x0020600000000000ULL, 0x0060600000000000ULL,
441 0x0020600000000000ULL, 0x0060600000000000ULL,
442 0x0020600000000000ULL, 0x0060600000000000ULL,
443 0x0020600000000000ULL, 0x0060600000000000ULL,
444 0x0020600000000000ULL, 0x0060600000000000ULL,
445 0x0020600000000000ULL, 0x0060600000000000ULL,
446 0x0020600000000000ULL, 0x0060600000000000ULL,
447 0x0020600000000000ULL, 0x0060600000000000ULL,
448 0x0020600000000000ULL, 0x0060600000000000ULL,
449 0x0020600000000000ULL, 0x0000600000000000ULL,
450 0x0040600000000000ULL, 0x0060600000000000ULL,
451 END_SIGN
452 };
453
454 MODULE_LICENSE("GPL");
455 MODULE_VERSION(DRV_VERSION);
456
457
458 /* Module Loadable parameters. */
459 S2IO_PARM_INT(tx_fifo_num, 1);
460 S2IO_PARM_INT(rx_ring_num, 1);
461
462
463 S2IO_PARM_INT(rx_ring_mode, 1);
464 S2IO_PARM_INT(use_continuous_tx_intrs, 1);
465 S2IO_PARM_INT(rmac_pause_time, 0x100);
466 S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
467 S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
468 S2IO_PARM_INT(shared_splits, 0);
469 S2IO_PARM_INT(tmac_util_period, 5);
470 S2IO_PARM_INT(rmac_util_period, 5);
471 S2IO_PARM_INT(l3l4hdr_size, 128);
472 /* Frequency of Rx desc syncs expressed as power of 2 */
473 S2IO_PARM_INT(rxsync_frequency, 3);
474 /* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
475 S2IO_PARM_INT(intr_type, 2);
476 /* Large receive offload feature */
477 static unsigned int lro_enable;
478 module_param_named(lro, lro_enable, uint, 0);
479
480 /* Max pkts to be aggregated by LRO at one time. If not specified,
481 * aggregation happens until we hit max IP pkt size(64K)
482 */
483 S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
484 S2IO_PARM_INT(indicate_max_pkts, 0);
485
486 S2IO_PARM_INT(napi, 1);
487 S2IO_PARM_INT(ufo, 0);
488 S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
489
490 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
491 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
492 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
493 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
494 static unsigned int rts_frm_len[MAX_RX_RINGS] =
495 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
496
497 module_param_array(tx_fifo_len, uint, NULL, 0);
498 module_param_array(rx_ring_sz, uint, NULL, 0);
499 module_param_array(rts_frm_len, uint, NULL, 0);
500
501 /*
502 * S2IO device table.
503 * This table lists all the devices that this driver supports.
504 */
505 static struct pci_device_id s2io_tbl[] __devinitdata = {
506 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
507 PCI_ANY_ID, PCI_ANY_ID},
508 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
509 PCI_ANY_ID, PCI_ANY_ID},
510 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
511 PCI_ANY_ID, PCI_ANY_ID},
512 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
513 PCI_ANY_ID, PCI_ANY_ID},
514 {0,}
515 };
516
517 MODULE_DEVICE_TABLE(pci, s2io_tbl);
518
519 static struct pci_error_handlers s2io_err_handler = {
520 .error_detected = s2io_io_error_detected,
521 .slot_reset = s2io_io_slot_reset,
522 .resume = s2io_io_resume,
523 };
524
525 static struct pci_driver s2io_driver = {
526 .name = "S2IO",
527 .id_table = s2io_tbl,
528 .probe = s2io_init_nic,
529 .remove = __devexit_p(s2io_rem_nic),
530 .err_handler = &s2io_err_handler,
531 };
532
533 /* A simplifier macro used both by init and free shared_mem Fns(). */
534 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
535
536 /**
537 * init_shared_mem - Allocation and Initialization of Memory
538 * @nic: Device private variable.
539 * Description: The function allocates all the memory areas shared
540 * between the NIC and the driver. This includes Tx descriptors,
541 * Rx descriptors and the statistics block.
542 */
543
544 static int init_shared_mem(struct s2io_nic *nic)
545 {
546 u32 size;
547 void *tmp_v_addr, *tmp_v_addr_next;
548 dma_addr_t tmp_p_addr, tmp_p_addr_next;
549 struct RxD_block *pre_rxd_blk = NULL;
550 int i, j, blk_cnt;
551 int lst_size, lst_per_page;
552 struct net_device *dev = nic->dev;
553 unsigned long tmp;
554 struct buffAdd *ba;
555
556 struct mac_info *mac_control;
557 struct config_param *config;
558 unsigned long long mem_allocated = 0;
559
560 mac_control = &nic->mac_control;
561 config = &nic->config;
562
563
564 /* Allocation and initialization of TXDLs in FIOFs */
565 size = 0;
566 for (i = 0; i < config->tx_fifo_num; i++) {
567 size += config->tx_cfg[i].fifo_len;
568 }
569 if (size > MAX_AVAILABLE_TXDS) {
570 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
571 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
572 return -EINVAL;
573 }
574
575 size = 0;
576 for (i = 0; i < config->tx_fifo_num; i++) {
577 size = config->tx_cfg[i].fifo_len;
578 /*
579 * Legal values are from 2 to 8192
580 */
581 if (size < 2) {
582 DBG_PRINT(ERR_DBG, "s2io: Invalid fifo len (%d)", size);
583 DBG_PRINT(ERR_DBG, "for fifo %d\n", i);
584 DBG_PRINT(ERR_DBG, "s2io: Legal values for fifo len"
585 "are 2 to 8192\n");
586 return -EINVAL;
587 }
588 }
589
590 lst_size = (sizeof(struct TxD) * config->max_txds);
591 lst_per_page = PAGE_SIZE / lst_size;
592
593 for (i = 0; i < config->tx_fifo_num; i++) {
594 int fifo_len = config->tx_cfg[i].fifo_len;
595 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
596 mac_control->fifos[i].list_info = kzalloc(list_holder_size,
597 GFP_KERNEL);
598 if (!mac_control->fifos[i].list_info) {
599 DBG_PRINT(INFO_DBG,
600 "Malloc failed for list_info\n");
601 return -ENOMEM;
602 }
603 mem_allocated += list_holder_size;
604 }
605 for (i = 0; i < config->tx_fifo_num; i++) {
606 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
607 lst_per_page);
608 mac_control->fifos[i].tx_curr_put_info.offset = 0;
609 mac_control->fifos[i].tx_curr_put_info.fifo_len =
610 config->tx_cfg[i].fifo_len - 1;
611 mac_control->fifos[i].tx_curr_get_info.offset = 0;
612 mac_control->fifos[i].tx_curr_get_info.fifo_len =
613 config->tx_cfg[i].fifo_len - 1;
614 mac_control->fifos[i].fifo_no = i;
615 mac_control->fifos[i].nic = nic;
616 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
617
618 for (j = 0; j < page_num; j++) {
619 int k = 0;
620 dma_addr_t tmp_p;
621 void *tmp_v;
622 tmp_v = pci_alloc_consistent(nic->pdev,
623 PAGE_SIZE, &tmp_p);
624 if (!tmp_v) {
625 DBG_PRINT(INFO_DBG,
626 "pci_alloc_consistent ");
627 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
628 return -ENOMEM;
629 }
630 /* If we got a zero DMA address(can happen on
631 * certain platforms like PPC), reallocate.
632 * Store virtual address of page we don't want,
633 * to be freed later.
634 */
635 if (!tmp_p) {
636 mac_control->zerodma_virt_addr = tmp_v;
637 DBG_PRINT(INIT_DBG,
638 "%s: Zero DMA address for TxDL. ", dev->name);
639 DBG_PRINT(INIT_DBG,
640 "Virtual address %p\n", tmp_v);
641 tmp_v = pci_alloc_consistent(nic->pdev,
642 PAGE_SIZE, &tmp_p);
643 if (!tmp_v) {
644 DBG_PRINT(INFO_DBG,
645 "pci_alloc_consistent ");
646 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
647 return -ENOMEM;
648 }
649 mem_allocated += PAGE_SIZE;
650 }
651 while (k < lst_per_page) {
652 int l = (j * lst_per_page) + k;
653 if (l == config->tx_cfg[i].fifo_len)
654 break;
655 mac_control->fifos[i].list_info[l].list_virt_addr =
656 tmp_v + (k * lst_size);
657 mac_control->fifos[i].list_info[l].list_phy_addr =
658 tmp_p + (k * lst_size);
659 k++;
660 }
661 }
662 }
663
664 for (i = 0; i < config->tx_fifo_num; i++) {
665 size = config->tx_cfg[i].fifo_len;
666 mac_control->fifos[i].ufo_in_band_v
667 = kcalloc(size, sizeof(u64), GFP_KERNEL);
668 if (!mac_control->fifos[i].ufo_in_band_v)
669 return -ENOMEM;
670 mem_allocated += (size * sizeof(u64));
671 }
672
673 /* Allocation and initialization of RXDs in Rings */
674 size = 0;
675 for (i = 0; i < config->rx_ring_num; i++) {
676 if (config->rx_cfg[i].num_rxd %
677 (rxd_count[nic->rxd_mode] + 1)) {
678 DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
679 DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
680 i);
681 DBG_PRINT(ERR_DBG, "RxDs per Block");
682 return FAILURE;
683 }
684 size += config->rx_cfg[i].num_rxd;
685 mac_control->rings[i].block_count =
686 config->rx_cfg[i].num_rxd /
687 (rxd_count[nic->rxd_mode] + 1 );
688 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
689 mac_control->rings[i].block_count;
690 }
691 if (nic->rxd_mode == RXD_MODE_1)
692 size = (size * (sizeof(struct RxD1)));
693 else
694 size = (size * (sizeof(struct RxD3)));
695
696 for (i = 0; i < config->rx_ring_num; i++) {
697 mac_control->rings[i].rx_curr_get_info.block_index = 0;
698 mac_control->rings[i].rx_curr_get_info.offset = 0;
699 mac_control->rings[i].rx_curr_get_info.ring_len =
700 config->rx_cfg[i].num_rxd - 1;
701 mac_control->rings[i].rx_curr_put_info.block_index = 0;
702 mac_control->rings[i].rx_curr_put_info.offset = 0;
703 mac_control->rings[i].rx_curr_put_info.ring_len =
704 config->rx_cfg[i].num_rxd - 1;
705 mac_control->rings[i].nic = nic;
706 mac_control->rings[i].ring_no = i;
707
708 blk_cnt = config->rx_cfg[i].num_rxd /
709 (rxd_count[nic->rxd_mode] + 1);
710 /* Allocating all the Rx blocks */
711 for (j = 0; j < blk_cnt; j++) {
712 struct rx_block_info *rx_blocks;
713 int l;
714
715 rx_blocks = &mac_control->rings[i].rx_blocks[j];
716 size = SIZE_OF_BLOCK; //size is always page size
717 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
718 &tmp_p_addr);
719 if (tmp_v_addr == NULL) {
720 /*
721 * In case of failure, free_shared_mem()
722 * is called, which should free any
723 * memory that was alloced till the
724 * failure happened.
725 */
726 rx_blocks->block_virt_addr = tmp_v_addr;
727 return -ENOMEM;
728 }
729 mem_allocated += size;
730 memset(tmp_v_addr, 0, size);
731 rx_blocks->block_virt_addr = tmp_v_addr;
732 rx_blocks->block_dma_addr = tmp_p_addr;
733 rx_blocks->rxds = kmalloc(sizeof(struct rxd_info)*
734 rxd_count[nic->rxd_mode],
735 GFP_KERNEL);
736 if (!rx_blocks->rxds)
737 return -ENOMEM;
738 mem_allocated +=
739 (sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
740 for (l=0; l<rxd_count[nic->rxd_mode];l++) {
741 rx_blocks->rxds[l].virt_addr =
742 rx_blocks->block_virt_addr +
743 (rxd_size[nic->rxd_mode] * l);
744 rx_blocks->rxds[l].dma_addr =
745 rx_blocks->block_dma_addr +
746 (rxd_size[nic->rxd_mode] * l);
747 }
748 }
749 /* Interlinking all Rx Blocks */
750 for (j = 0; j < blk_cnt; j++) {
751 tmp_v_addr =
752 mac_control->rings[i].rx_blocks[j].block_virt_addr;
753 tmp_v_addr_next =
754 mac_control->rings[i].rx_blocks[(j + 1) %
755 blk_cnt].block_virt_addr;
756 tmp_p_addr =
757 mac_control->rings[i].rx_blocks[j].block_dma_addr;
758 tmp_p_addr_next =
759 mac_control->rings[i].rx_blocks[(j + 1) %
760 blk_cnt].block_dma_addr;
761
762 pre_rxd_blk = (struct RxD_block *) tmp_v_addr;
763 pre_rxd_blk->reserved_2_pNext_RxD_block =
764 (unsigned long) tmp_v_addr_next;
765 pre_rxd_blk->pNext_RxD_Blk_physical =
766 (u64) tmp_p_addr_next;
767 }
768 }
769 if (nic->rxd_mode == RXD_MODE_3B) {
770 /*
771 * Allocation of Storages for buffer addresses in 2BUFF mode
772 * and the buffers as well.
773 */
774 for (i = 0; i < config->rx_ring_num; i++) {
775 blk_cnt = config->rx_cfg[i].num_rxd /
776 (rxd_count[nic->rxd_mode]+ 1);
777 mac_control->rings[i].ba =
778 kmalloc((sizeof(struct buffAdd *) * blk_cnt),
779 GFP_KERNEL);
780 if (!mac_control->rings[i].ba)
781 return -ENOMEM;
782 mem_allocated +=(sizeof(struct buffAdd *) * blk_cnt);
783 for (j = 0; j < blk_cnt; j++) {
784 int k = 0;
785 mac_control->rings[i].ba[j] =
786 kmalloc((sizeof(struct buffAdd) *
787 (rxd_count[nic->rxd_mode] + 1)),
788 GFP_KERNEL);
789 if (!mac_control->rings[i].ba[j])
790 return -ENOMEM;
791 mem_allocated += (sizeof(struct buffAdd) * \
792 (rxd_count[nic->rxd_mode] + 1));
793 while (k != rxd_count[nic->rxd_mode]) {
794 ba = &mac_control->rings[i].ba[j][k];
795
796 ba->ba_0_org = (void *) kmalloc
797 (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
798 if (!ba->ba_0_org)
799 return -ENOMEM;
800 mem_allocated +=
801 (BUF0_LEN + ALIGN_SIZE);
802 tmp = (unsigned long)ba->ba_0_org;
803 tmp += ALIGN_SIZE;
804 tmp &= ~((unsigned long) ALIGN_SIZE);
805 ba->ba_0 = (void *) tmp;
806
807 ba->ba_1_org = (void *) kmalloc
808 (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
809 if (!ba->ba_1_org)
810 return -ENOMEM;
811 mem_allocated
812 += (BUF1_LEN + ALIGN_SIZE);
813 tmp = (unsigned long) ba->ba_1_org;
814 tmp += ALIGN_SIZE;
815 tmp &= ~((unsigned long) ALIGN_SIZE);
816 ba->ba_1 = (void *) tmp;
817 k++;
818 }
819 }
820 }
821 }
822
823 /* Allocation and initialization of Statistics block */
824 size = sizeof(struct stat_block);
825 mac_control->stats_mem = pci_alloc_consistent
826 (nic->pdev, size, &mac_control->stats_mem_phy);
827
828 if (!mac_control->stats_mem) {
829 /*
830 * In case of failure, free_shared_mem() is called, which
831 * should free any memory that was alloced till the
832 * failure happened.
833 */
834 return -ENOMEM;
835 }
836 mem_allocated += size;
837 mac_control->stats_mem_sz = size;
838
839 tmp_v_addr = mac_control->stats_mem;
840 mac_control->stats_info = (struct stat_block *) tmp_v_addr;
841 memset(tmp_v_addr, 0, size);
842 DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
843 (unsigned long long) tmp_p_addr);
844 mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
845 return SUCCESS;
846 }
847
848 /**
849 * free_shared_mem - Free the allocated Memory
850 * @nic: Device private variable.
851 * Description: This function is to free all memory locations allocated by
852 * the init_shared_mem() function and return it to the kernel.
853 */
854
855 static void free_shared_mem(struct s2io_nic *nic)
856 {
857 int i, j, blk_cnt, size;
858 void *tmp_v_addr;
859 dma_addr_t tmp_p_addr;
860 struct mac_info *mac_control;
861 struct config_param *config;
862 int lst_size, lst_per_page;
863 struct net_device *dev;
864 int page_num = 0;
865
866 if (!nic)
867 return;
868
869 dev = nic->dev;
870
871 mac_control = &nic->mac_control;
872 config = &nic->config;
873
874 lst_size = (sizeof(struct TxD) * config->max_txds);
875 lst_per_page = PAGE_SIZE / lst_size;
876
877 for (i = 0; i < config->tx_fifo_num; i++) {
878 page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
879 lst_per_page);
880 for (j = 0; j < page_num; j++) {
881 int mem_blks = (j * lst_per_page);
882 if (!mac_control->fifos[i].list_info)
883 return;
884 if (!mac_control->fifos[i].list_info[mem_blks].
885 list_virt_addr)
886 break;
887 pci_free_consistent(nic->pdev, PAGE_SIZE,
888 mac_control->fifos[i].
889 list_info[mem_blks].
890 list_virt_addr,
891 mac_control->fifos[i].
892 list_info[mem_blks].
893 list_phy_addr);
894 nic->mac_control.stats_info->sw_stat.mem_freed
895 += PAGE_SIZE;
896 }
897 /* If we got a zero DMA address during allocation,
898 * free the page now
899 */
900 if (mac_control->zerodma_virt_addr) {
901 pci_free_consistent(nic->pdev, PAGE_SIZE,
902 mac_control->zerodma_virt_addr,
903 (dma_addr_t)0);
904 DBG_PRINT(INIT_DBG,
905 "%s: Freeing TxDL with zero DMA addr. ",
906 dev->name);
907 DBG_PRINT(INIT_DBG, "Virtual address %p\n",
908 mac_control->zerodma_virt_addr);
909 nic->mac_control.stats_info->sw_stat.mem_freed
910 += PAGE_SIZE;
911 }
912 kfree(mac_control->fifos[i].list_info);
913 nic->mac_control.stats_info->sw_stat.mem_freed +=
914 (nic->config.tx_cfg[i].fifo_len *sizeof(struct list_info_hold));
915 }
916
917 size = SIZE_OF_BLOCK;
918 for (i = 0; i < config->rx_ring_num; i++) {
919 blk_cnt = mac_control->rings[i].block_count;
920 for (j = 0; j < blk_cnt; j++) {
921 tmp_v_addr = mac_control->rings[i].rx_blocks[j].
922 block_virt_addr;
923 tmp_p_addr = mac_control->rings[i].rx_blocks[j].
924 block_dma_addr;
925 if (tmp_v_addr == NULL)
926 break;
927 pci_free_consistent(nic->pdev, size,
928 tmp_v_addr, tmp_p_addr);
929 nic->mac_control.stats_info->sw_stat.mem_freed += size;
930 kfree(mac_control->rings[i].rx_blocks[j].rxds);
931 nic->mac_control.stats_info->sw_stat.mem_freed +=
932 ( sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
933 }
934 }
935
936 if (nic->rxd_mode == RXD_MODE_3B) {
937 /* Freeing buffer storage addresses in 2BUFF mode. */
938 for (i = 0; i < config->rx_ring_num; i++) {
939 blk_cnt = config->rx_cfg[i].num_rxd /
940 (rxd_count[nic->rxd_mode] + 1);
941 for (j = 0; j < blk_cnt; j++) {
942 int k = 0;
943 if (!mac_control->rings[i].ba[j])
944 continue;
945 while (k != rxd_count[nic->rxd_mode]) {
946 struct buffAdd *ba =
947 &mac_control->rings[i].ba[j][k];
948 kfree(ba->ba_0_org);
949 nic->mac_control.stats_info->sw_stat.\
950 mem_freed += (BUF0_LEN + ALIGN_SIZE);
951 kfree(ba->ba_1_org);
952 nic->mac_control.stats_info->sw_stat.\
953 mem_freed += (BUF1_LEN + ALIGN_SIZE);
954 k++;
955 }
956 kfree(mac_control->rings[i].ba[j]);
957 nic->mac_control.stats_info->sw_stat.mem_freed +=
958 (sizeof(struct buffAdd) *
959 (rxd_count[nic->rxd_mode] + 1));
960 }
961 kfree(mac_control->rings[i].ba);
962 nic->mac_control.stats_info->sw_stat.mem_freed +=
963 (sizeof(struct buffAdd *) * blk_cnt);
964 }
965 }
966
967 for (i = 0; i < nic->config.tx_fifo_num; i++) {
968 if (mac_control->fifos[i].ufo_in_band_v) {
969 nic->mac_control.stats_info->sw_stat.mem_freed
970 += (config->tx_cfg[i].fifo_len * sizeof(u64));
971 kfree(mac_control->fifos[i].ufo_in_band_v);
972 }
973 }
974
975 if (mac_control->stats_mem) {
976 nic->mac_control.stats_info->sw_stat.mem_freed +=
977 mac_control->stats_mem_sz;
978 pci_free_consistent(nic->pdev,
979 mac_control->stats_mem_sz,
980 mac_control->stats_mem,
981 mac_control->stats_mem_phy);
982 }
983 }
984
985 /**
986 * s2io_verify_pci_mode -
987 */
988
989 static int s2io_verify_pci_mode(struct s2io_nic *nic)
990 {
991 struct XENA_dev_config __iomem *bar0 = nic->bar0;
992 register u64 val64 = 0;
993 int mode;
994
995 val64 = readq(&bar0->pci_mode);
996 mode = (u8)GET_PCI_MODE(val64);
997
998 if ( val64 & PCI_MODE_UNKNOWN_MODE)
999 return -1; /* Unknown PCI mode */
1000 return mode;
1001 }
1002
1003 #define NEC_VENID 0x1033
1004 #define NEC_DEVID 0x0125
1005 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1006 {
1007 struct pci_dev *tdev = NULL;
1008 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
1009 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
1010 if (tdev->bus == s2io_pdev->bus->parent)
1011 pci_dev_put(tdev);
1012 return 1;
1013 }
1014 }
1015 return 0;
1016 }
1017
1018 static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
1019 /**
1020 * s2io_print_pci_mode -
1021 */
1022 static int s2io_print_pci_mode(struct s2io_nic *nic)
1023 {
1024 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1025 register u64 val64 = 0;
1026 int mode;
1027 struct config_param *config = &nic->config;
1028
1029 val64 = readq(&bar0->pci_mode);
1030 mode = (u8)GET_PCI_MODE(val64);
1031
1032 if ( val64 & PCI_MODE_UNKNOWN_MODE)
1033 return -1; /* Unknown PCI mode */
1034
1035 config->bus_speed = bus_speed[mode];
1036
1037 if (s2io_on_nec_bridge(nic->pdev)) {
1038 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
1039 nic->dev->name);
1040 return mode;
1041 }
1042
1043 if (val64 & PCI_MODE_32_BITS) {
1044 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
1045 } else {
1046 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
1047 }
1048
1049 switch(mode) {
1050 case PCI_MODE_PCI_33:
1051 DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
1052 break;
1053 case PCI_MODE_PCI_66:
1054 DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
1055 break;
1056 case PCI_MODE_PCIX_M1_66:
1057 DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
1058 break;
1059 case PCI_MODE_PCIX_M1_100:
1060 DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
1061 break;
1062 case PCI_MODE_PCIX_M1_133:
1063 DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
1064 break;
1065 case PCI_MODE_PCIX_M2_66:
1066 DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
1067 break;
1068 case PCI_MODE_PCIX_M2_100:
1069 DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
1070 break;
1071 case PCI_MODE_PCIX_M2_133:
1072 DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
1073 break;
1074 default:
1075 return -1; /* Unsupported bus speed */
1076 }
1077
1078 return mode;
1079 }
1080
1081 /**
1082 * init_tti - Initialization transmit traffic interrupt scheme
1083 * @nic: device private variable
1084 * @link: link status (UP/DOWN) used to enable/disable continuous
1085 * transmit interrupts
1086 * Description: The function configures transmit traffic interrupts
1087 * Return Value: SUCCESS on success and
1088 * '-1' on failure
1089 */
1090
1091 <<<<<<< HEAD:drivers/net/s2io.c
1092 int init_tti(struct s2io_nic *nic, int link)
1093 =======
1094 static int init_tti(struct s2io_nic *nic, int link)
1095 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/s2io.c
1096 {
1097 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1098 register u64 val64 = 0;
1099 int i;
1100 struct config_param *config;
1101
1102 config = &nic->config;
1103
1104 for (i = 0; i < config->tx_fifo_num; i++) {
1105 /*
1106 * TTI Initialization. Default Tx timer gets us about
1107 * 250 interrupts per sec. Continuous interrupts are enabled
1108 * by default.
1109 */
1110 if (nic->device_type == XFRAME_II_DEVICE) {
1111 int count = (nic->config.bus_speed * 125)/2;
1112 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1113 } else
1114 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1115
1116 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1117 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1118 TTI_DATA1_MEM_TX_URNG_C(0x30) |
1119 TTI_DATA1_MEM_TX_TIMER_AC_EN;
1120
1121 if (use_continuous_tx_intrs && (link == LINK_UP))
1122 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1123 writeq(val64, &bar0->tti_data1_mem);
1124
1125 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1126 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1127 TTI_DATA2_MEM_TX_UFC_C(0x40) |
1128 TTI_DATA2_MEM_TX_UFC_D(0x80);
1129
1130 writeq(val64, &bar0->tti_data2_mem);
1131
1132 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD |
1133 TTI_CMD_MEM_OFFSET(i);
1134 writeq(val64, &bar0->tti_command_mem);
1135
1136 if (wait_for_cmd_complete(&bar0->tti_command_mem,
1137 TTI_CMD_MEM_STROBE_NEW_CMD, S2IO_BIT_RESET) != SUCCESS)
1138 return FAILURE;
1139 }
1140
1141 return SUCCESS;
1142 }
1143
1144 /**
1145 * init_nic - Initialization of hardware
1146 * @nic: device private variable
1147 * Description: The function sequentially configures every block
1148 * of the H/W from their reset values.
1149 * Return Value: SUCCESS on success and
1150 * '-1' on failure (endian settings incorrect).
1151 */
1152
1153 static int init_nic(struct s2io_nic *nic)
1154 {
1155 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1156 struct net_device *dev = nic->dev;
1157 register u64 val64 = 0;
1158 void __iomem *add;
1159 u32 time;
1160 int i, j;
1161 struct mac_info *mac_control;
1162 struct config_param *config;
1163 int dtx_cnt = 0;
1164 unsigned long long mem_share;
1165 int mem_size;
1166
1167 mac_control = &nic->mac_control;
1168 config = &nic->config;
1169
1170 /* to set the swapper controle on the card */
1171 if(s2io_set_swapper(nic)) {
1172 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
1173 return -EIO;
1174 }
1175
1176 /*
1177 * Herc requires EOI to be removed from reset before XGXS, so..
1178 */
1179 if (nic->device_type & XFRAME_II_DEVICE) {
1180 val64 = 0xA500000000ULL;
1181 writeq(val64, &bar0->sw_reset);
1182 msleep(500);
1183 val64 = readq(&bar0->sw_reset);
1184 }
1185
1186 /* Remove XGXS from reset state */
1187 val64 = 0;
1188 writeq(val64, &bar0->sw_reset);
1189 msleep(500);
1190 val64 = readq(&bar0->sw_reset);
1191
1192 /* Ensure that it's safe to access registers by checking
1193 * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1194 */
1195 if (nic->device_type == XFRAME_II_DEVICE) {
1196 for (i = 0; i < 50; i++) {
1197 val64 = readq(&bar0->adapter_status);
1198 if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1199 break;
1200 msleep(10);
1201 }
1202 if (i == 50)
1203 return -ENODEV;
1204 }
1205
1206 /* Enable Receiving broadcasts */
1207 add = &bar0->mac_cfg;
1208 val64 = readq(&bar0->mac_cfg);
1209 val64 |= MAC_RMAC_BCAST_ENABLE;
1210 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1211 writel((u32) val64, add);
1212 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1213 writel((u32) (val64 >> 32), (add + 4));
1214
1215 /* Read registers in all blocks */
1216 val64 = readq(&bar0->mac_int_mask);
1217 val64 = readq(&bar0->mc_int_mask);
1218 val64 = readq(&bar0->xgxs_int_mask);
1219
1220 /* Set MTU */
1221 val64 = dev->mtu;
1222 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1223
1224 if (nic->device_type & XFRAME_II_DEVICE) {
1225 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
1226 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1227 &bar0->dtx_control, UF);
1228 if (dtx_cnt & 0x1)
1229 msleep(1); /* Necessary!! */
1230 dtx_cnt++;
1231 }
1232 } else {
1233 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1234 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1235 &bar0->dtx_control, UF);
1236 val64 = readq(&bar0->dtx_control);
1237 dtx_cnt++;
1238 }
1239 }
1240
1241 /* Tx DMA Initialization */
1242 val64 = 0;
1243 writeq(val64, &bar0->tx_fifo_partition_0);
1244 writeq(val64, &bar0->tx_fifo_partition_1);
1245 writeq(val64, &bar0->tx_fifo_partition_2);
1246 writeq(val64, &bar0->tx_fifo_partition_3);
1247
1248
1249 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1250 val64 |=
1251 vBIT(config->tx_cfg[i].fifo_len - 1, ((j * 32) + 19),
1252 13) | vBIT(config->tx_cfg[i].fifo_priority,
1253 ((j * 32) + 5), 3);
1254
1255 if (i == (config->tx_fifo_num - 1)) {
1256 if (i % 2 == 0)
1257 i++;
1258 }
1259
1260 switch (i) {
1261 case 1:
1262 writeq(val64, &bar0->tx_fifo_partition_0);
1263 val64 = 0;
1264 j = 0;
1265 break;
1266 case 3:
1267 writeq(val64, &bar0->tx_fifo_partition_1);
1268 val64 = 0;
1269 j = 0;
1270 break;
1271 case 5:
1272 writeq(val64, &bar0->tx_fifo_partition_2);
1273 val64 = 0;
1274 j = 0;
1275 break;
1276 case 7:
1277 writeq(val64, &bar0->tx_fifo_partition_3);
1278 val64 = 0;
1279 j = 0;
1280 break;
1281 default:
1282 j++;
1283 break;
1284 }
1285 }
1286
1287 /*
1288 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1289 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1290 */
1291 if ((nic->device_type == XFRAME_I_DEVICE) &&
1292 (nic->pdev->revision < 4))
1293 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1294
1295 val64 = readq(&bar0->tx_fifo_partition_0);
1296 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1297 &bar0->tx_fifo_partition_0, (unsigned long long) val64);
1298
1299 /*
1300 * Initialization of Tx_PA_CONFIG register to ignore packet
1301 * integrity checking.
1302 */
1303 val64 = readq(&bar0->tx_pa_cfg);
1304 val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1305 TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1306 writeq(val64, &bar0->tx_pa_cfg);
1307
1308 /* Rx DMA intialization. */
1309 val64 = 0;
1310 for (i = 0; i < config->rx_ring_num; i++) {
1311 val64 |=
1312 vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1313 3);
1314 }
1315 writeq(val64, &bar0->rx_queue_priority);
1316
1317 /*
1318 * Allocating equal share of memory to all the
1319 * configured Rings.
1320 */
1321 val64 = 0;
1322 if (nic->device_type & XFRAME_II_DEVICE)
1323 mem_size = 32;
1324 else
1325 mem_size = 64;
1326
1327 for (i = 0; i < config->rx_ring_num; i++) {
1328 switch (i) {
1329 case 0:
1330 mem_share = (mem_size / config->rx_ring_num +
1331 mem_size % config->rx_ring_num);
1332 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1333 continue;
1334 case 1:
1335 mem_share = (mem_size / config->rx_ring_num);
1336 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1337 continue;
1338 case 2:
1339 mem_share = (mem_size / config->rx_ring_num);
1340 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1341 continue;
1342 case 3:
1343 mem_share = (mem_size / config->rx_ring_num);
1344 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1345 continue;
1346 case 4:
1347 mem_share = (mem_size / config->rx_ring_num);
1348 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1349 continue;
1350 case 5:
1351 mem_share = (mem_size / config->rx_ring_num);
1352 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1353 continue;
1354 case 6:
1355 mem_share = (mem_size / config->rx_ring_num);
1356 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1357 continue;
1358 case 7:
1359 mem_share = (mem_size / config->rx_ring_num);
1360 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1361 continue;
1362 }
1363 }
1364 writeq(val64, &bar0->rx_queue_cfg);
1365
1366 /*
1367 * Filling Tx round robin registers
1368 * as per the number of FIFOs for equal scheduling priority
1369 */
1370 switch (config->tx_fifo_num) {
1371 case 1:
1372 val64 = 0x0;
1373 writeq(val64, &bar0->tx_w_round_robin_0);
1374 writeq(val64, &bar0->tx_w_round_robin_1);
1375 writeq(val64, &bar0->tx_w_round_robin_2);
1376 writeq(val64, &bar0->tx_w_round_robin_3);
1377 writeq(val64, &bar0->tx_w_round_robin_4);
1378 break;
1379 case 2:
1380 val64 = 0x0001000100010001ULL;
1381 writeq(val64, &bar0->tx_w_round_robin_0);
1382 writeq(val64, &bar0->tx_w_round_robin_1);
1383 writeq(val64, &bar0->tx_w_round_robin_2);
1384 writeq(val64, &bar0->tx_w_round_robin_3);
1385 val64 = 0x0001000100000000ULL;
1386 writeq(val64, &bar0->tx_w_round_robin_4);
1387 break;
1388 case 3:
1389 val64 = 0x0001020001020001ULL;
1390 writeq(val64, &bar0->tx_w_round_robin_0);
1391 val64 = 0x0200010200010200ULL;
1392 writeq(val64, &bar0->tx_w_round_robin_1);
1393 val64 = 0x0102000102000102ULL;
1394 writeq(val64, &bar0->tx_w_round_robin_2);
1395 val64 = 0x0001020001020001ULL;
1396 writeq(val64, &bar0->tx_w_round_robin_3);
1397 val64 = 0x0200010200000000ULL;
1398 writeq(val64, &bar0->tx_w_round_robin_4);
1399 break;
1400 case 4:
1401 val64 = 0x0001020300010203ULL;
1402 writeq(val64, &bar0->tx_w_round_robin_0);
1403 writeq(val64, &bar0->tx_w_round_robin_1);
1404 writeq(val64, &bar0->tx_w_round_robin_2);
1405 writeq(val64, &bar0->tx_w_round_robin_3);
1406 val64 = 0x0001020300000000ULL;
1407 writeq(val64, &bar0->tx_w_round_robin_4);
1408 break;
1409 case 5:
1410 val64 = 0x0001020304000102ULL;
1411 writeq(val64, &bar0->tx_w_round_robin_0);
1412 val64 = 0x0304000102030400ULL;
1413 writeq(val64, &bar0->tx_w_round_robin_1);
1414 val64 = 0x0102030400010203ULL;
1415 writeq(val64, &bar0->tx_w_round_robin_2);
1416 val64 = 0x0400010203040001ULL;
1417 writeq(val64, &bar0->tx_w_round_robin_3);
1418 val64 = 0x0203040000000000ULL;
1419 writeq(val64, &bar0->tx_w_round_robin_4);
1420 break;
1421 case 6:
1422 val64 = 0x0001020304050001ULL;
1423 writeq(val64, &bar0->tx_w_round_robin_0);
1424 val64 = 0x0203040500010203ULL;
1425 writeq(val64, &bar0->tx_w_round_robin_1);
1426 val64 = 0x0405000102030405ULL;
1427 writeq(val64, &bar0->tx_w_round_robin_2);
1428 val64 = 0x0001020304050001ULL;
1429 writeq(val64, &bar0->tx_w_round_robin_3);
1430 val64 = 0x0203040500000000ULL;
1431 writeq(val64, &bar0->tx_w_round_robin_4);
1432 break;
1433 case 7:
1434 val64 = 0x0001020304050600ULL;
1435 writeq(val64, &bar0->tx_w_round_robin_0);
1436 val64 = 0x0102030405060001ULL;
1437 writeq(val64, &bar0->tx_w_round_robin_1);
1438 val64 = 0x0203040506000102ULL;
1439 writeq(val64, &bar0->tx_w_round_robin_2);
1440 val64 = 0x0304050600010203ULL;
1441 writeq(val64, &bar0->tx_w_round_robin_3);
1442 val64 = 0x0405060000000000ULL;
1443 writeq(val64, &bar0->tx_w_round_robin_4);
1444 break;
1445 case 8:
1446 val64 = 0x0001020304050607ULL;
1447 writeq(val64, &bar0->tx_w_round_robin_0);
1448 writeq(val64, &bar0->tx_w_round_robin_1);
1449 writeq(val64, &bar0->tx_w_round_robin_2);
1450 writeq(val64, &bar0->tx_w_round_robin_3);
1451 val64 = 0x0001020300000000ULL;
1452 writeq(val64, &bar0->tx_w_round_robin_4);
1453 break;
1454 }
1455
1456 /* Enable all configured Tx FIFO partitions */
1457 val64 = readq(&bar0->tx_fifo_partition_0);
1458 val64 |= (TX_FIFO_PARTITION_EN);
1459 writeq(val64, &bar0->tx_fifo_partition_0);
1460
1461 /* Filling the Rx round robin registers as per the
1462 * number of Rings and steering based on QoS.
1463 */
1464 switch (config->rx_ring_num) {
1465 case 1:
1466 val64 = 0x8080808080808080ULL;
1467 writeq(val64, &bar0->rts_qos_steering);
1468 break;
1469 case 2:
1470 val64 = 0x0000010000010000ULL;
1471 writeq(val64, &bar0->rx_w_round_robin_0);
1472 val64 = 0x0100000100000100ULL;
1473 writeq(val64, &bar0->rx_w_round_robin_1);
1474 val64 = 0x0001000001000001ULL;
1475 writeq(val64, &bar0->rx_w_round_robin_2);
1476 val64 = 0x0000010000010000ULL;
1477 writeq(val64, &bar0->rx_w_round_robin_3);
1478 val64 = 0x0100000000000000ULL;
1479 writeq(val64, &bar0->rx_w_round_robin_4);
1480
1481 val64 = 0x8080808040404040ULL;
1482 writeq(val64, &bar0->rts_qos_steering);
1483 break;
1484 case 3:
1485 val64 = 0x0001000102000001ULL;
1486 writeq(val64, &bar0->rx_w_round_robin_0);
1487 val64 = 0x0001020000010001ULL;
1488 writeq(val64, &bar0->rx_w_round_robin_1);
1489 val64 = 0x0200000100010200ULL;
1490 writeq(val64, &bar0->rx_w_round_robin_2);
1491 val64 = 0x0001000102000001ULL;
1492 writeq(val64, &bar0->rx_w_round_robin_3);
1493 val64 = 0x0001020000000000ULL;
1494 writeq(val64, &bar0->rx_w_round_robin_4);
1495
1496 val64 = 0x8080804040402020ULL;
1497 writeq(val64, &bar0->rts_qos_steering);
1498 break;
1499 case 4:
1500 val64 = 0x0001020300010200ULL;
1501 writeq(val64, &bar0->rx_w_round_robin_0);
1502 val64 = 0x0100000102030001ULL;
1503 writeq(val64, &bar0->rx_w_round_robin_1);
1504 val64 = 0x0200010000010203ULL;
1505 writeq(val64, &bar0->rx_w_round_robin_2);
1506 val64 = 0x0001020001000001ULL;
1507 writeq(val64, &bar0->rx_w_round_robin_3);
1508 val64 = 0x0203000100000000ULL;
1509 writeq(val64, &bar0->rx_w_round_robin_4);
1510
1511 val64 = 0x8080404020201010ULL;
1512 writeq(val64, &bar0->rts_qos_steering);
1513 break;
1514 case 5:
1515 val64 = 0x0001000203000102ULL;
1516 writeq(val64, &bar0->rx_w_round_robin_0);
1517 val64 = 0x0001020001030004ULL;
1518 writeq(val64, &bar0->rx_w_round_robin_1);
1519 val64 = 0x0001000203000102ULL;
1520 writeq(val64, &bar0->rx_w_round_robin_2);
1521 val64 = 0x0001020001030004ULL;
1522 writeq(val64, &bar0->rx_w_round_robin_3);
1523 val64 = 0x0001000000000000ULL;
1524 writeq(val64, &bar0->rx_w_round_robin_4);
1525
1526 val64 = 0x8080404020201008ULL;
1527 writeq(val64, &bar0->rts_qos_steering);
1528 break;
1529 case 6:
1530 val64 = 0x0001020304000102ULL;
1531 writeq(val64, &bar0->rx_w_round_robin_0);
1532 val64 = 0x0304050001020001ULL;
1533 writeq(val64, &bar0->rx_w_round_robin_1);
1534 val64 = 0x0203000100000102ULL;
1535 writeq(val64, &bar0->rx_w_round_robin_2);
1536 val64 = 0x0304000102030405ULL;
1537 writeq(val64, &bar0->rx_w_round_robin_3);
1538 val64 = 0x0001000200000000ULL;
1539 writeq(val64, &bar0->rx_w_round_robin_4);
1540
1541 val64 = 0x8080404020100804ULL;
1542 writeq(val64, &bar0->rts_qos_steering);
1543 break;
1544 case 7:
1545 val64 = 0x0001020001020300ULL;
1546 writeq(val64, &bar0->rx_w_round_robin_0);
1547 val64 = 0x0102030400010203ULL;
1548 writeq(val64, &bar0->rx_w_round_robin_1);
1549 val64 = 0x0405060001020001ULL;
1550 writeq(val64, &bar0->rx_w_round_robin_2);
1551 val64 = 0x0304050000010200ULL;
1552 writeq(val64, &bar0->rx_w_round_robin_3);
1553 val64 = 0x0102030000000000ULL;
1554 writeq(val64, &bar0->rx_w_round_robin_4);
1555
1556 val64 = 0x8080402010080402ULL;
1557 writeq(val64, &bar0->rts_qos_steering);
1558 break;
1559 case 8:
1560 val64 = 0x0001020300040105ULL;
1561 writeq(val64, &bar0->rx_w_round_robin_0);
1562 val64 = 0x0200030106000204ULL;
1563 writeq(val64, &bar0->rx_w_round_robin_1);
1564 val64 = 0x0103000502010007ULL;
1565 writeq(val64, &bar0->rx_w_round_robin_2);
1566 val64 = 0x0304010002060500ULL;
1567 writeq(val64, &bar0->rx_w_round_robin_3);
1568 val64 = 0x0103020400000000ULL;
1569 writeq(val64, &bar0->rx_w_round_robin_4);
1570
1571 val64 = 0x8040201008040201ULL;
1572 writeq(val64, &bar0->rts_qos_steering);
1573 break;
1574 }
1575
1576 /* UDP Fix */
1577 val64 = 0;
1578 for (i = 0; i < 8; i++)
1579 writeq(val64, &bar0->rts_frm_len_n[i]);
1580
1581 /* Set the default rts frame length for the rings configured */
1582 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1583 for (i = 0 ; i < config->rx_ring_num ; i++)
1584 writeq(val64, &bar0->rts_frm_len_n[i]);
1585
1586 /* Set the frame length for the configured rings
1587 * desired by the user
1588 */
1589 for (i = 0; i < config->rx_ring_num; i++) {
1590 /* If rts_frm_len[i] == 0 then it is assumed that user not
1591 * specified frame length steering.
1592 * If the user provides the frame length then program
1593 * the rts_frm_len register for those values or else
1594 * leave it as it is.
1595 */
1596 if (rts_frm_len[i] != 0) {
1597 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1598 &bar0->rts_frm_len_n[i]);
1599 }
1600 }
1601
1602 /* Disable differentiated services steering logic */
1603 for (i = 0; i < 64; i++) {
1604 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1605 DBG_PRINT(ERR_DBG, "%s: failed rts ds steering",
1606 dev->name);
1607 DBG_PRINT(ERR_DBG, "set on codepoint %d\n", i);
1608 return -ENODEV;
1609 }
1610 }
1611
1612 /* Program statistics memory */
1613 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1614
1615 if (nic->device_type == XFRAME_II_DEVICE) {
1616 val64 = STAT_BC(0x320);
1617 writeq(val64, &bar0->stat_byte_cnt);
1618 }
1619
1620 /*
1621 * Initializing the sampling rate for the device to calculate the
1622 * bandwidth utilization.
1623 */
1624 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1625 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1626 writeq(val64, &bar0->mac_link_util);
1627
1628 /*
1629 * Initializing the Transmit and Receive Traffic Interrupt
1630 * Scheme.
1631 */
1632
1633 /* Initialize TTI */
1634 if (SUCCESS != init_tti(nic, nic->last_link_state))
1635 return -ENODEV;
1636
1637 /* RTI Initialization */
1638 if (nic->device_type == XFRAME_II_DEVICE) {
1639 /*
1640 * Programmed to generate Apprx 500 Intrs per
1641 * second
1642 */
1643 int count = (nic->config.bus_speed * 125)/4;
1644 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1645 } else
1646 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1647 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1648 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1649 RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1650
1651 writeq(val64, &bar0->rti_data1_mem);
1652
1653 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1654 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1655 if (nic->config.intr_type == MSI_X)
1656 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1657 RTI_DATA2_MEM_RX_UFC_D(0x40));
1658 else
1659 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1660 RTI_DATA2_MEM_RX_UFC_D(0x80));
1661 writeq(val64, &bar0->rti_data2_mem);
1662
1663 for (i = 0; i < config->rx_ring_num; i++) {
1664 val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1665 | RTI_CMD_MEM_OFFSET(i);
1666 writeq(val64, &bar0->rti_command_mem);
1667
1668 /*
1669 * Once the operation completes, the Strobe bit of the
1670 * command register will be reset. We poll for this
1671 * particular condition. We wait for a maximum of 500ms
1672 * for the operation to complete, if it's not complete
1673 * by then we return error.
1674 */
1675 time = 0;
1676 while (TRUE) {
1677 val64 = readq(&bar0->rti_command_mem);
1678 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1679 break;
1680
1681 if (time > 10) {
1682 DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1683 dev->name);
1684 return -ENODEV;
1685 }
1686 time++;
1687 msleep(50);
1688 }
1689 }
1690
1691 /*
1692 * Initializing proper values as Pause threshold into all
1693 * the 8 Queues on Rx side.
1694 */
1695 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1696 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1697
1698 /* Disable RMAC PAD STRIPPING */
1699 add = &bar0->mac_cfg;
1700 val64 = readq(&bar0->mac_cfg);
1701 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1702 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1703 writel((u32) (val64), add);
1704 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1705 writel((u32) (val64 >> 32), (add + 4));
1706 val64 = readq(&bar0->mac_cfg);
1707
1708 /* Enable FCS stripping by adapter */
1709 add = &bar0->mac_cfg;
1710 val64 = readq(&bar0->mac_cfg);
1711 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1712 if (nic->device_type == XFRAME_II_DEVICE)
1713 writeq(val64, &bar0->mac_cfg);
1714 else {
1715 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1716 writel((u32) (val64), add);
1717 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1718 writel((u32) (val64 >> 32), (add + 4));
1719 }
1720
1721 /*
1722 * Set the time value to be inserted in the pause frame
1723 * generated by xena.
1724 */
1725 val64 = readq(&bar0->rmac_pause_cfg);
1726 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1727 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1728 writeq(val64, &bar0->rmac_pause_cfg);
1729
1730 /*
1731 * Set the Threshold Limit for Generating the pause frame
1732 * If the amount of data in any Queue exceeds ratio of
1733 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1734 * pause frame is generated
1735 */
1736 val64 = 0;
1737 for (i = 0; i < 4; i++) {
1738 val64 |=
1739 (((u64) 0xFF00 | nic->mac_control.
1740 mc_pause_threshold_q0q3)
1741 << (i * 2 * 8));
1742 }
1743 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1744
1745 val64 = 0;
1746 for (i = 0; i < 4; i++) {
1747 val64 |=
1748 (((u64) 0xFF00 | nic->mac_control.
1749 mc_pause_threshold_q4q7)
1750 << (i * 2 * 8));
1751 }
1752 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1753
1754 /*
1755 * TxDMA will stop Read request if the number of read split has
1756 * exceeded the limit pointed by shared_splits
1757 */
1758 val64 = readq(&bar0->pic_control);
1759 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1760 writeq(val64, &bar0->pic_control);
1761
1762 if (nic->config.bus_speed == 266) {
1763 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1764 writeq(0x0, &bar0->read_retry_delay);
1765 writeq(0x0, &bar0->write_retry_delay);
1766 }
1767
1768 /*
1769 * Programming the Herc to split every write transaction
1770 * that does not start on an ADB to reduce disconnects.
1771 */
1772 if (nic->device_type == XFRAME_II_DEVICE) {
1773 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1774 MISC_LINK_STABILITY_PRD(3);
1775 writeq(val64, &bar0->misc_control);
1776 val64 = readq(&bar0->pic_control2);
1777 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
1778 writeq(val64, &bar0->pic_control2);
1779 }
1780 if (strstr(nic->product_name, "CX4")) {
1781 val64 = TMAC_AVG_IPG(0x17);
1782 writeq(val64, &bar0->tmac_avg_ipg);
1783 }
1784
1785 return SUCCESS;
1786 }
1787 #define LINK_UP_DOWN_INTERRUPT 1
1788 #define MAC_RMAC_ERR_TIMER 2
1789
1790 static int s2io_link_fault_indication(struct s2io_nic *nic)
1791 {
1792 if (nic->config.intr_type != INTA)
1793 return MAC_RMAC_ERR_TIMER;
1794 if (nic->device_type == XFRAME_II_DEVICE)
1795 return LINK_UP_DOWN_INTERRUPT;
1796 else
1797 return MAC_RMAC_ERR_TIMER;
1798 }
1799
1800 /**
1801 * do_s2io_write_bits - update alarm bits in alarm register
1802 * @value: alarm bits
1803 * @flag: interrupt status
1804 * @addr: address value
1805 * Description: update alarm bits in alarm register
1806 * Return Value:
1807 * NONE.
1808 */
1809 static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1810 {
1811 u64 temp64;
1812
1813 temp64 = readq(addr);
1814
1815 if(flag == ENABLE_INTRS)
1816 temp64 &= ~((u64) value);
1817 else
1818 temp64 |= ((u64) value);
1819 writeq(temp64, addr);
1820 }
1821
1822 static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
1823 {
1824 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1825 register u64 gen_int_mask = 0;
1826
1827 if (mask & TX_DMA_INTR) {
1828
1829 gen_int_mask |= TXDMA_INT_M;
1830
1831 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
1832 TXDMA_PCC_INT | TXDMA_TTI_INT |
1833 TXDMA_LSO_INT | TXDMA_TPA_INT |
1834 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1835
1836 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
1837 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1838 PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1839 &bar0->pfc_err_mask);
1840
1841 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
1842 TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1843 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1844
1845 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
1846 PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1847 PCC_N_SERR | PCC_6_COF_OV_ERR |
1848 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1849 PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1850 PCC_TXB_ECC_SG_ERR, flag, &bar0->pcc_err_mask);
1851
1852 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
1853 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1854
1855 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
1856 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1857 LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1858 flag, &bar0->lso_err_mask);
1859
1860 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
1861 flag, &bar0->tpa_err_mask);
1862
1863 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1864
1865 }
1866
1867 if (mask & TX_MAC_INTR) {
1868 gen_int_mask |= TXMAC_INT_M;
1869 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
1870 &bar0->mac_int_mask);
1871 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
1872 TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1873 TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1874 flag, &bar0->mac_tmac_err_mask);
1875 }
1876
1877 if (mask & TX_XGXS_INTR) {
1878 gen_int_mask |= TXXGXS_INT_M;
1879 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
1880 &bar0->xgxs_int_mask);
1881 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
1882 TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1883 flag, &bar0->xgxs_txgxs_err_mask);
1884 }
1885
1886 if (mask & RX_DMA_INTR) {
1887 gen_int_mask |= RXDMA_INT_M;
1888 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
1889 RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1890 flag, &bar0->rxdma_int_mask);
1891 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
1892 RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
1893 RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
1894 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
1895 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
1896 PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
1897 PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
1898 &bar0->prc_pcix_err_mask);
1899 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
1900 RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
1901 &bar0->rpa_err_mask);
1902 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
1903 RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
1904 RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
1905 RDA_FRM_ECC_SG_ERR | RDA_MISC_ERR|RDA_PCIX_ERR,
1906 flag, &bar0->rda_err_mask);
1907 do_s2io_write_bits(RTI_SM_ERR_ALARM |
1908 RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
1909 flag, &bar0->rti_err_mask);
1910 }
1911
1912 if (mask & RX_MAC_INTR) {
1913 gen_int_mask |= RXMAC_INT_M;
1914 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
1915 &bar0->mac_int_mask);
1916 do_s2io_write_bits(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
1917 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
1918 RMAC_DOUBLE_ECC_ERR |
1919 RMAC_LINK_STATE_CHANGE_INT,
1920 flag, &bar0->mac_rmac_err_mask);
1921 }
1922
1923 if (mask & RX_XGXS_INTR)
1924 {
1925 gen_int_mask |= RXXGXS_INT_M;
1926 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
1927 &bar0->xgxs_int_mask);
1928 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
1929 &bar0->xgxs_rxgxs_err_mask);
1930 }
1931
1932 if (mask & MC_INTR) {
1933 gen_int_mask |= MC_INT_M;
1934 do_s2io_write_bits(MC_INT_MASK_MC_INT, flag, &bar0->mc_int_mask);
1935 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
1936 MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
1937 &bar0->mc_err_mask);
1938 }
1939 nic->general_int_mask = gen_int_mask;
1940
1941 /* Remove this line when alarm interrupts are enabled */
1942 nic->general_int_mask = 0;
1943 }
1944 /**
1945 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1946 * @nic: device private variable,
1947 * @mask: A mask indicating which Intr block must be modified and,
1948 * @flag: A flag indicating whether to enable or disable the Intrs.
1949 * Description: This function will either disable or enable the interrupts
1950 * depending on the flag argument. The mask argument can be used to
1951 * enable/disable any Intr block.
1952 * Return Value: NONE.
1953 */
1954
1955 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1956 {
1957 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1958 register u64 temp64 = 0, intr_mask = 0;
1959
1960 intr_mask = nic->general_int_mask;
1961
1962 /* Top level interrupt classification */
1963 /* PIC Interrupts */
1964 if (mask & TX_PIC_INTR) {
1965 /* Enable PIC Intrs in the general intr mask register */
1966 intr_mask |= TXPIC_INT_M;
1967 if (flag == ENABLE_INTRS) {
1968 /*
1969 * If Hercules adapter enable GPIO otherwise
1970 * disable all PCIX, Flash, MDIO, IIC and GPIO
1971 * interrupts for now.
1972 * TODO
1973 */
1974 if (s2io_link_fault_indication(nic) ==
1975 LINK_UP_DOWN_INTERRUPT ) {
1976 do_s2io_write_bits(PIC_INT_GPIO, flag,
1977 &bar0->pic_int_mask);
1978 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
1979 &bar0->gpio_int_mask);
1980 } else
1981 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1982 } else if (flag == DISABLE_INTRS) {
1983 /*
1984 * Disable PIC Intrs in the general
1985 * intr mask register
1986 */
1987 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1988 }
1989 }
1990
1991 /* Tx traffic interrupts */
1992 if (mask & TX_TRAFFIC_INTR) {
1993 intr_mask |= TXTRAFFIC_INT_M;
1994 if (flag == ENABLE_INTRS) {
1995 /*
1996 * Enable all the Tx side interrupts
1997 * writing 0 Enables all 64 TX interrupt levels
1998 */
1999 writeq(0x0, &bar0->tx_traffic_mask);
2000 } else if (flag == DISABLE_INTRS) {
2001 /*
2002 * Disable Tx Traffic Intrs in the general intr mask
2003 * register.
2004 */
2005 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
2006 }
2007 }
2008
2009 /* Rx traffic interrupts */
2010 if (mask & RX_TRAFFIC_INTR) {
2011 intr_mask |= RXTRAFFIC_INT_M;
2012 if (flag == ENABLE_INTRS) {
2013 /* writing 0 Enables all 8 RX interrupt levels */
2014 writeq(0x0, &bar0->rx_traffic_mask);
2015 } else if (flag == DISABLE_INTRS) {
2016 /*
2017 * Disable Rx Traffic Intrs in the general intr mask
2018 * register.
2019 */
2020 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
2021 }
2022 }
2023
2024 temp64 = readq(&bar0->general_int_mask);
2025 if (flag == ENABLE_INTRS)
2026 temp64 &= ~((u64) intr_mask);
2027 else
2028 temp64 = DISABLE_ALL_INTRS;
2029 writeq(temp64, &bar0->general_int_mask);
2030
2031 nic->general_int_mask = readq(&bar0->general_int_mask);
2032 }
2033
2034 /**
2035 * verify_pcc_quiescent- Checks for PCC quiescent state
2036 * Return: 1 If PCC is quiescence
2037 * 0 If PCC is not quiescence
2038 */
2039 static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
2040 {
2041 int ret = 0, herc;
2042 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2043 u64 val64 = readq(&bar0->adapter_status);
2044
2045 herc = (sp->device_type == XFRAME_II_DEVICE);
2046
2047 if (flag == FALSE) {
2048 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2049 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
2050 ret = 1;
2051 } else {
2052 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2053 ret = 1;
2054 }
2055 } else {
2056 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2057 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
2058 ADAPTER_STATUS_RMAC_PCC_IDLE))
2059 ret = 1;
2060 } else {
2061 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
2062 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2063 ret = 1;
2064 }
2065 }
2066
2067 return ret;
2068 }
2069 /**
2070 * verify_xena_quiescence - Checks whether the H/W is ready
2071 * Description: Returns whether the H/W is ready to go or not. Depending
2072 * on whether adapter enable bit was written or not the comparison
2073 * differs and the calling function passes the input argument flag to
2074 * indicate this.
2075 * Return: 1 If xena is quiescence
2076 * 0 If Xena is not quiescence
2077 */
2078
2079 static int verify_xena_quiescence(struct s2io_nic *sp)
2080 {
2081 int mode;
2082 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2083 u64 val64 = readq(&bar0->adapter_status);
2084 mode = s2io_verify_pci_mode(sp);
2085
2086 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2087 DBG_PRINT(ERR_DBG, "%s", "TDMA is not ready!");
2088 return 0;
2089 }
2090 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
2091 DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!");
2092 return 0;
2093 }
2094 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2095 DBG_PRINT(ERR_DBG, "%s", "PFC is not ready!");
2096 return 0;
2097 }
2098 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2099 DBG_PRINT(ERR_DBG, "%s", "TMAC BUF is not empty!");
2100 return 0;
2101 }
2102 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2103 DBG_PRINT(ERR_DBG, "%s", "PIC is not QUIESCENT!");
2104 return 0;
2105 }
2106 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2107 DBG_PRINT(ERR_DBG, "%s", "MC_DRAM is not ready!");
2108 return 0;
2109 }
2110 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2111 DBG_PRINT(ERR_DBG, "%s", "MC_QUEUES is not ready!");
2112 return 0;
2113 }
2114 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2115 DBG_PRINT(ERR_DBG, "%s", "M_PLL is not locked!");
2116 return 0;
2117 }
2118
2119 /*
2120 * In PCI 33 mode, the P_PLL is not used, and therefore,
2121 * the the P_PLL_LOCK bit in the adapter_status register will
2122 * not be asserted.
2123 */
2124 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
2125 sp->device_type == XFRAME_II_DEVICE && mode !=
2126 PCI_MODE_PCI_33) {
2127 DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!");
2128 return 0;
2129 }
2130 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
2131 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
2132 DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!");
2133 return 0;
2134 }
2135 return 1;
2136 }
2137
2138 /**
2139 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
2140 * @sp: Pointer to device specifc structure
2141 * Description :
2142 * New procedure to clear mac address reading problems on Alpha platforms
2143 *
2144 */
2145
2146 static void fix_mac_address(struct s2io_nic * sp)
2147 {
2148 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2149 u64 val64;
2150 int i = 0;
2151
2152 while (fix_mac[i] != END_SIGN) {
2153 writeq(fix_mac[i++], &bar0->gpio_control);
2154 udelay(10);
2155 val64 = readq(&bar0->gpio_control);
2156 }
2157 }
2158
2159 /**
2160 * start_nic - Turns the device on
2161 * @nic : device private variable.
2162 * Description:
2163 * This function actually turns the device on. Before this function is
2164 * called,all Registers are configured from their reset states
2165 * and shared memory is allocated but the NIC is still quiescent. On
2166 * calling this function, the device interrupts are cleared and the NIC is
2167 * literally switched on by writing into the adapter control register.
2168 * Return Value:
2169 * SUCCESS on success and -1 on failure.
2170 */
2171
2172 static int start_nic(struct s2io_nic *nic)
2173 {
2174 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2175 struct net_device *dev = nic->dev;
2176 register u64 val64 = 0;
2177 u16 subid, i;
2178 struct mac_info *mac_control;
2179 struct config_param *config;
2180
2181 mac_control = &nic->mac_control;
2182 config = &nic->config;
2183
2184 /* PRC Initialization and configuration */
2185 for (i = 0; i < config->rx_ring_num; i++) {
2186 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
2187 &bar0->prc_rxd0_n[i]);
2188
2189 val64 = readq(&bar0->prc_ctrl_n[i]);
2190 if (nic->rxd_mode == RXD_MODE_1)
2191 val64 |= PRC_CTRL_RC_ENABLED;
2192 else
2193 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
2194 if (nic->device_type == XFRAME_II_DEVICE)
2195 val64 |= PRC_CTRL_GROUP_READS;
2196 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2197 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2198 writeq(val64, &bar0->prc_ctrl_n[i]);
2199 }
2200
2201 if (nic->rxd_mode == RXD_MODE_3B) {
2202 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2203 val64 = readq(&bar0->rx_pa_cfg);
2204 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2205 writeq(val64, &bar0->rx_pa_cfg);
2206 }
2207
2208 if (vlan_tag_strip == 0) {
2209 val64 = readq(&bar0->rx_pa_cfg);
2210 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2211 writeq(val64, &bar0->rx_pa_cfg);
2212 vlan_strip_flag = 0;
2213 }
2214
2215 /*
2216 * Enabling MC-RLDRAM. After enabling the device, we timeout
2217 * for around 100ms, which is approximately the time required
2218 * for the device to be ready for operation.
2219 */
2220 val64 = readq(&bar0->mc_rldram_mrs);
2221 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2222 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2223 val64 = readq(&bar0->mc_rldram_mrs);
2224
2225 msleep(100); /* Delay by around 100 ms. */
2226
2227 /* Enabling ECC Protection. */
2228 val64 = readq(&bar0->adapter_control);
2229 val64 &= ~ADAPTER_ECC_EN;
2230 writeq(val64, &bar0->adapter_control);
2231
2232 /*
2233 * Verify if the device is ready to be enabled, if so enable
2234 * it.
2235 */
2236 val64 = readq(&bar0->adapter_status);
2237 if (!verify_xena_quiescence(nic)) {
2238 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2239 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
2240 (unsigned long long) val64);
2241 return FAILURE;
2242 }
2243
2244 /*
2245 * With some switches, link might be already up at this point.
2246 * Because of this weird behavior, when we enable laser,
2247 * we may not get link. We need to handle this. We cannot
2248 * figure out which switch is misbehaving. So we are forced to
2249 * make a global change.
2250 */
2251
2252 /* Enabling Laser. */
2253 val64 = readq(&bar0->adapter_control);
2254 val64 |= ADAPTER_EOI_TX_ON;
2255 writeq(val64, &bar0->adapter_control);
2256
2257 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2258 /*
2259 * Dont see link state interrupts initally on some switches,
2260 * so directly scheduling the link state task here.
2261 */
2262 schedule_work(&nic->set_link_task);
2263 }
2264 /* SXE-002: Initialize link and activity LED */
2265 subid = nic->pdev->subsystem_device;
2266 if (((subid & 0xFF) >= 0x07) &&
2267 (nic->device_type == XFRAME_I_DEVICE)) {
2268 val64 = readq(&bar0->gpio_control);
2269 val64 |= 0x0000800000000000ULL;
2270 writeq(val64, &bar0->gpio_control);
2271 val64 = 0x0411040400000000ULL;
2272 writeq(val64, (void __iomem *)bar0 + 0x2700);
2273 }
2274
2275 return SUCCESS;
2276 }
2277 /**
2278 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2279 */
2280 static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data, struct \
2281 TxD *txdlp, int get_off)
2282 {
2283 struct s2io_nic *nic = fifo_data->nic;
2284 struct sk_buff *skb;
2285 struct TxD *txds;
2286 u16 j, frg_cnt;
2287
2288 txds = txdlp;
2289 if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
2290 pci_unmap_single(nic->pdev, (dma_addr_t)
2291 txds->Buffer_Pointer, sizeof(u64),
2292 PCI_DMA_TODEVICE);
2293 txds++;
2294 }
2295
2296 skb = (struct sk_buff *) ((unsigned long)
2297 txds->Host_Control);
2298 if (!skb) {
2299 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2300 return NULL;
2301 }
2302 pci_unmap_single(nic->pdev, (dma_addr_t)
2303 txds->Buffer_Pointer,
2304 skb->len - skb->data_len,
2305 PCI_DMA_TODEVICE);
2306 frg_cnt = skb_shinfo(skb)->nr_frags;
2307 if (frg_cnt) {
2308 txds++;
2309 for (j = 0; j < frg_cnt; j++, txds++) {
2310 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2311 if (!txds->Buffer_Pointer)
2312 break;
2313 pci_unmap_page(nic->pdev, (dma_addr_t)
2314 txds->Buffer_Pointer,
2315 frag->size, PCI_DMA_TODEVICE);
2316 }
2317 }
2318 memset(txdlp,0, (sizeof(struct TxD) * fifo_data->max_txds));
2319 return(skb);
2320 }
2321
2322 /**
2323 * free_tx_buffers - Free all queued Tx buffers
2324 * @nic : device private variable.
2325 * Description:
2326 * Free all queued Tx buffers.
2327 * Return Value: void
2328 */
2329
2330 static void free_tx_buffers(struct s2io_nic *nic)
2331 {
2332 struct net_device *dev = nic->dev;
2333 struct sk_buff *skb;
2334 struct TxD *txdp;
2335 int i, j;
2336 struct mac_info *mac_control;
2337 struct config_param *config;
2338 int cnt = 0;
2339
2340 mac_control = &nic->mac_control;
2341 config = &nic->config;
2342
2343 for (i = 0; i < config->tx_fifo_num; i++) {
2344 unsigned long flags;
2345 spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags);
2346 for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
2347 txdp = (struct TxD *) \
2348 mac_control->fifos[i].list_info[j].list_virt_addr;
2349 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2350 if (skb) {
2351 nic->mac_control.stats_info->sw_stat.mem_freed
2352 += skb->truesize;
2353 dev_kfree_skb(skb);
2354 cnt++;
2355 }
2356 }
2357 DBG_PRINT(INTR_DBG,
2358 "%s:forcibly freeing %d skbs on FIFO%d\n",
2359 dev->name, cnt, i);
2360 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2361 mac_control->fifos[i].tx_curr_put_info.offset = 0;
2362 spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock, flags);
2363 }
2364 }
2365
2366 /**
2367 * stop_nic - To stop the nic
2368 * @nic ; device private variable.
2369 * Description:
2370 * This function does exactly the opposite of what the start_nic()
2371 * function does. This function is called to stop the device.
2372 * Return Value:
2373 * void.
2374 */
2375
2376 static void stop_nic(struct s2io_nic *nic)
2377 {
2378 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2379 register u64 val64 = 0;
2380 u16 interruptible;
2381 struct mac_info *mac_control;
2382 struct config_param *config;
2383
2384 mac_control = &nic->mac_control;
2385 config = &nic->config;
2386
2387 /* Disable all interrupts */
2388 en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
2389 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2390 interruptible |= TX_PIC_INTR;
2391 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2392
2393 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2394 val64 = readq(&bar0->adapter_control);
2395 val64 &= ~(ADAPTER_CNTL_EN);
2396 writeq(val64, &bar0->adapter_control);
2397 }
2398
2399 /**
2400 * fill_rx_buffers - Allocates the Rx side skbs
2401 * @nic: device private variable
2402 * @ring_no: ring number
2403 * Description:
2404 * The function allocates Rx side skbs and puts the physical
2405 * address of these buffers into the RxD buffer pointers, so that the NIC
2406 * can DMA the received frame into these locations.
2407 * The NIC supports 3 receive modes, viz
2408 * 1. single buffer,
2409 * 2. three buffer and
2410 * 3. Five buffer modes.
2411 * Each mode defines how many fragments the received frame will be split
2412 * up into by the NIC. The frame is split into L3 header, L4 Header,
2413 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2414 * is split into 3 fragments. As of now only single buffer mode is
2415 * supported.
2416 * Return Value:
2417 * SUCCESS on success or an appropriate -ve value on failure.
2418 */
2419
2420 static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
2421 {
2422 struct net_device *dev = nic->dev;
2423 struct sk_buff *skb;
2424 struct RxD_t *rxdp;
2425 int off, off1, size, block_no, block_no1;
2426 u32 alloc_tab = 0;
2427 u32 alloc_cnt;
2428 struct mac_info *mac_control;
2429 struct config_param *config;
2430 u64 tmp;
2431 struct buffAdd *ba;
2432 unsigned long flags;
2433 struct RxD_t *first_rxdp = NULL;
2434 u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
2435 struct RxD1 *rxdp1;
2436 struct RxD3 *rxdp3;
2437 struct swStat *stats = &nic->mac_control.stats_info->sw_stat;
2438
2439 mac_control = &nic->mac_control;
2440 config = &nic->config;
2441 alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
2442 atomic_read(&nic->rx_bufs_left[ring_no]);
2443
2444 block_no1 = mac_control->rings[ring_no].rx_curr_get_info.block_index;
2445 off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
2446 while (alloc_tab < alloc_cnt) {
2447 block_no = mac_control->rings[ring_no].rx_curr_put_info.
2448 block_index;
2449 off = mac_control->rings[ring_no].rx_curr_put_info.offset;
2450
2451 rxdp = mac_control->rings[ring_no].
2452 rx_blocks[block_no].rxds[off].virt_addr;
2453
2454 if ((block_no == block_no1) && (off == off1) &&
2455 (rxdp->Host_Control)) {
2456 DBG_PRINT(INTR_DBG, "%s: Get and Put",
2457 dev->name);
2458 DBG_PRINT(INTR_DBG, " info equated\n");
2459 goto end;
2460 }
2461 if (off && (off == rxd_count[nic->rxd_mode])) {
2462 mac_control->rings[ring_no].rx_curr_put_info.
2463 block_index++;
2464 if (mac_control->rings[ring_no].rx_curr_put_info.
2465 block_index == mac_control->rings[ring_no].
2466 block_count)
2467 mac_control->rings[ring_no].rx_curr_put_info.
2468 block_index = 0;
2469 block_no = mac_control->rings[ring_no].
2470 rx_curr_put_info.block_index;
2471 if (off == rxd_count[nic->rxd_mode])
2472 off = 0;
2473 mac_control->rings[ring_no].rx_curr_put_info.
2474 offset = off;
2475 rxdp = mac_control->rings[ring_no].
2476 rx_blocks[block_no].block_virt_addr;
2477 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2478 dev->name, rxdp);
2479 }
2480 if(!napi) {
2481 spin_lock_irqsave(&nic->put_lock, flags);
2482 mac_control->rings[ring_no].put_pos =
2483 (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2484 spin_unlock_irqrestore(&nic->put_lock, flags);
2485 } else {
2486 mac_control->rings[ring_no].put_pos =
2487 (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2488 }
2489 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2490 ((nic->rxd_mode == RXD_MODE_3B) &&
2491 (rxdp->Control_2 & s2BIT(0)))) {
2492 mac_control->rings[ring_no].rx_curr_put_info.
2493 offset = off;
2494 goto end;
2495 }
2496 /* calculate size of skb based on ring mode */
2497 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
2498 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2499 if (nic->rxd_mode == RXD_MODE_1)
2500 size += NET_IP_ALIGN;
2501 else
2502 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2503
2504 /* allocate skb */
2505 skb = dev_alloc_skb(size);
2506 if(!skb) {
2507 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
2508 DBG_PRINT(INFO_DBG, "memory to allocate SKBs\n");
2509 if (first_rxdp) {
2510 wmb();
2511 first_rxdp->Control_1 |= RXD_OWN_XENA;
2512 }
2513 nic->mac_control.stats_info->sw_stat. \
2514 mem_alloc_fail_cnt++;
2515 return -ENOMEM ;
2516 }
2517 nic->mac_control.stats_info->sw_stat.mem_allocated
2518 += skb->truesize;
2519 if (nic->rxd_mode == RXD_MODE_1) {
2520 /* 1 buffer mode - normal operation mode */
2521 rxdp1 = (struct RxD1*)rxdp;
2522 memset(rxdp, 0, sizeof(struct RxD1));
2523 skb_reserve(skb, NET_IP_ALIGN);
2524 rxdp1->Buffer0_ptr = pci_map_single
2525 (nic->pdev, skb->data, size - NET_IP_ALIGN,
2526 PCI_DMA_FROMDEVICE);
2527 if( (rxdp1->Buffer0_ptr == 0) ||
2528 (rxdp1->Buffer0_ptr ==
2529 DMA_ERROR_CODE))
2530 goto pci_map_failed;
2531
2532 rxdp->Control_2 =
2533 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2534
2535 } else if (nic->rxd_mode == RXD_MODE_3B) {
2536 /*
2537 * 2 buffer mode -
2538 * 2 buffer mode provides 128
2539 * byte aligned receive buffers.
2540 */
2541
2542 rxdp3 = (struct RxD3*)rxdp;
2543 /* save buffer pointers to avoid frequent dma mapping */
2544 Buffer0_ptr = rxdp3->Buffer0_ptr;
2545 Buffer1_ptr = rxdp3->Buffer1_ptr;
2546 memset(rxdp, 0, sizeof(struct RxD3));
2547 /* restore the buffer pointers for dma sync*/
2548 rxdp3->Buffer0_ptr = Buffer0_ptr;
2549 rxdp3->Buffer1_ptr = Buffer1_ptr;
2550
2551 ba = &mac_control->rings[ring_no].ba[block_no][off];
2552 skb_reserve(skb, BUF0_LEN);
2553 tmp = (u64)(unsigned long) skb->data;
2554 tmp += ALIGN_SIZE;
2555 tmp &= ~ALIGN_SIZE;
2556 skb->data = (void *) (unsigned long)tmp;
2557 skb_reset_tail_pointer(skb);
2558
2559 if (!(rxdp3->Buffer0_ptr))
2560 rxdp3->Buffer0_ptr =
2561 pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
2562 PCI_DMA_FROMDEVICE);
2563 else
2564 pci_dma_sync_single_for_device(nic->pdev,
2565 (dma_addr_t) rxdp3->Buffer0_ptr,
2566 BUF0_LEN, PCI_DMA_FROMDEVICE);
2567 if( (rxdp3->Buffer0_ptr == 0) ||
2568 (rxdp3->Buffer0_ptr == DMA_ERROR_CODE))
2569 goto pci_map_failed;
2570
2571 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2572 if (nic->rxd_mode == RXD_MODE_3B) {
2573 /* Two buffer mode */
2574
2575 /*
2576 * Buffer2 will have L3/L4 header plus
2577 * L4 payload
2578 */
2579 rxdp3->Buffer2_ptr = pci_map_single
2580 (nic->pdev, skb->data, dev->mtu + 4,
2581 PCI_DMA_FROMDEVICE);
2582
2583 if( (rxdp3->Buffer2_ptr == 0) ||
2584 (rxdp3->Buffer2_ptr == DMA_ERROR_CODE))
2585 goto pci_map_failed;
2586
2587 rxdp3->Buffer1_ptr =
2588 pci_map_single(nic->pdev,
2589 ba->ba_1, BUF1_LEN,
2590 PCI_DMA_FROMDEVICE);
2591 if( (rxdp3->Buffer1_ptr == 0) ||
2592 (rxdp3->Buffer1_ptr == DMA_ERROR_CODE)) {
2593 pci_unmap_single
2594 (nic->pdev,
2595 (dma_addr_t)rxdp3->Buffer2_ptr,
2596 dev->mtu + 4,
2597 PCI_DMA_FROMDEVICE);
2598 goto pci_map_failed;
2599 }
2600 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2601 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2602 (dev->mtu + 4);
2603 }
2604 rxdp->Control_2 |= s2BIT(0);
2605 }
2606 rxdp->Host_Control = (unsigned long) (skb);
2607 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2608 rxdp->Control_1 |= RXD_OWN_XENA;
2609 off++;
2610 if (off == (rxd_count[nic->rxd_mode] + 1))
2611 off = 0;
2612 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
2613
2614 rxdp->Control_2 |= SET_RXD_MARKER;
2615 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2616 if (first_rxdp) {
2617 wmb();
2618 first_rxdp->Control_1 |= RXD_OWN_XENA;
2619 }
2620 first_rxdp = rxdp;
2621 }
2622 atomic_inc(&nic->rx_bufs_left[ring_no]);
2623 alloc_tab++;
2624 }
2625
2626 end:
2627 /* Transfer ownership of first descriptor to adapter just before
2628 * exiting. Before that, use memory barrier so that ownership
2629 * and other fields are seen by adapter correctly.
2630 */
2631 if (first_rxdp) {
2632 wmb();
2633 first_rxdp->Control_1 |= RXD_OWN_XENA;
2634 }
2635
2636 return SUCCESS;
2637 pci_map_failed:
2638 stats->pci_map_fail_cnt++;
2639 stats->mem_freed += skb->truesize;
2640 dev_kfree_skb_irq(skb);
2641 return -ENOMEM;
2642 }
2643
2644 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2645 {
2646 struct net_device *dev = sp->dev;
2647 int j;
2648 struct sk_buff *skb;
2649 struct RxD_t *rxdp;
2650 struct mac_info *mac_control;
2651 struct buffAdd *ba;
2652 struct RxD1 *rxdp1;
2653 struct RxD3 *rxdp3;
2654
2655 mac_control = &sp->mac_control;
2656 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2657 rxdp = mac_control->rings[ring_no].
2658 rx_blocks[blk].rxds[j].virt_addr;
2659 skb = (struct sk_buff *)
2660 ((unsigned long) rxdp->Host_Control);
2661 if (!skb) {
2662 continue;
2663 }
2664 if (sp->rxd_mode == RXD_MODE_1) {
2665 rxdp1 = (struct RxD1*)rxdp;
2666 pci_unmap_single(sp->pdev, (dma_addr_t)
2667 rxdp1->Buffer0_ptr,
2668 dev->mtu +
2669 HEADER_ETHERNET_II_802_3_SIZE
2670 + HEADER_802_2_SIZE +
2671 HEADER_SNAP_SIZE,
2672 PCI_DMA_FROMDEVICE);
2673 memset(rxdp, 0, sizeof(struct RxD1));
2674 } else if(sp->rxd_mode == RXD_MODE_3B) {
2675 rxdp3 = (struct RxD3*)rxdp;
2676 ba = &mac_control->rings[ring_no].
2677 ba[blk][j];
2678 pci_unmap_single(sp->pdev, (dma_addr_t)
2679 rxdp3->Buffer0_ptr,
2680 BUF0_LEN,
2681 PCI_DMA_FROMDEVICE);
2682 pci_unmap_single(sp->pdev, (dma_addr_t)
2683 rxdp3->Buffer1_ptr,
2684 BUF1_LEN,
2685 PCI_DMA_FROMDEVICE);
2686 pci_unmap_single(sp->pdev, (dma_addr_t)
2687 rxdp3->Buffer2_ptr,
2688 dev->mtu + 4,
2689 PCI_DMA_FROMDEVICE);
2690 memset(rxdp, 0, sizeof(struct RxD3));
2691 }
2692 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
2693 dev_kfree_skb(skb);
2694 atomic_dec(&sp->rx_bufs_left[ring_no]);
2695 }
2696 }
2697
2698 /**
2699 * free_rx_buffers - Frees all Rx buffers
2700 * @sp: device private variable.
2701 * Description:
2702 * This function will free all Rx buffers allocated by host.
2703 * Return Value:
2704 * NONE.
2705 */
2706
2707 static void free_rx_buffers(struct s2io_nic *sp)
2708 {
2709 struct net_device *dev = sp->dev;
2710 int i, blk = 0, buf_cnt = 0;
2711 struct mac_info *mac_control;
2712 struct config_param *config;
2713
2714 mac_control = &sp->mac_control;
2715 config = &sp->config;
2716
2717 for (i = 0; i < config->rx_ring_num; i++) {
2718 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2719 free_rxd_blk(sp,i,blk);
2720
2721 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2722 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2723 mac_control->rings[i].rx_curr_put_info.offset = 0;
2724 mac_control->rings[i].rx_curr_get_info.offset = 0;
2725 atomic_set(&sp->rx_bufs_left[i], 0);
2726 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2727 dev->name, buf_cnt, i);
2728 }
2729 }
2730
2731 /**
2732 * s2io_poll - Rx interrupt handler for NAPI support
2733 * @napi : pointer to the napi structure.
2734 * @budget : The number of packets that were budgeted to be processed
2735 * during one pass through the 'Poll" function.
2736 * Description:
2737 * Comes into picture only if NAPI support has been incorporated. It does
2738 * the same thing that rx_intr_handler does, but not in a interrupt context
2739 * also It will process only a given number of packets.
2740 * Return value:
2741 * 0 on success and 1 if there are No Rx packets to be processed.
2742 */
2743
2744 static int s2io_poll(struct napi_struct *napi, int budget)
2745 {
2746 struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
2747 struct net_device *dev = nic->dev;
2748 int pkt_cnt = 0, org_pkts_to_process;
2749 struct mac_info *mac_control;
2750 struct config_param *config;
2751 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2752 int i;
2753
2754 mac_control = &nic->mac_control;
2755 config = &nic->config;
2756
2757 nic->pkts_to_process = budget;
2758 org_pkts_to_process = nic->pkts_to_process;
2759
2760 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
2761 readl(&bar0->rx_traffic_int);
2762
2763 for (i = 0; i < config->rx_ring_num; i++) {
2764 rx_intr_handler(&mac_control->rings[i]);
2765 pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
2766 if (!nic->pkts_to_process) {
2767 /* Quota for the current iteration has been met */
2768 goto no_rx;
2769 }
2770 }
2771
2772 netif_rx_complete(dev, napi);
2773
2774 for (i = 0; i < config->rx_ring_num; i++) {
2775 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2776 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2777 DBG_PRINT(INFO_DBG, " in Rx Poll!!\n");
2778 break;
2779 }
2780 }
2781 /* Re enable the Rx interrupts. */
2782 writeq(0x0, &bar0->rx_traffic_mask);
2783 readl(&bar0->rx_traffic_mask);
2784 return pkt_cnt;
2785
2786 no_rx:
2787 for (i = 0; i < config->rx_ring_num; i++) {
2788 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2789 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2790 DBG_PRINT(INFO_DBG, " in Rx Poll!!\n");
2791 break;
2792 }
2793 }
2794 return pkt_cnt;
2795 }
2796
2797 #ifdef CONFIG_NET_POLL_CONTROLLER
2798 /**
2799 * s2io_netpoll - netpoll event handler entry point
2800 * @dev : pointer to the device structure.
2801 * Description:
2802 * This function will be called by upper layer to check for events on the
2803 * interface in situations where interrupts are disabled. It is used for
2804 * specific in-kernel networking tasks, such as remote consoles and kernel
2805 * debugging over the network (example netdump in RedHat).
2806 */
2807 static void s2io_netpoll(struct net_device *dev)
2808 {
2809 struct s2io_nic *nic = dev->priv;
2810 struct mac_info *mac_control;
2811 struct config_param *config;
2812 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2813 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2814 int i;
2815
2816 if (pci_channel_offline(nic->pdev))
2817 return;
2818
2819 disable_irq(dev->irq);
2820
2821 mac_control = &nic->mac_control;
2822 config = &nic->config;
2823
2824 writeq(val64, &bar0->rx_traffic_int);
2825 writeq(val64, &bar0->tx_traffic_int);
2826
2827 /* we need to free up the transmitted skbufs or else netpoll will
2828 * run out of skbs and will fail and eventually netpoll application such
2829 * as netdump will fail.
2830 */
2831 for (i = 0; i < config->tx_fifo_num; i++)
2832 tx_intr_handler(&mac_control->fifos[i]);
2833
2834 /* check for received packet and indicate up to network */
2835 for (i = 0; i < config->rx_ring_num; i++)
2836 rx_intr_handler(&mac_control->rings[i]);
2837
2838 for (i = 0; i < config->rx_ring_num; i++) {
2839 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2840 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2841 DBG_PRINT(INFO_DBG, " in Rx Netpoll!!\n");
2842 break;
2843 }
2844 }
2845 enable_irq(dev->irq);
2846 return;
2847 }
2848 #endif
2849
2850 /**
2851 * rx_intr_handler - Rx interrupt handler
2852 * @nic: device private variable.
2853 * Description:
2854 * If the interrupt is because of a received frame or if the
2855 * receive ring contains fresh as yet un-processed frames,this function is
2856 * called. It picks out the RxD at which place the last Rx processing had
2857 * stopped and sends the skb to the OSM's Rx handler and then increments
2858 * the offset.
2859 * Return Value:
2860 * NONE.
2861 */
2862 static void rx_intr_handler(struct ring_info *ring_data)
2863 {
2864 struct s2io_nic *nic = ring_data->nic;
2865 struct net_device *dev = (struct net_device *) nic->dev;
2866 int get_block, put_block, put_offset;
2867 struct rx_curr_get_info get_info, put_info;
2868 struct RxD_t *rxdp;
2869 struct sk_buff *skb;
2870 int pkt_cnt = 0;
2871 int i;
2872 struct RxD1* rxdp1;
2873 struct RxD3* rxdp3;
2874
2875 spin_lock(&nic->rx_lock);
2876
2877 get_info = ring_data->rx_curr_get_info;
2878 get_block = get_info.block_index;
2879 memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
2880 put_block = put_info.block_index;
2881 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2882 if (!napi) {
2883 spin_lock(&nic->put_lock);
2884 put_offset = ring_data->put_pos;
2885 spin_unlock(&nic->put_lock);
2886 } else
2887 put_offset = ring_data->put_pos;
2888
2889 while (RXD_IS_UP2DT(rxdp)) {
2890 /*
2891 * If your are next to put index then it's
2892 * FIFO full condition
2893 */
2894 if ((get_block == put_block) &&
2895 (get_info.offset + 1) == put_info.offset) {
2896 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",dev->name);
2897 break;
2898 }
2899 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2900 if (skb == NULL) {
2901 DBG_PRINT(ERR_DBG, "%s: The skb is ",
2902 dev->name);
2903 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
2904 spin_unlock(&nic->rx_lock);
2905 return;
2906 }
2907 if (nic->rxd_mode == RXD_MODE_1) {
2908 rxdp1 = (struct RxD1*)rxdp;
2909 pci_unmap_single(nic->pdev, (dma_addr_t)
2910 rxdp1->Buffer0_ptr,
2911 dev->mtu +
2912 HEADER_ETHERNET_II_802_3_SIZE +
2913 HEADER_802_2_SIZE +
2914 HEADER_SNAP_SIZE,
2915 PCI_DMA_FROMDEVICE);
2916 } else if (nic->rxd_mode == RXD_MODE_3B) {
2917 rxdp3 = (struct RxD3*)rxdp;
2918 pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
2919 rxdp3->Buffer0_ptr,
2920 BUF0_LEN, PCI_DMA_FROMDEVICE);
2921 pci_unmap_single(nic->pdev, (dma_addr_t)
2922 rxdp3->Buffer2_ptr,
2923 dev->mtu + 4,
2924 PCI_DMA_FROMDEVICE);
2925 }
2926 prefetch(skb->data);
2927 rx_osm_handler(ring_data, rxdp);
2928 get_info.offset++;
2929 ring_data->rx_curr_get_info.offset = get_info.offset;
2930 rxdp = ring_data->rx_blocks[get_block].
2931 rxds[get_info.offset].virt_addr;
2932 if (get_info.offset == rxd_count[nic->rxd_mode]) {
2933 get_info.offset = 0;
2934 ring_data->rx_curr_get_info.offset = get_info.offset;
2935 get_block++;
2936 if (get_block == ring_data->block_count)
2937 get_block = 0;
2938 ring_data->rx_curr_get_info.block_index = get_block;
2939 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2940 }
2941
2942 nic->pkts_to_process -= 1;
2943 if ((napi) && (!nic->pkts_to_process))
2944 break;
2945 pkt_cnt++;
2946 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2947 break;
2948 }
2949 if (nic->lro) {
2950 /* Clear all LRO sessions before exiting */
2951 for (i=0; i<MAX_LRO_SESSIONS; i++) {
2952 struct lro *lro = &nic->lro0_n[i];
2953 if (lro->in_use) {
2954 update_L3L4_header(nic, lro);
2955 queue_rx_frame(lro->parent);
2956 clear_lro_session(lro);
2957 }
2958 }
2959 }
2960
2961 spin_unlock(&nic->rx_lock);
2962 }
2963
2964 /**
2965 * tx_intr_handler - Transmit interrupt handler
2966 * @nic : device private variable
2967 * Description:
2968 * If an interrupt was raised to indicate DMA complete of the
2969 * Tx packet, this function is called. It identifies the last TxD
2970 * whose buffer was freed and frees all skbs whose data have already
2971 * DMA'ed into the NICs internal memory.
2972 * Return Value:
2973 * NONE
2974 */
2975
2976 static void tx_intr_handler(struct fifo_info *fifo_data)
2977 {
2978 struct s2io_nic *nic = fifo_data->nic;
2979 struct net_device *dev = (struct net_device *) nic->dev;
2980 struct tx_curr_get_info get_info, put_info;
2981 struct sk_buff *skb;
2982 struct TxD *txdlp;
2983 unsigned long flags = 0;
2984 u8 err_mask;
2985
2986 if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
2987 return;
2988
2989 get_info = fifo_data->tx_curr_get_info;
2990 memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
2991 txdlp = (struct TxD *) fifo_data->list_info[get_info.offset].
2992 list_virt_addr;
2993 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
2994 (get_info.offset != put_info.offset) &&
2995 (txdlp->Host_Control)) {
2996 /* Check for TxD errors */
2997 if (txdlp->Control_1 & TXD_T_CODE) {
2998 unsigned long long err;
2999 err = txdlp->Control_1 & TXD_T_CODE;
3000 if (err & 0x1) {
3001 nic->mac_control.stats_info->sw_stat.
3002 parity_err_cnt++;
3003 }
3004
3005 /* update t_code statistics */
3006 err_mask = err >> 48;
3007 switch(err_mask) {
3008 case 2:
3009 nic->mac_control.stats_info->sw_stat.
3010 tx_buf_abort_cnt++;
3011 break;
3012
3013 case 3:
3014 nic->mac_control.stats_info->sw_stat.
3015 tx_desc_abort_cnt++;
3016 break;
3017
3018 case 7:
3019 nic->mac_control.stats_info->sw_stat.
3020 tx_parity_err_cnt++;
3021 break;
3022
3023 case 10:
3024 nic->mac_control.stats_info->sw_stat.
3025 tx_link_loss_cnt++;
3026 break;
3027
3028 case 15:
3029 nic->mac_control.stats_info->sw_stat.
3030 tx_list_proc_err_cnt++;
3031 break;
3032 }
3033 }
3034
3035 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
3036 if (skb == NULL) {
3037 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3038 DBG_PRINT(ERR_DBG, "%s: Null skb ",
3039 __FUNCTION__);
3040 DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
3041 return;
3042 }
3043
3044 /* Updating the statistics block */
3045 nic->stats.tx_bytes += skb->len;
3046 nic->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
3047 dev_kfree_skb_irq(skb);
3048
3049 get_info.offset++;
3050 if (get_info.offset == get_info.fifo_len + 1)
3051 get_info.offset = 0;
3052 txdlp = (struct TxD *) fifo_data->list_info
3053 [get_info.offset].list_virt_addr;
3054 fifo_data->tx_curr_get_info.offset =
3055 get_info.offset;
3056 }
3057
3058 if (netif_queue_stopped(dev))
3059 netif_wake_queue(dev);
3060
3061 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3062 }
3063
3064 /**
3065 * s2io_mdio_write - Function to write in to MDIO registers
3066 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3067 * @addr : address value
3068 * @value : data value
3069 * @dev : pointer to net_device structure
3070 * Description:
3071 * This function is used to write values to the MDIO registers
3072 * NONE
3073 */
3074 static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
3075 {
3076 u64 val64 = 0x0;
3077 struct s2io_nic *sp = dev->priv;
3078 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3079
3080 //address transaction
3081 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3082 | MDIO_MMD_DEV_ADDR(mmd_type)
3083 | MDIO_MMS_PRT_ADDR(0x0);
3084 writeq(val64, &bar0->mdio_control);
3085 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3086 writeq(val64, &bar0->mdio_control);
3087 udelay(100);
3088
3089 //Data transaction
3090 val64 = 0x0;
3091 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3092 | MDIO_MMD_DEV_ADDR(mmd_type)
3093 | MDIO_MMS_PRT_ADDR(0x0)
3094 | MDIO_MDIO_DATA(value)
3095 | MDIO_OP(MDIO_OP_WRITE_TRANS);
3096 writeq(val64, &bar0->mdio_control);
3097 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3098 writeq(val64, &bar0->mdio_control);
3099 udelay(100);
3100
3101 val64 = 0x0;
3102 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3103 | MDIO_MMD_DEV_ADDR(mmd_type)
3104 | MDIO_MMS_PRT_ADDR(0x0)
3105 | MDIO_OP(MDIO_OP_READ_TRANS);
3106 writeq(val64, &bar0->mdio_control);
3107 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3108 writeq(val64, &bar0->mdio_control);
3109 udelay(100);
3110
3111 }
3112
3113 /**
3114 * s2io_mdio_read - Function to write in to MDIO registers
3115 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3116 * @addr : address value
3117 * @dev : pointer to net_device structure
3118 * Description:
3119 * This function is used to read values to the MDIO registers
3120 * NONE
3121 */
3122 static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3123 {
3124 u64 val64 = 0x0;
3125 u64 rval64 = 0x0;
3126 struct s2io_nic *sp = dev->priv;
3127 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3128
3129 /* address transaction */
3130 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3131 | MDIO_MMD_DEV_ADDR(mmd_type)
3132 | MDIO_MMS_PRT_ADDR(0x0);
3133 writeq(val64, &bar0->mdio_control);
3134 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3135 writeq(val64, &bar0->mdio_control);
3136 udelay(100);
3137
3138 /* Data transaction */
3139 val64 = 0x0;
3140 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3141 | MDIO_MMD_DEV_ADDR(mmd_type)
3142 | MDIO_MMS_PRT_ADDR(0x0)
3143 | MDIO_OP(MDIO_OP_READ_TRANS);
3144 writeq(val64, &bar0->mdio_control);
3145 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3146 writeq(val64, &bar0->mdio_control);
3147 udelay(100);
3148
3149 /* Read the value from regs */
3150 rval64 = readq(&bar0->mdio_control);
3151 rval64 = rval64 & 0xFFFF0000;
3152 rval64 = rval64 >> 16;
3153 return rval64;
3154 }
3155 /**
3156 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
3157 * @counter : couter value to be updated
3158 * @flag : flag to indicate the status
3159 * @type : counter type
3160 * Description:
3161 * This function is to check the status of the xpak counters value
3162 * NONE
3163 */
3164
3165 static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
3166 {
3167 u64 mask = 0x3;
3168 u64 val64;
3169 int i;
3170 for(i = 0; i <index; i++)
3171 mask = mask << 0x2;
3172
3173 if(flag > 0)
3174 {
3175 *counter = *counter + 1;
3176 val64 = *regs_stat & mask;
3177 val64 = val64 >> (index * 0x2);
3178 val64 = val64 + 1;
3179 if(val64 == 3)
3180 {
3181 switch(type)
3182 {
3183 case 1:
3184 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3185 "service. Excessive temperatures may "
3186 "result in premature transceiver "
3187 "failure \n");
3188 break;
3189 case 2:
3190 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3191 "service Excessive bias currents may "
3192 "indicate imminent laser diode "
3193 "failure \n");
3194 break;
3195 case 3:
3196 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3197 "service Excessive laser output "
3198 "power may saturate far-end "
3199 "receiver\n");
3200 break;
3201 default:
3202 DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
3203 "type \n");
3204 }
3205 val64 = 0x0;
3206 }
3207 val64 = val64 << (index * 0x2);
3208 *regs_stat = (*regs_stat & (~mask)) | (val64);
3209
3210 } else {
3211 *regs_stat = *regs_stat & (~mask);
3212 }
3213 }
3214
3215 /**
3216 * s2io_updt_xpak_counter - Function to update the xpak counters
3217 * @dev : pointer to net_device struct
3218 * Description:
3219 * This function is to upate the status of the xpak counters value
3220 * NONE
3221 */
3222 static void s2io_updt_xpak_counter(struct net_device *dev)
3223 {
3224 u16 flag = 0x0;
3225 u16 type = 0x0;
3226 u16 val16 = 0x0;
3227 u64 val64 = 0x0;
3228 u64 addr = 0x0;
3229
3230 struct s2io_nic *sp = dev->priv;
3231 struct stat_block *stat_info = sp->mac_control.stats_info;
3232
3233 /* Check the communication with the MDIO slave */
3234 addr = 0x0000;
3235 val64 = 0x0;
3236 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3237 if((val64 == 0xFFFF) || (val64 == 0x0000))
3238 {
3239 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
3240 "Returned %llx\n", (unsigned long long)val64);
3241 return;
3242 }
3243
3244 /* Check for the expecte value of 2040 at PMA address 0x0000 */
3245 if(val64 != 0x2040)
3246 {
3247 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
3248 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x2040\n",
3249 (unsigned long long)val64);
3250 return;
3251 }
3252
3253 /* Loading the DOM register to MDIO register */
3254 addr = 0xA100;
3255 s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR, addr, val16, dev);
3256 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3257
3258 /* Reading the Alarm flags */
3259 addr = 0xA070;
3260 val64 = 0x0;
3261 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3262
3263 flag = CHECKBIT(val64, 0x7);
3264 type = 1;
3265 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
3266 &stat_info->xpak_stat.xpak_regs_stat,
3267 0x0, flag, type);
3268
3269 if(CHECKBIT(val64, 0x6))
3270 stat_info->xpak_stat.alarm_transceiver_temp_low++;
3271
3272 flag = CHECKBIT(val64, 0x3);
3273 type = 2;
3274 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
3275 &stat_info->xpak_stat.xpak_regs_stat,
3276 0x2, flag, type);
3277
3278 if(CHECKBIT(val64, 0x2))
3279 stat_info->xpak_stat.alarm_laser_bias_current_low++;
3280
3281 flag = CHECKBIT(val64, 0x1);
3282 type = 3;
3283 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
3284 &stat_info->xpak_stat.xpak_regs_stat,
3285 0x4, flag, type);
3286
3287 if(CHECKBIT(val64, 0x0))
3288 stat_info->xpak_stat.alarm_laser_output_power_low++;
3289
3290 /* Reading the Warning flags */
3291 addr = 0xA074;
3292 val64 = 0x0;
3293 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3294
3295 if(CHECKBIT(val64, 0x7))
3296 stat_info->xpak_stat.warn_transceiver_temp_high++;
3297
3298 if(CHECKBIT(val64, 0x6))
3299 stat_info->xpak_stat.warn_transceiver_temp_low++;
3300
3301 if(CHECKBIT(val64, 0x3))
3302 stat_info->xpak_stat.warn_laser_bias_current_high++;
3303
3304 if(CHECKBIT(val64, 0x2))
3305 stat_info->xpak_stat.warn_laser_bias_current_low++;
3306
3307 if(CHECKBIT(val64, 0x1))
3308 stat_info->xpak_stat.warn_laser_output_power_high++;
3309
3310 if(CHECKBIT(val64, 0x0))
3311 stat_info->xpak_stat.warn_laser_output_power_low++;
3312 }
3313
3314 /**
3315 * wait_for_cmd_complete - waits for a command to complete.
3316 * @sp : private member of the device structure, which is a pointer to the
3317 * s2io_nic structure.
3318 * Description: Function that waits for a command to Write into RMAC
3319 * ADDR DATA registers to be completed and returns either success or
3320 * error depending on whether the command was complete or not.
3321 * Return value:
3322 * SUCCESS on success and FAILURE on failure.
3323 */
3324
3325 static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3326 int bit_state)
3327 {
3328 int ret = FAILURE, cnt = 0, delay = 1;
3329 u64 val64;
3330
3331 if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3332 return FAILURE;
3333
3334 do {
3335 val64 = readq(addr);
3336 if (bit_state == S2IO_BIT_RESET) {
3337 if (!(val64 & busy_bit)) {
3338 ret = SUCCESS;
3339 break;
3340 }
3341 } else {
3342 if (!(val64 & busy_bit)) {
3343 ret = SUCCESS;
3344 break;
3345 }
3346 }
3347
3348 if(in_interrupt())
3349 mdelay(delay);
3350 else
3351 msleep(delay);
3352
3353 if (++cnt >= 10)
3354 delay = 50;
3355 } while (cnt < 20);
3356 return ret;
3357 }
3358 /*
3359 * check_pci_device_id - Checks if the device id is supported
3360 * @id : device id
3361 * Description: Function to check if the pci device id is supported by driver.
3362 * Return value: Actual device id if supported else PCI_ANY_ID
3363 */
3364 static u16 check_pci_device_id(u16 id)
3365 {
3366 switch (id) {
3367 case PCI_DEVICE_ID_HERC_WIN:
3368 case PCI_DEVICE_ID_HERC_UNI:
3369 return XFRAME_II_DEVICE;
3370 case PCI_DEVICE_ID_S2IO_UNI:
3371 case PCI_DEVICE_ID_S2IO_WIN:
3372 return XFRAME_I_DEVICE;
3373 default:
3374 return PCI_ANY_ID;
3375 }
3376 }
3377
3378 /**
3379 * s2io_reset - Resets the card.
3380 * @sp : private member of the device structure.
3381 * Description: Function to Reset the card. This function then also
3382 * restores the previously saved PCI configuration space registers as
3383 * the card reset also resets the configuration space.
3384 * Return value:
3385 * void.
3386 */
3387
3388 static void s2io_reset(struct s2io_nic * sp)
3389 {
3390 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3391 u64 val64;
3392 u16 subid, pci_cmd;
3393 int i;
3394 u16 val16;
3395 unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3396 unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3397
3398 DBG_PRINT(INIT_DBG,"%s - Resetting XFrame card %s\n",
3399 __FUNCTION__, sp->dev->name);
3400
3401 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3402 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
3403
3404 val64 = SW_RESET_ALL;
3405 writeq(val64, &bar0->sw_reset);
3406 if (strstr(sp->product_name, "CX4")) {
3407 msleep(750);
3408 }
3409 msleep(250);
3410 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
3411
3412 /* Restore the PCI state saved during initialization. */
3413 pci_restore_state(sp->pdev);
3414 pci_read_config_word(sp->pdev, 0x2, &val16);
3415 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3416 break;
3417 msleep(200);
3418 }
3419
3420 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID) {
3421 DBG_PRINT(ERR_DBG,"%s SW_Reset failed!\n", __FUNCTION__);
3422 }
3423
3424 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3425
3426 s2io_init_pci(sp);
3427
3428 /* Set swapper to enable I/O register access */
3429 s2io_set_swapper(sp);
3430
3431 /* restore mac_addr entries */
3432 do_s2io_restore_unicast_mc(sp);
3433
3434 /* Restore the MSIX table entries from local variables */
3435 restore_xmsi_data(sp);
3436
3437 /* Clear certain PCI/PCI-X fields after reset */
3438 if (sp->device_type == XFRAME_II_DEVICE) {
3439 /* Clear "detected parity error" bit */
3440 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
3441
3442 /* Clearing PCIX Ecc status register */
3443 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
3444
3445 /* Clearing PCI_STATUS error reflected here */
3446 writeq(s2BIT(62), &bar0->txpic_int_reg);
3447 }
3448
3449 /* Reset device statistics maintained by OS */
3450 memset(&sp->stats, 0, sizeof (struct net_device_stats));
3451
3452 up_cnt = sp->mac_control.stats_info->sw_stat.link_up_cnt;
3453 down_cnt = sp->mac_control.stats_info->sw_stat.link_down_cnt;
3454 up_time = sp->mac_control.stats_info->sw_stat.link_up_time;
3455 down_time = sp->mac_control.stats_info->sw_stat.link_down_time;
3456 reset_cnt = sp->mac_control.stats_info->sw_stat.soft_reset_cnt;
3457 mem_alloc_cnt = sp->mac_control.stats_info->sw_stat.mem_allocated;
3458 mem_free_cnt = sp->mac_control.stats_info->sw_stat.mem_freed;
3459 watchdog_cnt = sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt;
3460 /* save link up/down time/cnt, reset/memory/watchdog cnt */
3461 memset(sp->mac_control.stats_info, 0, sizeof(struct stat_block));
3462 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3463 sp->mac_control.stats_info->sw_stat.link_up_cnt = up_cnt;
3464 sp->mac_control.stats_info->sw_stat.link_down_cnt = down_cnt;
3465 sp->mac_control.stats_info->sw_stat.link_up_time = up_time;
3466 sp->mac_control.stats_info->sw_stat.link_down_time = down_time;
3467 sp->mac_control.stats_info->sw_stat.soft_reset_cnt = reset_cnt;
3468 sp->mac_control.stats_info->sw_stat.mem_allocated = mem_alloc_cnt;
3469 sp->mac_control.stats_info->sw_stat.mem_freed = mem_free_cnt;
3470 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt = watchdog_cnt;
3471
3472 /* SXE-002: Configure link and activity LED to turn it off */
3473 subid = sp->pdev->subsystem_device;
3474 if (((subid & 0xFF) >= 0x07) &&
3475 (sp->device_type == XFRAME_I_DEVICE)) {
3476 val64 = readq(&bar0->gpio_control);
3477 val64 |= 0x0000800000000000ULL;
3478 writeq(val64, &bar0->gpio_control);
3479 val64 = 0x0411040400000000ULL;
3480 writeq(val64, (void __iomem *)bar0 + 0x2700);
3481 }
3482
3483 /*
3484 * Clear spurious ECC interrupts that would have occured on
3485 * XFRAME II cards after reset.
3486 */
3487 if (sp->device_type == XFRAME_II_DEVICE) {
3488 val64 = readq(&bar0->pcc_err_reg);
3489 writeq(val64, &bar0->pcc_err_reg);
3490 }
3491
3492 sp->device_enabled_once = FALSE;
3493 }
3494
3495 /**
3496 * s2io_set_swapper - to set the swapper controle on the card
3497 * @sp : private member of the device structure,
3498 * pointer to the s2io_nic structure.
3499 * Description: Function to set the swapper control on the card
3500 * correctly depending on the 'endianness' of the system.
3501 * Return value:
3502 * SUCCESS on success and FAILURE on failure.
3503 */
3504
3505 static int s2io_set_swapper(struct s2io_nic * sp)
3506 {
3507 struct net_device *dev = sp->dev;
3508 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3509 u64 val64, valt, valr;
3510
3511 /*
3512 * Set proper endian settings and verify the same by reading
3513 * the PIF Feed-back register.
3514 */
3515
3516 val64 = readq(&bar0->pif_rd_swapper_fb);
3517 if (val64 != 0x0123456789ABCDEFULL) {
3518 int i = 0;
3519 u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3520 0x8100008181000081ULL, /* FE=1, SE=0 */
3521 0x4200004242000042ULL, /* FE=0, SE=1 */
3522 0}; /* FE=0, SE=0 */
3523
3524 while(i<4) {
3525 writeq(value[i], &bar0->swapper_ctrl);
3526 val64 = readq(&bar0->pif_rd_swapper_fb);
3527 if (val64 == 0x0123456789ABCDEFULL)
3528 break;
3529 i++;
3530 }
3531 if (i == 4) {
3532 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3533 dev->name);
3534 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3535 (unsigned long long) val64);
3536 return FAILURE;
3537 }
3538 valr = value[i];
3539 } else {
3540 valr = readq(&bar0->swapper_ctrl);
3541 }
3542
3543 valt = 0x0123456789ABCDEFULL;
3544 writeq(valt, &bar0->xmsi_address);
3545 val64 = readq(&bar0->xmsi_address);
3546
3547 if(val64 != valt) {
3548 int i = 0;
3549 u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3550 0x0081810000818100ULL, /* FE=1, SE=0 */
3551 0x0042420000424200ULL, /* FE=0, SE=1 */
3552 0}; /* FE=0, SE=0 */
3553
3554 while(i<4) {
3555 writeq((value[i] | valr), &bar0->swapper_ctrl);
3556 writeq(valt, &bar0->xmsi_address);
3557 val64 = readq(&bar0->xmsi_address);
3558 if(val64 == valt)
3559 break;
3560 i++;
3561 }
3562 if(i == 4) {
3563 unsigned long long x = val64;
3564 DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
3565 DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
3566 return FAILURE;
3567 }
3568 }
3569 val64 = readq(&bar0->swapper_ctrl);
3570 val64 &= 0xFFFF000000000000ULL;
3571
3572 #ifdef __BIG_ENDIAN
3573 /*
3574 * The device by default set to a big endian format, so a
3575 * big endian driver need not set anything.
3576 */
3577 val64 |= (SWAPPER_CTRL_TXP_FE |
3578 SWAPPER_CTRL_TXP_SE |
3579 SWAPPER_CTRL_TXD_R_FE |
3580 SWAPPER_CTRL_TXD_W_FE |
3581 SWAPPER_CTRL_TXF_R_FE |
3582 SWAPPER_CTRL_RXD_R_FE |
3583 SWAPPER_CTRL_RXD_W_FE |
3584 SWAPPER_CTRL_RXF_W_FE |
3585 SWAPPER_CTRL_XMSI_FE |
3586 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3587 if (sp->config.intr_type == INTA)
3588 val64 |= SWAPPER_CTRL_XMSI_SE;
3589 writeq(val64, &bar0->swapper_ctrl);
3590 #else
3591 /*
3592 * Initially we enable all bits to make it accessible by the
3593 * driver, then we selectively enable only those bits that
3594 * we want to set.
3595 */
3596 val64 |= (SWAPPER_CTRL_TXP_FE |
3597 SWAPPER_CTRL_TXP_SE |
3598 SWAPPER_CTRL_TXD_R_FE |
3599 SWAPPER_CTRL_TXD_R_SE |
3600 SWAPPER_CTRL_TXD_W_FE |
3601 SWAPPER_CTRL_TXD_W_SE |
3602 SWAPPER_CTRL_TXF_R_FE |
3603 SWAPPER_CTRL_RXD_R_FE |
3604 SWAPPER_CTRL_RXD_R_SE |
3605 SWAPPER_CTRL_RXD_W_FE |
3606 SWAPPER_CTRL_RXD_W_SE |
3607 SWAPPER_CTRL_RXF_W_FE |
3608 SWAPPER_CTRL_XMSI_FE |
3609 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3610 if (sp->config.intr_type == INTA)
3611 val64 |= SWAPPER_CTRL_XMSI_SE;
3612 writeq(val64, &bar0->swapper_ctrl);
3613 #endif
3614 val64 = readq(&bar0->swapper_ctrl);
3615
3616 /*
3617 * Verifying if endian settings are accurate by reading a
3618 * feedback register.
3619 */
3620 val64 = readq(&bar0->pif_rd_swapper_fb);
3621 if (val64 != 0x0123456789ABCDEFULL) {
3622 /* Endian settings are incorrect, calls for another dekko. */
3623 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3624 dev->name);
3625 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3626 (unsigned long long) val64);
3627 return FAILURE;
3628 }
3629
3630 return SUCCESS;
3631 }
3632
3633 static int wait_for_msix_trans(struct s2io_nic *nic, int i)
3634 {
3635 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3636 u64 val64;
3637 int ret = 0, cnt = 0;
3638
3639 do {
3640 val64 = readq(&bar0->xmsi_access);
3641 if (!(val64 & s2BIT(15)))
3642 break;
3643 mdelay(1);
3644 cnt++;
3645 } while(cnt < 5);
3646 if (cnt == 5) {
3647 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3648 ret = 1;
3649 }
3650
3651 return ret;
3652 }
3653
3654 static void restore_xmsi_data(struct s2io_nic *nic)
3655 {
3656 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3657 u64 val64;
3658 int i;
3659
3660 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
3661 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3662 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3663 val64 = (s2BIT(7) | s2BIT(15) | vBIT(i, 26, 6));
3664 writeq(val64, &bar0->xmsi_access);
3665 if (wait_for_msix_trans(nic, i)) {
3666 DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3667 continue;
3668 }
3669 }
3670 }
3671
3672 static void store_xmsi_data(struct s2io_nic *nic)
3673 {
3674 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3675 u64 val64, addr, data;
3676 int i;
3677
3678 /* Store and display */
3679 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
3680 val64 = (s2BIT(15) | vBIT(i, 26, 6));
3681 writeq(val64, &bar0->xmsi_access);
3682 if (wait_for_msix_trans(nic, i)) {
3683 DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3684 continue;
3685 }
3686 addr = readq(&bar0->xmsi_address);
3687 data = readq(&bar0->xmsi_data);
3688 if (addr && data) {
3689 nic->msix_info[i].addr = addr;
3690 nic->msix_info[i].data = data;
3691 }
3692 }
3693 }
3694
3695 static int s2io_enable_msi_x(struct s2io_nic *nic)
3696 {
3697 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3698 u64 tx_mat, rx_mat;
3699 u16 msi_control; /* Temp variable */
3700 int ret, i, j, msix_indx = 1;
3701
3702 nic->entries = kcalloc(MAX_REQUESTED_MSI_X, sizeof(struct msix_entry),
3703 GFP_KERNEL);
3704 if (!nic->entries) {
3705 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n", \
3706 __FUNCTION__);
3707 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
3708 return -ENOMEM;
3709 }
3710 nic->mac_control.stats_info->sw_stat.mem_allocated
3711 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3712
3713 nic->s2io_entries =
3714 kcalloc(MAX_REQUESTED_MSI_X, sizeof(struct s2io_msix_entry),
3715 GFP_KERNEL);
3716 if (!nic->s2io_entries) {
3717 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3718 __FUNCTION__);
3719 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
3720 kfree(nic->entries);
3721 nic->mac_control.stats_info->sw_stat.mem_freed
3722 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3723 return -ENOMEM;
3724 }
3725 nic->mac_control.stats_info->sw_stat.mem_allocated
3726 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3727
3728 for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3729 nic->entries[i].entry = i;
3730 nic->s2io_entries[i].entry = i;
3731 nic->s2io_entries[i].arg = NULL;
3732 nic->s2io_entries[i].in_use = 0;
3733 }
3734
3735 tx_mat = readq(&bar0->tx_mat0_n[0]);
3736 for (i=0; i<nic->config.tx_fifo_num; i++, msix_indx++) {
3737 tx_mat |= TX_MAT_SET(i, msix_indx);
3738 nic->s2io_entries[msix_indx].arg = &nic->mac_control.fifos[i];
3739 nic->s2io_entries[msix_indx].type = MSIX_FIFO_TYPE;
3740 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3741 }
3742 writeq(tx_mat, &bar0->tx_mat0_n[0]);
3743
3744 rx_mat = readq(&bar0->rx_mat);
3745 for (j = 0; j < nic->config.rx_ring_num; j++, msix_indx++) {
3746 rx_mat |= RX_MAT_SET(j, msix_indx);
3747 nic->s2io_entries[msix_indx].arg
3748 = &nic->mac_control.rings[j];
3749 nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3750 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3751 }
3752 writeq(rx_mat, &bar0->rx_mat);
3753
3754 nic->avail_msix_vectors = 0;
3755 ret = pci_enable_msix(nic->pdev, nic->entries, MAX_REQUESTED_MSI_X);
3756 /* We fail init if error or we get less vectors than min required */
3757 if (ret >= (nic->config.tx_fifo_num + nic->config.rx_ring_num + 1)) {
3758 nic->avail_msix_vectors = ret;
3759 ret = pci_enable_msix(nic->pdev, nic->entries, ret);
3760 }
3761 if (ret) {
3762 DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name);
3763 kfree(nic->entries);
3764 nic->mac_control.stats_info->sw_stat.mem_freed
3765 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3766 kfree(nic->s2io_entries);
3767 nic->mac_control.stats_info->sw_stat.mem_freed
3768 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3769 nic->entries = NULL;
3770 nic->s2io_entries = NULL;
3771 nic->avail_msix_vectors = 0;
3772 return -ENOMEM;
3773 }
3774 if (!nic->avail_msix_vectors)
3775 nic->avail_msix_vectors = MAX_REQUESTED_MSI_X;
3776
3777 /*
3778 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3779 * in the herc NIC. (Temp change, needs to be removed later)
3780 */
3781 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3782 msi_control |= 0x1; /* Enable MSI */
3783 pci_write_config_word(nic->pdev, 0x42, msi_control);
3784
3785 return 0;
3786 }
3787
3788 /* Handle software interrupt used during MSI(X) test */
3789 static irqreturn_t s2io_test_intr(int irq, void *dev_id)
3790 {
3791 struct s2io_nic *sp = dev_id;
3792
3793 sp->msi_detected = 1;
3794 wake_up(&sp->msi_wait);
3795
3796 return IRQ_HANDLED;
3797 }
3798
3799 /* Test interrupt path by forcing a a software IRQ */
3800 static int s2io_test_msi(struct s2io_nic *sp)
3801 {
3802 struct pci_dev *pdev = sp->pdev;
3803 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3804 int err;
3805 u64 val64, saved64;
3806
3807 err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
3808 sp->name, sp);
3809 if (err) {
3810 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
3811 sp->dev->name, pci_name(pdev), pdev->irq);
3812 return err;
3813 }
3814
3815 init_waitqueue_head (&sp->msi_wait);
3816 sp->msi_detected = 0;
3817
3818 saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3819 val64 |= SCHED_INT_CTRL_ONE_SHOT;
3820 val64 |= SCHED_INT_CTRL_TIMER_EN;
3821 val64 |= SCHED_INT_CTRL_INT2MSI(1);
3822 writeq(val64, &bar0->scheduled_int_ctrl);
3823
3824 wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3825
3826 if (!sp->msi_detected) {
3827 /* MSI(X) test failed, go back to INTx mode */
3828 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
3829 "using MSI(X) during test\n", sp->dev->name,
3830 pci_name(pdev));
3831
3832 err = -EOPNOTSUPP;
3833 }
3834
3835 free_irq(sp->entries[1].vector, sp);
3836
3837 writeq(saved64, &bar0->scheduled_int_ctrl);
3838
3839 return err;
3840 }
3841
3842 static void remove_msix_isr(struct s2io_nic *sp)
3843 {
3844 int i;
3845 u16 msi_control;
3846
3847 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3848 if (sp->s2io_entries[i].in_use ==
3849 MSIX_REGISTERED_SUCCESS) {
3850 int vector = sp->entries[i].vector;
3851 void *arg = sp->s2io_entries[i].arg;
3852 free_irq(vector, arg);
3853 }
3854 }
3855
3856 kfree(sp->entries);
3857 kfree(sp->s2io_entries);
3858 sp->entries = NULL;
3859 sp->s2io_entries = NULL;
3860
3861 pci_read_config_word(sp->pdev, 0x42, &msi_control);
3862 msi_control &= 0xFFFE; /* Disable MSI */
3863 pci_write_config_word(sp->pdev, 0x42, msi_control);
3864
3865 pci_disable_msix(sp->pdev);
3866 }
3867
3868 static void remove_inta_isr(struct s2io_nic *sp)
3869 {
3870 struct net_device *dev = sp->dev;
3871
3872 free_irq(sp->pdev->irq, dev);
3873 }
3874
3875 /* ********************************************************* *
3876 * Functions defined below concern the OS part of the driver *
3877 * ********************************************************* */
3878
3879 /**
3880 * s2io_open - open entry point of the driver
3881 * @dev : pointer to the device structure.
3882 * Description:
3883 * This function is the open entry point of the driver. It mainly calls a
3884 * function to allocate Rx buffers and inserts them into the buffer
3885 * descriptors and then enables the Rx part of the NIC.
3886 * Return value:
3887 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3888 * file on failure.
3889 */
3890
3891 static int s2io_open(struct net_device *dev)
3892 {
3893 struct s2io_nic *sp = dev->priv;
3894 int err = 0;
3895
3896 /*
3897 * Make sure you have link off by default every time
3898 * Nic is initialized
3899 */
3900 netif_carrier_off(dev);
3901 sp->last_link_state = 0;
3902
3903 if (sp->config.intr_type == MSI_X) {
3904 int ret = s2io_enable_msi_x(sp);
3905
3906 if (!ret) {
3907 ret = s2io_test_msi(sp);
3908 /* rollback MSI-X, will re-enable during add_isr() */
3909 remove_msix_isr(sp);
3910 }
3911 if (ret) {
3912
3913 DBG_PRINT(ERR_DBG,
3914 "%s: MSI-X requested but failed to enable\n",
3915 dev->name);
3916 sp->config.intr_type = INTA;
3917 }
3918 }
3919
3920 /* NAPI doesn't work well with MSI(X) */
3921 if (sp->config.intr_type != INTA) {
3922 if(sp->config.napi)
3923 sp->config.napi = 0;
3924 }
3925
3926 /* Initialize H/W and enable interrupts */
3927 err = s2io_card_up(sp);
3928 if (err) {
3929 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3930 dev->name);
3931 goto hw_init_failed;
3932 }
3933
3934 if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
3935 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
3936 s2io_card_down(sp);
3937 err = -ENODEV;
3938 goto hw_init_failed;
3939 }
3940
3941 netif_start_queue(dev);
3942 return 0;
3943
3944 hw_init_failed:
3945 if (sp->config.intr_type == MSI_X) {
3946 if (sp->entries) {
3947 kfree(sp->entries);
3948 sp->mac_control.stats_info->sw_stat.mem_freed
3949 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3950 }
3951 if (sp->s2io_entries) {
3952 kfree(sp->s2io_entries);
3953 sp->mac_control.stats_info->sw_stat.mem_freed
3954 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3955 }
3956 }
3957 return err;
3958 }
3959
3960 /**
3961 * s2io_close -close entry point of the driver
3962 * @dev : device pointer.
3963 * Description:
3964 * This is the stop entry point of the driver. It needs to undo exactly
3965 * whatever was done by the open entry point,thus it's usually referred to
3966 * as the close function.Among other things this function mainly stops the
3967 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
3968 * Return value:
3969 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3970 * file on failure.
3971 */
3972
3973 static int s2io_close(struct net_device *dev)
3974 {
3975 struct s2io_nic *sp = dev->priv;
3976 struct config_param *config = &sp->config;
3977 u64 tmp64;
3978 int offset;
3979
3980 /* Return if the device is already closed *
3981 * Can happen when s2io_card_up failed in change_mtu *
3982 */
3983 if (!is_s2io_card_up(sp))
3984 return 0;
3985
3986 netif_stop_queue(dev);
3987
3988 /* delete all populated mac entries */
3989 for (offset = 1; offset < config->max_mc_addr; offset++) {
3990 tmp64 = do_s2io_read_unicast_mc(sp, offset);
3991 if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
3992 do_s2io_delete_unicast_mc(sp, tmp64);
3993 }
3994
3995 /* Reset card, kill tasklet and free Tx and Rx buffers. */
3996 s2io_card_down(sp);
3997
3998 return 0;
3999 }
4000
4001 /**
4002 * s2io_xmit - Tx entry point of te driver
4003 * @skb : the socket buffer containing the Tx data.
4004 * @dev : device pointer.
4005 * Description :
4006 * This function is the Tx entry point of the driver. S2IO NIC supports
4007 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
4008 * NOTE: when device cant queue the pkt,just the trans_start variable will
4009 * not be upadted.
4010 * Return value:
4011 * 0 on success & 1 on failure.
4012 */
4013
4014 static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
4015 {
4016 struct s2io_nic *sp = dev->priv;
4017 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
4018 register u64 val64;
4019 struct TxD *txdp;
4020 struct TxFIFO_element __iomem *tx_fifo;
4021 unsigned long flags = 0;
4022 u16 vlan_tag = 0;
4023 int vlan_priority = 0;
4024 struct fifo_info *fifo = NULL;
4025 struct mac_info *mac_control;
4026 struct config_param *config;
4027 int offload_type;
4028 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
4029
4030 mac_control = &sp->mac_control;
4031 config = &sp->config;
4032
4033 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
4034
4035 if (unlikely(skb->len <= 0)) {
4036 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
4037 dev_kfree_skb_any(skb);
4038 return 0;
4039 }
4040
4041 if (!is_s2io_card_up(sp)) {
4042 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
4043 dev->name);
4044 dev_kfree_skb(skb);
4045 return 0;
4046 }
4047
4048 queue = 0;
4049 /* Get Fifo number to Transmit based on vlan priority */
4050 if (sp->vlgrp && vlan_tx_tag_present(skb)) {
4051 vlan_tag = vlan_tx_tag_get(skb);
4052 vlan_priority = vlan_tag >> 13;
4053 queue = config->fifo_mapping[vlan_priority];
4054 }
4055
4056 fifo = &mac_control->fifos[queue];
4057 spin_lock_irqsave(&fifo->tx_lock, flags);
4058 put_off = (u16) fifo->tx_curr_put_info.offset;
4059 get_off = (u16) fifo->tx_curr_get_info.offset;
4060 txdp = (struct TxD *) fifo->list_info[put_off].list_virt_addr;
4061
4062 queue_len = fifo->tx_curr_put_info.fifo_len + 1;
4063 /* Avoid "put" pointer going beyond "get" pointer */
4064 if (txdp->Host_Control ||
4065 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4066 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
4067 netif_stop_queue(dev);
4068 dev_kfree_skb(skb);
4069 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4070 return 0;
4071 }
4072
4073 offload_type = s2io_offload_type(skb);
4074 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
4075 txdp->Control_1 |= TXD_TCP_LSO_EN;
4076 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
4077 }
4078 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4079 txdp->Control_2 |=
4080 (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
4081 TXD_TX_CKO_UDP_EN);
4082 }
4083 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4084 txdp->Control_1 |= TXD_LIST_OWN_XENA;
4085 txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
4086
4087 if (sp->vlgrp && vlan_tx_tag_present(skb)) {
4088 txdp->Control_2 |= TXD_VLAN_ENABLE;
4089 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4090 }
4091
4092 frg_len = skb->len - skb->data_len;
4093 if (offload_type == SKB_GSO_UDP) {
4094 int ufo_size;
4095
4096 ufo_size = s2io_udp_mss(skb);
4097 ufo_size &= ~7;
4098 txdp->Control_1 |= TXD_UFO_EN;
4099 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4100 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4101 #ifdef __BIG_ENDIAN
4102 fifo->ufo_in_band_v[put_off] =
4103 (u64)skb_shinfo(skb)->ip6_frag_id;
4104 #else
4105 fifo->ufo_in_band_v[put_off] =
4106 (u64)skb_shinfo(skb)->ip6_frag_id << 32;
4107 #endif
4108 txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v;
4109 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
4110 fifo->ufo_in_band_v,
4111 sizeof(u64), PCI_DMA_TODEVICE);
4112 if((txdp->Buffer_Pointer == 0) ||
4113 (txdp->Buffer_Pointer == DMA_ERROR_CODE))
4114 goto pci_map_failed;
4115 txdp++;
4116 }
4117
4118 txdp->Buffer_Pointer = pci_map_single
4119 (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
4120 if((txdp->Buffer_Pointer == 0) ||
4121 (txdp->Buffer_Pointer == DMA_ERROR_CODE))
4122 goto pci_map_failed;
4123
4124 txdp->Host_Control = (unsigned long) skb;
4125 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
4126 if (offload_type == SKB_GSO_UDP)
4127 txdp->Control_1 |= TXD_UFO_EN;
4128
4129 frg_cnt = skb_shinfo(skb)->nr_frags;
4130 /* For fragmented SKB. */
4131 for (i = 0; i < frg_cnt; i++) {
4132 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4133 /* A '0' length fragment will be ignored */
4134 if (!frag->size)
4135 continue;
4136 txdp++;
4137 txdp->Buffer_Pointer = (u64) pci_map_page
4138 (sp->pdev, frag->page, frag->page_offset,
4139 frag->size, PCI_DMA_TODEVICE);
4140 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
4141 if (offload_type == SKB_GSO_UDP)
4142 txdp->Control_1 |= TXD_UFO_EN;
4143 }
4144 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4145
4146 if (offload_type == SKB_GSO_UDP)
4147 frg_cnt++; /* as Txd0 was used for inband header */
4148
4149 tx_fifo = mac_control->tx_FIFO_start[queue];
4150 val64 = fifo->list_info[put_off].list_phy_addr;
4151 writeq(val64, &tx_fifo->TxDL_Pointer);
4152
4153 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4154 TX_FIFO_LAST_LIST);
4155 if (offload_type)
4156 val64 |= TX_FIFO_SPECIAL_FUNC;
4157
4158 writeq(val64, &tx_fifo->List_Control);
4159
4160 mmiowb();
4161
4162 put_off++;
4163 if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
4164 put_off = 0;
4165 fifo->tx_curr_put_info.offset = put_off;
4166
4167 /* Avoid "put" pointer going beyond "get" pointer */
4168 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4169 sp->mac_control.stats_info->sw_stat.fifo_full_cnt++;
4170 DBG_PRINT(TX_DBG,
4171 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4172 put_off, get_off);
4173 netif_stop_queue(dev);
4174 }
4175 mac_control->stats_info->sw_stat.mem_allocated += skb->truesize;
4176 dev->trans_start = jiffies;
4177 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4178
4179 return 0;
4180 pci_map_failed:
4181 stats->pci_map_fail_cnt++;
4182 netif_stop_queue(dev);
4183 stats->mem_freed += skb->truesize;
4184 dev_kfree_skb(skb);
4185 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4186 return 0;
4187 }
4188
4189 static void
4190 s2io_alarm_handle(unsigned long data)
4191 {
4192 struct s2io_nic *sp = (struct s2io_nic *)data;
4193 struct net_device *dev = sp->dev;
4194
4195 s2io_handle_errors(dev);
4196 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4197 }
4198
4199 static int s2io_chk_rx_buffers(struct s2io_nic *sp, int rng_n)
4200 {
4201 int rxb_size, level;
4202
4203 if (!sp->lro) {
4204 rxb_size = atomic_read(&sp->rx_bufs_left[rng_n]);
4205 level = rx_buffer_level(sp, rxb_size, rng_n);
4206
4207 if ((level == PANIC) && (!TASKLET_IN_USE)) {
4208 int ret;
4209 DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", __FUNCTION__);
4210 DBG_PRINT(INTR_DBG, "PANIC levels\n");
4211 if ((ret = fill_rx_buffers(sp, rng_n)) == -ENOMEM) {
4212 DBG_PRINT(INFO_DBG, "Out of memory in %s",
4213 __FUNCTION__);
4214 clear_bit(0, (&sp->tasklet_status));
4215 return -1;
4216 }
4217 clear_bit(0, (&sp->tasklet_status));
4218 } else if (level == LOW)
4219 tasklet_schedule(&sp->task);
4220
4221 } else if (fill_rx_buffers(sp, rng_n) == -ENOMEM) {
4222 DBG_PRINT(INFO_DBG, "%s:Out of memory", sp->dev->name);
4223 DBG_PRINT(INFO_DBG, " in Rx Intr!!\n");
4224 }
4225 return 0;
4226 }
4227
4228 static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
4229 {
4230 struct ring_info *ring = (struct ring_info *)dev_id;
4231 struct s2io_nic *sp = ring->nic;
4232
4233 if (!is_s2io_card_up(sp))
4234 return IRQ_HANDLED;
4235
4236 rx_intr_handler(ring);
4237 s2io_chk_rx_buffers(sp, ring->ring_no);
4238
4239 return IRQ_HANDLED;
4240 }
4241
4242 static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
4243 {
4244 struct fifo_info *fifo = (struct fifo_info *)dev_id;
4245 struct s2io_nic *sp = fifo->nic;
4246
4247 if (!is_s2io_card_up(sp))
4248 return IRQ_HANDLED;
4249
4250 tx_intr_handler(fifo);
4251 return IRQ_HANDLED;
4252 }
4253 static void s2io_txpic_intr_handle(struct s2io_nic *sp)
4254 {
4255 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4256 u64 val64;
4257
4258 val64 = readq(&bar0->pic_int_status);
4259 if (val64 & PIC_INT_GPIO) {
4260 val64 = readq(&bar0->gpio_int_reg);
4261 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4262 (val64 & GPIO_INT_REG_LINK_UP)) {
4263 /*
4264 * This is unstable state so clear both up/down
4265 * interrupt and adapter to re-evaluate the link state.
4266 */
4267 val64 |= GPIO_INT_REG_LINK_DOWN;
4268 val64 |= GPIO_INT_REG_LINK_UP;
4269 writeq(val64, &bar0->gpio_int_reg);
4270 val64 = readq(&bar0->gpio_int_mask);
4271 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4272 GPIO_INT_MASK_LINK_DOWN);
4273 writeq(val64, &bar0->gpio_int_mask);
4274 }
4275 else if (val64 & GPIO_INT_REG_LINK_UP) {
4276 val64 = readq(&bar0->adapter_status);
4277 /* Enable Adapter */
4278 val64 = readq(&bar0->adapter_control);
4279 val64 |= ADAPTER_CNTL_EN;
4280 writeq(val64, &bar0->adapter_control);
4281 val64 |= ADAPTER_LED_ON;
4282 writeq(val64, &bar0->adapter_control);
4283 if (!sp->device_enabled_once)
4284 sp->device_enabled_once = 1;
4285
4286 s2io_link(sp, LINK_UP);
4287 /*
4288 * unmask link down interrupt and mask link-up
4289 * intr
4290 */
4291 val64 = readq(&bar0->gpio_int_mask);
4292 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4293 val64 |= GPIO_INT_MASK_LINK_UP;
4294 writeq(val64, &bar0->gpio_int_mask);
4295
4296 }else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4297 val64 = readq(&bar0->adapter_status);
4298 s2io_link(sp, LINK_DOWN);
4299 /* Link is down so unmaks link up interrupt */
4300 val64 = readq(&bar0->gpio_int_mask);
4301 val64 &= ~GPIO_INT_MASK_LINK_UP;
4302 val64 |= GPIO_INT_MASK_LINK_DOWN;
4303 writeq(val64, &bar0->gpio_int_mask);
4304
4305 /* turn off LED */
4306 val64 = readq(&bar0->adapter_control);
4307 val64 = val64 &(~ADAPTER_LED_ON);
4308 writeq(val64, &bar0->adapter_control);
4309 }
4310 }
4311 val64 = readq(&bar0->gpio_int_mask);
4312 }
4313
4314 /**
4315 * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4316 * @value: alarm bits
4317 * @addr: address value
4318 * @cnt: counter variable
4319 * Description: Check for alarm and increment the counter
4320 * Return Value:
4321 * 1 - if alarm bit set
4322 * 0 - if alarm bit is not set
4323 */
4324 static int do_s2io_chk_alarm_bit(u64 value, void __iomem * addr,
4325 unsigned long long *cnt)
4326 {
4327 u64 val64;
4328 val64 = readq(addr);
4329 if ( val64 & value ) {
4330 writeq(val64, addr);
4331 (*cnt)++;
4332 return 1;
4333 }
4334 return 0;
4335
4336 }
4337
4338 /**
4339 * s2io_handle_errors - Xframe error indication handler
4340 * @nic: device private variable
4341 * Description: Handle alarms such as loss of link, single or
4342 * double ECC errors, critical and serious errors.
4343 * Return Value:
4344 * NONE
4345 */
4346 static void s2io_handle_errors(void * dev_id)
4347 {
4348 struct net_device *dev = (struct net_device *) dev_id;
4349 struct s2io_nic *sp = dev->priv;
4350 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4351 u64 temp64 = 0,val64=0;
4352 int i = 0;
4353
4354 struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4355 struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4356
4357 if (!is_s2io_card_up(sp))
4358 return;
4359
4360 if (pci_channel_offline(sp->pdev))
4361 return;
4362
4363 memset(&sw_stat->ring_full_cnt, 0,
4364 sizeof(sw_stat->ring_full_cnt));
4365
4366 /* Handling the XPAK counters update */
4367 if(stats->xpak_timer_count < 72000) {
4368 /* waiting for an hour */
4369 stats->xpak_timer_count++;
4370 } else {
4371 s2io_updt_xpak_counter(dev);
4372 /* reset the count to zero */
4373 stats->xpak_timer_count = 0;
4374 }
4375
4376 /* Handling link status change error Intr */
4377 if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4378 val64 = readq(&bar0->mac_rmac_err_reg);
4379 writeq(val64, &bar0->mac_rmac_err_reg);
4380 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4381 schedule_work(&sp->set_link_task);
4382 }
4383
4384 /* In case of a serious error, the device will be Reset. */
4385 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
4386 &sw_stat->serious_err_cnt))
4387 goto reset;
4388
4389 /* Check for data parity error */
4390 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
4391 &sw_stat->parity_err_cnt))
4392 goto reset;
4393
4394 /* Check for ring full counter */
4395 if (sp->device_type == XFRAME_II_DEVICE) {
4396 val64 = readq(&bar0->ring_bump_counter1);
4397 for (i=0; i<4; i++) {
4398 temp64 = ( val64 & vBIT(0xFFFF,(i*16),16));
4399 temp64 >>= 64 - ((i+1)*16);
4400 sw_stat->ring_full_cnt[i] += temp64;
4401 }
4402
4403 val64 = readq(&bar0->ring_bump_counter2);
4404 for (i=0; i<4; i++) {
4405 temp64 = ( val64 & vBIT(0xFFFF,(i*16),16));
4406 temp64 >>= 64 - ((i+1)*16);
4407 sw_stat->ring_full_cnt[i+4] += temp64;
4408 }
4409 }
4410
4411 val64 = readq(&bar0->txdma_int_status);
4412 /*check for pfc_err*/
4413 if (val64 & TXDMA_PFC_INT) {
4414 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM|
4415 PFC_MISC_0_ERR | PFC_MISC_1_ERR|
4416 PFC_PCIX_ERR, &bar0->pfc_err_reg,
4417 &sw_stat->pfc_err_cnt))
4418 goto reset;
4419 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR, &bar0->pfc_err_reg,
4420 &sw_stat->pfc_err_cnt);
4421 }
4422
4423 /*check for tda_err*/
4424 if (val64 & TXDMA_TDA_INT) {
4425 if(do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
4426 TDA_SM1_ERR_ALARM, &bar0->tda_err_reg,
4427 &sw_stat->tda_err_cnt))
4428 goto reset;
4429 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
4430 &bar0->tda_err_reg, &sw_stat->tda_err_cnt);
4431 }
4432 /*check for pcc_err*/
4433 if (val64 & TXDMA_PCC_INT) {
4434 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM
4435 | PCC_N_SERR | PCC_6_COF_OV_ERR
4436 | PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR
4437 | PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR
4438 | PCC_TXB_ECC_DB_ERR, &bar0->pcc_err_reg,
4439 &sw_stat->pcc_err_cnt))
4440 goto reset;
4441 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
4442 &bar0->pcc_err_reg, &sw_stat->pcc_err_cnt);
4443 }
4444
4445 /*check for tti_err*/
4446 if (val64 & TXDMA_TTI_INT) {
4447 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM, &bar0->tti_err_reg,
4448 &sw_stat->tti_err_cnt))
4449 goto reset;
4450 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
4451 &bar0->tti_err_reg, &sw_stat->tti_err_cnt);
4452 }
4453
4454 /*check for lso_err*/
4455 if (val64 & TXDMA_LSO_INT) {
4456 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT
4457 | LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4458 &bar0->lso_err_reg, &sw_stat->lso_err_cnt))
4459 goto reset;
4460 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
4461 &bar0->lso_err_reg, &sw_stat->lso_err_cnt);
4462 }
4463
4464 /*check for tpa_err*/
4465 if (val64 & TXDMA_TPA_INT) {
4466 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM, &bar0->tpa_err_reg,
4467 &sw_stat->tpa_err_cnt))
4468 goto reset;
4469 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP, &bar0->tpa_err_reg,
4470 &sw_stat->tpa_err_cnt);
4471 }
4472
4473 /*check for sm_err*/
4474 if (val64 & TXDMA_SM_INT) {
4475 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM, &bar0->sm_err_reg,
4476 &sw_stat->sm_err_cnt))
4477 goto reset;
4478 }
4479
4480 val64 = readq(&bar0->mac_int_status);
4481 if (val64 & MAC_INT_STATUS_TMAC_INT) {
4482 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
4483 &bar0->mac_tmac_err_reg,
4484 &sw_stat->mac_tmac_err_cnt))
4485 goto reset;
4486 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR
4487 | TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
4488 &bar0->mac_tmac_err_reg,
4489 &sw_stat->mac_tmac_err_cnt);
4490 }
4491
4492 val64 = readq(&bar0->xgxs_int_status);
4493 if (val64 & XGXS_INT_STATUS_TXGXS) {
4494 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
4495 &bar0->xgxs_txgxs_err_reg,
4496 &sw_stat->xgxs_txgxs_err_cnt))
4497 goto reset;
4498 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
4499 &bar0->xgxs_txgxs_err_reg,
4500 &sw_stat->xgxs_txgxs_err_cnt);
4501 }
4502
4503 val64 = readq(&bar0->rxdma_int_status);
4504 if (val64 & RXDMA_INT_RC_INT_M) {
4505 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR
4506 | RC_PRCn_SM_ERR_ALARM |RC_FTC_SM_ERR_ALARM,
4507 &bar0->rc_err_reg, &sw_stat->rc_err_cnt))
4508 goto reset;
4509 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR
4510 | RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4511 &sw_stat->rc_err_cnt);
4512 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn
4513 | PRC_PCI_AB_F_WR_Rn, &bar0->prc_pcix_err_reg,
4514 &sw_stat->prc_pcix_err_cnt))
4515 goto reset;
4516 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn | PRC_PCI_DP_WR_Rn
4517 | PRC_PCI_DP_F_WR_Rn, &bar0->prc_pcix_err_reg,
4518 &sw_stat->prc_pcix_err_cnt);
4519 }
4520
4521 if (val64 & RXDMA_INT_RPA_INT_M) {
4522 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
4523 &bar0->rpa_err_reg, &sw_stat->rpa_err_cnt))
4524 goto reset;
4525 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
4526 &bar0->rpa_err_reg, &sw_stat->rpa_err_cnt);
4527 }
4528
4529 if (val64 & RXDMA_INT_RDA_INT_M) {
4530 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR
4531 | RDA_FRM_ECC_DB_N_AERR | RDA_SM1_ERR_ALARM
4532 | RDA_SM0_ERR_ALARM | RDA_RXD_ECC_DB_SERR,
4533 &bar0->rda_err_reg, &sw_stat->rda_err_cnt))
4534 goto reset;
4535 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR | RDA_FRM_ECC_SG_ERR
4536 | RDA_MISC_ERR | RDA_PCIX_ERR,
4537 &bar0->rda_err_reg, &sw_stat->rda_err_cnt);
4538 }
4539
4540 if (val64 & RXDMA_INT_RTI_INT_M) {
4541 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM, &bar0->rti_err_reg,
4542 &sw_stat->rti_err_cnt))
4543 goto reset;
4544 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
4545 &bar0->rti_err_reg, &sw_stat->rti_err_cnt);
4546 }
4547
4548 val64 = readq(&bar0->mac_int_status);
4549 if (val64 & MAC_INT_STATUS_RMAC_INT) {
4550 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
4551 &bar0->mac_rmac_err_reg,
4552 &sw_stat->mac_rmac_err_cnt))
4553 goto reset;
4554 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT|RMAC_SINGLE_ECC_ERR|
4555 RMAC_DOUBLE_ECC_ERR, &bar0->mac_rmac_err_reg,
4556 &sw_stat->mac_rmac_err_cnt);
4557 }
4558
4559 val64 = readq(&bar0->xgxs_int_status);
4560 if (val64 & XGXS_INT_STATUS_RXGXS) {
4561 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
4562 &bar0->xgxs_rxgxs_err_reg,
4563 &sw_stat->xgxs_rxgxs_err_cnt))
4564 goto reset;
4565 }
4566
4567 val64 = readq(&bar0->mc_int_status);
4568 if(val64 & MC_INT_STATUS_MC_INT) {
4569 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR, &bar0->mc_err_reg,
4570 &sw_stat->mc_err_cnt))
4571 goto reset;
4572
4573 /* Handling Ecc errors */
4574 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4575 writeq(val64, &bar0->mc_err_reg);
4576 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4577 sw_stat->double_ecc_errs++;
4578 if (sp->device_type != XFRAME_II_DEVICE) {
4579 /*
4580 * Reset XframeI only if critical error
4581 */
4582 if (val64 &
4583 (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4584 MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4585 goto reset;
4586 }
4587 } else
4588 sw_stat->single_ecc_errs++;
4589 }
4590 }
4591 return;
4592
4593 reset:
4594 netif_stop_queue(dev);
4595 schedule_work(&sp->rst_timer_task);
4596 sw_stat->soft_reset_cnt++;
4597 return;
4598 }
4599
4600 /**
4601 * s2io_isr - ISR handler of the device .
4602 * @irq: the irq of the device.
4603 * @dev_id: a void pointer to the dev structure of the NIC.
4604 * Description: This function is the ISR handler of the device. It
4605 * identifies the reason for the interrupt and calls the relevant
4606 * service routines. As a contongency measure, this ISR allocates the
4607 * recv buffers, if their numbers are below the panic value which is
4608 * presently set to 25% of the original number of rcv buffers allocated.
4609 * Return value:
4610 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
4611 * IRQ_NONE: will be returned if interrupt is not from our device
4612 */
4613 static irqreturn_t s2io_isr(int irq, void *dev_id)
4614 {
4615 struct net_device *dev = (struct net_device *) dev_id;
4616 struct s2io_nic *sp = dev->priv;
4617 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4618 int i;
4619 u64 reason = 0;
4620 struct mac_info *mac_control;
4621 struct config_param *config;
4622
4623 /* Pretend we handled any irq's from a disconnected card */
4624 if (pci_channel_offline(sp->pdev))
4625 return IRQ_NONE;
4626
4627 if (!is_s2io_card_up(sp))
4628 return IRQ_NONE;
4629
4630 mac_control = &sp->mac_control;
4631 config = &sp->config;
4632
4633 /*
4634 * Identify the cause for interrupt and call the appropriate
4635 * interrupt handler. Causes for the interrupt could be;
4636 * 1. Rx of packet.
4637 * 2. Tx complete.
4638 * 3. Link down.
4639 */
4640 reason = readq(&bar0->general_int_status);
4641
4642 if (unlikely(reason == S2IO_MINUS_ONE) ) {
4643 /* Nothing much can be done. Get out */
4644 return IRQ_HANDLED;
4645 }
4646
4647 if (reason & (GEN_INTR_RXTRAFFIC |
4648 GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC))
4649 {
4650 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4651
4652 if (config->napi) {
4653 if (reason & GEN_INTR_RXTRAFFIC) {
4654 if (likely(netif_rx_schedule_prep(dev,
4655 &sp->napi))) {
4656 __netif_rx_schedule(dev, &sp->napi);
4657 writeq(S2IO_MINUS_ONE,
4658 &bar0->rx_traffic_mask);
4659 } else
4660 writeq(S2IO_MINUS_ONE,
4661 &bar0->rx_traffic_int);
4662 }
4663 } else {
4664 /*
4665 * rx_traffic_int reg is an R1 register, writing all 1's
4666 * will ensure that the actual interrupt causing bit
4667 * get's cleared and hence a read can be avoided.
4668 */
4669 if (reason & GEN_INTR_RXTRAFFIC)
4670 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4671
4672 for (i = 0; i < config->rx_ring_num; i++)
4673 rx_intr_handler(&mac_control->rings[i]);
4674 }
4675
4676 /*
4677 * tx_traffic_int reg is an R1 register, writing all 1's
4678 * will ensure that the actual interrupt causing bit get's
4679 * cleared and hence a read can be avoided.
4680 */
4681 if (reason & GEN_INTR_TXTRAFFIC)
4682 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4683
4684 for (i = 0; i < config->tx_fifo_num; i++)
4685 tx_intr_handler(&mac_control->fifos[i]);
4686
4687 if (reason & GEN_INTR_TXPIC)
4688 s2io_txpic_intr_handle(sp);
4689
4690 /*
4691 * Reallocate the buffers from the interrupt handler itself.
4692 */
4693 if (!config->napi) {
4694 for (i = 0; i < config->rx_ring_num; i++)
4695 s2io_chk_rx_buffers(sp, i);
4696 }
4697 writeq(sp->general_int_mask, &bar0->general_int_mask);
4698 readl(&bar0->general_int_status);
4699
4700 return IRQ_HANDLED;
4701
4702 }
4703 else if (!reason) {
4704 /* The interrupt was not raised by us */
4705 return IRQ_NONE;
4706 }
4707
4708 return IRQ_HANDLED;
4709 }
4710
4711 /**
4712 * s2io_updt_stats -
4713 */
4714 static void s2io_updt_stats(struct s2io_nic *sp)
4715 {
4716 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4717 u64 val64;
4718 int cnt = 0;
4719
4720 if (is_s2io_card_up(sp)) {
4721 /* Apprx 30us on a 133 MHz bus */
4722 val64 = SET_UPDT_CLICKS(10) |
4723 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4724 writeq(val64, &bar0->stat_cfg);
4725 do {
4726 udelay(100);
4727 val64 = readq(&bar0->stat_cfg);
4728 if (!(val64 & s2BIT(0)))
4729 break;
4730 cnt++;
4731 if (cnt == 5)
4732 break; /* Updt failed */
4733 } while(1);
4734 }
4735 }
4736
4737 /**
4738 * s2io_get_stats - Updates the device statistics structure.
4739 * @dev : pointer to the device structure.
4740 * Description:
4741 * This function updates the device statistics structure in the s2io_nic
4742 * structure and returns a pointer to the same.
4743 * Return value:
4744 * pointer to the updated net_device_stats structure.
4745 */
4746
4747 static struct net_device_stats *s2io_get_stats(struct net_device *dev)
4748 {
4749 struct s2io_nic *sp = dev->priv;
4750 struct mac_info *mac_control;
4751 struct config_param *config;
4752
4753
4754 mac_control = &sp->mac_control;
4755 config = &sp->config;
4756
4757 /* Configure Stats for immediate updt */
4758 s2io_updt_stats(sp);
4759
4760 sp->stats.tx_packets =
4761 le32_to_cpu(mac_control->stats_info->tmac_frms);
4762 sp->stats.tx_errors =
4763 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
4764 sp->stats.rx_errors =
4765 le64_to_cpu(mac_control->stats_info->rmac_drop_frms);
4766 sp->stats.multicast =
4767 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
4768 sp->stats.rx_length_errors =
4769 le64_to_cpu(mac_control->stats_info->rmac_long_frms);
4770
4771 return (&sp->stats);
4772 }
4773
4774 /**
4775 * s2io_set_multicast - entry point for multicast address enable/disable.
4776 * @dev : pointer to the device structure
4777 * Description:
4778 * This function is a driver entry point which gets called by the kernel
4779 * whenever multicast addresses must be enabled/disabled. This also gets
4780 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4781 * determine, if multicast address must be enabled or if promiscuous mode
4782 * is to be disabled etc.
4783 * Return value:
4784 * void.
4785 */
4786
4787 static void s2io_set_multicast(struct net_device *dev)
4788 {
4789 int i, j, prev_cnt;
4790 struct dev_mc_list *mclist;
4791 struct s2io_nic *sp = dev->priv;
4792 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4793 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4794 0xfeffffffffffULL;
4795 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
4796 void __iomem *add;
4797 struct config_param *config = &sp->config;
4798
4799 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4800 /* Enable all Multicast addresses */
4801 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4802 &bar0->rmac_addr_data0_mem);
4803 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4804 &bar0->rmac_addr_data1_mem);
4805 val64 = RMAC_ADDR_CMD_MEM_WE |
4806 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4807 RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
4808 writeq(val64, &bar0->rmac_addr_cmd_mem);
4809 /* Wait till command completes */
4810 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4811 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4812 S2IO_BIT_RESET);
4813
4814 sp->m_cast_flg = 1;
4815 sp->all_multi_pos = config->max_mc_addr - 1;
4816 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4817 /* Disable all Multicast addresses */
4818 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4819 &bar0->rmac_addr_data0_mem);
4820 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4821 &bar0->rmac_addr_data1_mem);
4822 val64 = RMAC_ADDR_CMD_MEM_WE |
4823 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4824 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4825 writeq(val64, &bar0->rmac_addr_cmd_mem);
4826 /* Wait till command completes */
4827 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4828 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4829 S2IO_BIT_RESET);
4830
4831 sp->m_cast_flg = 0;
4832 sp->all_multi_pos = 0;
4833 }
4834
4835 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4836 /* Put the NIC into promiscuous mode */
4837 add = &bar0->mac_cfg;
4838 val64 = readq(&bar0->mac_cfg);
4839 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
4840
4841 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4842 writel((u32) val64, add);
4843 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4844 writel((u32) (val64 >> 32), (add + 4));
4845
4846 if (vlan_tag_strip != 1) {
4847 val64 = readq(&bar0->rx_pa_cfg);
4848 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
4849 writeq(val64, &bar0->rx_pa_cfg);
4850 vlan_strip_flag = 0;
4851 }
4852
4853 val64 = readq(&bar0->mac_cfg);
4854 sp->promisc_flg = 1;
4855 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
4856 dev->name);
4857 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
4858 /* Remove the NIC from promiscuous mode */
4859 add = &bar0->mac_cfg;
4860 val64 = readq(&bar0->mac_cfg);
4861 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
4862
4863 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4864 writel((u32) val64, add);
4865 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4866 writel((u32) (val64 >> 32), (add + 4));
4867
4868 if (vlan_tag_strip != 0) {
4869 val64 = readq(&bar0->rx_pa_cfg);
4870 val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
4871 writeq(val64, &bar0->rx_pa_cfg);
4872 vlan_strip_flag = 1;
4873 }
4874
4875 val64 = readq(&bar0->mac_cfg);
4876 sp->promisc_flg = 0;
4877 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
4878 dev->name);
4879 }
4880
4881 /* Update individual M_CAST address list */
4882 if ((!sp->m_cast_flg) && dev->mc_count) {
4883 if (dev->mc_count >
4884 (config->max_mc_addr - config->max_mac_addr)) {
4885 DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
4886 dev->name);
4887 DBG_PRINT(ERR_DBG, "can be added, please enable ");
4888 DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
4889 return;
4890 }
4891
4892 prev_cnt = sp->mc_addr_count;
4893 sp->mc_addr_count = dev->mc_count;
4894
4895 /* Clear out the previous list of Mc in the H/W. */
4896 for (i = 0; i < prev_cnt; i++) {
4897 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4898 &bar0->rmac_addr_data0_mem);
4899 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4900 &bar0->rmac_addr_data1_mem);
4901 val64 = RMAC_ADDR_CMD_MEM_WE |
4902 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4903 RMAC_ADDR_CMD_MEM_OFFSET
4904 (config->mc_start_offset + i);
4905 writeq(val64, &bar0->rmac_addr_cmd_mem);
4906
4907 /* Wait for command completes */
4908 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4909 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4910 S2IO_BIT_RESET)) {
4911 DBG_PRINT(ERR_DBG, "%s: Adding ",
4912 dev->name);
4913 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4914 return;
4915 }
4916 }
4917
4918 /* Create the new Rx filter list and update the same in H/W. */
4919 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
4920 i++, mclist = mclist->next) {
4921 memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
4922 ETH_ALEN);
4923 mac_addr = 0;
4924 for (j = 0; j < ETH_ALEN; j++) {
4925 mac_addr |= mclist->dmi_addr[j];
4926 mac_addr <<= 8;
4927 }
4928 mac_addr >>= 8;
4929 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4930 &bar0->rmac_addr_data0_mem);
4931 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4932 &bar0->rmac_addr_data1_mem);
4933 val64 = RMAC_ADDR_CMD_MEM_WE |
4934 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4935 RMAC_ADDR_CMD_MEM_OFFSET
4936 (i + config->mc_start_offset);
4937 writeq(val64, &bar0->rmac_addr_cmd_mem);
4938
4939 /* Wait for command completes */
4940 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4941 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4942 S2IO_BIT_RESET)) {
4943 DBG_PRINT(ERR_DBG, "%s: Adding ",
4944 dev->name);
4945 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4946 return;
4947 }
4948 }
4949 }
4950 }
4951
4952 /* read from CAM unicast & multicast addresses and store it in
4953 * def_mac_addr structure
4954 */
4955 void do_s2io_store_unicast_mc(struct s2io_nic *sp)
4956 {
4957 int offset;
4958 u64 mac_addr = 0x0;
4959 struct config_param *config = &sp->config;
4960
4961 /* store unicast & multicast mac addresses */
4962 for (offset = 0; offset < config->max_mc_addr; offset++) {
4963 mac_addr = do_s2io_read_unicast_mc(sp, offset);
4964 /* if read fails disable the entry */
4965 if (mac_addr == FAILURE)
4966 mac_addr = S2IO_DISABLE_MAC_ENTRY;
4967 do_s2io_copy_mac_addr(sp, offset, mac_addr);
4968 }
4969 }
4970
4971 /* restore unicast & multicast MAC to CAM from def_mac_addr structure */
4972 static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
4973 {
4974 int offset;
4975 struct config_param *config = &sp->config;
4976 /* restore unicast mac address */
4977 for (offset = 0; offset < config->max_mac_addr; offset++)
4978 do_s2io_prog_unicast(sp->dev,
4979 sp->def_mac_addr[offset].mac_addr);
4980
4981 /* restore multicast mac address */
4982 for (offset = config->mc_start_offset;
4983 offset < config->max_mc_addr; offset++)
4984 do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
4985 }
4986
4987 /* add a multicast MAC address to CAM */
4988 static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
4989 {
4990 int i;
4991 u64 mac_addr = 0;
4992 struct config_param *config = &sp->config;
4993
4994 for (i = 0; i < ETH_ALEN; i++) {
4995 mac_addr <<= 8;
4996 mac_addr |= addr[i];
4997 }
4998 if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
4999 return SUCCESS;
5000
5001 /* check if the multicast mac already preset in CAM */
5002 for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5003 u64 tmp64;
5004 tmp64 = do_s2io_read_unicast_mc(sp, i);
5005 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5006 break;
5007
5008 if (tmp64 == mac_addr)
5009 return SUCCESS;
5010 }
5011 if (i == config->max_mc_addr) {
5012 DBG_PRINT(ERR_DBG,
5013 "CAM full no space left for multicast MAC\n");
5014 return FAILURE;
5015 }
5016 /* Update the internal structure with this new mac address */
5017 do_s2io_copy_mac_addr(sp, i, mac_addr);
5018
5019 return (do_s2io_add_mac(sp, mac_addr, i));
5020 }
5021
5022 /* add MAC address to CAM */
5023 static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
5024 {
5025 u64 val64;
5026 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5027
5028 writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
5029 &bar0->rmac_addr_data0_mem);
5030
5031 val64 =
5032 RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5033 RMAC_ADDR_CMD_MEM_OFFSET(off);
5034 writeq(val64, &bar0->rmac_addr_cmd_mem);
5035
5036 /* Wait till command completes */
5037 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5038 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5039 S2IO_BIT_RESET)) {
5040 DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
5041 return FAILURE;
5042 }
5043 return SUCCESS;
5044 }
5045 /* deletes a specified unicast/multicast mac entry from CAM */
5046 static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5047 {
5048 int offset;
5049 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5050 struct config_param *config = &sp->config;
5051
5052 for (offset = 1;
5053 offset < config->max_mc_addr; offset++) {
5054 tmp64 = do_s2io_read_unicast_mc(sp, offset);
5055 if (tmp64 == addr) {
5056 /* disable the entry by writing 0xffffffffffffULL */
5057 if (do_s2io_add_mac(sp, dis_addr, offset) == FAILURE)
5058 return FAILURE;
5059 /* store the new mac list from CAM */
5060 do_s2io_store_unicast_mc(sp);
5061 return SUCCESS;
5062 }
5063 }
5064 DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
5065 (unsigned long long)addr);
5066 return FAILURE;
5067 }
5068
5069 /* read mac entries from CAM */
5070 static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5071 {
5072 u64 tmp64 = 0xffffffffffff0000ULL, val64;
5073 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5074
5075 /* read mac addr */
5076 val64 =
5077 RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5078 RMAC_ADDR_CMD_MEM_OFFSET(offset);
5079 writeq(val64, &bar0->rmac_addr_cmd_mem);
5080
5081 /* Wait till command completes */
5082 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5083 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5084 S2IO_BIT_RESET)) {
5085 DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5086 return FAILURE;
5087 }
5088 tmp64 = readq(&bar0->rmac_addr_data0_mem);
5089 return (tmp64 >> 16);
5090 }
5091
5092 /**
5093 * s2io_set_mac_addr driver entry point
5094 */
5095
5096 static int s2io_set_mac_addr(struct net_device *dev, void *p)
5097 {
5098 struct sockaddr *addr = p;
5099
5100 if (!is_valid_ether_addr(addr->sa_data))
5101 return -EINVAL;
5102
5103 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5104
5105 /* store the MAC address in CAM */
5106 return (do_s2io_prog_unicast(dev, dev->dev_addr));
5107 }
5108 /**
5109 * do_s2io_prog_unicast - Programs the Xframe mac address
5110 * @dev : pointer to the device structure.
5111 * @addr: a uchar pointer to the new mac address which is to be set.
5112 * Description : This procedure will program the Xframe to receive
5113 * frames with new Mac Address
5114 * Return value: SUCCESS on success and an appropriate (-)ve integer
5115 * as defined in errno.h file on failure.
5116 */
5117
5118 static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
5119 {
5120 struct s2io_nic *sp = dev->priv;
5121 register u64 mac_addr = 0, perm_addr = 0;
5122 int i;
5123 u64 tmp64;
5124 struct config_param *config = &sp->config;
5125
5126 /*
5127 * Set the new MAC address as the new unicast filter and reflect this
5128 * change on the device address registered with the OS. It will be
5129 * at offset 0.
5130 */
5131 for (i = 0; i < ETH_ALEN; i++) {
5132 mac_addr <<= 8;
5133 mac_addr |= addr[i];
5134 perm_addr <<= 8;
5135 perm_addr |= sp->def_mac_addr[0].mac_addr[i];
5136 }
5137
5138 /* check if the dev_addr is different than perm_addr */
5139 if (mac_addr == perm_addr)
5140 return SUCCESS;
5141
5142 /* check if the mac already preset in CAM */
5143 for (i = 1; i < config->max_mac_addr; i++) {
5144 tmp64 = do_s2io_read_unicast_mc(sp, i);
5145 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5146 break;
5147
5148 if (tmp64 == mac_addr) {
5149 DBG_PRINT(INFO_DBG,
5150 "MAC addr:0x%llx already present in CAM\n",
5151 (unsigned long long)mac_addr);
5152 return SUCCESS;
5153 }
5154 }
5155 if (i == config->max_mac_addr) {
5156 DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5157 return FAILURE;
5158 }
5159 /* Update the internal structure with this new mac address */
5160 do_s2io_copy_mac_addr(sp, i, mac_addr);
5161 return (do_s2io_add_mac(sp, mac_addr, i));
5162 }
5163
5164 /**
5165 * s2io_ethtool_sset - Sets different link parameters.
5166 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5167 * @info: pointer to the structure with parameters given by ethtool to set
5168 * link information.
5169 * Description:
5170 * The function sets different link parameters provided by the user onto
5171 * the NIC.
5172 * Return value:
5173 * 0 on success.
5174 */
5175
5176 static int s2io_ethtool_sset(struct net_device *dev,
5177 struct ethtool_cmd *info)
5178 {
5179 struct s2io_nic *sp = dev->priv;
5180 if ((info->autoneg == AUTONEG_ENABLE) ||
5181 (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
5182 return -EINVAL;
5183 else {
5184 s2io_close(sp->dev);
5185 s2io_open(sp->dev);
5186 }
5187
5188 return 0;
5189 }
5190
5191 /**
5192 * s2io_ethtol_gset - Return link specific information.
5193 * @sp : private member of the device structure, pointer to the
5194 * s2io_nic structure.
5195 * @info : pointer to the structure with parameters given by ethtool
5196 * to return link information.
5197 * Description:
5198 * Returns link specific information like speed, duplex etc.. to ethtool.
5199 * Return value :
5200 * return 0 on success.
5201 */
5202
5203 static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
5204 {
5205 struct s2io_nic *sp = dev->priv;
5206 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5207 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5208 info->port = PORT_FIBRE;
5209
5210 /* info->transceiver */
5211 info->transceiver = XCVR_EXTERNAL;
5212
5213 if (netif_carrier_ok(sp->dev)) {
5214 info->speed = 10000;
5215 info->duplex = DUPLEX_FULL;
5216 } else {
5217 info->speed = -1;
5218 info->duplex = -1;
5219 }
5220
5221 info->autoneg = AUTONEG_DISABLE;
5222 return 0;
5223 }
5224
5225 /**
5226 * s2io_ethtool_gdrvinfo - Returns driver specific information.
5227 * @sp : private member of the device structure, which is a pointer to the
5228 * s2io_nic structure.
5229 * @info : pointer to the structure with parameters given by ethtool to
5230 * return driver information.
5231 * Description:
5232 * Returns driver specefic information like name, version etc.. to ethtool.
5233 * Return value:
5234 * void
5235 */
5236
5237 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5238 struct ethtool_drvinfo *info)
5239 {
5240 struct s2io_nic *sp = dev->priv;
5241
5242 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
5243 strncpy(info->version, s2io_driver_version, sizeof(info->version));
5244 strncpy(info->fw_version, "", sizeof(info->fw_version));
5245 strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
5246 info->regdump_len = XENA_REG_SPACE;
5247 info->eedump_len = XENA_EEPROM_SPACE;
5248 }
5249
5250 /**
5251 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
5252 * @sp: private member of the device structure, which is a pointer to the
5253 * s2io_nic structure.
5254 * @regs : pointer to the structure with parameters given by ethtool for
5255 * dumping the registers.
5256 * @reg_space: The input argumnet into which all the registers are dumped.
5257 * Description:
5258 * Dumps the entire register space of xFrame NIC into the user given
5259 * buffer area.
5260 * Return value :
5261 * void .
5262 */
5263
5264 static void s2io_ethtool_gregs(struct net_device *dev,
5265 struct ethtool_regs *regs, void *space)
5266 {
5267 int i;
5268 u64 reg;
5269 u8 *reg_space = (u8 *) space;
5270 struct s2io_nic *sp = dev->priv;
5271
5272 regs->len = XENA_REG_SPACE;
5273 regs->version = sp->pdev->subsystem_device;
5274
5275 for (i = 0; i < regs->len; i += 8) {
5276 reg = readq(sp->bar0 + i);
5277 memcpy((reg_space + i), &reg, 8);
5278 }
5279 }
5280
5281 /**
5282 * s2io_phy_id - timer function that alternates adapter LED.
5283 * @data : address of the private member of the device structure, which
5284 * is a pointer to the s2io_nic structure, provided as an u32.
5285 * Description: This is actually the timer function that alternates the
5286 * adapter LED bit of the adapter control bit to set/reset every time on
5287 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
5288 * once every second.
5289 */
5290 static void s2io_phy_id(unsigned long data)
5291 {
5292 struct s2io_nic *sp = (struct s2io_nic *) data;
5293 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5294 u64 val64 = 0;
5295 u16 subid;
5296
5297 subid = sp->pdev->subsystem_device;
5298 if ((sp->device_type == XFRAME_II_DEVICE) ||
5299 ((subid & 0xFF) >= 0x07)) {
5300 val64 = readq(&bar0->gpio_control);
5301 val64 ^= GPIO_CTRL_GPIO_0;
5302 writeq(val64, &bar0->gpio_control);
5303 } else {
5304 val64 = readq(&bar0->adapter_control);
5305 val64 ^= ADAPTER_LED_ON;
5306 writeq(val64, &bar0->adapter_control);
5307 }
5308
5309 mod_timer(&sp->id_timer, jiffies + HZ / 2);
5310 }
5311
5312 /**
5313 * s2io_ethtool_idnic - To physically identify the nic on the system.
5314 * @sp : private member of the device structure, which is a pointer to the
5315 * s2io_nic structure.
5316 * @id : pointer to the structure with identification parameters given by
5317 * ethtool.
5318 * Description: Used to physically identify the NIC on the system.
5319 * The Link LED will blink for a time specified by the user for
5320 * identification.
5321 * NOTE: The Link has to be Up to be able to blink the LED. Hence
5322 * identification is possible only if it's link is up.
5323 * Return value:
5324 * int , returns 0 on success
5325 */
5326
5327 static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
5328 {
5329 u64 val64 = 0, last_gpio_ctrl_val;
5330 struct s2io_nic *sp = dev->priv;
5331 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5332 u16 subid;
5333
5334 subid = sp->pdev->subsystem_device;
5335 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5336 if ((sp->device_type == XFRAME_I_DEVICE) &&
5337 ((subid & 0xFF) < 0x07)) {
5338 val64 = readq(&bar0->adapter_control);
5339 if (!(val64 & ADAPTER_CNTL_EN)) {
5340 printk(KERN_ERR
5341 "Adapter Link down, cannot blink LED\n");
5342 return -EFAULT;
5343 }
5344 }
5345 if (sp->id_timer.function == NULL) {
5346 init_timer(&sp->id_timer);
5347 sp->id_timer.function = s2io_phy_id;
5348 sp->id_timer.data = (unsigned long) sp;
5349 }
5350 mod_timer(&sp->id_timer, jiffies);
5351 if (data)
5352 msleep_interruptible(data * HZ);
5353 else
5354 msleep_interruptible(MAX_FLICKER_TIME);
5355 del_timer_sync(&sp->id_timer);
5356
5357 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
5358 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
5359 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5360 }
5361
5362 return 0;
5363 }
5364
5365 static void s2io_ethtool_gringparam(struct net_device *dev,
5366 struct ethtool_ringparam *ering)
5367 {
5368 struct s2io_nic *sp = dev->priv;
5369 int i,tx_desc_count=0,rx_desc_count=0;
5370
5371 if (sp->rxd_mode == RXD_MODE_1)
5372 ering->rx_max_pending = MAX_RX_DESC_1;
5373 else if (sp->rxd_mode == RXD_MODE_3B)
5374 ering->rx_max_pending = MAX_RX_DESC_2;
5375
5376 ering->tx_max_pending = MAX_TX_DESC;
5377 for (i = 0 ; i < sp->config.tx_fifo_num ; i++)
5378 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
5379
5380 DBG_PRINT(INFO_DBG,"\nmax txds : %d\n",sp->config.max_txds);
5381 ering->tx_pending = tx_desc_count;
5382 rx_desc_count = 0;
5383 for (i = 0 ; i < sp->config.rx_ring_num ; i++)
5384 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
5385
5386 ering->rx_pending = rx_desc_count;
5387
5388 ering->rx_mini_max_pending = 0;
5389 ering->rx_mini_pending = 0;
5390 if(sp->rxd_mode == RXD_MODE_1)
5391 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
5392 else if (sp->rxd_mode == RXD_MODE_3B)
5393 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
5394 ering->rx_jumbo_pending = rx_desc_count;
5395 }
5396
5397 /**
5398 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
5399 * @sp : private member of the device structure, which is a pointer to the
5400 * s2io_nic structure.
5401 * @ep : pointer to the structure with pause parameters given by ethtool.
5402 * Description:
5403 * Returns the Pause frame generation and reception capability of the NIC.
5404 * Return value:
5405 * void
5406 */
5407 static void s2io_ethtool_getpause_data(struct net_device *dev,
5408 struct ethtool_pauseparam *ep)
5409 {
5410 u64 val64;
5411 struct s2io_nic *sp = dev->priv;
5412 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5413
5414 val64 = readq(&bar0->rmac_pause_cfg);
5415 if (val64 & RMAC_PAUSE_GEN_ENABLE)
5416 ep->tx_pause = TRUE;
5417 if (val64 & RMAC_PAUSE_RX_ENABLE)
5418 ep->rx_pause = TRUE;
5419 ep->autoneg = FALSE;
5420 }
5421
5422 /**
5423 * s2io_ethtool_setpause_data - set/reset pause frame generation.
5424 * @sp : private member of the device structure, which is a pointer to the
5425 * s2io_nic structure.
5426 * @ep : pointer to the structure with pause parameters given by ethtool.
5427 * Description:
5428 * It can be used to set or reset Pause frame generation or reception
5429 * support of the NIC.
5430 * Return value:
5431 * int, returns 0 on Success
5432 */
5433
5434 static int s2io_ethtool_setpause_data(struct net_device *dev,
5435 struct ethtool_pauseparam *ep)
5436 {
5437 u64 val64;
5438 struct s2io_nic *sp = dev->priv;
5439 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5440
5441 val64 = readq(&bar0->rmac_pause_cfg);
5442 if (ep->tx_pause)
5443 val64 |= RMAC_PAUSE_GEN_ENABLE;
5444 else
5445 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5446 if (ep->rx_pause)
5447 val64 |= RMAC_PAUSE_RX_ENABLE;
5448 else
5449 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5450 writeq(val64, &bar0->rmac_pause_cfg);
5451 return 0;
5452 }
5453
5454 /**
5455 * read_eeprom - reads 4 bytes of data from user given offset.
5456 * @sp : private member of the device structure, which is a pointer to the
5457 * s2io_nic structure.
5458 * @off : offset at which the data must be written
5459 * @data : Its an output parameter where the data read at the given
5460 * offset is stored.
5461 * Description:
5462 * Will read 4 bytes of data from the user given offset and return the
5463 * read data.
5464 * NOTE: Will allow to read only part of the EEPROM visible through the
5465 * I2C bus.
5466 * Return value:
5467 * -1 on failure and 0 on success.
5468 */
5469
5470 #define S2IO_DEV_ID 5
5471 static int read_eeprom(struct s2io_nic * sp, int off, u64 * data)
5472 {
5473 int ret = -1;
5474 u32 exit_cnt = 0;
5475 u64 val64;
5476 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5477
5478 if (sp->device_type == XFRAME_I_DEVICE) {
5479 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
5480 I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
5481 I2C_CONTROL_CNTL_START;
5482 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5483
5484 while (exit_cnt < 5) {
5485 val64 = readq(&bar0->i2c_control);
5486 if (I2C_CONTROL_CNTL_END(val64)) {
5487 *data = I2C_CONTROL_GET_DATA(val64);
5488 ret = 0;
5489 break;
5490 }
5491 msleep(50);
5492 exit_cnt++;
5493 }
5494 }
5495
5496 if (sp->device_type == XFRAME_II_DEVICE) {
5497 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5498 SPI_CONTROL_BYTECNT(0x3) |
5499 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5500 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5501 val64 |= SPI_CONTROL_REQ;
5502 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5503 while (exit_cnt < 5) {
5504 val64 = readq(&bar0->spi_control);
5505 if (val64 & SPI_CONTROL_NACK) {
5506 ret = 1;
5507 break;
5508 } else if (val64 & SPI_CONTROL_DONE) {
5509 *data = readq(&bar0->spi_data);
5510 *data &= 0xffffff;
5511 ret = 0;
5512 break;
5513 }
5514 msleep(50);
5515 exit_cnt++;
5516 }
5517 }
5518 return ret;
5519 }
5520
5521 /**
5522 * write_eeprom - actually writes the relevant part of the data value.
5523 * @sp : private member of the device structure, which is a pointer to the
5524 * s2io_nic structure.
5525 * @off : offset at which the data must be written
5526 * @data : The data that is to be written
5527 * @cnt : Number of bytes of the data that are actually to be written into
5528 * the Eeprom. (max of 3)
5529 * Description:
5530 * Actually writes the relevant part of the data value into the Eeprom
5531 * through the I2C bus.
5532 * Return value:
5533 * 0 on success, -1 on failure.
5534 */
5535
5536 static int write_eeprom(struct s2io_nic * sp, int off, u64 data, int cnt)
5537 {
5538 int exit_cnt = 0, ret = -1;
5539 u64 val64;
5540 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5541
5542 if (sp->device_type == XFRAME_I_DEVICE) {
5543 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
5544 I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
5545 I2C_CONTROL_CNTL_START;
5546 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5547
5548 while (exit_cnt < 5) {
5549 val64 = readq(&bar0->i2c_control);
5550 if (I2C_CONTROL_CNTL_END(val64)) {
5551 if (!(val64 & I2C_CONTROL_NACK))
5552 ret = 0;
5553 break;
5554 }
5555 msleep(50);
5556 exit_cnt++;
5557 }
5558 }
5559
5560 if (sp->device_type == XFRAME_II_DEVICE) {
5561 int write_cnt = (cnt == 8) ? 0 : cnt;
5562 writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
5563
5564 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5565 SPI_CONTROL_BYTECNT(write_cnt) |
5566 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5567 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5568 val64 |= SPI_CONTROL_REQ;
5569 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5570 while (exit_cnt < 5) {
5571 val64 = readq(&bar0->spi_control);
5572 if (val64 & SPI_CONTROL_NACK) {
5573 ret = 1;
5574 break;
5575 } else if (val64 & SPI_CONTROL_DONE) {
5576 ret = 0;
5577 break;
5578 }
5579 msleep(50);
5580 exit_cnt++;
5581 }
5582 }
5583 return ret;
5584 }
5585 static void s2io_vpd_read(struct s2io_nic *nic)
5586 {
5587 u8 *vpd_data;
5588 u8 data;
5589 int i=0, cnt, fail = 0;
5590 int vpd_addr = 0x80;
5591
5592 if (nic->device_type == XFRAME_II_DEVICE) {
5593 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5594 vpd_addr = 0x80;
5595 }
5596 else {
5597 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5598 vpd_addr = 0x50;
5599 }
5600 strcpy(nic->serial_num, "NOT AVAILABLE");
5601
5602 vpd_data = kmalloc(256, GFP_KERNEL);
5603 if (!vpd_data) {
5604 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
5605 return;
5606 }
5607 nic->mac_control.stats_info->sw_stat.mem_allocated += 256;
5608
5609 for (i = 0; i < 256; i +=4 ) {
5610 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5611 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
5612 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
5613 for (cnt = 0; cnt <5; cnt++) {
5614 msleep(2);
5615 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5616 if (data == 0x80)
5617 break;
5618 }
5619 if (cnt >= 5) {
5620 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5621 fail = 1;
5622 break;
5623 }
5624 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
5625 (u32 *)&vpd_data[i]);
5626 }
5627
5628 if(!fail) {
5629 /* read serial number of adapter */
5630 for (cnt = 0; cnt < 256; cnt++) {
5631 if ((vpd_data[cnt] == 'S') &&
5632 (vpd_data[cnt+1] == 'N') &&
5633 (vpd_data[cnt+2] < VPD_STRING_LEN)) {
5634 memset(nic->serial_num, 0, VPD_STRING_LEN);
5635 memcpy(nic->serial_num, &vpd_data[cnt + 3],
5636 vpd_data[cnt+2]);
5637 break;
5638 }
5639 }
5640 }
5641
5642 if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
5643 memset(nic->product_name, 0, vpd_data[1]);
5644 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
5645 }
5646 kfree(vpd_data);
5647 nic->mac_control.stats_info->sw_stat.mem_freed += 256;
5648 }
5649
5650 /**
5651 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5652 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5653 * @eeprom : pointer to the user level structure provided by ethtool,
5654 * containing all relevant information.
5655 * @data_buf : user defined value to be written into Eeprom.
5656 * Description: Reads the values stored in the Eeprom at given offset
5657 * for a given length. Stores these values int the input argument data
5658 * buffer 'data_buf' and returns these to the caller (ethtool.)
5659 * Return value:
5660 * int 0 on success
5661 */
5662
5663 static int s2io_ethtool_geeprom(struct net_device *dev,
5664 struct ethtool_eeprom *eeprom, u8 * data_buf)
5665 {
5666 u32 i, valid;
5667 u64 data;
5668 struct s2io_nic *sp = dev->priv;
5669
5670 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5671
5672 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5673 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5674
5675 for (i = 0; i < eeprom->len; i += 4) {
5676 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5677 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5678 return -EFAULT;
5679 }
5680 valid = INV(data);
5681 memcpy((data_buf + i), &valid, 4);
5682 }
5683 return 0;
5684 }
5685
5686 /**
5687 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5688 * @sp : private member of the device structure, which is a pointer to the
5689 * s2io_nic structure.
5690 * @eeprom : pointer to the user level structure provided by ethtool,
5691 * containing all relevant information.
5692 * @data_buf ; user defined value to be written into Eeprom.
5693 * Description:
5694 * Tries to write the user provided value in the Eeprom, at the offset
5695 * given by the user.
5696 * Return value:
5697 * 0 on success, -EFAULT on failure.
5698 */
5699
5700 static int s2io_ethtool_seeprom(struct net_device *dev,
5701 struct ethtool_eeprom *eeprom,
5702 u8 * data_buf)
5703 {
5704 int len = eeprom->len, cnt = 0;
5705 u64 valid = 0, data;
5706 struct s2io_nic *sp = dev->priv;
5707
5708 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5709 DBG_PRINT(ERR_DBG,
5710 "ETHTOOL_WRITE_EEPROM Err: Magic value ");
5711 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
5712 eeprom->magic);
5713 return -EFAULT;
5714 }
5715
5716 while (len) {
5717 data = (u32) data_buf[cnt] & 0x000000FF;
5718 if (data) {
5719 valid = (u32) (data << 24);
5720 } else
5721 valid = data;
5722
5723 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5724 DBG_PRINT(ERR_DBG,
5725 "ETHTOOL_WRITE_EEPROM Err: Cannot ");
5726 DBG_PRINT(ERR_DBG,
5727 "write into the specified offset\n");
5728 return -EFAULT;
5729 }
5730 cnt++;
5731 len--;
5732 }
5733
5734 return 0;
5735 }
5736
5737 /**
5738 * s2io_register_test - reads and writes into all clock domains.
5739 * @sp : private member of the device structure, which is a pointer to the
5740 * s2io_nic structure.
5741 * @data : variable that returns the result of each of the test conducted b
5742 * by the driver.
5743 * Description:
5744 * Read and write into all clock domains. The NIC has 3 clock domains,
5745 * see that registers in all the three regions are accessible.
5746 * Return value:
5747 * 0 on success.
5748 */
5749
5750 static int s2io_register_test(struct s2io_nic * sp, uint64_t * data)
5751 {
5752 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5753 u64 val64 = 0, exp_val;
5754 int fail = 0;
5755
5756 val64 = readq(&bar0->pif_rd_swapper_fb);
5757 if (val64 != 0x123456789abcdefULL) {
5758 fail = 1;
5759 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
5760 }
5761
5762 val64 = readq(&bar0->rmac_pause_cfg);
5763 if (val64 != 0xc000ffff00000000ULL) {
5764 fail = 1;
5765 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
5766 }
5767
5768 val64 = readq(&bar0->rx_queue_cfg);
5769 if (sp->device_type == XFRAME_II_DEVICE)
5770 exp_val = 0x0404040404040404ULL;
5771 else
5772 exp_val = 0x0808080808080808ULL;
5773 if (val64 != exp_val) {
5774 fail = 1;
5775 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
5776 }
5777
5778 val64 = readq(&bar0->xgxs_efifo_cfg);
5779 if (val64 != 0x000000001923141EULL) {
5780 fail = 1;
5781 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
5782 }
5783
5784 val64 = 0x5A5A5A5A5A5A5A5AULL;
5785 writeq(val64, &bar0->xmsi_data);
5786 val64 = readq(&bar0->xmsi_data);
5787 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5788 fail = 1;
5789 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
5790 }
5791
5792 val64 = 0xA5A5A5A5A5A5A5A5ULL;
5793 writeq(val64, &bar0->xmsi_data);
5794 val64 = readq(&bar0->xmsi_data);
5795 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5796 fail = 1;
5797 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
5798 }
5799
5800 *data = fail;
5801 return fail;
5802 }
5803
5804 /**
5805 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
5806 * @sp : private member of the device structure, which is a pointer to the
5807 * s2io_nic structure.
5808 * @data:variable that returns the result of each of the test conducted by
5809 * the driver.
5810 * Description:
5811 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
5812 * register.
5813 * Return value:
5814 * 0 on success.
5815 */
5816
5817 static int s2io_eeprom_test(struct s2io_nic * sp, uint64_t * data)
5818 {
5819 int fail = 0;
5820 u64 ret_data, org_4F0, org_7F0;
5821 u8 saved_4F0 = 0, saved_7F0 = 0;
5822 struct net_device *dev = sp->dev;
5823
5824 /* Test Write Error at offset 0 */
5825 /* Note that SPI interface allows write access to all areas
5826 * of EEPROM. Hence doing all negative testing only for Xframe I.
5827 */
5828 if (sp->device_type == XFRAME_I_DEVICE)
5829 if (!write_eeprom(sp, 0, 0, 3))
5830 fail = 1;
5831
5832 /* Save current values at offsets 0x4F0 and 0x7F0 */
5833 if (!read_eeprom(sp, 0x4F0, &org_4F0))
5834 saved_4F0 = 1;
5835 if (!read_eeprom(sp, 0x7F0, &org_7F0))
5836 saved_7F0 = 1;
5837
5838 /* Test Write at offset 4f0 */
5839 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
5840 fail = 1;
5841 if (read_eeprom(sp, 0x4F0, &ret_data))
5842 fail = 1;
5843
5844 if (ret_data != 0x012345) {
5845 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
5846 "Data written %llx Data read %llx\n",
5847 dev->name, (unsigned long long)0x12345,
5848 (unsigned long long)ret_data);
5849 fail = 1;
5850 }
5851
5852 /* Reset the EEPROM data go FFFF */
5853 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
5854
5855 /* Test Write Request Error at offset 0x7c */
5856 if (sp->device_type == XFRAME_I_DEVICE)
5857 if (!write_eeprom(sp, 0x07C, 0, 3))
5858 fail = 1;
5859
5860 /* Test Write Request at offset 0x7f0 */
5861 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
5862 fail = 1;
5863 if (read_eeprom(sp, 0x7F0, &ret_data))
5864 fail = 1;
5865
5866 if (ret_data != 0x012345) {
5867 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
5868 "Data written %llx Data read %llx\n",
5869 dev->name, (unsigned long long)0x12345,
5870 (unsigned long long)ret_data);
5871 fail = 1;
5872 }
5873
5874 /* Reset the EEPROM data go FFFF */
5875 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
5876
5877 if (sp->device_type == XFRAME_I_DEVICE) {
5878 /* Test Write Error at offset 0x80 */
5879 if (!write_eeprom(sp, 0x080, 0, 3))
5880 fail = 1;
5881
5882 /* Test Write Error at offset 0xfc */
5883 if (!write_eeprom(sp, 0x0FC, 0, 3))
5884 fail = 1;
5885
5886 /* Test Write Error at offset 0x100 */
5887 if (!write_eeprom(sp, 0x100, 0, 3))
5888 fail = 1;
5889
5890 /* Test Write Error at offset 4ec */
5891 if (!write_eeprom(sp, 0x4EC, 0, 3))
5892 fail = 1;
5893 }
5894
5895 /* Restore values at offsets 0x4F0 and 0x7F0 */
5896 if (saved_4F0)
5897 write_eeprom(sp, 0x4F0, org_4F0, 3);
5898 if (saved_7F0)
5899 write_eeprom(sp, 0x7F0, org_7F0, 3);
5900
5901 *data = fail;
5902 return fail;
5903 }
5904
5905 /**
5906 * s2io_bist_test - invokes the MemBist test of the card .
5907 * @sp : private member of the device structure, which is a pointer to the
5908 * s2io_nic structure.
5909 * @data:variable that returns the result of each of the test conducted by
5910 * the driver.
5911 * Description:
5912 * This invokes the MemBist test of the card. We give around
5913 * 2 secs time for the Test to complete. If it's still not complete
5914 * within this peiod, we consider that the test failed.
5915 * Return value:
5916 * 0 on success and -1 on failure.
5917 */
5918
5919 static int s2io_bist_test(struct s2io_nic * sp, uint64_t * data)
5920 {
5921 u8 bist = 0;
5922 int cnt = 0, ret = -1;
5923
5924 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5925 bist |= PCI_BIST_START;
5926 pci_write_config_word(sp->pdev, PCI_BIST, bist);
5927
5928 while (cnt < 20) {
5929 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5930 if (!(bist & PCI_BIST_START)) {
5931 *data = (bist & PCI_BIST_CODE_MASK);
5932 ret = 0;
5933 break;
5934 }
5935 msleep(100);
5936 cnt++;
5937 }
5938
5939 return ret;
5940 }
5941
5942 /**
5943 * s2io-link_test - verifies the link state of the nic
5944 * @sp ; private member of the device structure, which is a pointer to the
5945 * s2io_nic structure.
5946 * @data: variable that returns the result of each of the test conducted by
5947 * the driver.
5948 * Description:
5949 * The function verifies the link state of the NIC and updates the input
5950 * argument 'data' appropriately.
5951 * Return value:
5952 * 0 on success.
5953 */
5954
5955 static int s2io_link_test(struct s2io_nic * sp, uint64_t * data)
5956 {
5957 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5958 u64 val64;
5959
5960 val64 = readq(&bar0->adapter_status);
5961 if(!(LINK_IS_UP(val64)))
5962 *data = 1;
5963 else
5964 *data = 0;
5965
5966 return *data;
5967 }
5968
5969 /**
5970 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
5971 * @sp - private member of the device structure, which is a pointer to the
5972 * s2io_nic structure.
5973 * @data - variable that returns the result of each of the test
5974 * conducted by the driver.
5975 * Description:
5976 * This is one of the offline test that tests the read and write
5977 * access to the RldRam chip on the NIC.
5978 * Return value:
5979 * 0 on success.
5980 */
5981
5982 static int s2io_rldram_test(struct s2io_nic * sp, uint64_t * data)
5983 {
5984 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5985 u64 val64;
5986 int cnt, iteration = 0, test_fail = 0;
5987
5988 val64 = readq(&bar0->adapter_control);
5989 val64 &= ~ADAPTER_ECC_EN;
5990 writeq(val64, &bar0->adapter_control);
5991
5992 val64 = readq(&bar0->mc_rldram_test_ctrl);
5993 val64 |= MC_RLDRAM_TEST_MODE;
5994 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
5995
5996 val64 = readq(&bar0->mc_rldram_mrs);
5997 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
5998 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
5999
6000 val64 |= MC_RLDRAM_MRS_ENABLE;
6001 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6002
6003 while (iteration < 2) {
6004 val64 = 0x55555555aaaa0000ULL;
6005 if (iteration == 1) {
6006 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6007 }
6008 writeq(val64, &bar0->mc_rldram_test_d0);
6009
6010 val64 = 0xaaaa5a5555550000ULL;
6011 if (iteration == 1) {
6012 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6013 }
6014 writeq(val64, &bar0->mc_rldram_test_d1);
6015
6016 val64 = 0x55aaaaaaaa5a0000ULL;
6017 if (iteration == 1) {
6018 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6019 }
6020 writeq(val64, &bar0->mc_rldram_test_d2);
6021
6022 val64 = (u64) (0x0000003ffffe0100ULL);
6023 writeq(val64, &bar0->mc_rldram_test_add);
6024
6025 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
6026 MC_RLDRAM_TEST_GO;
6027 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6028
6029 for (cnt = 0; cnt < 5; cnt++) {
6030 val64 = readq(&bar0->mc_rldram_test_ctrl);
6031 if (val64 & MC_RLDRAM_TEST_DONE)
6032 break;
6033 msleep(200);
6034 }
6035
6036 if (cnt == 5)
6037 break;
6038
6039 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
6040 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6041
6042 for (cnt = 0; cnt < 5; cnt++) {
6043 val64 = readq(&bar0->mc_rldram_test_ctrl);
6044 if (val64 & MC_RLDRAM_TEST_DONE)
6045 break;
6046 msleep(500);
6047 }
6048
6049 if (cnt == 5)
6050 break;
6051
6052 val64 = readq(&bar0->mc_rldram_test_ctrl);
6053 if (!(val64 & MC_RLDRAM_TEST_PASS))
6054 test_fail = 1;
6055
6056 iteration++;
6057 }
6058
6059 *data = test_fail;
6060
6061 /* Bring the adapter out of test mode */
6062 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
6063
6064 return test_fail;
6065 }
6066
6067 /**
6068 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
6069 * @sp : private member of the device structure, which is a pointer to the
6070 * s2io_nic structure.
6071 * @ethtest : pointer to a ethtool command specific structure that will be
6072 * returned to the user.
6073 * @data : variable that returns the result of each of the test
6074 * conducted by the driver.
6075 * Description:
6076 * This function conducts 6 tests ( 4 offline and 2 online) to determine
6077 * the health of the card.
6078 * Return value:
6079 * void
6080 */
6081
6082 static void s2io_ethtool_test(struct net_device *dev,
6083 struct ethtool_test *ethtest,
6084 uint64_t * data)
6085 {
6086 struct s2io_nic *sp = dev->priv;
6087 int orig_state = netif_running(sp->dev);
6088
6089 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
6090 /* Offline Tests. */
6091 if (orig_state)
6092 s2io_close(sp->dev);
6093
6094 if (s2io_register_test(sp, &data[0]))
6095 ethtest->flags |= ETH_TEST_FL_FAILED;
6096
6097 s2io_reset(sp);
6098
6099 if (s2io_rldram_test(sp, &data[3]))
6100 ethtest->flags |= ETH_TEST_FL_FAILED;
6101
6102 s2io_reset(sp);
6103
6104 if (s2io_eeprom_test(sp, &data[1]))
6105 ethtest->flags |= ETH_TEST_FL_FAILED;
6106
6107 if (s2io_bist_test(sp, &data[4]))
6108 ethtest->flags |= ETH_TEST_FL_FAILED;
6109
6110 if (orig_state)
6111 s2io_open(sp->dev);
6112
6113 data[2] = 0;
6114 } else {
6115 /* Online Tests. */
6116 if (!orig_state) {
6117 DBG_PRINT(ERR_DBG,
6118 "%s: is not up, cannot run test\n",
6119 dev->name);
6120 data[0] = -1;
6121 data[1] = -1;
6122 data[2] = -1;
6123 data[3] = -1;
6124 data[4] = -1;
6125 }
6126
6127 if (s2io_link_test(sp, &data[2]))
6128 ethtest->flags |= ETH_TEST_FL_FAILED;
6129
6130 data[0] = 0;
6131 data[1] = 0;
6132 data[3] = 0;
6133 data[4] = 0;
6134 }
6135 }
6136
6137 static void s2io_get_ethtool_stats(struct net_device *dev,
6138 struct ethtool_stats *estats,
6139 u64 * tmp_stats)
6140 {
6141 int i = 0, k;
6142 struct s2io_nic *sp = dev->priv;
6143 struct stat_block *stat_info = sp->mac_control.stats_info;
6144
6145 s2io_updt_stats(sp);
6146 tmp_stats[i++] =
6147 (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32 |
6148 le32_to_cpu(stat_info->tmac_frms);
6149 tmp_stats[i++] =
6150 (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
6151 le32_to_cpu(stat_info->tmac_data_octets);
6152 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
6153 tmp_stats[i++] =
6154 (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
6155 le32_to_cpu(stat_info->tmac_mcst_frms);
6156 tmp_stats[i++] =
6157 (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
6158 le32_to_cpu(stat_info->tmac_bcst_frms);
6159 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
6160 tmp_stats[i++] =
6161 (u64)le32_to_cpu(stat_info->tmac_ttl_octets_oflow) << 32 |
6162 le32_to_cpu(stat_info->tmac_ttl_octets);
6163 tmp_stats[i++] =
6164 (u64)le32_to_cpu(stat_info->tmac_ucst_frms_oflow) << 32 |
6165 le32_to_cpu(stat_info->tmac_ucst_frms);
6166 tmp_stats[i++] =
6167 (u64)le32_to_cpu(stat_info->tmac_nucst_frms_oflow) << 32 |
6168 le32_to_cpu(stat_info->tmac_nucst_frms);
6169 tmp_stats[i++] =
6170 (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
6171 le32_to_cpu(stat_info->tmac_any_err_frms);
6172 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_ttl_less_fb_octets);
6173 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
6174 tmp_stats[i++] =
6175 (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
6176 le32_to_cpu(stat_info->tmac_vld_ip);
6177 tmp_stats[i++] =
6178 (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
6179 le32_to_cpu(stat_info->tmac_drop_ip);
6180 tmp_stats[i++] =
6181 (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
6182 le32_to_cpu(stat_info->tmac_icmp);
6183 tmp_stats[i++] =
6184 (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
6185 le32_to_cpu(stat_info->tmac_rst_tcp);
6186 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
6187 tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
6188 le32_to_cpu(stat_info->tmac_udp);
6189 tmp_stats[i++] =
6190 (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
6191 le32_to_cpu(stat_info->rmac_vld_frms);
6192 tmp_stats[i++] =
6193 (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
6194 le32_to_cpu(stat_info->rmac_data_octets);
6195 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
6196 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
6197 tmp_stats[i++] =
6198 (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
6199 le32_to_cpu(stat_info->rmac_vld_mcst_frms);
6200 tmp_stats[i++] =
6201 (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
6202 le32_to_cpu(stat_info->rmac_vld_bcst_frms);
6203 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
6204 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_out_rng_len_err_frms);
6205 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
6206 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
6207 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_unsup_ctrl_frms);
6208 tmp_stats[i++] =
6209 (u64)le32_to_cpu(stat_info->rmac_ttl_octets_oflow) << 32 |
6210 le32_to_cpu(stat_info->rmac_ttl_octets);
6211 tmp_stats[i++] =
6212 (u64)le32_to_cpu(stat_info->rmac_accepted_ucst_frms_oflow)
6213 << 32 | le32_to_cpu(stat_info->rmac_accepted_ucst_frms);
6214 tmp_stats[i++] =
6215 (u64)le32_to_cpu(stat_info->rmac_accepted_nucst_frms_oflow)
6216 << 32 | le32_to_cpu(stat_info->rmac_accepted_nucst_frms);
6217 tmp_stats[i++] =
6218 (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
6219 le32_to_cpu(stat_info->rmac_discarded_frms);
6220 tmp_stats[i++] =
6221 (u64)le32_to_cpu(stat_info->rmac_drop_events_oflow)
6222 << 32 | le32_to_cpu(stat_info->rmac_drop_events);
6223 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_less_fb_octets);
6224 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_frms);
6225 tmp_stats[i++] =
6226 (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
6227 le32_to_cpu(stat_info->rmac_usized_frms);
6228 tmp_stats[i++] =
6229 (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
6230 le32_to_cpu(stat_info->rmac_osized_frms);
6231 tmp_stats[i++] =
6232 (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
6233 le32_to_cpu(stat_info->rmac_frag_frms);
6234 tmp_stats[i++] =
6235 (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
6236 le32_to_cpu(stat_info->rmac_jabber_frms);
6237 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_64_frms);
6238 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_65_127_frms);
6239 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_128_255_frms);
6240 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_256_511_frms);
6241 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_512_1023_frms);
6242 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1024_1518_frms);
6243 tmp_stats[i++] =
6244 (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
6245 le32_to_cpu(stat_info->rmac_ip);
6246 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
6247 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
6248 tmp_stats[i++] =
6249 (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
6250 le32_to_cpu(stat_info->rmac_drop_ip);
6251 tmp_stats[i++] =
6252 (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
6253 le32_to_cpu(stat_info->rmac_icmp);
6254 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
6255 tmp_stats[i++] =
6256 (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
6257 le32_to_cpu(stat_info->rmac_udp);
6258 tmp_stats[i++] =
6259 (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
6260 le32_to_cpu(stat_info->rmac_err_drp_udp);
6261 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_err_sym);
6262 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q0);
6263 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q1);
6264 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q2);
6265 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q3);
6266 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q4);
6267 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q5);
6268 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q6);
6269 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q7);
6270 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q0);
6271 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q1);
6272 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q2);
6273 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q3);
6274 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q4);
6275 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q5);
6276 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q6);
6277 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q7);
6278 tmp_stats[i++] =
6279 (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
6280 le32_to_cpu(stat_info->rmac_pause_cnt);
6281 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_data_err_cnt);
6282 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_ctrl_err_cnt);
6283 tmp_stats[i++] =
6284 (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
6285 le32_to_cpu(stat_info->rmac_accepted_ip);
6286 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
6287 tmp_stats[i++] = le32_to_cpu(stat_info->rd_req_cnt);
6288 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_cnt);
6289 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_rtry_cnt);
6290 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_cnt);
6291 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_rd_ack_cnt);
6292 tmp_stats[i++] = le32_to_cpu(stat_info->wr_req_cnt);
6293 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_cnt);
6294 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_rtry_cnt);
6295 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_cnt);
6296 tmp_stats[i++] = le32_to_cpu(stat_info->wr_disc_cnt);
6297 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_wr_ack_cnt);
6298 tmp_stats[i++] = le32_to_cpu(stat_info->txp_wr_cnt);
6299 tmp_stats[i++] = le32_to_cpu(stat_info->txd_rd_cnt);
6300 tmp_stats[i++] = le32_to_cpu(stat_info->txd_wr_cnt);
6301 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_rd_cnt);
6302 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_wr_cnt);
6303 tmp_stats[i++] = le32_to_cpu(stat_info->txf_rd_cnt);
6304 tmp_stats[i++] = le32_to_cpu(stat_info->rxf_wr_cnt);
6305
6306 /* Enhanced statistics exist only for Hercules */
6307 if(sp->device_type == XFRAME_II_DEVICE) {
6308 tmp_stats[i++] =
6309 le64_to_cpu(stat_info->rmac_ttl_1519_4095_frms);
6310 tmp_stats[i++] =
6311 le64_to_cpu(stat_info->rmac_ttl_4096_8191_frms);
6312 tmp_stats[i++] =
6313 le64_to_cpu(stat_info->rmac_ttl_8192_max_frms);
6314 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_gt_max_frms);
6315 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_osized_alt_frms);
6316 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_jabber_alt_frms);
6317 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_gt_max_alt_frms);
6318 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_vlan_frms);
6319 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_len_discard);
6320 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_fcs_discard);
6321 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_pf_discard);
6322 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_da_discard);
6323 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_red_discard);
6324 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_rts_discard);
6325 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_ingm_full_discard);
6326 tmp_stats[i++] = le32_to_cpu(stat_info->link_fault_cnt);
6327 }
6328
6329 tmp_stats[i++] = 0;
6330 tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
6331 tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
6332 tmp_stats[i++] = stat_info->sw_stat.parity_err_cnt;
6333 tmp_stats[i++] = stat_info->sw_stat.serious_err_cnt;
6334 tmp_stats[i++] = stat_info->sw_stat.soft_reset_cnt;
6335 tmp_stats[i++] = stat_info->sw_stat.fifo_full_cnt;
6336 for (k = 0; k < MAX_RX_RINGS; k++)
6337 tmp_stats[i++] = stat_info->sw_stat.ring_full_cnt[k];
6338 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_high;
6339 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_low;
6340 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_high;
6341 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_low;
6342 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_high;
6343 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_low;
6344 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_high;
6345 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_low;
6346 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_high;
6347 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_low;
6348 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_high;
6349 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_low;
6350 tmp_stats[i++] = stat_info->sw_stat.clubbed_frms_cnt;
6351 tmp_stats[i++] = stat_info->sw_stat.sending_both;
6352 tmp_stats[i++] = stat_info->sw_stat.outof_sequence_pkts;
6353 tmp_stats[i++] = stat_info->sw_stat.flush_max_pkts;
6354 if (stat_info->sw_stat.num_aggregations) {
6355 u64 tmp = stat_info->sw_stat.sum_avg_pkts_aggregated;
6356 int count = 0;
6357 /*
6358 * Since 64-bit divide does not work on all platforms,
6359 * do repeated subtraction.
6360 */
6361 while (tmp >= stat_info->sw_stat.num_aggregations) {
6362 tmp -= stat_info->sw_stat.num_aggregations;
6363 count++;
6364 }
6365 tmp_stats[i++] = count;
6366 }
6367 else
6368 tmp_stats[i++] = 0;
6369 tmp_stats[i++] = stat_info->sw_stat.mem_alloc_fail_cnt;
6370 tmp_stats[i++] = stat_info->sw_stat.pci_map_fail_cnt;
6371 tmp_stats[i++] = stat_info->sw_stat.watchdog_timer_cnt;
6372 tmp_stats[i++] = stat_info->sw_stat.mem_allocated;
6373 tmp_stats[i++] = stat_info->sw_stat.mem_freed;
6374 tmp_stats[i++] = stat_info->sw_stat.link_up_cnt;
6375 tmp_stats[i++] = stat_info->sw_stat.link_down_cnt;
6376 tmp_stats[i++] = stat_info->sw_stat.link_up_time;
6377 tmp_stats[i++] = stat_info->sw_stat.link_down_time;
6378
6379 tmp_stats[i++] = stat_info->sw_stat.tx_buf_abort_cnt;
6380 tmp_stats[i++] = stat_info->sw_stat.tx_desc_abort_cnt;
6381 tmp_stats[i++] = stat_info->sw_stat.tx_parity_err_cnt;
6382 tmp_stats[i++] = stat_info->sw_stat.tx_link_loss_cnt;
6383 tmp_stats[i++] = stat_info->sw_stat.tx_list_proc_err_cnt;
6384
6385 tmp_stats[i++] = stat_info->sw_stat.rx_parity_err_cnt;
6386 tmp_stats[i++] = stat_info->sw_stat.rx_abort_cnt;
6387 tmp_stats[i++] = stat_info->sw_stat.rx_parity_abort_cnt;
6388 tmp_stats[i++] = stat_info->sw_stat.rx_rda_fail_cnt;
6389 tmp_stats[i++] = stat_info->sw_stat.rx_unkn_prot_cnt;
6390 tmp_stats[i++] = stat_info->sw_stat.rx_fcs_err_cnt;
6391 tmp_stats[i++] = stat_info->sw_stat.rx_buf_size_err_cnt;
6392 tmp_stats[i++] = stat_info->sw_stat.rx_rxd_corrupt_cnt;
6393 tmp_stats[i++] = stat_info->sw_stat.rx_unkn_err_cnt;
6394 tmp_stats[i++] = stat_info->sw_stat.tda_err_cnt;
6395 tmp_stats[i++] = stat_info->sw_stat.pfc_err_cnt;
6396 tmp_stats[i++] = stat_info->sw_stat.pcc_err_cnt;
6397 tmp_stats[i++] = stat_info->sw_stat.tti_err_cnt;
6398 tmp_stats[i++] = stat_info->sw_stat.tpa_err_cnt;
6399 tmp_stats[i++] = stat_info->sw_stat.sm_err_cnt;
6400 tmp_stats[i++] = stat_info->sw_stat.lso_err_cnt;
6401 tmp_stats[i++] = stat_info->sw_stat.mac_tmac_err_cnt;
6402 tmp_stats[i++] = stat_info->sw_stat.mac_rmac_err_cnt;
6403 tmp_stats[i++] = stat_info->sw_stat.xgxs_txgxs_err_cnt;
6404 tmp_stats[i++] = stat_info->sw_stat.xgxs_rxgxs_err_cnt;
6405 tmp_stats[i++] = stat_info->sw_stat.rc_err_cnt;
6406 tmp_stats[i++] = stat_info->sw_stat.prc_pcix_err_cnt;
6407 tmp_stats[i++] = stat_info->sw_stat.rpa_err_cnt;
6408 tmp_stats[i++] = stat_info->sw_stat.rda_err_cnt;
6409 tmp_stats[i++] = stat_info->sw_stat.rti_err_cnt;
6410 tmp_stats[i++] = stat_info->sw_stat.mc_err_cnt;
6411 }
6412
6413 static int s2io_ethtool_get_regs_len(struct net_device *dev)
6414 {
6415 return (XENA_REG_SPACE);
6416 }
6417
6418
6419 static u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
6420 {
6421 struct s2io_nic *sp = dev->priv;
6422
6423 return (sp->rx_csum);
6424 }
6425
6426 static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
6427 {
6428 struct s2io_nic *sp = dev->priv;
6429
6430 if (data)
6431 sp->rx_csum = 1;
6432 else
6433 sp->rx_csum = 0;
6434
6435 return 0;
6436 }
6437
6438 static int s2io_get_eeprom_len(struct net_device *dev)
6439 {
6440 return (XENA_EEPROM_SPACE);
6441 }
6442
6443 static int s2io_get_sset_count(struct net_device *dev, int sset)
6444 {
6445 struct s2io_nic *sp = dev->priv;
6446
6447 switch (sset) {
6448 case ETH_SS_TEST:
6449 return S2IO_TEST_LEN;
6450 case ETH_SS_STATS:
6451 switch(sp->device_type) {
6452 case XFRAME_I_DEVICE:
6453 return XFRAME_I_STAT_LEN;
6454 case XFRAME_II_DEVICE:
6455 return XFRAME_II_STAT_LEN;
6456 default:
6457 return 0;
6458 }
6459 default:
6460 return -EOPNOTSUPP;
6461 }
6462 }
6463
6464 static void s2io_ethtool_get_strings(struct net_device *dev,
6465 u32 stringset, u8 * data)
6466 {
6467 int stat_size = 0;
6468 struct s2io_nic *sp = dev->priv;
6469
6470 switch (stringset) {
6471 case ETH_SS_TEST:
6472 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
6473 break;
6474 case ETH_SS_STATS:
6475 stat_size = sizeof(ethtool_xena_stats_keys);
6476 memcpy(data, &ethtool_xena_stats_keys,stat_size);
6477 if(sp->device_type == XFRAME_II_DEVICE) {
6478 memcpy(data + stat_size,
6479 &ethtool_enhanced_stats_keys,
6480 sizeof(ethtool_enhanced_stats_keys));
6481 stat_size += sizeof(ethtool_enhanced_stats_keys);
6482 }
6483
6484 memcpy(data + stat_size, &ethtool_driver_stats_keys,
6485 sizeof(ethtool_driver_stats_keys));
6486 }
6487 }
6488
6489 static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
6490 {
6491 if (data)
6492 dev->features |= NETIF_F_IP_CSUM;
6493 else
6494 dev->features &= ~NETIF_F_IP_CSUM;
6495
6496 return 0;
6497 }
6498
6499 static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
6500 {
6501 return (dev->features & NETIF_F_TSO) != 0;
6502 }
6503 static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
6504 {
6505 if (data)
6506 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
6507 else
6508 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
6509
6510 return 0;
6511 }
6512
6513 static const struct ethtool_ops netdev_ethtool_ops = {
6514 .get_settings = s2io_ethtool_gset,
6515 .set_settings = s2io_ethtool_sset,
6516 .get_drvinfo = s2io_ethtool_gdrvinfo,
6517 .get_regs_len = s2io_ethtool_get_regs_len,
6518 .get_regs = s2io_ethtool_gregs,
6519 .get_link = ethtool_op_get_link,
6520 .get_eeprom_len = s2io_get_eeprom_len,
6521 .get_eeprom = s2io_ethtool_geeprom,
6522 .set_eeprom = s2io_ethtool_seeprom,
6523 .get_ringparam = s2io_ethtool_gringparam,
6524 .get_pauseparam = s2io_ethtool_getpause_data,
6525 .set_pauseparam = s2io_ethtool_setpause_data,
6526 .get_rx_csum = s2io_ethtool_get_rx_csum,
6527 .set_rx_csum = s2io_ethtool_set_rx_csum,
6528 .set_tx_csum = s2io_ethtool_op_set_tx_csum,
6529 .set_sg = ethtool_op_set_sg,
6530 .get_tso = s2io_ethtool_op_get_tso,
6531 .set_tso = s2io_ethtool_op_set_tso,
6532 .set_ufo = ethtool_op_set_ufo,
6533 .self_test = s2io_ethtool_test,
6534 .get_strings = s2io_ethtool_get_strings,
6535 .phys_id = s2io_ethtool_idnic,
6536 .get_ethtool_stats = s2io_get_ethtool_stats,
6537 .get_sset_count = s2io_get_sset_count,
6538 };
6539
6540 /**
6541 * s2io_ioctl - Entry point for the Ioctl
6542 * @dev : Device pointer.
6543 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6544 * a proprietary structure used to pass information to the driver.
6545 * @cmd : This is used to distinguish between the different commands that
6546 * can be passed to the IOCTL functions.
6547 * Description:
6548 * Currently there are no special functionality supported in IOCTL, hence
6549 * function always return EOPNOTSUPPORTED
6550 */
6551
6552 static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
6553 {
6554 return -EOPNOTSUPP;
6555 }
6556
6557 /**
6558 * s2io_change_mtu - entry point to change MTU size for the device.
6559 * @dev : device pointer.
6560 * @new_mtu : the new MTU size for the device.
6561 * Description: A driver entry point to change MTU size for the device.
6562 * Before changing the MTU the device must be stopped.
6563 * Return value:
6564 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6565 * file on failure.
6566 */
6567
6568 static int s2io_change_mtu(struct net_device *dev, int new_mtu)
6569 {
6570 struct s2io_nic *sp = dev->priv;
6571 int ret = 0;
6572
6573 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
6574 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
6575 dev->name);
6576 return -EPERM;
6577 }
6578
6579 dev->mtu = new_mtu;
6580 if (netif_running(dev)) {
6581 s2io_card_down(sp);
6582 netif_stop_queue(dev);
6583 ret = s2io_card_up(sp);
6584 if (ret) {
6585 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6586 __FUNCTION__);
6587 return ret;
6588 }
6589 if (netif_queue_stopped(dev))
6590 netif_wake_queue(dev);
6591 } else { /* Device is down */
6592 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6593 u64 val64 = new_mtu;
6594
6595 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6596 }
6597
6598 return ret;
6599 }
6600
6601 /**
6602 * s2io_tasklet - Bottom half of the ISR.
6603 * @dev_adr : address of the device structure in dma_addr_t format.
6604 * Description:
6605 * This is the tasklet or the bottom half of the ISR. This is
6606 * an extension of the ISR which is scheduled by the scheduler to be run
6607 * when the load on the CPU is low. All low priority tasks of the ISR can
6608 * be pushed into the tasklet. For now the tasklet is used only to
6609 * replenish the Rx buffers in the Rx buffer descriptors.
6610 * Return value:
6611 * void.
6612 */
6613
6614 static void s2io_tasklet(unsigned long dev_addr)
6615 {
6616 struct net_device *dev = (struct net_device *) dev_addr;
6617 struct s2io_nic *sp = dev->priv;
6618 int i, ret;
6619 struct mac_info *mac_control;
6620 struct config_param *config;
6621
6622 mac_control = &sp->mac_control;
6623 config = &sp->config;
6624
6625 if (!TASKLET_IN_USE) {
6626 for (i = 0; i < config->rx_ring_num; i++) {
6627 ret = fill_rx_buffers(sp, i);
6628 if (ret == -ENOMEM) {
6629 DBG_PRINT(INFO_DBG, "%s: Out of ",
6630 dev->name);
6631 DBG_PRINT(INFO_DBG, "memory in tasklet\n");
6632 break;
6633 } else if (ret == -EFILL) {
6634 DBG_PRINT(INFO_DBG,
6635 "%s: Rx Ring %d is full\n",
6636 dev->name, i);
6637 break;
6638 }
6639 }
6640 clear_bit(0, (&sp->tasklet_status));
6641 }
6642 }
6643
6644 /**
6645 * s2io_set_link - Set the LInk status
6646 * @data: long pointer to device private structue
6647 * Description: Sets the link status for the adapter
6648 */
6649
6650 static void s2io_set_link(struct work_struct *work)
6651 {
6652 struct s2io_nic *nic = container_of(work, struct s2io_nic, set_link_task);
6653 struct net_device *dev = nic->dev;
6654 struct XENA_dev_config __iomem *bar0 = nic->bar0;
6655 register u64 val64;
6656 u16 subid;
6657
6658 rtnl_lock();
6659
6660 if (!netif_running(dev))
6661 goto out_unlock;
6662
6663 if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
6664 /* The card is being reset, no point doing anything */
6665 goto out_unlock;
6666 }
6667
6668 subid = nic->pdev->subsystem_device;
6669 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6670 /*
6671 * Allow a small delay for the NICs self initiated
6672 * cleanup to complete.
6673 */
6674 msleep(100);
6675 }
6676
6677 val64 = readq(&bar0->adapter_status);
6678 if (LINK_IS_UP(val64)) {
6679 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6680 if (verify_xena_quiescence(nic)) {
6681 val64 = readq(&bar0->adapter_control);
6682 val64 |= ADAPTER_CNTL_EN;
6683 writeq(val64, &bar0->adapter_control);
6684 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6685 nic->device_type, subid)) {
6686 val64 = readq(&bar0->gpio_control);
6687 val64 |= GPIO_CTRL_GPIO_0;
6688 writeq(val64, &bar0->gpio_control);
6689 val64 = readq(&bar0->gpio_control);
6690 } else {
6691 val64 |= ADAPTER_LED_ON;
6692 writeq(val64, &bar0->adapter_control);
6693 }
6694 nic->device_enabled_once = TRUE;
6695 } else {
6696 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
6697 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
6698 netif_stop_queue(dev);
6699 }
6700 }
6701 val64 = readq(&bar0->adapter_control);
6702 val64 |= ADAPTER_LED_ON;
6703 writeq(val64, &bar0->adapter_control);
6704 s2io_link(nic, LINK_UP);
6705 } else {
6706 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6707 subid)) {
6708 val64 = readq(&bar0->gpio_control);
6709 val64 &= ~GPIO_CTRL_GPIO_0;
6710 writeq(val64, &bar0->gpio_control);
6711 val64 = readq(&bar0->gpio_control);
6712 }
6713 /* turn off LED */
6714 val64 = readq(&bar0->adapter_control);
6715 val64 = val64 &(~ADAPTER_LED_ON);
6716 writeq(val64, &bar0->adapter_control);
6717 s2io_link(nic, LINK_DOWN);
6718 }
6719 clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
6720
6721 out_unlock:
6722 rtnl_unlock();
6723 }
6724
6725 static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
6726 struct buffAdd *ba,
6727 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6728 u64 *temp2, int size)
6729 {
6730 struct net_device *dev = sp->dev;
6731 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
6732
6733 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6734 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
6735 /* allocate skb */
6736 if (*skb) {
6737 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6738 /*
6739 * As Rx frame are not going to be processed,
6740 * using same mapped address for the Rxd
6741 * buffer pointer
6742 */
6743 rxdp1->Buffer0_ptr = *temp0;
6744 } else {
6745 *skb = dev_alloc_skb(size);
6746 if (!(*skb)) {
6747 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
6748 DBG_PRINT(INFO_DBG, "memory to allocate ");
6749 DBG_PRINT(INFO_DBG, "1 buf mode SKBs\n");
6750 sp->mac_control.stats_info->sw_stat. \
6751 mem_alloc_fail_cnt++;
6752 return -ENOMEM ;
6753 }
6754 sp->mac_control.stats_info->sw_stat.mem_allocated
6755 += (*skb)->truesize;
6756 /* storing the mapped addr in a temp variable
6757 * such it will be used for next rxd whose
6758 * Host Control is NULL
6759 */
6760 rxdp1->Buffer0_ptr = *temp0 =
6761 pci_map_single( sp->pdev, (*skb)->data,
6762 size - NET_IP_ALIGN,
6763 PCI_DMA_FROMDEVICE);
6764 if( (rxdp1->Buffer0_ptr == 0) ||
6765 (rxdp1->Buffer0_ptr == DMA_ERROR_CODE)) {
6766 goto memalloc_failed;
6767 }
6768 rxdp->Host_Control = (unsigned long) (*skb);
6769 }
6770 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6771 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
6772 /* Two buffer Mode */
6773 if (*skb) {
6774 rxdp3->Buffer2_ptr = *temp2;
6775 rxdp3->Buffer0_ptr = *temp0;
6776 rxdp3->Buffer1_ptr = *temp1;
6777 } else {
6778 *skb = dev_alloc_skb(size);
6779 if (!(*skb)) {
6780 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
6781 DBG_PRINT(INFO_DBG, "memory to allocate ");
6782 DBG_PRINT(INFO_DBG, "2 buf mode SKBs\n");
6783 sp->mac_control.stats_info->sw_stat. \
6784 mem_alloc_fail_cnt++;
6785 return -ENOMEM;
6786 }
6787 sp->mac_control.stats_info->sw_stat.mem_allocated
6788 += (*skb)->truesize;
6789 rxdp3->Buffer2_ptr = *temp2 =
6790 pci_map_single(sp->pdev, (*skb)->data,
6791 dev->mtu + 4,
6792 PCI_DMA_FROMDEVICE);
6793 if( (rxdp3->Buffer2_ptr == 0) ||
6794 (rxdp3->Buffer2_ptr == DMA_ERROR_CODE)) {
6795 goto memalloc_failed;
6796 }
6797 rxdp3->Buffer0_ptr = *temp0 =
6798 pci_map_single( sp->pdev, ba->ba_0, BUF0_LEN,
6799 PCI_DMA_FROMDEVICE);
6800 if( (rxdp3->Buffer0_ptr == 0) ||
6801 (rxdp3->Buffer0_ptr == DMA_ERROR_CODE)) {
6802 pci_unmap_single (sp->pdev,
6803 (dma_addr_t)rxdp3->Buffer2_ptr,
6804 dev->mtu + 4, PCI_DMA_FROMDEVICE);
6805 goto memalloc_failed;
6806 }
6807 rxdp->Host_Control = (unsigned long) (*skb);
6808
6809 /* Buffer-1 will be dummy buffer not used */
6810 rxdp3->Buffer1_ptr = *temp1 =
6811 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
6812 PCI_DMA_FROMDEVICE);
6813 if( (rxdp3->Buffer1_ptr == 0) ||
6814 (rxdp3->Buffer1_ptr == DMA_ERROR_CODE)) {
6815 pci_unmap_single (sp->pdev,
6816 (dma_addr_t)rxdp3->Buffer0_ptr,
6817 BUF0_LEN, PCI_DMA_FROMDEVICE);
6818 pci_unmap_single (sp->pdev,
6819 (dma_addr_t)rxdp3->Buffer2_ptr,
6820 dev->mtu + 4, PCI_DMA_FROMDEVICE);
6821 goto memalloc_failed;
6822 }
6823 }
6824 }
6825 return 0;
6826 memalloc_failed:
6827 stats->pci_map_fail_cnt++;
6828 stats->mem_freed += (*skb)->truesize;
6829 dev_kfree_skb(*skb);
6830 return -ENOMEM;
6831 }
6832
6833 static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6834 int size)
6835 {
6836 struct net_device *dev = sp->dev;
6837 if (sp->rxd_mode == RXD_MODE_1) {
6838 rxdp->Control_2 = SET_BUFFER0_SIZE_1( size - NET_IP_ALIGN);
6839 } else if (sp->rxd_mode == RXD_MODE_3B) {
6840 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6841 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
6842 rxdp->Control_2 |= SET_BUFFER2_SIZE_3( dev->mtu + 4);
6843 }
6844 }
6845
6846 static int rxd_owner_bit_reset(struct s2io_nic *sp)
6847 {
6848 int i, j, k, blk_cnt = 0, size;
6849 struct mac_info * mac_control = &sp->mac_control;
6850 struct config_param *config = &sp->config;
6851 struct net_device *dev = sp->dev;
6852 struct RxD_t *rxdp = NULL;
6853 struct sk_buff *skb = NULL;
6854 struct buffAdd *ba = NULL;
6855 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6856
6857 /* Calculate the size based on ring mode */
6858 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6859 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6860 if (sp->rxd_mode == RXD_MODE_1)
6861 size += NET_IP_ALIGN;
6862 else if (sp->rxd_mode == RXD_MODE_3B)
6863 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
6864
6865 for (i = 0; i < config->rx_ring_num; i++) {
6866 blk_cnt = config->rx_cfg[i].num_rxd /
6867 (rxd_count[sp->rxd_mode] +1);
6868
6869 for (j = 0; j < blk_cnt; j++) {
6870 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
6871 rxdp = mac_control->rings[i].
6872 rx_blocks[j].rxds[k].virt_addr;
6873 if(sp->rxd_mode == RXD_MODE_3B)
6874 ba = &mac_control->rings[i].ba[j][k];
6875 if (set_rxd_buffer_pointer(sp, rxdp, ba,
6876 &skb,(u64 *)&temp0_64,
6877 (u64 *)&temp1_64,
6878 (u64 *)&temp2_64,
6879 size) == ENOMEM) {
6880 return 0;
6881 }
6882
6883 set_rxd_buffer_size(sp, rxdp, size);
6884 wmb();
6885 /* flip the Ownership bit to Hardware */
6886 rxdp->Control_1 |= RXD_OWN_XENA;
6887 }
6888 }
6889 }
6890 return 0;
6891
6892 }
6893
6894 static int s2io_add_isr(struct s2io_nic * sp)
6895 {
6896 int ret = 0;
6897 struct net_device *dev = sp->dev;
6898 int err = 0;
6899
6900 if (sp->config.intr_type == MSI_X)
6901 ret = s2io_enable_msi_x(sp);
6902 if (ret) {
6903 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
6904 sp->config.intr_type = INTA;
6905 }
6906
6907 /* Store the values of the MSIX table in the struct s2io_nic structure */
6908 store_xmsi_data(sp);
6909
6910 /* After proper initialization of H/W, register ISR */
6911 if (sp->config.intr_type == MSI_X) {
6912 int i, msix_tx_cnt=0,msix_rx_cnt=0;
6913
6914 for (i=1; (sp->s2io_entries[i].in_use == MSIX_FLG); i++) {
6915 if (sp->s2io_entries[i].type == MSIX_FIFO_TYPE) {
6916 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
6917 dev->name, i);
6918 err = request_irq(sp->entries[i].vector,
6919 s2io_msix_fifo_handle, 0, sp->desc[i],
6920 sp->s2io_entries[i].arg);
6921 /* If either data or addr is zero print it */
6922 if(!(sp->msix_info[i].addr &&
6923 sp->msix_info[i].data)) {
6924 DBG_PRINT(ERR_DBG, "%s @ Addr:0x%llx "
6925 "Data:0x%lx\n",sp->desc[i],
6926 (unsigned long long)
6927 sp->msix_info[i].addr,
6928 (unsigned long)
6929 ntohl(sp->msix_info[i].data));
6930 } else {
6931 msix_tx_cnt++;
6932 }
6933 } else {
6934 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
6935 dev->name, i);
6936 err = request_irq(sp->entries[i].vector,
6937 s2io_msix_ring_handle, 0, sp->desc[i],
6938 sp->s2io_entries[i].arg);
6939 /* If either data or addr is zero print it */
6940 if(!(sp->msix_info[i].addr &&
6941 sp->msix_info[i].data)) {
6942 DBG_PRINT(ERR_DBG, "%s @ Addr:0x%llx "
6943 "Data:0x%lx\n",sp->desc[i],
6944 (unsigned long long)
6945 sp->msix_info[i].addr,
6946 (unsigned long)
6947 ntohl(sp->msix_info[i].data));
6948 } else {
6949 msix_rx_cnt++;
6950 }
6951 }
6952 if (err) {
6953 remove_msix_isr(sp);
6954 DBG_PRINT(ERR_DBG,"%s:MSI-X-%d registration "
6955 "failed\n", dev->name, i);
6956 DBG_PRINT(ERR_DBG, "%s: defaulting to INTA\n",
6957 dev->name);
6958 sp->config.intr_type = INTA;
6959 break;
6960 }
6961 sp->s2io_entries[i].in_use = MSIX_REGISTERED_SUCCESS;
6962 }
6963 if (!err) {
6964 printk(KERN_INFO "MSI-X-TX %d entries enabled\n",
6965 msix_tx_cnt);
6966 printk(KERN_INFO "MSI-X-RX %d entries enabled\n",
6967 msix_rx_cnt);
6968 }
6969 }
6970 if (sp->config.intr_type == INTA) {
6971 err = request_irq((int) sp->pdev->irq, s2io_isr, IRQF_SHARED,
6972 sp->name, dev);
6973 if (err) {
6974 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
6975 dev->name);
6976 return -1;
6977 }
6978 }
6979 return 0;
6980 }
6981 static void s2io_rem_isr(struct s2io_nic * sp)
6982 {
6983 if (sp->config.intr_type == MSI_X)
6984 remove_msix_isr(sp);
6985 else
6986 remove_inta_isr(sp);
6987 }
6988
6989 static void do_s2io_card_down(struct s2io_nic * sp, int do_io)
6990 {
6991 int cnt = 0;
6992 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6993 unsigned long flags;
6994 register u64 val64 = 0;
6995 struct config_param *config;
6996 config = &sp->config;
6997
6998 if (!is_s2io_card_up(sp))
6999 return;
7000
7001 del_timer_sync(&sp->alarm_timer);
7002 /* If s2io_set_link task is executing, wait till it completes. */
7003 while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state))) {
7004 msleep(50);
7005 }
7006 clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
7007
7008 /* Disable napi */
7009 if (config->napi)
7010 napi_disable(&sp->napi);
7011
7012 /* disable Tx and Rx traffic on the NIC */
7013 if (do_io)
7014 stop_nic(sp);
7015
7016 s2io_rem_isr(sp);
7017
7018 /* Kill tasklet. */
7019 tasklet_kill(&sp->task);
7020
7021 /* Check if the device is Quiescent and then Reset the NIC */
7022 while(do_io) {
7023 /* As per the HW requirement we need to replenish the
7024 * receive buffer to avoid the ring bump. Since there is
7025 * no intention of processing the Rx frame at this pointwe are
7026 * just settting the ownership bit of rxd in Each Rx
7027 * ring to HW and set the appropriate buffer size
7028 * based on the ring mode
7029 */
7030 rxd_owner_bit_reset(sp);
7031
7032 val64 = readq(&bar0->adapter_status);
7033 if (verify_xena_quiescence(sp)) {
7034 if(verify_pcc_quiescent(sp, sp->device_enabled_once))
7035 break;
7036 }
7037
7038 msleep(50);
7039 cnt++;
7040 if (cnt == 10) {
7041 DBG_PRINT(ERR_DBG,
7042 "s2io_close:Device not Quiescent ");
7043 DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
7044 (unsigned long long) val64);
7045 break;
7046 }
7047 }
7048 if (do_io)
7049 s2io_reset(sp);
7050
7051 /* Free all Tx buffers */
7052 free_tx_buffers(sp);
7053
7054 /* Free all Rx buffers */
7055 spin_lock_irqsave(&sp->rx_lock, flags);
7056 free_rx_buffers(sp);
7057 spin_unlock_irqrestore(&sp->rx_lock, flags);
7058
7059 clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
7060 }
7061
7062 static void s2io_card_down(struct s2io_nic * sp)
7063 {
7064 do_s2io_card_down(sp, 1);
7065 }
7066
7067 static int s2io_card_up(struct s2io_nic * sp)
7068 {
7069 int i, ret = 0;
7070 struct mac_info *mac_control;
7071 struct config_param *config;
7072 struct net_device *dev = (struct net_device *) sp->dev;
7073 u16 interruptible;
7074
7075 /* Initialize the H/W I/O registers */
7076 ret = init_nic(sp);
7077 if (ret != 0) {
7078 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
7079 dev->name);
7080 if (ret != -EIO)
7081 s2io_reset(sp);
7082 return ret;
7083 }
7084
7085 /*
7086 * Initializing the Rx buffers. For now we are considering only 1
7087 * Rx ring and initializing buffers into 30 Rx blocks
7088 */
7089 mac_control = &sp->mac_control;
7090 config = &sp->config;
7091
7092 for (i = 0; i < config->rx_ring_num; i++) {
7093 if ((ret = fill_rx_buffers(sp, i))) {
7094 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
7095 dev->name);
7096 s2io_reset(sp);
7097 free_rx_buffers(sp);
7098 return -ENOMEM;
7099 }
7100 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
7101 atomic_read(&sp->rx_bufs_left[i]));
7102 }
7103
7104 /* Initialise napi */
7105 if (config->napi)
7106 napi_enable(&sp->napi);
7107
7108 /* Maintain the state prior to the open */
7109 if (sp->promisc_flg)
7110 sp->promisc_flg = 0;
7111 if (sp->m_cast_flg) {
7112 sp->m_cast_flg = 0;
7113 sp->all_multi_pos= 0;
7114 }
7115
7116 /* Setting its receive mode */
7117 s2io_set_multicast(dev);
7118
7119 if (sp->lro) {
7120 /* Initialize max aggregatable pkts per session based on MTU */
7121 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
7122 /* Check if we can use(if specified) user provided value */
7123 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
7124 sp->lro_max_aggr_per_sess = lro_max_pkts;
7125 }
7126
7127 /* Enable Rx Traffic and interrupts on the NIC */
7128 if (start_nic(sp)) {
7129 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
7130 s2io_reset(sp);
7131 free_rx_buffers(sp);
7132 return -ENODEV;
7133 }
7134
7135 /* Add interrupt service routine */
7136 if (s2io_add_isr(sp) != 0) {
7137 if (sp->config.intr_type == MSI_X)
7138 s2io_rem_isr(sp);
7139 s2io_reset(sp);
7140 free_rx_buffers(sp);
7141 return -ENODEV;
7142 }
7143
7144 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
7145
7146 /* Enable tasklet for the device */
7147 tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev);
7148
7149 /* Enable select interrupts */
7150 en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
7151 if (sp->config.intr_type != INTA)
7152 en_dis_able_nic_intrs(sp, ENA_ALL_INTRS, DISABLE_INTRS);
7153 else {
7154 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
7155 interruptible |= TX_PIC_INTR;
7156 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7157 }
7158
7159 set_bit(__S2IO_STATE_CARD_UP, &sp->state);
7160 return 0;
7161 }
7162
7163 /**
7164 * s2io_restart_nic - Resets the NIC.
7165 * @data : long pointer to the device private structure
7166 * Description:
7167 * This function is scheduled to be run by the s2io_tx_watchdog
7168 * function after 0.5 secs to reset the NIC. The idea is to reduce
7169 * the run time of the watch dog routine which is run holding a
7170 * spin lock.
7171 */
7172
7173 static void s2io_restart_nic(struct work_struct *work)
7174 {
7175 struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
7176 struct net_device *dev = sp->dev;
7177
7178 rtnl_lock();
7179
7180 if (!netif_running(dev))
7181 goto out_unlock;
7182
7183 s2io_card_down(sp);
7184 if (s2io_card_up(sp)) {
7185 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
7186 dev->name);
7187 }
7188 netif_wake_queue(dev);
7189 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
7190 dev->name);
7191 out_unlock:
7192 rtnl_unlock();
7193 }
7194
7195 /**
7196 * s2io_tx_watchdog - Watchdog for transmit side.
7197 * @dev : Pointer to net device structure
7198 * Description:
7199 * This function is triggered if the Tx Queue is stopped
7200 * for a pre-defined amount of time when the Interface is still up.
7201 * If the Interface is jammed in such a situation, the hardware is
7202 * reset (by s2io_close) and restarted again (by s2io_open) to
7203 * overcome any problem that might have been caused in the hardware.
7204 * Return value:
7205 * void
7206 */
7207
7208 static void s2io_tx_watchdog(struct net_device *dev)
7209 {
7210 struct s2io_nic *sp = dev->priv;
7211
7212 if (netif_carrier_ok(dev)) {
7213 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt++;
7214 schedule_work(&sp->rst_timer_task);
7215 sp->mac_control.stats_info->sw_stat.soft_reset_cnt++;
7216 }
7217 }
7218
7219 /**
7220 * rx_osm_handler - To perform some OS related operations on SKB.
7221 * @sp: private member of the device structure,pointer to s2io_nic structure.
7222 * @skb : the socket buffer pointer.
7223 * @len : length of the packet
7224 * @cksum : FCS checksum of the frame.
7225 * @ring_no : the ring from which this RxD was extracted.
7226 * Description:
7227 * This function is called by the Rx interrupt serivce routine to perform
7228 * some OS related operations on the SKB before passing it to the upper
7229 * layers. It mainly checks if the checksum is OK, if so adds it to the
7230 * SKBs cksum variable, increments the Rx packet count and passes the SKB
7231 * to the upper layer. If the checksum is wrong, it increments the Rx
7232 * packet error count, frees the SKB and returns error.
7233 * Return value:
7234 * SUCCESS on success and -1 on failure.
7235 */
7236 static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
7237 {
7238 struct s2io_nic *sp = ring_data->nic;
7239 struct net_device *dev = (struct net_device *) sp->dev;
7240 struct sk_buff *skb = (struct sk_buff *)
7241 ((unsigned long) rxdp->Host_Control);
7242 int ring_no = ring_data->ring_no;
7243 u16 l3_csum, l4_csum;
7244 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
7245 struct lro *lro;
7246 u8 err_mask;
7247
7248 skb->dev = dev;
7249
7250 if (err) {
7251 /* Check for parity error */
7252 if (err & 0x1) {
7253 sp->mac_control.stats_info->sw_stat.parity_err_cnt++;
7254 }
7255 err_mask = err >> 48;
7256 switch(err_mask) {
7257 case 1:
7258 sp->mac_control.stats_info->sw_stat.
7259 rx_parity_err_cnt++;
7260 break;
7261
7262 case 2:
7263 sp->mac_control.stats_info->sw_stat.
7264 rx_abort_cnt++;
7265 break;
7266
7267 case 3:
7268 sp->mac_control.stats_info->sw_stat.
7269 rx_parity_abort_cnt++;
7270 break;
7271
7272 case 4:
7273 sp->mac_control.stats_info->sw_stat.
7274 rx_rda_fail_cnt++;
7275 break;
7276
7277 case 5:
7278 sp->mac_control.stats_info->sw_stat.
7279 rx_unkn_prot_cnt++;
7280 break;
7281
7282 case 6:
7283 sp->mac_control.stats_info->sw_stat.
7284 rx_fcs_err_cnt++;
7285 break;
7286
7287 case 7:
7288 sp->mac_control.stats_info->sw_stat.
7289 rx_buf_size_err_cnt++;
7290 break;
7291
7292 case 8:
7293 sp->mac_control.stats_info->sw_stat.
7294 rx_rxd_corrupt_cnt++;
7295 break;
7296
7297 case 15:
7298 sp->mac_control.stats_info->sw_stat.
7299 rx_unkn_err_cnt++;
7300 break;
7301 }
7302 /*
7303 * Drop the packet if bad transfer code. Exception being
7304 * 0x5, which could be due to unsupported IPv6 extension header.
7305 * In this case, we let stack handle the packet.
7306 * Note that in this case, since checksum will be incorrect,
7307 * stack will validate the same.
7308 */
7309 if (err_mask != 0x5) {
7310 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
7311 dev->name, err_mask);
7312 sp->stats.rx_crc_errors++;
7313 sp->mac_control.stats_info->sw_stat.mem_freed
7314 += skb->truesize;
7315 dev_kfree_skb(skb);
7316 atomic_dec(&sp->rx_bufs_left[ring_no]);
7317 rxdp->Host_Control = 0;
7318 return 0;
7319 }
7320 }
7321
7322 /* Updating statistics */
7323 sp->stats.rx_packets++;
7324 rxdp->Host_Control = 0;
7325 if (sp->rxd_mode == RXD_MODE_1) {
7326 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
7327
7328 sp->stats.rx_bytes += len;
7329 skb_put(skb, len);
7330
7331 } else if (sp->rxd_mode == RXD_MODE_3B) {
7332 int get_block = ring_data->rx_curr_get_info.block_index;
7333 int get_off = ring_data->rx_curr_get_info.offset;
7334 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
7335 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
7336 unsigned char *buff = skb_push(skb, buf0_len);
7337
7338 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
7339 sp->stats.rx_bytes += buf0_len + buf2_len;
7340 memcpy(buff, ba->ba_0, buf0_len);
7341 skb_put(skb, buf2_len);
7342 }
7343
7344 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && ((!sp->lro) ||
7345 (sp->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
7346 (sp->rx_csum)) {
7347 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
7348 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
7349 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
7350 /*
7351 * NIC verifies if the Checksum of the received
7352 * frame is Ok or not and accordingly returns
7353 * a flag in the RxD.
7354 */
7355 skb->ip_summed = CHECKSUM_UNNECESSARY;
7356 if (sp->lro) {
7357 u32 tcp_len;
7358 u8 *tcp;
7359 int ret = 0;
7360
7361 ret = s2io_club_tcp_session(skb->data, &tcp,
7362 &tcp_len, &lro,
7363 rxdp, sp);
7364 switch (ret) {
7365 case 3: /* Begin anew */
7366 lro->parent = skb;
7367 goto aggregate;
7368 case 1: /* Aggregate */
7369 {
7370 lro_append_pkt(sp, lro,
7371 skb, tcp_len);
7372 goto aggregate;
7373 }
7374 case 4: /* Flush session */
7375 {
7376 lro_append_pkt(sp, lro,
7377 skb, tcp_len);
7378 queue_rx_frame(lro->parent);
7379 clear_lro_session(lro);
7380 sp->mac_control.stats_info->
7381 sw_stat.flush_max_pkts++;
7382 goto aggregate;
7383 }
7384 case 2: /* Flush both */
7385 lro->parent->data_len =
7386 lro->frags_len;
7387 sp->mac_control.stats_info->
7388 sw_stat.sending_both++;
7389 queue_rx_frame(lro->parent);
7390 clear_lro_session(lro);
7391 goto send_up;
7392 case 0: /* sessions exceeded */
7393 case -1: /* non-TCP or not
7394 * L2 aggregatable
7395 */
7396 case 5: /*
7397 * First pkt in session not
7398 * L3/L4 aggregatable
7399 */
7400 break;
7401 default:
7402 DBG_PRINT(ERR_DBG,
7403 "%s: Samadhana!!\n",
7404 __FUNCTION__);
7405 BUG();
7406 }
7407 }
7408 } else {
7409 /*
7410 * Packet with erroneous checksum, let the
7411 * upper layers deal with it.
7412 */
7413 skb->ip_summed = CHECKSUM_NONE;
7414 }
7415 } else {
7416 skb->ip_summed = CHECKSUM_NONE;
7417 }
7418 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
7419 if (!sp->lro) {
7420 skb->protocol = eth_type_trans(skb, dev);
7421 if ((sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2) &&
7422 vlan_strip_flag)) {
7423 /* Queueing the vlan frame to the upper layer */
7424 if (napi)
7425 vlan_hwaccel_receive_skb(skb, sp->vlgrp,
7426 RXD_GET_VLAN_TAG(rxdp->Control_2));
7427 else
7428 vlan_hwaccel_rx(skb, sp->vlgrp,
7429 RXD_GET_VLAN_TAG(rxdp->Control_2));
7430 } else {
7431 if (napi)
7432 netif_receive_skb(skb);
7433 else
7434 netif_rx(skb);
7435 }
7436 } else {
7437 send_up:
7438 queue_rx_frame(skb);
7439 }
7440 dev->last_rx = jiffies;
7441 aggregate:
7442 atomic_dec(&sp->rx_bufs_left[ring_no]);
7443 return SUCCESS;
7444 }
7445
7446 /**
7447 * s2io_link - stops/starts the Tx queue.
7448 * @sp : private member of the device structure, which is a pointer to the
7449 * s2io_nic structure.
7450 * @link : inidicates whether link is UP/DOWN.
7451 * Description:
7452 * This function stops/starts the Tx queue depending on whether the link
7453 * status of the NIC is is down or up. This is called by the Alarm
7454 * interrupt handler whenever a link change interrupt comes up.
7455 * Return value:
7456 * void.
7457 */
7458
7459 static void s2io_link(struct s2io_nic * sp, int link)
7460 {
7461 struct net_device *dev = (struct net_device *) sp->dev;
7462
7463 if (link != sp->last_link_state) {
7464 init_tti(sp, link);
7465 if (link == LINK_DOWN) {
7466 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
7467 netif_carrier_off(dev);
7468 if(sp->mac_control.stats_info->sw_stat.link_up_cnt)
7469 sp->mac_control.stats_info->sw_stat.link_up_time =
7470 jiffies - sp->start_time;
7471 sp->mac_control.stats_info->sw_stat.link_down_cnt++;
7472 } else {
7473 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
7474 if (sp->mac_control.stats_info->sw_stat.link_down_cnt)
7475 sp->mac_control.stats_info->sw_stat.link_down_time =
7476 jiffies - sp->start_time;
7477 sp->mac_control.stats_info->sw_stat.link_up_cnt++;
7478 netif_carrier_on(dev);
7479 }
7480 }
7481 sp->last_link_state = link;
7482 sp->start_time = jiffies;
7483 }
7484
7485 /**
7486 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7487 * @sp : private member of the device structure, which is a pointer to the
7488 * s2io_nic structure.
7489 * Description:
7490 * This function initializes a few of the PCI and PCI-X configuration registers
7491 * with recommended values.
7492 * Return value:
7493 * void
7494 */
7495
7496 static void s2io_init_pci(struct s2io_nic * sp)
7497 {
7498 u16 pci_cmd = 0, pcix_cmd = 0;
7499
7500 /* Enable Data Parity Error Recovery in PCI-X command register. */
7501 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7502 &(pcix_cmd));
7503 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7504 (pcix_cmd | 1));
7505 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7506 &(pcix_cmd));
7507
7508 /* Set the PErr Response bit in PCI command register. */
7509 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7510 pci_write_config_word(sp->pdev, PCI_COMMAND,
7511 (pci_cmd | PCI_COMMAND_PARITY));
7512 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7513 }
7514
7515 static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type)
7516 {
7517 if ((tx_fifo_num > MAX_TX_FIFOS) ||
7518 (tx_fifo_num < FIFO_DEFAULT_NUM)) {
7519 DBG_PRINT(ERR_DBG, "s2io: Requested number of tx fifos "
7520 "(%d) not supported\n", tx_fifo_num);
7521 tx_fifo_num =
7522 ((tx_fifo_num > MAX_TX_FIFOS)? MAX_TX_FIFOS :
7523 ((tx_fifo_num < FIFO_DEFAULT_NUM) ? FIFO_DEFAULT_NUM :
7524 tx_fifo_num));
7525 DBG_PRINT(ERR_DBG, "s2io: Default to %d ", tx_fifo_num);
7526 DBG_PRINT(ERR_DBG, "tx fifos\n");
7527 }
7528
7529 if ( rx_ring_num > 8) {
7530 DBG_PRINT(ERR_DBG, "s2io: Requested number of Rx rings not "
7531 "supported\n");
7532 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Rx rings\n");
7533 rx_ring_num = 8;
7534 }
7535 if (*dev_intr_type != INTA)
7536 napi = 0;
7537
7538 if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
7539 DBG_PRINT(ERR_DBG, "s2io: Wrong intr_type requested. "
7540 "Defaulting to INTA\n");
7541 *dev_intr_type = INTA;
7542 }
7543
7544 if ((*dev_intr_type == MSI_X) &&
7545 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7546 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
7547 DBG_PRINT(ERR_DBG, "s2io: Xframe I does not support MSI_X. "
7548 "Defaulting to INTA\n");
7549 *dev_intr_type = INTA;
7550 }
7551
7552 if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
7553 DBG_PRINT(ERR_DBG, "s2io: Requested ring mode not supported\n");
7554 DBG_PRINT(ERR_DBG, "s2io: Defaulting to 1-buffer mode\n");
7555 rx_ring_mode = 1;
7556 }
7557 return SUCCESS;
7558 }
7559
7560 /**
7561 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7562 * or Traffic class respectively.
7563 * @nic: device private variable
7564 * Description: The function configures the receive steering to
7565 * desired receive ring.
7566 * Return Value: SUCCESS on success and
7567 * '-1' on failure (endian settings incorrect).
7568 */
7569 static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7570 {
7571 struct XENA_dev_config __iomem *bar0 = nic->bar0;
7572 register u64 val64 = 0;
7573
7574 if (ds_codepoint > 63)
7575 return FAILURE;
7576
7577 val64 = RTS_DS_MEM_DATA(ring);
7578 writeq(val64, &bar0->rts_ds_mem_data);
7579
7580 val64 = RTS_DS_MEM_CTRL_WE |
7581 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7582 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7583
7584 writeq(val64, &bar0->rts_ds_mem_ctrl);
7585
7586 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
7587 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7588 S2IO_BIT_RESET);
7589 }
7590
7591 /**
7592 * s2io_init_nic - Initialization of the adapter .
7593 * @pdev : structure containing the PCI related information of the device.
7594 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7595 * Description:
7596 * The function initializes an adapter identified by the pci_dec structure.
7597 * All OS related initialization including memory and device structure and
7598 * initlaization of the device private variable is done. Also the swapper
7599 * control register is initialized to enable read and write into the I/O
7600 * registers of the device.
7601 * Return value:
7602 * returns 0 on success and negative on failure.
7603 */
7604
7605 static int __devinit
7606 s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7607 {
7608 struct s2io_nic *sp;
7609 struct net_device *dev;
7610 int i, j, ret;
7611 int dma_flag = FALSE;
7612 u32 mac_up, mac_down;
7613 u64 val64 = 0, tmp64 = 0;
7614 struct XENA_dev_config __iomem *bar0 = NULL;
7615 u16 subid;
7616 struct mac_info *mac_control;
7617 struct config_param *config;
7618 int mode;
7619 u8 dev_intr_type = intr_type;
7620 DECLARE_MAC_BUF(mac);
7621
7622 if ((ret = s2io_verify_parm(pdev, &dev_intr_type)))
7623 return ret;
7624
7625 if ((ret = pci_enable_device(pdev))) {
7626 DBG_PRINT(ERR_DBG,
7627 "s2io_init_nic: pci_enable_device failed\n");
7628 return ret;
7629 }
7630
7631 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
7632 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
7633 dma_flag = TRUE;
7634 if (pci_set_consistent_dma_mask
7635 (pdev, DMA_64BIT_MASK)) {
7636 DBG_PRINT(ERR_DBG,
7637 "Unable to obtain 64bit DMA for \
7638 consistent allocations\n");
7639 pci_disable_device(pdev);
7640 return -ENOMEM;
7641 }
7642 } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
7643 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
7644 } else {
7645 pci_disable_device(pdev);
7646 return -ENOMEM;
7647 }
7648 if ((ret = pci_request_regions(pdev, s2io_driver_name))) {
7649 DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x \n", __FUNCTION__, ret);
7650 pci_disable_device(pdev);
7651 return -ENODEV;
7652 }
7653
7654 dev = alloc_etherdev(sizeof(struct s2io_nic));
7655 if (dev == NULL) {
7656 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7657 pci_disable_device(pdev);
7658 pci_release_regions(pdev);
7659 return -ENODEV;
7660 }
7661
7662 pci_set_master(pdev);
7663 pci_set_drvdata(pdev, dev);
7664 SET_NETDEV_DEV(dev, &pdev->dev);
7665
7666 /* Private member variable initialized to s2io NIC structure */
7667 sp = dev->priv;
7668 memset(sp, 0, sizeof(struct s2io_nic));
7669 sp->dev = dev;
7670 sp->pdev = pdev;
7671 sp->high_dma_flag = dma_flag;
7672 sp->device_enabled_once = FALSE;
7673 if (rx_ring_mode == 1)
7674 sp->rxd_mode = RXD_MODE_1;
7675 if (rx_ring_mode == 2)
7676 sp->rxd_mode = RXD_MODE_3B;
7677
7678 sp->config.intr_type = dev_intr_type;
7679
7680 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
7681 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
7682 sp->device_type = XFRAME_II_DEVICE;
7683 else
7684 sp->device_type = XFRAME_I_DEVICE;
7685
7686 sp->lro = lro_enable;
7687
7688 /* Initialize some PCI/PCI-X fields of the NIC. */
7689 s2io_init_pci(sp);
7690
7691 /*
7692 * Setting the device configuration parameters.
7693 * Most of these parameters can be specified by the user during
7694 * module insertion as they are module loadable parameters. If
7695 * these parameters are not not specified during load time, they
7696 * are initialized with default values.
7697 */
7698 mac_control = &sp->mac_control;
7699 config = &sp->config;
7700
7701 config->napi = napi;
7702
7703 /* Tx side parameters. */
7704 config->tx_fifo_num = tx_fifo_num;
7705 for (i = 0; i < MAX_TX_FIFOS; i++) {
7706 config->tx_cfg[i].fifo_len = tx_fifo_len[i];
7707 config->tx_cfg[i].fifo_priority = i;
7708 }
7709
7710 /* mapping the QoS priority to the configured fifos */
7711 for (i = 0; i < MAX_TX_FIFOS; i++)
7712 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num][i];
7713
7714 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7715 for (i = 0; i < config->tx_fifo_num; i++) {
7716 config->tx_cfg[i].f_no_snoop =
7717 (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7718 if (config->tx_cfg[i].fifo_len < 65) {
7719 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7720 break;
7721 }
7722 }
7723 /* + 2 because one Txd for skb->data and one Txd for UFO */
7724 config->max_txds = MAX_SKB_FRAGS + 2;
7725
7726 /* Rx side parameters. */
7727 config->rx_ring_num = rx_ring_num;
7728 for (i = 0; i < MAX_RX_RINGS; i++) {
7729 config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
7730 (rxd_count[sp->rxd_mode] + 1);
7731 config->rx_cfg[i].ring_priority = i;
7732 }
7733
7734 for (i = 0; i < rx_ring_num; i++) {
7735 config->rx_cfg[i].ring_org = RING_ORG_BUFF1;
7736 config->rx_cfg[i].f_no_snoop =
7737 (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
7738 }
7739
7740 /* Setting Mac Control parameters */
7741 mac_control->rmac_pause_time = rmac_pause_time;
7742 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7743 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7744
7745
7746 /* Initialize Ring buffer parameters. */
7747 for (i = 0; i < config->rx_ring_num; i++)
7748 atomic_set(&sp->rx_bufs_left[i], 0);
7749
7750 /* initialize the shared memory used by the NIC and the host */
7751 if (init_shared_mem(sp)) {
7752 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
7753 dev->name);
7754 ret = -ENOMEM;
7755 goto mem_alloc_failed;
7756 }
7757
7758 sp->bar0 = ioremap(pci_resource_start(pdev, 0),
7759 pci_resource_len(pdev, 0));
7760 if (!sp->bar0) {
7761 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
7762 dev->name);
7763 ret = -ENOMEM;
7764 goto bar0_remap_failed;
7765 }
7766
7767 sp->bar1 = ioremap(pci_resource_start(pdev, 2),
7768 pci_resource_len(pdev, 2));
7769 if (!sp->bar1) {
7770 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
7771 dev->name);
7772 ret = -ENOMEM;
7773 goto bar1_remap_failed;
7774 }
7775
7776 dev->irq = pdev->irq;
7777 dev->base_addr = (unsigned long) sp->bar0;
7778
7779 /* Initializing the BAR1 address as the start of the FIFO pointer. */
7780 for (j = 0; j < MAX_TX_FIFOS; j++) {
7781 mac_control->tx_FIFO_start[j] = (struct TxFIFO_element __iomem *)
7782 (sp->bar1 + (j * 0x00020000));
7783 }
7784
7785 /* Driver entry points */
7786 dev->open = &s2io_open;
7787 dev->stop = &s2io_close;
7788 dev->hard_start_xmit = &s2io_xmit;
7789 dev->get_stats = &s2io_get_stats;
7790 dev->set_multicast_list = &s2io_set_multicast;
7791 dev->do_ioctl = &s2io_ioctl;
7792 dev->set_mac_address = &s2io_set_mac_addr;
7793 dev->change_mtu = &s2io_change_mtu;
7794 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
7795 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7796 dev->vlan_rx_register = s2io_vlan_rx_register;
7797
7798 /*
7799 * will use eth_mac_addr() for dev->set_mac_address
7800 * mac address will be set every time dev->open() is called
7801 */
7802 netif_napi_add(dev, &sp->napi, s2io_poll, 32);
7803
7804 #ifdef CONFIG_NET_POLL_CONTROLLER
7805 dev->poll_controller = s2io_netpoll;
7806 #endif
7807
7808 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
7809 if (sp->high_dma_flag == TRUE)
7810 dev->features |= NETIF_F_HIGHDMA;
7811 dev->features |= NETIF_F_TSO;
7812 dev->features |= NETIF_F_TSO6;
7813 if ((sp->device_type & XFRAME_II_DEVICE) && (ufo)) {
7814 dev->features |= NETIF_F_UFO;
7815 dev->features |= NETIF_F_HW_CSUM;
7816 }
7817
7818 dev->tx_timeout = &s2io_tx_watchdog;
7819 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
7820 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
7821 INIT_WORK(&sp->set_link_task, s2io_set_link);
7822
7823 pci_save_state(sp->pdev);
7824
7825 /* Setting swapper control on the NIC, for proper reset operation */
7826 if (s2io_set_swapper(sp)) {
7827 DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
7828 dev->name);
7829 ret = -EAGAIN;
7830 goto set_swap_failed;
7831 }
7832
7833 /* Verify if the Herc works on the slot its placed into */
7834 if (sp->device_type & XFRAME_II_DEVICE) {
7835 mode = s2io_verify_pci_mode(sp);
7836 if (mode < 0) {
7837 DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__);
7838 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
7839 ret = -EBADSLT;
7840 goto set_swap_failed;
7841 }
7842 }
7843
7844 /* Not needed for Herc */
7845 if (sp->device_type & XFRAME_I_DEVICE) {
7846 /*
7847 * Fix for all "FFs" MAC address problems observed on
7848 * Alpha platforms
7849 */
7850 fix_mac_address(sp);
7851 s2io_reset(sp);
7852 }
7853
7854 /*
7855 * MAC address initialization.
7856 * For now only one mac address will be read and used.
7857 */
7858 bar0 = sp->bar0;
7859 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
7860 RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET);
7861 writeq(val64, &bar0->rmac_addr_cmd_mem);
7862 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
7863 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, S2IO_BIT_RESET);
7864 tmp64 = readq(&bar0->rmac_addr_data0_mem);
7865 mac_down = (u32) tmp64;
7866 mac_up = (u32) (tmp64 >> 32);
7867
7868 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
7869 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
7870 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
7871 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
7872 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
7873 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
7874
7875 /* Set the factory defined MAC address initially */
7876 dev->addr_len = ETH_ALEN;
7877 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
7878 memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN);
7879
7880 /* initialize number of multicast & unicast MAC entries variables */
7881 if (sp->device_type == XFRAME_I_DEVICE) {
7882 config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES;
7883 config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES;
7884 config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET;
7885 } else if (sp->device_type == XFRAME_II_DEVICE) {
7886 config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES;
7887 config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES;
7888 config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET;
7889 }
7890
7891 /* store mac addresses from CAM to s2io_nic structure */
7892 do_s2io_store_unicast_mc(sp);
7893
7894 /* Store the values of the MSIX table in the s2io_nic structure */
7895 store_xmsi_data(sp);
7896 /* reset Nic and bring it to known state */
7897 s2io_reset(sp);
7898
7899 /*
7900 * Initialize the tasklet status and link state flags
7901 * and the card state parameter
7902 */
7903 sp->tasklet_status = 0;
7904 sp->state = 0;
7905
7906 /* Initialize spinlocks */
7907 for (i = 0; i < sp->config.tx_fifo_num; i++)
7908 spin_lock_init(&mac_control->fifos[i].tx_lock);
7909
7910 if (!napi)
7911 spin_lock_init(&sp->put_lock);
7912 spin_lock_init(&sp->rx_lock);
7913
7914 /*
7915 * SXE-002: Configure link and activity LED to init state
7916 * on driver load.
7917 */
7918 subid = sp->pdev->subsystem_device;
7919 if ((subid & 0xFF) >= 0x07) {
7920 val64 = readq(&bar0->gpio_control);
7921 val64 |= 0x0000800000000000ULL;
7922 writeq(val64, &bar0->gpio_control);
7923 val64 = 0x0411040400000000ULL;
7924 writeq(val64, (void __iomem *) bar0 + 0x2700);
7925 val64 = readq(&bar0->gpio_control);
7926 }
7927
7928 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
7929
7930 if (register_netdev(dev)) {
7931 DBG_PRINT(ERR_DBG, "Device registration failed\n");
7932 ret = -ENODEV;
7933 goto register_failed;
7934 }
7935 s2io_vpd_read(sp);
7936 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2007 Neterion Inc.\n");
7937 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n",dev->name,
7938 sp->product_name, pdev->revision);
7939 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
7940 s2io_driver_version);
7941 DBG_PRINT(ERR_DBG, "%s: MAC ADDR: %s\n",
7942 dev->name, print_mac(mac, dev->dev_addr));
7943 DBG_PRINT(ERR_DBG, "SERIAL NUMBER: %s\n", sp->serial_num);
7944 if (sp->device_type & XFRAME_II_DEVICE) {
7945 mode = s2io_print_pci_mode(sp);
7946 if (mode < 0) {
7947 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
7948 ret = -EBADSLT;
7949 unregister_netdev(dev);
7950 goto set_swap_failed;
7951 }
7952 }
7953 switch(sp->rxd_mode) {
7954 case RXD_MODE_1:
7955 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
7956 dev->name);
7957 break;
7958 case RXD_MODE_3B:
7959 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
7960 dev->name);
7961 break;
7962 }
7963
7964 if (napi)
7965 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
7966 switch(sp->config.intr_type) {
7967 case INTA:
7968 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
7969 break;
7970 case MSI_X:
7971 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
7972 break;
7973 }
7974 if (sp->lro)
7975 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
7976 dev->name);
7977 if (ufo)
7978 DBG_PRINT(ERR_DBG, "%s: UDP Fragmentation Offload(UFO)"
7979 " enabled\n", dev->name);
7980 /* Initialize device name */
7981 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
7982
7983 /*
7984 * Make Link state as off at this point, when the Link change
7985 * interrupt comes the state will be automatically changed to
7986 * the right state.
7987 */
7988 netif_carrier_off(dev);
7989
7990 return 0;
7991
7992 register_failed:
7993 set_swap_failed:
7994 iounmap(sp->bar1);
7995 bar1_remap_failed:
7996 iounmap(sp->bar0);
7997 bar0_remap_failed:
7998 mem_alloc_failed:
7999 free_shared_mem(sp);
8000 pci_disable_device(pdev);
8001 pci_release_regions(pdev);
8002 pci_set_drvdata(pdev, NULL);
8003 free_netdev(dev);
8004
8005 return ret;
8006 }
8007
8008 /**
8009 * s2io_rem_nic - Free the PCI device
8010 * @pdev: structure containing the PCI related information of the device.
8011 * Description: This function is called by the Pci subsystem to release a
8012 * PCI device and free up all resource held up by the device. This could
8013 * be in response to a Hot plug event or when the driver is to be removed
8014 * from memory.
8015 */
8016
8017 static void __devexit s2io_rem_nic(struct pci_dev *pdev)
8018 {
8019 struct net_device *dev =
8020 (struct net_device *) pci_get_drvdata(pdev);
8021 struct s2io_nic *sp;
8022
8023 if (dev == NULL) {
8024 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
8025 return;
8026 }
8027
8028 flush_scheduled_work();
8029
8030 sp = dev->priv;
8031 unregister_netdev(dev);
8032
8033 free_shared_mem(sp);
8034 iounmap(sp->bar0);
8035 iounmap(sp->bar1);
8036 pci_release_regions(pdev);
8037 pci_set_drvdata(pdev, NULL);
8038 free_netdev(dev);
8039 pci_disable_device(pdev);
8040 }
8041
8042 /**
8043 * s2io_starter - Entry point for the driver
8044 * Description: This function is the entry point for the driver. It verifies
8045 * the module loadable parameters and initializes PCI configuration space.
8046 */
8047
8048 static int __init s2io_starter(void)
8049 {
8050 return pci_register_driver(&s2io_driver);
8051 }
8052
8053 /**
8054 * s2io_closer - Cleanup routine for the driver
8055 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
8056 */
8057
8058 static __exit void s2io_closer(void)
8059 {
8060 pci_unregister_driver(&s2io_driver);
8061 DBG_PRINT(INIT_DBG, "cleanup done\n");
8062 }
8063
8064 module_init(s2io_starter);
8065 module_exit(s2io_closer);
8066
8067 static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
8068 struct tcphdr **tcp, struct RxD_t *rxdp)
8069 {
8070 int ip_off;
8071 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
8072
8073 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
8074 DBG_PRINT(INIT_DBG,"%s: Non-TCP frames not supported for LRO\n",
8075 __FUNCTION__);
8076 return -1;
8077 }
8078
8079 /* TODO:
8080 * By default the VLAN field in the MAC is stripped by the card, if this
8081 * feature is turned off in rx_pa_cfg register, then the ip_off field
8082 * has to be shifted by a further 2 bytes
8083 */
8084 switch (l2_type) {
8085 case 0: /* DIX type */
8086 case 4: /* DIX type with VLAN */
8087 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
8088 break;
8089 /* LLC, SNAP etc are considered non-mergeable */
8090 default:
8091 return -1;
8092 }
8093
8094 *ip = (struct iphdr *)((u8 *)buffer + ip_off);
8095 ip_len = (u8)((*ip)->ihl);
8096 ip_len <<= 2;
8097 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
8098
8099 return 0;
8100 }
8101
8102 static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
8103 struct tcphdr *tcp)
8104 {
8105 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8106 if ((lro->iph->saddr != ip->saddr) || (lro->iph->daddr != ip->daddr) ||
8107 (lro->tcph->source != tcp->source) || (lro->tcph->dest != tcp->dest))
8108 return -1;
8109 return 0;
8110 }
8111
8112 static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
8113 {
8114 return(ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2));
8115 }
8116
8117 static void initiate_new_session(struct lro *lro, u8 *l2h,
8118 struct iphdr *ip, struct tcphdr *tcp, u32 tcp_pyld_len)
8119 {
8120 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8121 lro->l2h = l2h;
8122 lro->iph = ip;
8123 lro->tcph = tcp;
8124 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
8125 lro->tcp_ack = tcp->ack_seq;
8126 lro->sg_num = 1;
8127 lro->total_len = ntohs(ip->tot_len);
8128 lro->frags_len = 0;
8129 /*
8130 * check if we saw TCP timestamp. Other consistency checks have
8131 * already been done.
8132 */
8133 if (tcp->doff == 8) {
8134 __be32 *ptr;
8135 ptr = (__be32 *)(tcp+1);
8136 lro->saw_ts = 1;
8137 lro->cur_tsval = ntohl(*(ptr+1));
8138 lro->cur_tsecr = *(ptr+2);
8139 }
8140 lro->in_use = 1;
8141 }
8142
8143 static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
8144 {
8145 struct iphdr *ip = lro->iph;
8146 struct tcphdr *tcp = lro->tcph;
8147 __sum16 nchk;
8148 struct stat_block *statinfo = sp->mac_control.stats_info;
8149 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8150
8151 /* Update L3 header */
8152 ip->tot_len = htons(lro->total_len);
8153 ip->check = 0;
8154 nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
8155 ip->check = nchk;
8156
8157 /* Update L4 header */
8158 tcp->ack_seq = lro->tcp_ack;
8159 tcp->window = lro->window;
8160
8161 /* Update tsecr field if this session has timestamps enabled */
8162 if (lro->saw_ts) {
8163 __be32 *ptr = (__be32 *)(tcp + 1);
8164 *(ptr+2) = lro->cur_tsecr;
8165 }
8166
8167 /* Update counters required for calculation of
8168 * average no. of packets aggregated.
8169 */
8170 statinfo->sw_stat.sum_avg_pkts_aggregated += lro->sg_num;
8171 statinfo->sw_stat.num_aggregations++;
8172 }
8173
8174 static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
8175 struct tcphdr *tcp, u32 l4_pyld)
8176 {
8177 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8178 lro->total_len += l4_pyld;
8179 lro->frags_len += l4_pyld;
8180 lro->tcp_next_seq += l4_pyld;
8181 lro->sg_num++;
8182
8183 /* Update ack seq no. and window ad(from this pkt) in LRO object */
8184 lro->tcp_ack = tcp->ack_seq;
8185 lro->window = tcp->window;
8186
8187 if (lro->saw_ts) {
8188 __be32 *ptr;
8189 /* Update tsecr and tsval from this packet */
8190 ptr = (__be32 *)(tcp+1);
8191 lro->cur_tsval = ntohl(*(ptr+1));
8192 lro->cur_tsecr = *(ptr + 2);
8193 }
8194 }
8195
8196 static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
8197 struct tcphdr *tcp, u32 tcp_pyld_len)
8198 {
8199 u8 *ptr;
8200
8201 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8202
8203 if (!tcp_pyld_len) {
8204 /* Runt frame or a pure ack */
8205 return -1;
8206 }
8207
8208 if (ip->ihl != 5) /* IP has options */
8209 return -1;
8210
8211 /* If we see CE codepoint in IP header, packet is not mergeable */
8212 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
8213 return -1;
8214
8215 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
8216 if (tcp->urg || tcp->psh || tcp->rst || tcp->syn || tcp->fin ||
8217 tcp->ece || tcp->cwr || !tcp->ack) {
8218 /*
8219 * Currently recognize only the ack control word and
8220 * any other control field being set would result in
8221 * flushing the LRO session
8222 */
8223 return -1;
8224 }
8225
8226 /*
8227 * Allow only one TCP timestamp option. Don't aggregate if
8228 * any other options are detected.
8229 */
8230 if (tcp->doff != 5 && tcp->doff != 8)
8231 return -1;
8232
8233 if (tcp->doff == 8) {
8234 ptr = (u8 *)(tcp + 1);
8235 while (*ptr == TCPOPT_NOP)
8236 ptr++;
8237 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
8238 return -1;
8239
8240 /* Ensure timestamp value increases monotonically */
8241 if (l_lro)
8242 if (l_lro->cur_tsval > ntohl(*((__be32 *)(ptr+2))))
8243 return -1;
8244
8245 /* timestamp echo reply should be non-zero */
8246 if (*((__be32 *)(ptr+6)) == 0)
8247 return -1;
8248 }
8249
8250 return 0;
8251 }
8252
8253 static int
8254 s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, struct lro **lro,
8255 struct RxD_t *rxdp, struct s2io_nic *sp)
8256 {
8257 struct iphdr *ip;
8258 struct tcphdr *tcph;
8259 int ret = 0, i;
8260
8261 if (!(ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
8262 rxdp))) {
8263 DBG_PRINT(INFO_DBG,"IP Saddr: %x Daddr: %x\n",
8264 ip->saddr, ip->daddr);
8265 } else {
8266 return ret;
8267 }
8268
8269 tcph = (struct tcphdr *)*tcp;
8270 *tcp_len = get_l4_pyld_length(ip, tcph);
8271 for (i=0; i<MAX_LRO_SESSIONS; i++) {
8272 struct lro *l_lro = &sp->lro0_n[i];
8273 if (l_lro->in_use) {
8274 if (check_for_socket_match(l_lro, ip, tcph))
8275 continue;
8276 /* Sock pair matched */
8277 *lro = l_lro;
8278
8279 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
8280 DBG_PRINT(INFO_DBG, "%s:Out of order. expected "
8281 "0x%x, actual 0x%x\n", __FUNCTION__,
8282 (*lro)->tcp_next_seq,
8283 ntohl(tcph->seq));
8284
8285 sp->mac_control.stats_info->
8286 sw_stat.outof_sequence_pkts++;
8287 ret = 2;
8288 break;
8289 }
8290
8291 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,*tcp_len))
8292 ret = 1; /* Aggregate */
8293 else
8294 ret = 2; /* Flush both */
8295 break;
8296 }
8297 }
8298
8299 if (ret == 0) {
8300 /* Before searching for available LRO objects,
8301 * check if the pkt is L3/L4 aggregatable. If not
8302 * don't create new LRO session. Just send this
8303 * packet up.
8304 */
8305 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len)) {
8306 return 5;
8307 }
8308
8309 for (i=0; i<MAX_LRO_SESSIONS; i++) {
8310 struct lro *l_lro = &sp->lro0_n[i];
8311 if (!(l_lro->in_use)) {
8312 *lro = l_lro;
8313 ret = 3; /* Begin anew */
8314 break;
8315 }
8316 }
8317 }
8318
8319 if (ret == 0) { /* sessions exceeded */
8320 DBG_PRINT(INFO_DBG,"%s:All LRO sessions already in use\n",
8321 __FUNCTION__);
8322 *lro = NULL;
8323 return ret;
8324 }
8325
8326 switch (ret) {
8327 case 3:
8328 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len);
8329 break;
8330 case 2:
8331 update_L3L4_header(sp, *lro);
8332 break;
8333 case 1:
8334 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
8335 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
8336 update_L3L4_header(sp, *lro);
8337 ret = 4; /* Flush the LRO */
8338 }
8339 break;
8340 default:
8341 DBG_PRINT(ERR_DBG,"%s:Dont know, can't say!!\n",
8342 __FUNCTION__);
8343 break;
8344 }
8345
8346 return ret;
8347 }
8348
8349 static void clear_lro_session(struct lro *lro)
8350 {
8351 static u16 lro_struct_size = sizeof(struct lro);
8352
8353 memset(lro, 0, lro_struct_size);
8354 }
8355
8356 static void queue_rx_frame(struct sk_buff *skb)
8357 {
8358 struct net_device *dev = skb->dev;
8359
8360 skb->protocol = eth_type_trans(skb, dev);
8361 if (napi)
8362 netif_receive_skb(skb);
8363 else
8364 netif_rx(skb);
8365 }
8366
8367 static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
8368 struct sk_buff *skb,
8369 u32 tcp_len)
8370 {
8371 struct sk_buff *first = lro->parent;
8372
8373 first->len += tcp_len;
8374 first->data_len = lro->frags_len;
8375 skb_pull(skb, (skb->len - tcp_len));
8376 if (skb_shinfo(first)->frag_list)
8377 lro->last_frag->next = skb;
8378 else
8379 skb_shinfo(first)->frag_list = skb;
8380 first->truesize += skb->truesize;
8381 lro->last_frag = skb;
8382 sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++;
8383 return;
8384 }
8385
8386 /**
8387 * s2io_io_error_detected - called when PCI error is detected
8388 * @pdev: Pointer to PCI device
8389 * @state: The current pci connection state
8390 *
8391 * This function is called after a PCI bus error affecting
8392 * this device has been detected.
8393 */
8394 static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
8395 pci_channel_state_t state)
8396 {
8397 struct net_device *netdev = pci_get_drvdata(pdev);
8398 struct s2io_nic *sp = netdev->priv;
8399
8400 netif_device_detach(netdev);
8401
8402 if (netif_running(netdev)) {
8403 /* Bring down the card, while avoiding PCI I/O */
8404 do_s2io_card_down(sp, 0);
8405 }
8406 pci_disable_device(pdev);
8407
8408 return PCI_ERS_RESULT_NEED_RESET;
8409 }
8410
8411 /**
8412 * s2io_io_slot_reset - called after the pci bus has been reset.
8413 * @pdev: Pointer to PCI device
8414 *
8415 * Restart the card from scratch, as if from a cold-boot.
8416 * At this point, the card has exprienced a hard reset,
8417 * followed by fixups by BIOS, and has its config space
8418 * set up identically to what it was at cold boot.
8419 */
8420 static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8421 {
8422 struct net_device *netdev = pci_get_drvdata(pdev);
8423 struct s2io_nic *sp = netdev->priv;
8424
8425 if (pci_enable_device(pdev)) {
8426 printk(KERN_ERR "s2io: "
8427 "Cannot re-enable PCI device after reset.\n");
8428 return PCI_ERS_RESULT_DISCONNECT;
8429 }
8430
8431 pci_set_master(pdev);
8432 s2io_reset(sp);
8433
8434 return PCI_ERS_RESULT_RECOVERED;
8435 }
8436
8437 /**
8438 * s2io_io_resume - called when traffic can start flowing again.
8439 * @pdev: Pointer to PCI device
8440 *
8441 * This callback is called when the error recovery driver tells
8442 * us that its OK to resume normal operation.
8443 */
8444 static void s2io_io_resume(struct pci_dev *pdev)
8445 {
8446 struct net_device *netdev = pci_get_drvdata(pdev);
8447 struct s2io_nic *sp = netdev->priv;
8448
8449 if (netif_running(netdev)) {
8450 if (s2io_card_up(sp)) {
8451 printk(KERN_ERR "s2io: "
8452 "Can't bring device back up after reset.\n");
8453 return;
8454 }
8455
8456 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
8457 s2io_card_down(sp);
8458 printk(KERN_ERR "s2io: "
8459 "Can't resetore mac addr after reset.\n");
8460 return;
8461 }
8462 }
8463
8464 netif_device_attach(netdev);
8465 netif_wake_queue(netdev);
8466 }
WRT350N Kernel Patches