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mm/slab.c: proper prototypes
[wrt350n-kernel.git] / drivers / media / dvb / frontends / tda1004x.c
blob33a84372c9e6ce079b3bacb9104e37b73c77b1ab
1 /*
2 Driver for Philips tda1004xh OFDM Demodulator
3
4 (c) 2003, 2004 Andrew de Quincey & Robert Schlabbach
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20
21 */
22 /*
23 * This driver needs external firmware. Please use the commands
24 * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10045",
25 * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10046" to
26 * download/extract them, and then copy them to /usr/lib/hotplug/firmware
27 * or /lib/firmware (depending on configuration of firmware hotplug).
28 */
29 #define TDA10045_DEFAULT_FIRMWARE "dvb-fe-tda10045.fw"
30 #define TDA10046_DEFAULT_FIRMWARE "dvb-fe-tda10046.fw"
31
32 #include <linux/init.h>
33 #include <linux/module.h>
34 #include <linux/moduleparam.h>
35 #include <linux/device.h>
36 #include <linux/jiffies.h>
37 #include <linux/string.h>
38 #include <linux/slab.h>
39
40 #include "dvb_frontend.h"
41 #include "tda1004x.h"
42
43 static int debug;
44 #define dprintk(args...) \
45 do { \
46 if (debug) printk(KERN_DEBUG "tda1004x: " args); \
47 } while (0)
48
49 #define TDA1004X_CHIPID 0x00
50 #define TDA1004X_AUTO 0x01
51 #define TDA1004X_IN_CONF1 0x02
52 #define TDA1004X_IN_CONF2 0x03
53 #define TDA1004X_OUT_CONF1 0x04
54 #define TDA1004X_OUT_CONF2 0x05
55 #define TDA1004X_STATUS_CD 0x06
56 #define TDA1004X_CONFC4 0x07
57 #define TDA1004X_DSSPARE2 0x0C
58 #define TDA10045H_CODE_IN 0x0D
59 #define TDA10045H_FWPAGE 0x0E
60 #define TDA1004X_SCAN_CPT 0x10
61 #define TDA1004X_DSP_CMD 0x11
62 #define TDA1004X_DSP_ARG 0x12
63 #define TDA1004X_DSP_DATA1 0x13
64 #define TDA1004X_DSP_DATA2 0x14
65 #define TDA1004X_CONFADC1 0x15
66 #define TDA1004X_CONFC1 0x16
67 #define TDA10045H_S_AGC 0x1a
68 #define TDA10046H_AGC_TUN_LEVEL 0x1a
69 #define TDA1004X_SNR 0x1c
70 #define TDA1004X_CONF_TS1 0x1e
71 #define TDA1004X_CONF_TS2 0x1f
72 #define TDA1004X_CBER_RESET 0x20
73 #define TDA1004X_CBER_MSB 0x21
74 #define TDA1004X_CBER_LSB 0x22
75 #define TDA1004X_CVBER_LUT 0x23
76 #define TDA1004X_VBER_MSB 0x24
77 #define TDA1004X_VBER_MID 0x25
78 #define TDA1004X_VBER_LSB 0x26
79 #define TDA1004X_UNCOR 0x27
80
81 #define TDA10045H_CONFPLL_P 0x2D
82 #define TDA10045H_CONFPLL_M_MSB 0x2E
83 #define TDA10045H_CONFPLL_M_LSB 0x2F
84 #define TDA10045H_CONFPLL_N 0x30
85
86 #define TDA10046H_CONFPLL1 0x2D
87 #define TDA10046H_CONFPLL2 0x2F
88 #define TDA10046H_CONFPLL3 0x30
89 #define TDA10046H_TIME_WREF1 0x31
90 #define TDA10046H_TIME_WREF2 0x32
91 #define TDA10046H_TIME_WREF3 0x33
92 #define TDA10046H_TIME_WREF4 0x34
93 #define TDA10046H_TIME_WREF5 0x35
94
95 #define TDA10045H_UNSURW_MSB 0x31
96 #define TDA10045H_UNSURW_LSB 0x32
97 #define TDA10045H_WREF_MSB 0x33
98 #define TDA10045H_WREF_MID 0x34
99 #define TDA10045H_WREF_LSB 0x35
100 #define TDA10045H_MUXOUT 0x36
101 #define TDA1004X_CONFADC2 0x37
102
103 #define TDA10045H_IOFFSET 0x38
104
105 #define TDA10046H_CONF_TRISTATE1 0x3B
106 #define TDA10046H_CONF_TRISTATE2 0x3C
107 #define TDA10046H_CONF_POLARITY 0x3D
108 #define TDA10046H_FREQ_OFFSET 0x3E
109 #define TDA10046H_GPIO_OUT_SEL 0x41
110 #define TDA10046H_GPIO_SELECT 0x42
111 #define TDA10046H_AGC_CONF 0x43
112 #define TDA10046H_AGC_THR 0x44
113 #define TDA10046H_AGC_RENORM 0x45
114 #define TDA10046H_AGC_GAINS 0x46
115 #define TDA10046H_AGC_TUN_MIN 0x47
116 #define TDA10046H_AGC_TUN_MAX 0x48
117 #define TDA10046H_AGC_IF_MIN 0x49
118 #define TDA10046H_AGC_IF_MAX 0x4A
119
120 #define TDA10046H_FREQ_PHY2_MSB 0x4D
121 #define TDA10046H_FREQ_PHY2_LSB 0x4E
122
123 #define TDA10046H_CVBER_CTRL 0x4F
124 #define TDA10046H_AGC_IF_LEVEL 0x52
125 #define TDA10046H_CODE_CPT 0x57
126 #define TDA10046H_CODE_IN 0x58
127
128
129 static int tda1004x_write_byteI(struct tda1004x_state *state, int reg, int data)
130 {
131 int ret;
132 u8 buf[] = { reg, data };
133 struct i2c_msg msg = { .flags = 0, .buf = buf, .len = 2 };
134
135 dprintk("%s: reg=0x%x, data=0x%x\n", __FUNCTION__, reg, data);
136
137 msg.addr = state->config->demod_address;
138 ret = i2c_transfer(state->i2c, &msg, 1);
139
140 if (ret != 1)
141 dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n",
142 __FUNCTION__, reg, data, ret);
143
144 dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
145 reg, data, ret);
146 return (ret != 1) ? -1 : 0;
147 }
148
149 static int tda1004x_read_byte(struct tda1004x_state *state, int reg)
150 {
151 int ret;
152 u8 b0[] = { reg };
153 u8 b1[] = { 0 };
154 struct i2c_msg msg[] = {{ .flags = 0, .buf = b0, .len = 1 },
155 { .flags = I2C_M_RD, .buf = b1, .len = 1 }};
156
157 dprintk("%s: reg=0x%x\n", __FUNCTION__, reg);
158
159 msg[0].addr = state->config->demod_address;
160 msg[1].addr = state->config->demod_address;
161 ret = i2c_transfer(state->i2c, msg, 2);
162
163 if (ret != 2) {
164 dprintk("%s: error reg=0x%x, ret=%i\n", __FUNCTION__, reg,
165 ret);
166 return -1;
167 }
168
169 dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
170 reg, b1[0], ret);
171 return b1[0];
172 }
173
174 static int tda1004x_write_mask(struct tda1004x_state *state, int reg, int mask, int data)
175 {
176 int val;
177 dprintk("%s: reg=0x%x, mask=0x%x, data=0x%x\n", __FUNCTION__, reg,
178 mask, data);
179
180 // read a byte and check
181 val = tda1004x_read_byte(state, reg);
182 if (val < 0)
183 return val;
184
185 // mask if off
186 val = val & ~mask;
187 val |= data & 0xff;
188
189 // write it out again
190 return tda1004x_write_byteI(state, reg, val);
191 }
192
193 static int tda1004x_write_buf(struct tda1004x_state *state, int reg, unsigned char *buf, int len)
194 {
195 int i;
196 int result;
197
198 dprintk("%s: reg=0x%x, len=0x%x\n", __FUNCTION__, reg, len);
199
200 result = 0;
201 for (i = 0; i < len; i++) {
202 result = tda1004x_write_byteI(state, reg + i, buf[i]);
203 if (result != 0)
204 break;
205 }
206
207 return result;
208 }
209
210 static int tda1004x_enable_tuner_i2c(struct tda1004x_state *state)
211 {
212 int result;
213 dprintk("%s\n", __FUNCTION__);
214
215 result = tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 2);
216 msleep(20);
217 return result;
218 }
219
220 static int tda1004x_disable_tuner_i2c(struct tda1004x_state *state)
221 {
222 dprintk("%s\n", __FUNCTION__);
223
224 return tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 0);
225 }
226
227 static int tda10045h_set_bandwidth(struct tda1004x_state *state,
228 fe_bandwidth_t bandwidth)
229 {
230 static u8 bandwidth_6mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x60, 0x1e, 0xa7, 0x45, 0x4f };
231 static u8 bandwidth_7mhz[] = { 0x02, 0x00, 0x37, 0x00, 0x4a, 0x2f, 0x6d, 0x76, 0xdb };
232 static u8 bandwidth_8mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x48, 0x17, 0x89, 0xc7, 0x14 };
233
234 switch (bandwidth) {
235 case BANDWIDTH_6_MHZ:
236 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz));
237 break;
238
239 case BANDWIDTH_7_MHZ:
240 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz));
241 break;
242
243 case BANDWIDTH_8_MHZ:
244 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz));
245 break;
246
247 default:
248 return -EINVAL;
249 }
250
251 tda1004x_write_byteI(state, TDA10045H_IOFFSET, 0);
252
253 return 0;
254 }
255
256 static int tda10046h_set_bandwidth(struct tda1004x_state *state,
257 fe_bandwidth_t bandwidth)
258 {
259 static u8 bandwidth_6mhz_53M[] = { 0x7b, 0x2e, 0x11, 0xf0, 0xd2 };
260 static u8 bandwidth_7mhz_53M[] = { 0x6a, 0x02, 0x6a, 0x43, 0x9f };
261 static u8 bandwidth_8mhz_53M[] = { 0x5c, 0x32, 0xc2, 0x96, 0x6d };
262
263 static u8 bandwidth_6mhz_48M[] = { 0x70, 0x02, 0x49, 0x24, 0x92 };
264 static u8 bandwidth_7mhz_48M[] = { 0x60, 0x02, 0xaa, 0xaa, 0xab };
265 static u8 bandwidth_8mhz_48M[] = { 0x54, 0x03, 0x0c, 0x30, 0xc3 };
266 int tda10046_clk53m;
267
268 if ((state->config->if_freq == TDA10046_FREQ_045) ||
269 (state->config->if_freq == TDA10046_FREQ_052))
270 tda10046_clk53m = 0;
271 else
272 tda10046_clk53m = 1;
273 switch (bandwidth) {
274 case BANDWIDTH_6_MHZ:
275 if (tda10046_clk53m)
276 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_53M,
277 sizeof(bandwidth_6mhz_53M));
278 else
279 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_48M,
280 sizeof(bandwidth_6mhz_48M));
281 if (state->config->if_freq == TDA10046_FREQ_045) {
282 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0a);
283 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xab);
284 }
285 break;
286
287 case BANDWIDTH_7_MHZ:
288 if (tda10046_clk53m)
289 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_53M,
290 sizeof(bandwidth_7mhz_53M));
291 else
292 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_48M,
293 sizeof(bandwidth_7mhz_48M));
294 if (state->config->if_freq == TDA10046_FREQ_045) {
295 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
296 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
297 }
298 break;
299
300 case BANDWIDTH_8_MHZ:
301 if (tda10046_clk53m)
302 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_53M,
303 sizeof(bandwidth_8mhz_53M));
304 else
305 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_48M,
306 sizeof(bandwidth_8mhz_48M));
307 if (state->config->if_freq == TDA10046_FREQ_045) {
308 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
309 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x55);
310 }
311 break;
312
313 default:
314 return -EINVAL;
315 }
316
317 return 0;
318 }
319
320 static int tda1004x_do_upload(struct tda1004x_state *state,
321 unsigned char *mem, unsigned int len,
322 u8 dspCodeCounterReg, u8 dspCodeInReg)
323 {
324 u8 buf[65];
325 struct i2c_msg fw_msg = { .flags = 0, .buf = buf, .len = 0 };
326 int tx_size;
327 int pos = 0;
328
329 /* clear code counter */
330 tda1004x_write_byteI(state, dspCodeCounterReg, 0);
331 fw_msg.addr = state->config->demod_address;
332
333 buf[0] = dspCodeInReg;
334 while (pos != len) {
335 // work out how much to send this time
336 tx_size = len - pos;
337 if (tx_size > 0x10)
338 tx_size = 0x10;
339
340 // send the chunk
341 memcpy(buf + 1, mem + pos, tx_size);
342 fw_msg.len = tx_size + 1;
343 if (i2c_transfer(state->i2c, &fw_msg, 1) != 1) {
344 printk(KERN_ERR "tda1004x: Error during firmware upload\n");
345 return -EIO;
346 }
347 pos += tx_size;
348
349 dprintk("%s: fw_pos=0x%x\n", __FUNCTION__, pos);
350 }
351 // give the DSP a chance to settle 03/10/05 Hac
352 msleep(100);
353
354 return 0;
355 }
356
357 static int tda1004x_check_upload_ok(struct tda1004x_state *state)
358 {
359 u8 data1, data2;
360 unsigned long timeout;
361
362 if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
363 timeout = jiffies + 2 * HZ;
364 while(!(tda1004x_read_byte(state, TDA1004X_STATUS_CD) & 0x20)) {
365 if (time_after(jiffies, timeout)) {
366 printk(KERN_ERR "tda1004x: timeout waiting for DSP ready\n");
367 break;
368 }
369 msleep(1);
370 }
371 } else
372 msleep(100);
373
374 // check upload was OK
375 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP
376 tda1004x_write_byteI(state, TDA1004X_DSP_CMD, 0x67);
377
378 data1 = tda1004x_read_byte(state, TDA1004X_DSP_DATA1);
379 data2 = tda1004x_read_byte(state, TDA1004X_DSP_DATA2);
380 if (data1 != 0x67 || data2 < 0x20 || data2 > 0x2e) {
381 printk(KERN_INFO "tda1004x: found firmware revision %x -- invalid\n", data2);
382 return -EIO;
383 }
384 printk(KERN_INFO "tda1004x: found firmware revision %x -- ok\n", data2);
385 return 0;
386 }
387
388 static int tda10045_fwupload(struct dvb_frontend* fe)
389 {
390 struct tda1004x_state* state = fe->demodulator_priv;
391 int ret;
392 const struct firmware *fw;
393
394 /* don't re-upload unless necessary */
395 if (tda1004x_check_upload_ok(state) == 0)
396 return 0;
397
398 /* request the firmware, this will block until someone uploads it */
399 printk(KERN_INFO "tda1004x: waiting for firmware upload (%s)...\n", TDA10045_DEFAULT_FIRMWARE);
400 ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE);
401 if (ret) {
402 printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
403 return ret;
404 }
405
406 /* reset chip */
407 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0);
408 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
409 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
410 msleep(10);
411
412 /* set parameters */
413 tda10045h_set_bandwidth(state, BANDWIDTH_8_MHZ);
414
415 ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10045H_FWPAGE, TDA10045H_CODE_IN);
416 release_firmware(fw);
417 if (ret)
418 return ret;
419 printk(KERN_INFO "tda1004x: firmware upload complete\n");
420
421 /* wait for DSP to initialise */
422 /* DSPREADY doesn't seem to work on the TDA10045H */
423 msleep(100);
424
425 return tda1004x_check_upload_ok(state);
426 }
427
428 static void tda10046_init_plls(struct dvb_frontend* fe)
429 {
430 struct tda1004x_state* state = fe->demodulator_priv;
431 int tda10046_clk53m;
432
433 if ((state->config->if_freq == TDA10046_FREQ_045) ||
434 (state->config->if_freq == TDA10046_FREQ_052))
435 tda10046_clk53m = 0;
436 else
437 tda10046_clk53m = 1;
438
439 tda1004x_write_byteI(state, TDA10046H_CONFPLL1, 0xf0);
440 if(tda10046_clk53m) {
441 printk(KERN_INFO "tda1004x: setting up plls for 53MHz sampling clock\n");
442 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x08); // PLL M = 8
443 } else {
444 printk(KERN_INFO "tda1004x: setting up plls for 48MHz sampling clock\n");
445 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x03); // PLL M = 3
446 }
447 if (state->config->xtal_freq == TDA10046_XTAL_4M ) {
448 dprintk("%s: setting up PLLs for a 4 MHz Xtal\n", __FUNCTION__);
449 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0
450 } else {
451 dprintk("%s: setting up PLLs for a 16 MHz Xtal\n", __FUNCTION__);
452 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 3); // PLL P = 0, N = 3
453 }
454 if(tda10046_clk53m)
455 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x67);
456 else
457 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x72);
458 /* Note clock frequency is handled implicitly */
459 switch (state->config->if_freq) {
460 case TDA10046_FREQ_045:
461 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
462 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
463 break;
464 case TDA10046_FREQ_052:
465 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
466 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xc7);
467 break;
468 case TDA10046_FREQ_3617:
469 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
470 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x59);
471 break;
472 case TDA10046_FREQ_3613:
473 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
474 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x3f);
475 break;
476 }
477 tda10046h_set_bandwidth(state, BANDWIDTH_8_MHZ); // default bandwidth 8 MHz
478 /* let the PLLs settle */
479 msleep(120);
480 }
481
482 static int tda10046_fwupload(struct dvb_frontend* fe)
483 {
484 struct tda1004x_state* state = fe->demodulator_priv;
485 int ret;
486 const struct firmware *fw;
487
488 /* reset + wake up chip */
489 if (state->config->xtal_freq == TDA10046_XTAL_4M) {
490 tda1004x_write_byteI(state, TDA1004X_CONFC4, 0);
491 } else {
492 dprintk("%s: 16MHz Xtal, reducing I2C speed\n", __FUNCTION__);
493 tda1004x_write_byteI(state, TDA1004X_CONFC4, 0x80);
494 }
495 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 1, 0);
496 /* set GPIO 1 and 3 */
497 if (state->config->gpio_config != TDA10046_GPTRI) {
498 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE2, 0x33);
499 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x0f, state->config->gpio_config &0x0f);
500 }
501 /* let the clocks recover from sleep */
502 msleep(10);
503
504 /* The PLLs need to be reprogrammed after sleep */
505 tda10046_init_plls(fe);
506 tda1004x_write_mask(state, TDA1004X_CONFADC2, 0xc0, 0);
507
508 /* don't re-upload unless necessary */
509 if (tda1004x_check_upload_ok(state) == 0)
510 return 0;
511
512 printk(KERN_INFO "tda1004x: trying to boot from eeprom\n");
513 tda1004x_write_mask(state, TDA1004X_CONFC4, 4, 4);
514 msleep(300);
515 /* don't re-upload unless necessary */
516 if (tda1004x_check_upload_ok(state) == 0)
517 return 0;
518
519 if (state->config->request_firmware != NULL) {
520 /* request the firmware, this will block until someone uploads it */
521 printk(KERN_INFO "tda1004x: waiting for firmware upload...\n");
522 ret = state->config->request_firmware(fe, &fw, TDA10046_DEFAULT_FIRMWARE);
523 if (ret) {
524 /* remain compatible to old bug: try to load with tda10045 image name */
525 ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE);
526 if (ret) {
527 printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
528 return ret;
529 } else {
530 printk(KERN_INFO "tda1004x: please rename the firmware file to %s\n",
531 TDA10046_DEFAULT_FIRMWARE);
532 }
533 }
534 } else {
535 printk(KERN_ERR "tda1004x: no request function defined, can't upload from file\n");
536 return -EIO;
537 }
538 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST
539 ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10046H_CODE_CPT, TDA10046H_CODE_IN);
540 release_firmware(fw);
541 return tda1004x_check_upload_ok(state);
542 }
543
544 static int tda1004x_encode_fec(int fec)
545 {
546 // convert known FEC values
547 switch (fec) {
548 case FEC_1_2:
549 return 0;
550 case FEC_2_3:
551 return 1;
552 case FEC_3_4:
553 return 2;
554 case FEC_5_6:
555 return 3;
556 case FEC_7_8:
557 return 4;
558 }
559
560 // unsupported
561 return -EINVAL;
562 }
563
564 static int tda1004x_decode_fec(int tdafec)
565 {
566 // convert known FEC values
567 switch (tdafec) {
568 case 0:
569 return FEC_1_2;
570 case 1:
571 return FEC_2_3;
572 case 2:
573 return FEC_3_4;
574 case 3:
575 return FEC_5_6;
576 case 4:
577 return FEC_7_8;
578 }
579
580 // unsupported
581 return -1;
582 }
583
584 static int tda1004x_write(struct dvb_frontend* fe, u8 *buf, int len)
585 {
586 struct tda1004x_state* state = fe->demodulator_priv;
587
588 if (len != 2)
589 return -EINVAL;
590
591 return tda1004x_write_byteI(state, buf[0], buf[1]);
592 }
593
594 static int tda10045_init(struct dvb_frontend* fe)
595 {
596 struct tda1004x_state* state = fe->demodulator_priv;
597
598 dprintk("%s\n", __FUNCTION__);
599
600 if (tda10045_fwupload(fe)) {
601 printk("tda1004x: firmware upload failed\n");
602 return -EIO;
603 }
604
605 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC
606
607 // tda setup
608 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
609 tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream
610 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0); // set polarity of VAGC signal
611 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer
612 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset
613 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset
614 tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 0); // setup MPEG2 TS interface
615 tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0); // setup MPEG2 TS interface
616 tda1004x_write_mask(state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits
617 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity
618 tda1004x_write_byteI(state, TDA1004X_CONFADC1, 0x2e);
619
620 tda1004x_write_mask(state, 0x1f, 0x01, state->config->invert_oclk);
621
622 return 0;
623 }
624
625 static int tda10046_init(struct dvb_frontend* fe)
626 {
627 struct tda1004x_state* state = fe->demodulator_priv;
628 dprintk("%s\n", __FUNCTION__);
629
630 if (tda10046_fwupload(fe)) {
631 printk("tda1004x: firmware upload failed\n");
632 return -EIO;
633 }
634
635 // tda setup
636 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
637 tda1004x_write_byteI(state, TDA1004X_AUTO, 0x87); // 100 ppm crystal, select HP stream
638 tda1004x_write_byteI(state, TDA1004X_CONFC1, 0x88); // enable pulse killer
639
640 switch (state->config->agc_config) {
641 case TDA10046_AGC_DEFAULT:
642 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x00); // AGC setup
643 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities
644 break;
645 case TDA10046_AGC_IFO_AUTO_NEG:
646 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
647 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities
648 break;
649 case TDA10046_AGC_IFO_AUTO_POS:
650 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
651 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x00); // set AGC polarities
652 break;
653 case TDA10046_AGC_TDA827X:
654 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x02); // AGC setup
655 tda1004x_write_byteI(state, TDA10046H_AGC_THR, 0x70); // AGC Threshold
656 tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x08); // Gain Renormalize
657 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities
658 break;
659 }
660 if (state->config->ts_mode == 0) {
661 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0xc0, 0x40);
662 tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7);
663 } else {
664 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0xc0, 0x80);
665 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x10,
666 state->config->invert_oclk << 4);
667 }
668 tda1004x_write_byteI(state, TDA1004X_CONFADC2, 0x38);
669 tda1004x_write_mask (state, TDA10046H_CONF_TRISTATE1, 0x3e, 0x38); // Turn IF AGC output on
670 tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0); // }
671 tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values
672 tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0); // }
673 tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff); // }
674 tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 0x12); // IF gain 2, TUN gain 1
675 tda1004x_write_byteI(state, TDA10046H_CVBER_CTRL, 0x1a); // 10^6 VBER measurement bits
676 tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config
677 tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0xc0); // MPEG2 interface config
678 // tda1004x_write_mask(state, 0x50, 0x80, 0x80); // handle out of guard echoes
679
680 return 0;
681 }
682
683 static int tda1004x_set_fe(struct dvb_frontend* fe,
684 struct dvb_frontend_parameters *fe_params)
685 {
686 struct tda1004x_state* state = fe->demodulator_priv;
687 int tmp;
688 int inversion;
689
690 dprintk("%s\n", __FUNCTION__);
691
692 if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
693 // setup auto offset
694 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10);
695 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x80, 0);
696 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0);
697
698 // disable agc_conf[2]
699 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 0);
700 }
701
702 // set frequency
703 if (fe->ops.tuner_ops.set_params) {
704 fe->ops.tuner_ops.set_params(fe, fe_params);
705 if (fe->ops.i2c_gate_ctrl)
706 fe->ops.i2c_gate_ctrl(fe, 0);
707 }
708
709 // Hardcoded to use auto as much as possible on the TDA10045 as it
710 // is very unreliable if AUTO mode is _not_ used.
711 if (state->demod_type == TDA1004X_DEMOD_TDA10045) {
712 fe_params->u.ofdm.code_rate_HP = FEC_AUTO;
713 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_AUTO;
714 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_AUTO;
715 }
716
717 // Set standard params.. or put them to auto
718 if ((fe_params->u.ofdm.code_rate_HP == FEC_AUTO) ||
719 (fe_params->u.ofdm.code_rate_LP == FEC_AUTO) ||
720 (fe_params->u.ofdm.constellation == QAM_AUTO) ||
721 (fe_params->u.ofdm.hierarchy_information == HIERARCHY_AUTO)) {
722 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1); // enable auto
723 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); // turn off constellation bits
724 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits
725 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits
726 } else {
727 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 0); // disable auto
728
729 // set HP FEC
730 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_HP);
731 if (tmp < 0)
732 return tmp;
733 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 7, tmp);
734
735 // set LP FEC
736 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_LP);
737 if (tmp < 0)
738 return tmp;
739 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x38, tmp << 3);
740
741 // set constellation
742 switch (fe_params->u.ofdm.constellation) {
743 case QPSK:
744 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 0);
745 break;
746
747 case QAM_16:
748 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 1);
749 break;
750
751 case QAM_64:
752 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 2);
753 break;
754
755 default:
756 return -EINVAL;
757 }
758
759 // set hierarchy
760 switch (fe_params->u.ofdm.hierarchy_information) {
761 case HIERARCHY_NONE:
762 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0 << 5);
763 break;
764
765 case HIERARCHY_1:
766 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 1 << 5);
767 break;
768
769 case HIERARCHY_2:
770 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 2 << 5);
771 break;
772
773 case HIERARCHY_4:
774 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 3 << 5);
775 break;
776
777 default:
778 return -EINVAL;
779 }
780 }
781
782 // set bandwidth
783 switch (state->demod_type) {
784 case TDA1004X_DEMOD_TDA10045:
785 tda10045h_set_bandwidth(state, fe_params->u.ofdm.bandwidth);
786 break;
787
788 case TDA1004X_DEMOD_TDA10046:
789 tda10046h_set_bandwidth(state, fe_params->u.ofdm.bandwidth);
790 break;
791 }
792
793 // set inversion
794 inversion = fe_params->inversion;
795 if (state->config->invert)
796 inversion = inversion ? INVERSION_OFF : INVERSION_ON;
797 switch (inversion) {
798 case INVERSION_OFF:
799 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0);
800 break;
801
802 case INVERSION_ON:
803 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0x20);
804 break;
805
806 default:
807 return -EINVAL;
808 }
809
810 // set guard interval
811 switch (fe_params->u.ofdm.guard_interval) {
812 case GUARD_INTERVAL_1_32:
813 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
814 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
815 break;
816
817 case GUARD_INTERVAL_1_16:
818 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
819 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 1 << 2);
820 break;
821
822 case GUARD_INTERVAL_1_8:
823 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
824 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 2 << 2);
825 break;
826
827 case GUARD_INTERVAL_1_4:
828 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
829 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 3 << 2);
830 break;
831
832 case GUARD_INTERVAL_AUTO:
833 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 2);
834 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
835 break;
836
837 default:
838 return -EINVAL;
839 }
840
841 // set transmission mode
842 switch (fe_params->u.ofdm.transmission_mode) {
843 case TRANSMISSION_MODE_2K:
844 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
845 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0 << 4);
846 break;
847
848 case TRANSMISSION_MODE_8K:
849 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
850 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 1 << 4);
851 break;
852
853 case TRANSMISSION_MODE_AUTO:
854 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 4);
855 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0);
856 break;
857
858 default:
859 return -EINVAL;
860 }
861
862 // start the lock
863 switch (state->demod_type) {
864 case TDA1004X_DEMOD_TDA10045:
865 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
866 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
867 break;
868
869 case TDA1004X_DEMOD_TDA10046:
870 tda1004x_write_mask(state, TDA1004X_AUTO, 0x40, 0x40);
871 msleep(1);
872 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 1);
873 break;
874 }
875
876 msleep(10);
877
878 return 0;
879 }
880
881 static int tda1004x_get_fe(struct dvb_frontend* fe, struct dvb_frontend_parameters *fe_params)
882 {
883 struct tda1004x_state* state = fe->demodulator_priv;
884
885 dprintk("%s\n", __FUNCTION__);
886
887 // inversion status
888 fe_params->inversion = INVERSION_OFF;
889 if (tda1004x_read_byte(state, TDA1004X_CONFC1) & 0x20)
890 fe_params->inversion = INVERSION_ON;
891 if (state->config->invert)
892 fe_params->inversion = fe_params->inversion ? INVERSION_OFF : INVERSION_ON;
893
894 // bandwidth
895 switch (state->demod_type) {
896 case TDA1004X_DEMOD_TDA10045:
897 switch (tda1004x_read_byte(state, TDA10045H_WREF_LSB)) {
898 case 0x14:
899 fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
900 break;
901 case 0xdb:
902 fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
903 break;
904 case 0x4f:
905 fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
906 break;
907 }
908 break;
909 case TDA1004X_DEMOD_TDA10046:
910 switch (tda1004x_read_byte(state, TDA10046H_TIME_WREF1)) {
911 case 0x5c:
912 case 0x54:
913 fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
914 break;
915 case 0x6a:
916 case 0x60:
917 fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
918 break;
919 case 0x7b:
920 case 0x70:
921 fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
922 break;
923 }
924 break;
925 }
926
927 // FEC
928 fe_params->u.ofdm.code_rate_HP =
929 tda1004x_decode_fec(tda1004x_read_byte(state, TDA1004X_OUT_CONF2) & 7);
930 fe_params->u.ofdm.code_rate_LP =
931 tda1004x_decode_fec((tda1004x_read_byte(state, TDA1004X_OUT_CONF2) >> 3) & 7);
932
933 // constellation
934 switch (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 3) {
935 case 0:
936 fe_params->u.ofdm.constellation = QPSK;
937 break;
938 case 1:
939 fe_params->u.ofdm.constellation = QAM_16;
940 break;
941 case 2:
942 fe_params->u.ofdm.constellation = QAM_64;
943 break;
944 }
945
946 // transmission mode
947 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K;
948 if (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x10)
949 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
950
951 // guard interval
952 switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) {
953 case 0:
954 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
955 break;
956 case 1:
957 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_16;
958 break;
959 case 2:
960 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_8;
961 break;
962 case 3:
963 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_4;
964 break;
965 }
966
967 // hierarchy
968 switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x60) >> 5) {
969 case 0:
970 fe_params->u.ofdm.hierarchy_information = HIERARCHY_NONE;
971 break;
972 case 1:
973 fe_params->u.ofdm.hierarchy_information = HIERARCHY_1;
974 break;
975 case 2:
976 fe_params->u.ofdm.hierarchy_information = HIERARCHY_2;
977 break;
978 case 3:
979 fe_params->u.ofdm.hierarchy_information = HIERARCHY_4;
980 break;
981 }
982
983 return 0;
984 }
985
986 static int tda1004x_read_status(struct dvb_frontend* fe, fe_status_t * fe_status)
987 {
988 struct tda1004x_state* state = fe->demodulator_priv;
989 int status;
990 int cber;
991 int vber;
992
993 dprintk("%s\n", __FUNCTION__);
994
995 // read status
996 status = tda1004x_read_byte(state, TDA1004X_STATUS_CD);
997 if (status == -1)
998 return -EIO;
999
1000 // decode
1001 *fe_status = 0;
1002 if (status & 4)
1003 *fe_status |= FE_HAS_SIGNAL;
1004 if (status & 2)
1005 *fe_status |= FE_HAS_CARRIER;
1006 if (status & 8)
1007 *fe_status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
1008
1009 // if we don't already have VITERBI (i.e. not LOCKED), see if the viterbi
1010 // is getting anything valid
1011 if (!(*fe_status & FE_HAS_VITERBI)) {
1012 // read the CBER
1013 cber = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
1014 if (cber == -1)
1015 return -EIO;
1016 status = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
1017 if (status == -1)
1018 return -EIO;
1019 cber |= (status << 8);
1020 // The address 0x20 should be read to cope with a TDA10046 bug
1021 tda1004x_read_byte(state, TDA1004X_CBER_RESET);
1022
1023 if (cber != 65535)
1024 *fe_status |= FE_HAS_VITERBI;
1025 }
1026
1027 // if we DO have some valid VITERBI output, but don't already have SYNC
1028 // bytes (i.e. not LOCKED), see if the RS decoder is getting anything valid.
1029 if ((*fe_status & FE_HAS_VITERBI) && (!(*fe_status & FE_HAS_SYNC))) {
1030 // read the VBER
1031 vber = tda1004x_read_byte(state, TDA1004X_VBER_LSB);
1032 if (vber == -1)
1033 return -EIO;
1034 status = tda1004x_read_byte(state, TDA1004X_VBER_MID);
1035 if (status == -1)
1036 return -EIO;
1037 vber |= (status << 8);
1038 status = tda1004x_read_byte(state, TDA1004X_VBER_MSB);
1039 if (status == -1)
1040 return -EIO;
1041 vber |= (status & 0x0f) << 16;
1042 // The CVBER_LUT should be read to cope with TDA10046 hardware bug
1043 tda1004x_read_byte(state, TDA1004X_CVBER_LUT);
1044
1045 // if RS has passed some valid TS packets, then we must be
1046 // getting some SYNC bytes
1047 if (vber < 16632)
1048 *fe_status |= FE_HAS_SYNC;
1049 }
1050
1051 // success
1052 dprintk("%s: fe_status=0x%x\n", __FUNCTION__, *fe_status);
1053 return 0;
1054 }
1055
1056 static int tda1004x_read_signal_strength(struct dvb_frontend* fe, u16 * signal)
1057 {
1058 struct tda1004x_state* state = fe->demodulator_priv;
1059 int tmp;
1060 int reg = 0;
1061
1062 dprintk("%s\n", __FUNCTION__);
1063
1064 // determine the register to use
1065 switch (state->demod_type) {
1066 case TDA1004X_DEMOD_TDA10045:
1067 reg = TDA10045H_S_AGC;
1068 break;
1069
1070 case TDA1004X_DEMOD_TDA10046:
1071 reg = TDA10046H_AGC_IF_LEVEL;
1072 break;
1073 }
1074
1075 // read it
1076 tmp = tda1004x_read_byte(state, reg);
1077 if (tmp < 0)
1078 return -EIO;
1079
1080 *signal = (tmp << 8) | tmp;
1081 dprintk("%s: signal=0x%x\n", __FUNCTION__, *signal);
1082 return 0;
1083 }
1084
1085 static int tda1004x_read_snr(struct dvb_frontend* fe, u16 * snr)
1086 {
1087 struct tda1004x_state* state = fe->demodulator_priv;
1088 int tmp;
1089
1090 dprintk("%s\n", __FUNCTION__);
1091
1092 // read it
1093 tmp = tda1004x_read_byte(state, TDA1004X_SNR);
1094 if (tmp < 0)
1095 return -EIO;
1096 tmp = 255 - tmp;
1097
1098 *snr = ((tmp << 8) | tmp);
1099 dprintk("%s: snr=0x%x\n", __FUNCTION__, *snr);
1100 return 0;
1101 }
1102
1103 static int tda1004x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
1104 {
1105 struct tda1004x_state* state = fe->demodulator_priv;
1106 int tmp;
1107 int tmp2;
1108 int counter;
1109
1110 dprintk("%s\n", __FUNCTION__);
1111
1112 // read the UCBLOCKS and reset
1113 counter = 0;
1114 tmp = tda1004x_read_byte(state, TDA1004X_UNCOR);
1115 if (tmp < 0)
1116 return -EIO;
1117 tmp &= 0x7f;
1118 while (counter++ < 5) {
1119 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1120 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1121 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1122
1123 tmp2 = tda1004x_read_byte(state, TDA1004X_UNCOR);
1124 if (tmp2 < 0)
1125 return -EIO;
1126 tmp2 &= 0x7f;
1127 if ((tmp2 < tmp) || (tmp2 == 0))
1128 break;
1129 }
1130
1131 if (tmp != 0x7f)
1132 *ucblocks = tmp;
1133 else
1134 *ucblocks = 0xffffffff;
1135
1136 dprintk("%s: ucblocks=0x%x\n", __FUNCTION__, *ucblocks);
1137 return 0;
1138 }
1139
1140 static int tda1004x_read_ber(struct dvb_frontend* fe, u32* ber)
1141 {
1142 struct tda1004x_state* state = fe->demodulator_priv;
1143 int tmp;
1144
1145 dprintk("%s\n", __FUNCTION__);
1146
1147 // read it in
1148 tmp = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
1149 if (tmp < 0)
1150 return -EIO;
1151 *ber = tmp << 1;
1152 tmp = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
1153 if (tmp < 0)
1154 return -EIO;
1155 *ber |= (tmp << 9);
1156 // The address 0x20 should be read to cope with a TDA10046 bug
1157 tda1004x_read_byte(state, TDA1004X_CBER_RESET);
1158
1159 dprintk("%s: ber=0x%x\n", __FUNCTION__, *ber);
1160 return 0;
1161 }
1162
1163 static int tda1004x_sleep(struct dvb_frontend* fe)
1164 {
1165 struct tda1004x_state* state = fe->demodulator_priv;
1166 int gpio_conf;
1167
1168 switch (state->demod_type) {
1169 case TDA1004X_DEMOD_TDA10045:
1170 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0x10);
1171 break;
1172
1173 case TDA1004X_DEMOD_TDA10046:
1174 /* set outputs to tristate */
1175 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0xff);
1176 /* invert GPIO 1 and 3 if desired*/
1177 gpio_conf = state->config->gpio_config;
1178 if (gpio_conf >= TDA10046_GP00_I)
1179 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x0f,
1180 (gpio_conf & 0x0f) ^ 0x0a);
1181
1182 tda1004x_write_mask(state, TDA1004X_CONFADC2, 0xc0, 0xc0);
1183 tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 1);
1184 break;
1185 }
1186
1187 return 0;
1188 }
1189
1190 static int tda1004x_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
1191 {
1192 struct tda1004x_state* state = fe->demodulator_priv;
1193
1194 if (enable) {
1195 return tda1004x_enable_tuner_i2c(state);
1196 } else {
1197 return tda1004x_disable_tuner_i2c(state);
1198 }
1199 }
1200
1201 static int tda1004x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
1202 {
1203 fesettings->min_delay_ms = 800;
1204 /* Drift compensation makes no sense for DVB-T */
1205 fesettings->step_size = 0;
1206 fesettings->max_drift = 0;
1207 return 0;
1208 }
1209
1210 static void tda1004x_release(struct dvb_frontend* fe)
1211 {
1212 struct tda1004x_state *state = fe->demodulator_priv;
1213 kfree(state);
1214 }
1215
1216 static struct dvb_frontend_ops tda10045_ops = {
1217 .info = {
1218 .name = "Philips TDA10045H DVB-T",
1219 .type = FE_OFDM,
1220 .frequency_min = 51000000,
1221 .frequency_max = 858000000,
1222 .frequency_stepsize = 166667,
1223 .caps =
1224 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1225 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1226 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1227 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1228 },
1229
1230 .release = tda1004x_release,
1231
1232 .init = tda10045_init,
1233 .sleep = tda1004x_sleep,
1234 .write = tda1004x_write,
1235 .i2c_gate_ctrl = tda1004x_i2c_gate_ctrl,
1236
1237 .set_frontend = tda1004x_set_fe,
1238 .get_frontend = tda1004x_get_fe,
1239 .get_tune_settings = tda1004x_get_tune_settings,
1240
1241 .read_status = tda1004x_read_status,
1242 .read_ber = tda1004x_read_ber,
1243 .read_signal_strength = tda1004x_read_signal_strength,
1244 .read_snr = tda1004x_read_snr,
1245 .read_ucblocks = tda1004x_read_ucblocks,
1246 };
1247
1248 struct dvb_frontend* tda10045_attach(const struct tda1004x_config* config,
1249 struct i2c_adapter* i2c)
1250 {
1251 struct tda1004x_state *state;
1252
1253 /* allocate memory for the internal state */
1254 state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1255 if (!state)
1256 return NULL;
1257
1258 /* setup the state */
1259 state->config = config;
1260 state->i2c = i2c;
1261 state->demod_type = TDA1004X_DEMOD_TDA10045;
1262
1263 /* check if the demod is there */
1264 if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x25) {
1265 kfree(state);
1266 return NULL;
1267 }
1268
1269 /* create dvb_frontend */
1270 memcpy(&state->frontend.ops, &tda10045_ops, sizeof(struct dvb_frontend_ops));
1271 state->frontend.demodulator_priv = state;
1272 return &state->frontend;
1273 }
1274
1275 static struct dvb_frontend_ops tda10046_ops = {
1276 .info = {
1277 .name = "Philips TDA10046H DVB-T",
1278 .type = FE_OFDM,
1279 .frequency_min = 51000000,
1280 .frequency_max = 858000000,
1281 .frequency_stepsize = 166667,
1282 .caps =
1283 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1284 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1285 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1286 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1287 },
1288
1289 .release = tda1004x_release,
1290
1291 .init = tda10046_init,
1292 .sleep = tda1004x_sleep,
1293 .write = tda1004x_write,
1294 .i2c_gate_ctrl = tda1004x_i2c_gate_ctrl,
1295
1296 .set_frontend = tda1004x_set_fe,
1297 .get_frontend = tda1004x_get_fe,
1298 .get_tune_settings = tda1004x_get_tune_settings,
1299
1300 .read_status = tda1004x_read_status,
1301 .read_ber = tda1004x_read_ber,
1302 .read_signal_strength = tda1004x_read_signal_strength,
1303 .read_snr = tda1004x_read_snr,
1304 .read_ucblocks = tda1004x_read_ucblocks,
1305 };
1306
1307 struct dvb_frontend* tda10046_attach(const struct tda1004x_config* config,
1308 struct i2c_adapter* i2c)
1309 {
1310 struct tda1004x_state *state;
1311
1312 /* allocate memory for the internal state */
1313 state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1314 if (!state)
1315 return NULL;
1316
1317 /* setup the state */
1318 state->config = config;
1319 state->i2c = i2c;
1320 state->demod_type = TDA1004X_DEMOD_TDA10046;
1321
1322 /* check if the demod is there */
1323 if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x46) {
1324 kfree(state);
1325 return NULL;
1326 }
1327
1328 /* create dvb_frontend */
1329 memcpy(&state->frontend.ops, &tda10046_ops, sizeof(struct dvb_frontend_ops));
1330 state->frontend.demodulator_priv = state;
1331 return &state->frontend;
1332 }
1333
1334 module_param(debug, int, 0644);
1335 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
1336
1337 MODULE_DESCRIPTION("Philips TDA10045H & TDA10046H DVB-T Demodulator");
1338 MODULE_AUTHOR("Andrew de Quincey & Robert Schlabbach");
1339 MODULE_LICENSE("GPL");
1340
1341 EXPORT_SYMBOL(tda10045_attach);
1342 EXPORT_SYMBOL(tda10046_attach);
WRT350N Kernel Patches