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Merge git://git.kernel.org/pub/scm/linux/kernel/git/rusty/linux-2.6-for-linus
[wrt350n-kernel.git] / drivers / net / sky2.c
blob54c662690f65482b613954918ce499121a84ea61
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
34 #include <linux/ip.h>
35 #include <net/ip.h>
36 #include <linux/tcp.h>
37 #include <linux/in.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/debugfs.h>
43 #include <linux/mii.h>
44
45 #include <asm/irq.h>
46
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
49 #endif
50
51 #include "sky2.h"
52
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "1.21"
55 #define PFX DRV_NAME " "
56
57 /*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
60 * similar to Tigon3.
61 */
62
63 #define RX_LE_SIZE 1024
64 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
65 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
66 #define RX_DEF_PENDING RX_MAX_PENDING
67
68 #define TX_RING_SIZE 512
69 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
70 #define TX_MIN_PENDING 64
71 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
72
73 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
74 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
75 #define TX_WATCHDOG (5 * HZ)
76 #define NAPI_WEIGHT 64
77 #define PHY_RETRIES 1000
78
79 #define SKY2_EEPROM_MAGIC 0x9955aabb
80
81
82 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
83
84 static const u32 default_msg =
85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
88
89 static int debug = -1; /* defaults above */
90 module_param(debug, int, 0);
91 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92
93 static int copybreak __read_mostly = 128;
94 module_param(copybreak, int, 0);
95 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96
97 static int disable_msi = 0;
98 module_param(disable_msi, int, 0);
99 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100
101 static const struct pci_device_id sky2_id_table[] = {
102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
139 { 0 }
140 };
141
142 MODULE_DEVICE_TABLE(pci, sky2_id_table);
143
144 /* Avoid conditionals by using array */
145 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
146 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
147 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
148
149 /* This driver supports yukon2 chipset only */
150 static const char *yukon2_name[] = {
151 "XL", /* 0xb3 */
152 "EC Ultra", /* 0xb4 */
153 "Extreme", /* 0xb5 */
154 "EC", /* 0xb6 */
155 "FE", /* 0xb7 */
156 "FE+", /* 0xb8 */
157 };
158
159 static void sky2_set_multicast(struct net_device *dev);
160
161 /* Access to PHY via serial interconnect */
162 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
163 {
164 int i;
165
166 gma_write16(hw, port, GM_SMI_DATA, val);
167 gma_write16(hw, port, GM_SMI_CTRL,
168 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
169
170 for (i = 0; i < PHY_RETRIES; i++) {
171 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
172 if (ctrl == 0xffff)
173 goto io_error;
174
175 if (!(ctrl & GM_SMI_CT_BUSY))
176 return 0;
177
178 udelay(10);
179 }
180
181 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
182 return -ETIMEDOUT;
183
184 io_error:
185 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
186 return -EIO;
187 }
188
189 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
190 {
191 int i;
192
193 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
194 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
195
196 for (i = 0; i < PHY_RETRIES; i++) {
197 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
198 if (ctrl == 0xffff)
199 goto io_error;
200
201 if (ctrl & GM_SMI_CT_RD_VAL) {
202 *val = gma_read16(hw, port, GM_SMI_DATA);
203 return 0;
204 }
205
206 udelay(10);
207 }
208
209 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
210 return -ETIMEDOUT;
211 io_error:
212 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
213 return -EIO;
214 }
215
216 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
217 {
218 u16 v;
219 __gm_phy_read(hw, port, reg, &v);
220 return v;
221 }
222
223
224 static void sky2_power_on(struct sky2_hw *hw)
225 {
226 /* switch power to VCC (WA for VAUX problem) */
227 sky2_write8(hw, B0_POWER_CTRL,
228 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
229
230 /* disable Core Clock Division, */
231 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
232
233 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
234 /* enable bits are inverted */
235 sky2_write8(hw, B2_Y2_CLK_GATE,
236 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
237 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
238 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
239 else
240 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
241
242 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
243 u32 reg;
244
245 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
246
247 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
248 /* set all bits to 0 except bits 15..12 and 8 */
249 reg &= P_ASPM_CONTROL_MSK;
250 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
251
252 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
253 /* set all bits to 0 except bits 28 & 27 */
254 reg &= P_CTL_TIM_VMAIN_AV_MSK;
255 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
256
257 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
258
259 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
260 reg = sky2_read32(hw, B2_GP_IO);
261 reg |= GLB_GPIO_STAT_RACE_DIS;
262 sky2_write32(hw, B2_GP_IO, reg);
263
264 sky2_read32(hw, B2_GP_IO);
265 }
266 }
267
268 static void sky2_power_aux(struct sky2_hw *hw)
269 {
270 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
271 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
272 else
273 /* enable bits are inverted */
274 sky2_write8(hw, B2_Y2_CLK_GATE,
275 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
276 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
277 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
278
279 /* switch power to VAUX */
280 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
281 sky2_write8(hw, B0_POWER_CTRL,
282 (PC_VAUX_ENA | PC_VCC_ENA |
283 PC_VAUX_ON | PC_VCC_OFF));
284 }
285
286 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
287 {
288 u16 reg;
289
290 /* disable all GMAC IRQ's */
291 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
292
293 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
294 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
295 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
296 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
297
298 reg = gma_read16(hw, port, GM_RX_CTRL);
299 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
300 gma_write16(hw, port, GM_RX_CTRL, reg);
301 }
302
303 /* flow control to advertise bits */
304 static const u16 copper_fc_adv[] = {
305 [FC_NONE] = 0,
306 [FC_TX] = PHY_M_AN_ASP,
307 [FC_RX] = PHY_M_AN_PC,
308 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
309 };
310
311 /* flow control to advertise bits when using 1000BaseX */
312 static const u16 fiber_fc_adv[] = {
313 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
314 [FC_TX] = PHY_M_P_ASYM_MD_X,
315 [FC_RX] = PHY_M_P_SYM_MD_X,
316 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
317 };
318
319 /* flow control to GMA disable bits */
320 static const u16 gm_fc_disable[] = {
321 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
322 [FC_TX] = GM_GPCR_FC_RX_DIS,
323 [FC_RX] = GM_GPCR_FC_TX_DIS,
324 [FC_BOTH] = 0,
325 };
326
327
328 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
329 {
330 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
331 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
332
333 if (sky2->autoneg == AUTONEG_ENABLE &&
334 !(hw->flags & SKY2_HW_NEWER_PHY)) {
335 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
336
337 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
338 PHY_M_EC_MAC_S_MSK);
339 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
340
341 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
342 if (hw->chip_id == CHIP_ID_YUKON_EC)
343 /* set downshift counter to 3x and enable downshift */
344 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
345 else
346 /* set master & slave downshift counter to 1x */
347 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
348
349 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
350 }
351
352 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
353 if (sky2_is_copper(hw)) {
354 if (!(hw->flags & SKY2_HW_GIGABIT)) {
355 /* enable automatic crossover */
356 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
357
358 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
359 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
360 u16 spec;
361
362 /* Enable Class A driver for FE+ A0 */
363 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
364 spec |= PHY_M_FESC_SEL_CL_A;
365 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
366 }
367 } else {
368 /* disable energy detect */
369 ctrl &= ~PHY_M_PC_EN_DET_MSK;
370
371 /* enable automatic crossover */
372 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
373
374 /* downshift on PHY 88E1112 and 88E1149 is changed */
375 if (sky2->autoneg == AUTONEG_ENABLE
376 && (hw->flags & SKY2_HW_NEWER_PHY)) {
377 /* set downshift counter to 3x and enable downshift */
378 ctrl &= ~PHY_M_PC_DSC_MSK;
379 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
380 }
381 }
382 } else {
383 /* workaround for deviation #4.88 (CRC errors) */
384 /* disable Automatic Crossover */
385
386 ctrl &= ~PHY_M_PC_MDIX_MSK;
387 }
388
389 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
390
391 /* special setup for PHY 88E1112 Fiber */
392 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
393 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
394
395 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
396 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
397 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
398 ctrl &= ~PHY_M_MAC_MD_MSK;
399 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
400 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
401
402 if (hw->pmd_type == 'P') {
403 /* select page 1 to access Fiber registers */
404 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
405
406 /* for SFP-module set SIGDET polarity to low */
407 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
408 ctrl |= PHY_M_FIB_SIGD_POL;
409 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
410 }
411
412 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
413 }
414
415 ctrl = PHY_CT_RESET;
416 ct1000 = 0;
417 adv = PHY_AN_CSMA;
418 reg = 0;
419
420 if (sky2->autoneg == AUTONEG_ENABLE) {
421 if (sky2_is_copper(hw)) {
422 if (sky2->advertising & ADVERTISED_1000baseT_Full)
423 ct1000 |= PHY_M_1000C_AFD;
424 if (sky2->advertising & ADVERTISED_1000baseT_Half)
425 ct1000 |= PHY_M_1000C_AHD;
426 if (sky2->advertising & ADVERTISED_100baseT_Full)
427 adv |= PHY_M_AN_100_FD;
428 if (sky2->advertising & ADVERTISED_100baseT_Half)
429 adv |= PHY_M_AN_100_HD;
430 if (sky2->advertising & ADVERTISED_10baseT_Full)
431 adv |= PHY_M_AN_10_FD;
432 if (sky2->advertising & ADVERTISED_10baseT_Half)
433 adv |= PHY_M_AN_10_HD;
434
435 adv |= copper_fc_adv[sky2->flow_mode];
436 } else { /* special defines for FIBER (88E1040S only) */
437 if (sky2->advertising & ADVERTISED_1000baseT_Full)
438 adv |= PHY_M_AN_1000X_AFD;
439 if (sky2->advertising & ADVERTISED_1000baseT_Half)
440 adv |= PHY_M_AN_1000X_AHD;
441
442 adv |= fiber_fc_adv[sky2->flow_mode];
443 }
444
445 /* Restart Auto-negotiation */
446 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
447 } else {
448 /* forced speed/duplex settings */
449 ct1000 = PHY_M_1000C_MSE;
450
451 /* Disable auto update for duplex flow control and speed */
452 reg |= GM_GPCR_AU_ALL_DIS;
453
454 switch (sky2->speed) {
455 case SPEED_1000:
456 ctrl |= PHY_CT_SP1000;
457 reg |= GM_GPCR_SPEED_1000;
458 break;
459 case SPEED_100:
460 ctrl |= PHY_CT_SP100;
461 reg |= GM_GPCR_SPEED_100;
462 break;
463 }
464
465 if (sky2->duplex == DUPLEX_FULL) {
466 reg |= GM_GPCR_DUP_FULL;
467 ctrl |= PHY_CT_DUP_MD;
468 } else if (sky2->speed < SPEED_1000)
469 sky2->flow_mode = FC_NONE;
470
471
472 reg |= gm_fc_disable[sky2->flow_mode];
473
474 /* Forward pause packets to GMAC? */
475 if (sky2->flow_mode & FC_RX)
476 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
477 else
478 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
479 }
480
481 gma_write16(hw, port, GM_GP_CTRL, reg);
482
483 if (hw->flags & SKY2_HW_GIGABIT)
484 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
485
486 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
487 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
488
489 /* Setup Phy LED's */
490 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
491 ledover = 0;
492
493 switch (hw->chip_id) {
494 case CHIP_ID_YUKON_FE:
495 /* on 88E3082 these bits are at 11..9 (shifted left) */
496 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
497
498 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
499
500 /* delete ACT LED control bits */
501 ctrl &= ~PHY_M_FELP_LED1_MSK;
502 /* change ACT LED control to blink mode */
503 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
504 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
505 break;
506
507 case CHIP_ID_YUKON_FE_P:
508 /* Enable Link Partner Next Page */
509 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
510 ctrl |= PHY_M_PC_ENA_LIP_NP;
511
512 /* disable Energy Detect and enable scrambler */
513 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
514 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
515
516 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
517 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
518 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
519 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
520
521 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
522 break;
523
524 case CHIP_ID_YUKON_XL:
525 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
526
527 /* select page 3 to access LED control register */
528 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
529
530 /* set LED Function Control register */
531 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
532 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
533 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
534 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
535 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
536
537 /* set Polarity Control register */
538 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
539 (PHY_M_POLC_LS1_P_MIX(4) |
540 PHY_M_POLC_IS0_P_MIX(4) |
541 PHY_M_POLC_LOS_CTRL(2) |
542 PHY_M_POLC_INIT_CTRL(2) |
543 PHY_M_POLC_STA1_CTRL(2) |
544 PHY_M_POLC_STA0_CTRL(2)));
545
546 /* restore page register */
547 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
548 break;
549
550 case CHIP_ID_YUKON_EC_U:
551 case CHIP_ID_YUKON_EX:
552 case CHIP_ID_YUKON_SUPR:
553 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
554
555 /* select page 3 to access LED control register */
556 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
557
558 /* set LED Function Control register */
559 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
560 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
561 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
562 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
563 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
564
565 /* set Blink Rate in LED Timer Control Register */
566 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
567 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
568 /* restore page register */
569 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
570 break;
571
572 default:
573 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
574 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
575
576 /* turn off the Rx LED (LED_RX) */
577 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
578 }
579
580 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
581 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
582 /* apply fixes in PHY AFE */
583 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
584
585 /* increase differential signal amplitude in 10BASE-T */
586 gm_phy_write(hw, port, 0x18, 0xaa99);
587 gm_phy_write(hw, port, 0x17, 0x2011);
588
589 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
590 gm_phy_write(hw, port, 0x18, 0xa204);
591 gm_phy_write(hw, port, 0x17, 0x2002);
592
593 /* set page register to 0 */
594 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
595 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
596 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
597 /* apply workaround for integrated resistors calibration */
598 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
599 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
600 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
601 /* no effect on Yukon-XL */
602 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
603
604 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
605 /* turn on 100 Mbps LED (LED_LINK100) */
606 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
607 }
608
609 if (ledover)
610 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
611
612 }
613
614 /* Enable phy interrupt on auto-negotiation complete (or link up) */
615 if (sky2->autoneg == AUTONEG_ENABLE)
616 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
617 else
618 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
619 }
620
621 static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
622 {
623 u32 reg1;
624 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
625 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
626
627 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
628 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
629 /* Turn on/off phy power saving */
630 if (onoff)
631 reg1 &= ~phy_power[port];
632 else
633 reg1 |= phy_power[port];
634
635 if (onoff && hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
636 reg1 |= coma_mode[port];
637
638 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
639 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
640 sky2_pci_read32(hw, PCI_DEV_REG1);
641
642 udelay(100);
643 }
644
645 /* Force a renegotiation */
646 static void sky2_phy_reinit(struct sky2_port *sky2)
647 {
648 spin_lock_bh(&sky2->phy_lock);
649 sky2_phy_init(sky2->hw, sky2->port);
650 spin_unlock_bh(&sky2->phy_lock);
651 }
652
653 /* Put device in state to listen for Wake On Lan */
654 static void sky2_wol_init(struct sky2_port *sky2)
655 {
656 struct sky2_hw *hw = sky2->hw;
657 unsigned port = sky2->port;
658 enum flow_control save_mode;
659 u16 ctrl;
660 u32 reg1;
661
662 /* Bring hardware out of reset */
663 sky2_write16(hw, B0_CTST, CS_RST_CLR);
664 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
665
666 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
667 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
668
669 /* Force to 10/100
670 * sky2_reset will re-enable on resume
671 */
672 save_mode = sky2->flow_mode;
673 ctrl = sky2->advertising;
674
675 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
676 sky2->flow_mode = FC_NONE;
677 sky2_phy_power(hw, port, 1);
678 sky2_phy_reinit(sky2);
679
680 sky2->flow_mode = save_mode;
681 sky2->advertising = ctrl;
682
683 /* Set GMAC to no flow control and auto update for speed/duplex */
684 gma_write16(hw, port, GM_GP_CTRL,
685 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
686 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
687
688 /* Set WOL address */
689 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
690 sky2->netdev->dev_addr, ETH_ALEN);
691
692 /* Turn on appropriate WOL control bits */
693 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
694 ctrl = 0;
695 if (sky2->wol & WAKE_PHY)
696 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
697 else
698 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
699
700 if (sky2->wol & WAKE_MAGIC)
701 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
702 else
703 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
704
705 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
706 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
707
708 /* Turn on legacy PCI-Express PME mode */
709 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
710 reg1 |= PCI_Y2_PME_LEGACY;
711 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
712
713 /* block receiver */
714 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
715
716 }
717
718 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
719 {
720 struct net_device *dev = hw->dev[port];
721
722 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
723 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
724 hw->chip_id == CHIP_ID_YUKON_FE_P ||
725 hw->chip_id == CHIP_ID_YUKON_SUPR) {
726 /* Yukon-Extreme B0 and further Extreme devices */
727 /* enable Store & Forward mode for TX */
728
729 if (dev->mtu <= ETH_DATA_LEN)
730 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
731 TX_JUMBO_DIS | TX_STFW_ENA);
732
733 else
734 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
735 TX_JUMBO_ENA| TX_STFW_ENA);
736 } else {
737 if (dev->mtu <= ETH_DATA_LEN)
738 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
739 else {
740 /* set Tx GMAC FIFO Almost Empty Threshold */
741 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
742 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
743
744 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
745
746 /* Can't do offload because of lack of store/forward */
747 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
748 }
749 }
750 }
751
752 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
753 {
754 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
755 u16 reg;
756 u32 rx_reg;
757 int i;
758 const u8 *addr = hw->dev[port]->dev_addr;
759
760 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
761 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
762
763 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
764
765 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
766 /* WA DEV_472 -- looks like crossed wires on port 2 */
767 /* clear GMAC 1 Control reset */
768 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
769 do {
770 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
771 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
772 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
773 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
774 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
775 }
776
777 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
778
779 /* Enable Transmit FIFO Underrun */
780 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
781
782 spin_lock_bh(&sky2->phy_lock);
783 sky2_phy_init(hw, port);
784 spin_unlock_bh(&sky2->phy_lock);
785
786 /* MIB clear */
787 reg = gma_read16(hw, port, GM_PHY_ADDR);
788 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
789
790 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
791 gma_read16(hw, port, i);
792 gma_write16(hw, port, GM_PHY_ADDR, reg);
793
794 /* transmit control */
795 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
796
797 /* receive control reg: unicast + multicast + no FCS */
798 gma_write16(hw, port, GM_RX_CTRL,
799 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
800
801 /* transmit flow control */
802 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
803
804 /* transmit parameter */
805 gma_write16(hw, port, GM_TX_PARAM,
806 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
807 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
808 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
809 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
810
811 /* serial mode register */
812 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
813 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
814
815 if (hw->dev[port]->mtu > ETH_DATA_LEN)
816 reg |= GM_SMOD_JUMBO_ENA;
817
818 gma_write16(hw, port, GM_SERIAL_MODE, reg);
819
820 /* virtual address for data */
821 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
822
823 /* physical address: used for pause frames */
824 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
825
826 /* ignore counter overflows */
827 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
828 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
829 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
830
831 /* Configure Rx MAC FIFO */
832 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
833 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
834 if (hw->chip_id == CHIP_ID_YUKON_EX ||
835 hw->chip_id == CHIP_ID_YUKON_FE_P)
836 rx_reg |= GMF_RX_OVER_ON;
837
838 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
839
840 if (hw->chip_id == CHIP_ID_YUKON_XL) {
841 /* Hardware errata - clear flush mask */
842 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
843 } else {
844 /* Flush Rx MAC FIFO on any flow control or error */
845 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
846 }
847
848 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
849 reg = RX_GMF_FL_THR_DEF + 1;
850 /* Another magic mystery workaround from sk98lin */
851 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
852 hw->chip_rev == CHIP_REV_YU_FE2_A0)
853 reg = 0x178;
854 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
855
856 /* Configure Tx MAC FIFO */
857 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
858 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
859
860 /* On chips without ram buffer, pause is controled by MAC level */
861 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
862 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
863 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
864
865 sky2_set_tx_stfwd(hw, port);
866 }
867
868 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
869 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
870 /* disable dynamic watermark */
871 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
872 reg &= ~TX_DYN_WM_ENA;
873 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
874 }
875 }
876
877 /* Assign Ram Buffer allocation to queue */
878 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
879 {
880 u32 end;
881
882 /* convert from K bytes to qwords used for hw register */
883 start *= 1024/8;
884 space *= 1024/8;
885 end = start + space - 1;
886
887 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
888 sky2_write32(hw, RB_ADDR(q, RB_START), start);
889 sky2_write32(hw, RB_ADDR(q, RB_END), end);
890 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
891 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
892
893 if (q == Q_R1 || q == Q_R2) {
894 u32 tp = space - space/4;
895
896 /* On receive queue's set the thresholds
897 * give receiver priority when > 3/4 full
898 * send pause when down to 2K
899 */
900 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
901 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
902
903 tp = space - 2048/8;
904 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
905 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
906 } else {
907 /* Enable store & forward on Tx queue's because
908 * Tx FIFO is only 1K on Yukon
909 */
910 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
911 }
912
913 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
914 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
915 }
916
917 /* Setup Bus Memory Interface */
918 static void sky2_qset(struct sky2_hw *hw, u16 q)
919 {
920 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
921 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
922 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
923 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
924 }
925
926 /* Setup prefetch unit registers. This is the interface between
927 * hardware and driver list elements
928 */
929 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
930 u64 addr, u32 last)
931 {
932 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
933 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
934 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
935 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
936 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
937 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
938
939 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
940 }
941
942 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
943 {
944 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
945
946 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
947 le->ctrl = 0;
948 return le;
949 }
950
951 static void tx_init(struct sky2_port *sky2)
952 {
953 struct sky2_tx_le *le;
954
955 sky2->tx_prod = sky2->tx_cons = 0;
956 sky2->tx_tcpsum = 0;
957 sky2->tx_last_mss = 0;
958
959 le = get_tx_le(sky2);
960 le->addr = 0;
961 le->opcode = OP_ADDR64 | HW_OWNER;
962 }
963
964 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
965 struct sky2_tx_le *le)
966 {
967 return sky2->tx_ring + (le - sky2->tx_le);
968 }
969
970 /* Update chip's next pointer */
971 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
972 {
973 /* Make sure write' to descriptors are complete before we tell hardware */
974 wmb();
975 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
976
977 /* Synchronize I/O on since next processor may write to tail */
978 mmiowb();
979 }
980
981
982 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
983 {
984 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
985 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
986 le->ctrl = 0;
987 return le;
988 }
989
990 /* Build description to hardware for one receive segment */
991 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
992 dma_addr_t map, unsigned len)
993 {
994 struct sky2_rx_le *le;
995
996 if (sizeof(dma_addr_t) > sizeof(u32)) {
997 le = sky2_next_rx(sky2);
998 le->addr = cpu_to_le32(upper_32_bits(map));
999 le->opcode = OP_ADDR64 | HW_OWNER;
1000 }
1001
1002 le = sky2_next_rx(sky2);
1003 le->addr = cpu_to_le32((u32) map);
1004 le->length = cpu_to_le16(len);
1005 le->opcode = op | HW_OWNER;
1006 }
1007
1008 /* Build description to hardware for one possibly fragmented skb */
1009 static void sky2_rx_submit(struct sky2_port *sky2,
1010 const struct rx_ring_info *re)
1011 {
1012 int i;
1013
1014 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1015
1016 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1017 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1018 }
1019
1020
1021 static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1022 unsigned size)
1023 {
1024 struct sk_buff *skb = re->skb;
1025 int i;
1026
1027 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1028 pci_unmap_len_set(re, data_size, size);
1029
1030 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1031 re->frag_addr[i] = pci_map_page(pdev,
1032 skb_shinfo(skb)->frags[i].page,
1033 skb_shinfo(skb)->frags[i].page_offset,
1034 skb_shinfo(skb)->frags[i].size,
1035 PCI_DMA_FROMDEVICE);
1036 }
1037
1038 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1039 {
1040 struct sk_buff *skb = re->skb;
1041 int i;
1042
1043 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1044 PCI_DMA_FROMDEVICE);
1045
1046 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1047 pci_unmap_page(pdev, re->frag_addr[i],
1048 skb_shinfo(skb)->frags[i].size,
1049 PCI_DMA_FROMDEVICE);
1050 }
1051
1052 /* Tell chip where to start receive checksum.
1053 * Actually has two checksums, but set both same to avoid possible byte
1054 * order problems.
1055 */
1056 static void rx_set_checksum(struct sky2_port *sky2)
1057 {
1058 struct sky2_rx_le *le = sky2_next_rx(sky2);
1059
1060 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1061 le->ctrl = 0;
1062 le->opcode = OP_TCPSTART | HW_OWNER;
1063
1064 sky2_write32(sky2->hw,
1065 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1066 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1067 }
1068
1069 /*
1070 * The RX Stop command will not work for Yukon-2 if the BMU does not
1071 * reach the end of packet and since we can't make sure that we have
1072 * incoming data, we must reset the BMU while it is not doing a DMA
1073 * transfer. Since it is possible that the RX path is still active,
1074 * the RX RAM buffer will be stopped first, so any possible incoming
1075 * data will not trigger a DMA. After the RAM buffer is stopped, the
1076 * BMU is polled until any DMA in progress is ended and only then it
1077 * will be reset.
1078 */
1079 static void sky2_rx_stop(struct sky2_port *sky2)
1080 {
1081 struct sky2_hw *hw = sky2->hw;
1082 unsigned rxq = rxqaddr[sky2->port];
1083 int i;
1084
1085 /* disable the RAM Buffer receive queue */
1086 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1087
1088 for (i = 0; i < 0xffff; i++)
1089 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1090 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1091 goto stopped;
1092
1093 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1094 sky2->netdev->name);
1095 stopped:
1096 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1097
1098 /* reset the Rx prefetch unit */
1099 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1100 mmiowb();
1101 }
1102
1103 /* Clean out receive buffer area, assumes receiver hardware stopped */
1104 static void sky2_rx_clean(struct sky2_port *sky2)
1105 {
1106 unsigned i;
1107
1108 memset(sky2->rx_le, 0, RX_LE_BYTES);
1109 for (i = 0; i < sky2->rx_pending; i++) {
1110 struct rx_ring_info *re = sky2->rx_ring + i;
1111
1112 if (re->skb) {
1113 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1114 kfree_skb(re->skb);
1115 re->skb = NULL;
1116 }
1117 }
1118 }
1119
1120 /* Basic MII support */
1121 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1122 {
1123 struct mii_ioctl_data *data = if_mii(ifr);
1124 struct sky2_port *sky2 = netdev_priv(dev);
1125 struct sky2_hw *hw = sky2->hw;
1126 int err = -EOPNOTSUPP;
1127
1128 if (!netif_running(dev))
1129 return -ENODEV; /* Phy still in reset */
1130
1131 switch (cmd) {
1132 case SIOCGMIIPHY:
1133 data->phy_id = PHY_ADDR_MARV;
1134
1135 /* fallthru */
1136 case SIOCGMIIREG: {
1137 u16 val = 0;
1138
1139 spin_lock_bh(&sky2->phy_lock);
1140 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1141 spin_unlock_bh(&sky2->phy_lock);
1142
1143 data->val_out = val;
1144 break;
1145 }
1146
1147 case SIOCSMIIREG:
1148 if (!capable(CAP_NET_ADMIN))
1149 return -EPERM;
1150
1151 spin_lock_bh(&sky2->phy_lock);
1152 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1153 data->val_in);
1154 spin_unlock_bh(&sky2->phy_lock);
1155 break;
1156 }
1157 return err;
1158 }
1159
1160 #ifdef SKY2_VLAN_TAG_USED
1161 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1162 {
1163 struct sky2_port *sky2 = netdev_priv(dev);
1164 struct sky2_hw *hw = sky2->hw;
1165 u16 port = sky2->port;
1166
1167 netif_tx_lock_bh(dev);
1168 napi_disable(&hw->napi);
1169
1170 sky2->vlgrp = grp;
1171 if (grp) {
1172 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1173 RX_VLAN_STRIP_ON);
1174 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1175 TX_VLAN_TAG_ON);
1176 } else {
1177 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1178 RX_VLAN_STRIP_OFF);
1179 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1180 TX_VLAN_TAG_OFF);
1181 }
1182
1183 sky2_read32(hw, B0_Y2_SP_LISR);
1184 napi_enable(&hw->napi);
1185 netif_tx_unlock_bh(dev);
1186 }
1187 #endif
1188
1189 /*
1190 * Allocate an skb for receiving. If the MTU is large enough
1191 * make the skb non-linear with a fragment list of pages.
1192 */
1193 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1194 {
1195 struct sk_buff *skb;
1196 int i;
1197
1198 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1199 unsigned char *start;
1200 /*
1201 * Workaround for a bug in FIFO that cause hang
1202 * if the FIFO if the receive buffer is not 64 byte aligned.
1203 * The buffer returned from netdev_alloc_skb is
1204 * aligned except if slab debugging is enabled.
1205 */
1206 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + 8);
1207 if (!skb)
1208 goto nomem;
1209 start = PTR_ALIGN(skb->data, 8);
1210 skb_reserve(skb, start - skb->data);
1211 } else {
1212 skb = netdev_alloc_skb(sky2->netdev,
1213 sky2->rx_data_size + NET_IP_ALIGN);
1214 if (!skb)
1215 goto nomem;
1216 skb_reserve(skb, NET_IP_ALIGN);
1217 }
1218
1219 for (i = 0; i < sky2->rx_nfrags; i++) {
1220 struct page *page = alloc_page(GFP_ATOMIC);
1221
1222 if (!page)
1223 goto free_partial;
1224 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1225 }
1226
1227 return skb;
1228 free_partial:
1229 kfree_skb(skb);
1230 nomem:
1231 return NULL;
1232 }
1233
1234 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1235 {
1236 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1237 }
1238
1239 /*
1240 * Allocate and setup receiver buffer pool.
1241 * Normal case this ends up creating one list element for skb
1242 * in the receive ring. Worst case if using large MTU and each
1243 * allocation falls on a different 64 bit region, that results
1244 * in 6 list elements per ring entry.
1245 * One element is used for checksum enable/disable, and one
1246 * extra to avoid wrap.
1247 */
1248 static int sky2_rx_start(struct sky2_port *sky2)
1249 {
1250 struct sky2_hw *hw = sky2->hw;
1251 struct rx_ring_info *re;
1252 unsigned rxq = rxqaddr[sky2->port];
1253 unsigned i, size, thresh;
1254
1255 sky2->rx_put = sky2->rx_next = 0;
1256 sky2_qset(hw, rxq);
1257
1258 /* On PCI express lowering the watermark gives better performance */
1259 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1260 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1261
1262 /* These chips have no ram buffer?
1263 * MAC Rx RAM Read is controlled by hardware */
1264 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1265 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1266 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1267 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1268
1269 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1270
1271 if (!(hw->flags & SKY2_HW_NEW_LE))
1272 rx_set_checksum(sky2);
1273
1274 /* Space needed for frame data + headers rounded up */
1275 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1276
1277 /* Stopping point for hardware truncation */
1278 thresh = (size - 8) / sizeof(u32);
1279
1280 sky2->rx_nfrags = size >> PAGE_SHIFT;
1281 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1282
1283 /* Compute residue after pages */
1284 size -= sky2->rx_nfrags << PAGE_SHIFT;
1285
1286 /* Optimize to handle small packets and headers */
1287 if (size < copybreak)
1288 size = copybreak;
1289 if (size < ETH_HLEN)
1290 size = ETH_HLEN;
1291
1292 sky2->rx_data_size = size;
1293
1294 /* Fill Rx ring */
1295 for (i = 0; i < sky2->rx_pending; i++) {
1296 re = sky2->rx_ring + i;
1297
1298 re->skb = sky2_rx_alloc(sky2);
1299 if (!re->skb)
1300 goto nomem;
1301
1302 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1303 sky2_rx_submit(sky2, re);
1304 }
1305
1306 /*
1307 * The receiver hangs if it receives frames larger than the
1308 * packet buffer. As a workaround, truncate oversize frames, but
1309 * the register is limited to 9 bits, so if you do frames > 2052
1310 * you better get the MTU right!
1311 */
1312 if (thresh > 0x1ff)
1313 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1314 else {
1315 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1316 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1317 }
1318
1319 /* Tell chip about available buffers */
1320 sky2_rx_update(sky2, rxq);
1321 return 0;
1322 nomem:
1323 sky2_rx_clean(sky2);
1324 return -ENOMEM;
1325 }
1326
1327 /* Bring up network interface. */
1328 static int sky2_up(struct net_device *dev)
1329 {
1330 struct sky2_port *sky2 = netdev_priv(dev);
1331 struct sky2_hw *hw = sky2->hw;
1332 unsigned port = sky2->port;
1333 u32 imask, ramsize;
1334 int cap, err = -ENOMEM;
1335 struct net_device *otherdev = hw->dev[sky2->port^1];
1336
1337 /*
1338 * On dual port PCI-X card, there is an problem where status
1339 * can be received out of order due to split transactions
1340 */
1341 if (otherdev && netif_running(otherdev) &&
1342 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1343 u16 cmd;
1344
1345 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1346 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1347 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1348
1349 }
1350
1351 if (netif_msg_ifup(sky2))
1352 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1353
1354 netif_carrier_off(dev);
1355
1356 /* must be power of 2 */
1357 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1358 TX_RING_SIZE *
1359 sizeof(struct sky2_tx_le),
1360 &sky2->tx_le_map);
1361 if (!sky2->tx_le)
1362 goto err_out;
1363
1364 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1365 GFP_KERNEL);
1366 if (!sky2->tx_ring)
1367 goto err_out;
1368
1369 tx_init(sky2);
1370
1371 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1372 &sky2->rx_le_map);
1373 if (!sky2->rx_le)
1374 goto err_out;
1375 memset(sky2->rx_le, 0, RX_LE_BYTES);
1376
1377 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1378 GFP_KERNEL);
1379 if (!sky2->rx_ring)
1380 goto err_out;
1381
1382 sky2_phy_power(hw, port, 1);
1383
1384 sky2_mac_init(hw, port);
1385
1386 /* Register is number of 4K blocks on internal RAM buffer. */
1387 ramsize = sky2_read8(hw, B2_E_0) * 4;
1388 if (ramsize > 0) {
1389 u32 rxspace;
1390
1391 hw->flags |= SKY2_HW_RAM_BUFFER;
1392 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1393 if (ramsize < 16)
1394 rxspace = ramsize / 2;
1395 else
1396 rxspace = 8 + (2*(ramsize - 16))/3;
1397
1398 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1399 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1400
1401 /* Make sure SyncQ is disabled */
1402 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1403 RB_RST_SET);
1404 }
1405
1406 sky2_qset(hw, txqaddr[port]);
1407
1408 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1409 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1410 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1411
1412 /* Set almost empty threshold */
1413 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1414 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1415 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1416
1417 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1418 TX_RING_SIZE - 1);
1419
1420 err = sky2_rx_start(sky2);
1421 if (err)
1422 goto err_out;
1423
1424 /* Enable interrupts from phy/mac for port */
1425 imask = sky2_read32(hw, B0_IMSK);
1426 imask |= portirq_msk[port];
1427 sky2_write32(hw, B0_IMSK, imask);
1428
1429 sky2_set_multicast(dev);
1430 return 0;
1431
1432 err_out:
1433 if (sky2->rx_le) {
1434 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1435 sky2->rx_le, sky2->rx_le_map);
1436 sky2->rx_le = NULL;
1437 }
1438 if (sky2->tx_le) {
1439 pci_free_consistent(hw->pdev,
1440 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1441 sky2->tx_le, sky2->tx_le_map);
1442 sky2->tx_le = NULL;
1443 }
1444 kfree(sky2->tx_ring);
1445 kfree(sky2->rx_ring);
1446
1447 sky2->tx_ring = NULL;
1448 sky2->rx_ring = NULL;
1449 return err;
1450 }
1451
1452 /* Modular subtraction in ring */
1453 static inline int tx_dist(unsigned tail, unsigned head)
1454 {
1455 return (head - tail) & (TX_RING_SIZE - 1);
1456 }
1457
1458 /* Number of list elements available for next tx */
1459 static inline int tx_avail(const struct sky2_port *sky2)
1460 {
1461 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1462 }
1463
1464 /* Estimate of number of transmit list elements required */
1465 static unsigned tx_le_req(const struct sk_buff *skb)
1466 {
1467 unsigned count;
1468
1469 count = sizeof(dma_addr_t) / sizeof(u32);
1470 count += skb_shinfo(skb)->nr_frags * count;
1471
1472 if (skb_is_gso(skb))
1473 ++count;
1474
1475 if (skb->ip_summed == CHECKSUM_PARTIAL)
1476 ++count;
1477
1478 return count;
1479 }
1480
1481 /*
1482 * Put one packet in ring for transmit.
1483 * A single packet can generate multiple list elements, and
1484 * the number of ring elements will probably be less than the number
1485 * of list elements used.
1486 */
1487 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1488 {
1489 struct sky2_port *sky2 = netdev_priv(dev);
1490 struct sky2_hw *hw = sky2->hw;
1491 struct sky2_tx_le *le = NULL;
1492 struct tx_ring_info *re;
1493 unsigned i, len;
1494 dma_addr_t mapping;
1495 u16 mss;
1496 u8 ctrl;
1497
1498 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1499 return NETDEV_TX_BUSY;
1500
1501 if (unlikely(netif_msg_tx_queued(sky2)))
1502 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1503 dev->name, sky2->tx_prod, skb->len);
1504
1505 len = skb_headlen(skb);
1506 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1507
1508 /* Send high bits if needed */
1509 if (sizeof(dma_addr_t) > sizeof(u32)) {
1510 le = get_tx_le(sky2);
1511 le->addr = cpu_to_le32(upper_32_bits(mapping));
1512 le->opcode = OP_ADDR64 | HW_OWNER;
1513 }
1514
1515 /* Check for TCP Segmentation Offload */
1516 mss = skb_shinfo(skb)->gso_size;
1517 if (mss != 0) {
1518
1519 if (!(hw->flags & SKY2_HW_NEW_LE))
1520 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1521
1522 if (mss != sky2->tx_last_mss) {
1523 le = get_tx_le(sky2);
1524 le->addr = cpu_to_le32(mss);
1525
1526 if (hw->flags & SKY2_HW_NEW_LE)
1527 le->opcode = OP_MSS | HW_OWNER;
1528 else
1529 le->opcode = OP_LRGLEN | HW_OWNER;
1530 sky2->tx_last_mss = mss;
1531 }
1532 }
1533
1534 ctrl = 0;
1535 #ifdef SKY2_VLAN_TAG_USED
1536 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1537 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1538 if (!le) {
1539 le = get_tx_le(sky2);
1540 le->addr = 0;
1541 le->opcode = OP_VLAN|HW_OWNER;
1542 } else
1543 le->opcode |= OP_VLAN;
1544 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1545 ctrl |= INS_VLAN;
1546 }
1547 #endif
1548
1549 /* Handle TCP checksum offload */
1550 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1551 /* On Yukon EX (some versions) encoding change. */
1552 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1553 ctrl |= CALSUM; /* auto checksum */
1554 else {
1555 const unsigned offset = skb_transport_offset(skb);
1556 u32 tcpsum;
1557
1558 tcpsum = offset << 16; /* sum start */
1559 tcpsum |= offset + skb->csum_offset; /* sum write */
1560
1561 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1562 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1563 ctrl |= UDPTCP;
1564
1565 if (tcpsum != sky2->tx_tcpsum) {
1566 sky2->tx_tcpsum = tcpsum;
1567
1568 le = get_tx_le(sky2);
1569 le->addr = cpu_to_le32(tcpsum);
1570 le->length = 0; /* initial checksum value */
1571 le->ctrl = 1; /* one packet */
1572 le->opcode = OP_TCPLISW | HW_OWNER;
1573 }
1574 }
1575 }
1576
1577 le = get_tx_le(sky2);
1578 le->addr = cpu_to_le32((u32) mapping);
1579 le->length = cpu_to_le16(len);
1580 le->ctrl = ctrl;
1581 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1582
1583 re = tx_le_re(sky2, le);
1584 re->skb = skb;
1585 pci_unmap_addr_set(re, mapaddr, mapping);
1586 pci_unmap_len_set(re, maplen, len);
1587
1588 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1589 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1590
1591 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1592 frag->size, PCI_DMA_TODEVICE);
1593
1594 if (sizeof(dma_addr_t) > sizeof(u32)) {
1595 le = get_tx_le(sky2);
1596 le->addr = cpu_to_le32(upper_32_bits(mapping));
1597 le->ctrl = 0;
1598 le->opcode = OP_ADDR64 | HW_OWNER;
1599 }
1600
1601 le = get_tx_le(sky2);
1602 le->addr = cpu_to_le32((u32) mapping);
1603 le->length = cpu_to_le16(frag->size);
1604 le->ctrl = ctrl;
1605 le->opcode = OP_BUFFER | HW_OWNER;
1606
1607 re = tx_le_re(sky2, le);
1608 re->skb = skb;
1609 pci_unmap_addr_set(re, mapaddr, mapping);
1610 pci_unmap_len_set(re, maplen, frag->size);
1611 }
1612
1613 le->ctrl |= EOP;
1614
1615 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1616 netif_stop_queue(dev);
1617
1618 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1619
1620 dev->trans_start = jiffies;
1621 return NETDEV_TX_OK;
1622 }
1623
1624 /*
1625 * Free ring elements from starting at tx_cons until "done"
1626 *
1627 * NB: the hardware will tell us about partial completion of multi-part
1628 * buffers so make sure not to free skb to early.
1629 */
1630 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1631 {
1632 struct net_device *dev = sky2->netdev;
1633 struct pci_dev *pdev = sky2->hw->pdev;
1634 unsigned idx;
1635
1636 BUG_ON(done >= TX_RING_SIZE);
1637
1638 for (idx = sky2->tx_cons; idx != done;
1639 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1640 struct sky2_tx_le *le = sky2->tx_le + idx;
1641 struct tx_ring_info *re = sky2->tx_ring + idx;
1642
1643 switch(le->opcode & ~HW_OWNER) {
1644 case OP_LARGESEND:
1645 case OP_PACKET:
1646 pci_unmap_single(pdev,
1647 pci_unmap_addr(re, mapaddr),
1648 pci_unmap_len(re, maplen),
1649 PCI_DMA_TODEVICE);
1650 break;
1651 case OP_BUFFER:
1652 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1653 pci_unmap_len(re, maplen),
1654 PCI_DMA_TODEVICE);
1655 break;
1656 }
1657
1658 if (le->ctrl & EOP) {
1659 if (unlikely(netif_msg_tx_done(sky2)))
1660 printk(KERN_DEBUG "%s: tx done %u\n",
1661 dev->name, idx);
1662
1663 dev->stats.tx_packets++;
1664 dev->stats.tx_bytes += re->skb->len;
1665
1666 dev_kfree_skb_any(re->skb);
1667 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
1668 }
1669 }
1670
1671 sky2->tx_cons = idx;
1672 smp_mb();
1673
1674 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1675 netif_wake_queue(dev);
1676 }
1677
1678 /* Cleanup all untransmitted buffers, assume transmitter not running */
1679 static void sky2_tx_clean(struct net_device *dev)
1680 {
1681 struct sky2_port *sky2 = netdev_priv(dev);
1682
1683 netif_tx_lock_bh(dev);
1684 sky2_tx_complete(sky2, sky2->tx_prod);
1685 netif_tx_unlock_bh(dev);
1686 }
1687
1688 /* Network shutdown */
1689 static int sky2_down(struct net_device *dev)
1690 {
1691 struct sky2_port *sky2 = netdev_priv(dev);
1692 struct sky2_hw *hw = sky2->hw;
1693 unsigned port = sky2->port;
1694 u16 ctrl;
1695 u32 imask;
1696
1697 /* Never really got started! */
1698 if (!sky2->tx_le)
1699 return 0;
1700
1701 if (netif_msg_ifdown(sky2))
1702 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1703
1704 /* Stop more packets from being queued */
1705 netif_stop_queue(dev);
1706
1707 /* Disable port IRQ */
1708 imask = sky2_read32(hw, B0_IMSK);
1709 imask &= ~portirq_msk[port];
1710 sky2_write32(hw, B0_IMSK, imask);
1711
1712 synchronize_irq(hw->pdev->irq);
1713
1714 sky2_gmac_reset(hw, port);
1715
1716 /* Stop transmitter */
1717 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1718 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1719
1720 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1721 RB_RST_SET | RB_DIS_OP_MD);
1722
1723 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1724 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1725 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1726
1727 /* Make sure no packets are pending */
1728 napi_synchronize(&hw->napi);
1729
1730 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1731
1732 /* Workaround shared GMAC reset */
1733 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1734 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1735 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1736
1737 /* Disable Force Sync bit and Enable Alloc bit */
1738 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1739 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1740
1741 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1742 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1743 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1744
1745 /* Reset the PCI FIFO of the async Tx queue */
1746 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1747 BMU_RST_SET | BMU_FIFO_RST);
1748
1749 /* Reset the Tx prefetch units */
1750 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1751 PREF_UNIT_RST_SET);
1752
1753 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1754
1755 sky2_rx_stop(sky2);
1756
1757 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1758 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1759
1760 sky2_phy_power(hw, port, 0);
1761
1762 netif_carrier_off(dev);
1763
1764 /* turn off LED's */
1765 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1766
1767 sky2_tx_clean(dev);
1768 sky2_rx_clean(sky2);
1769
1770 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1771 sky2->rx_le, sky2->rx_le_map);
1772 kfree(sky2->rx_ring);
1773
1774 pci_free_consistent(hw->pdev,
1775 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1776 sky2->tx_le, sky2->tx_le_map);
1777 kfree(sky2->tx_ring);
1778
1779 sky2->tx_le = NULL;
1780 sky2->rx_le = NULL;
1781
1782 sky2->rx_ring = NULL;
1783 sky2->tx_ring = NULL;
1784
1785 return 0;
1786 }
1787
1788 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1789 {
1790 if (hw->flags & SKY2_HW_FIBRE_PHY)
1791 return SPEED_1000;
1792
1793 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1794 if (aux & PHY_M_PS_SPEED_100)
1795 return SPEED_100;
1796 else
1797 return SPEED_10;
1798 }
1799
1800 switch (aux & PHY_M_PS_SPEED_MSK) {
1801 case PHY_M_PS_SPEED_1000:
1802 return SPEED_1000;
1803 case PHY_M_PS_SPEED_100:
1804 return SPEED_100;
1805 default:
1806 return SPEED_10;
1807 }
1808 }
1809
1810 static void sky2_link_up(struct sky2_port *sky2)
1811 {
1812 struct sky2_hw *hw = sky2->hw;
1813 unsigned port = sky2->port;
1814 u16 reg;
1815 static const char *fc_name[] = {
1816 [FC_NONE] = "none",
1817 [FC_TX] = "tx",
1818 [FC_RX] = "rx",
1819 [FC_BOTH] = "both",
1820 };
1821
1822 /* enable Rx/Tx */
1823 reg = gma_read16(hw, port, GM_GP_CTRL);
1824 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1825 gma_write16(hw, port, GM_GP_CTRL, reg);
1826
1827 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1828
1829 netif_carrier_on(sky2->netdev);
1830
1831 mod_timer(&hw->watchdog_timer, jiffies + 1);
1832
1833 /* Turn on link LED */
1834 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1835 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1836
1837 if (netif_msg_link(sky2))
1838 printk(KERN_INFO PFX
1839 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1840 sky2->netdev->name, sky2->speed,
1841 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1842 fc_name[sky2->flow_status]);
1843 }
1844
1845 static void sky2_link_down(struct sky2_port *sky2)
1846 {
1847 struct sky2_hw *hw = sky2->hw;
1848 unsigned port = sky2->port;
1849 u16 reg;
1850
1851 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1852
1853 reg = gma_read16(hw, port, GM_GP_CTRL);
1854 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1855 gma_write16(hw, port, GM_GP_CTRL, reg);
1856
1857 netif_carrier_off(sky2->netdev);
1858
1859 /* Turn on link LED */
1860 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1861
1862 if (netif_msg_link(sky2))
1863 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1864
1865 sky2_phy_init(hw, port);
1866 }
1867
1868 static enum flow_control sky2_flow(int rx, int tx)
1869 {
1870 if (rx)
1871 return tx ? FC_BOTH : FC_RX;
1872 else
1873 return tx ? FC_TX : FC_NONE;
1874 }
1875
1876 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1877 {
1878 struct sky2_hw *hw = sky2->hw;
1879 unsigned port = sky2->port;
1880 u16 advert, lpa;
1881
1882 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1883 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1884 if (lpa & PHY_M_AN_RF) {
1885 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1886 return -1;
1887 }
1888
1889 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1890 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1891 sky2->netdev->name);
1892 return -1;
1893 }
1894
1895 sky2->speed = sky2_phy_speed(hw, aux);
1896 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1897
1898 /* Since the pause result bits seem to in different positions on
1899 * different chips. look at registers.
1900 */
1901 if (hw->flags & SKY2_HW_FIBRE_PHY) {
1902 /* Shift for bits in fiber PHY */
1903 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1904 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1905
1906 if (advert & ADVERTISE_1000XPAUSE)
1907 advert |= ADVERTISE_PAUSE_CAP;
1908 if (advert & ADVERTISE_1000XPSE_ASYM)
1909 advert |= ADVERTISE_PAUSE_ASYM;
1910 if (lpa & LPA_1000XPAUSE)
1911 lpa |= LPA_PAUSE_CAP;
1912 if (lpa & LPA_1000XPAUSE_ASYM)
1913 lpa |= LPA_PAUSE_ASYM;
1914 }
1915
1916 sky2->flow_status = FC_NONE;
1917 if (advert & ADVERTISE_PAUSE_CAP) {
1918 if (lpa & LPA_PAUSE_CAP)
1919 sky2->flow_status = FC_BOTH;
1920 else if (advert & ADVERTISE_PAUSE_ASYM)
1921 sky2->flow_status = FC_RX;
1922 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1923 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1924 sky2->flow_status = FC_TX;
1925 }
1926
1927 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
1928 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
1929 sky2->flow_status = FC_NONE;
1930
1931 if (sky2->flow_status & FC_TX)
1932 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1933 else
1934 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1935
1936 return 0;
1937 }
1938
1939 /* Interrupt from PHY */
1940 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1941 {
1942 struct net_device *dev = hw->dev[port];
1943 struct sky2_port *sky2 = netdev_priv(dev);
1944 u16 istatus, phystat;
1945
1946 if (!netif_running(dev))
1947 return;
1948
1949 spin_lock(&sky2->phy_lock);
1950 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1951 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1952
1953 if (netif_msg_intr(sky2))
1954 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1955 sky2->netdev->name, istatus, phystat);
1956
1957 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
1958 if (sky2_autoneg_done(sky2, phystat) == 0)
1959 sky2_link_up(sky2);
1960 goto out;
1961 }
1962
1963 if (istatus & PHY_M_IS_LSP_CHANGE)
1964 sky2->speed = sky2_phy_speed(hw, phystat);
1965
1966 if (istatus & PHY_M_IS_DUP_CHANGE)
1967 sky2->duplex =
1968 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1969
1970 if (istatus & PHY_M_IS_LST_CHANGE) {
1971 if (phystat & PHY_M_PS_LINK_UP)
1972 sky2_link_up(sky2);
1973 else
1974 sky2_link_down(sky2);
1975 }
1976 out:
1977 spin_unlock(&sky2->phy_lock);
1978 }
1979
1980 /* Transmit timeout is only called if we are running, carrier is up
1981 * and tx queue is full (stopped).
1982 */
1983 static void sky2_tx_timeout(struct net_device *dev)
1984 {
1985 struct sky2_port *sky2 = netdev_priv(dev);
1986 struct sky2_hw *hw = sky2->hw;
1987
1988 if (netif_msg_timer(sky2))
1989 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1990
1991 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1992 dev->name, sky2->tx_cons, sky2->tx_prod,
1993 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1994 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
1995
1996 /* can't restart safely under softirq */
1997 schedule_work(&hw->restart_work);
1998 }
1999
2000 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2001 {
2002 struct sky2_port *sky2 = netdev_priv(dev);
2003 struct sky2_hw *hw = sky2->hw;
2004 unsigned port = sky2->port;
2005 int err;
2006 u16 ctl, mode;
2007 u32 imask;
2008
2009 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2010 return -EINVAL;
2011
2012 if (new_mtu > ETH_DATA_LEN &&
2013 (hw->chip_id == CHIP_ID_YUKON_FE ||
2014 hw->chip_id == CHIP_ID_YUKON_FE_P))
2015 return -EINVAL;
2016
2017 if (!netif_running(dev)) {
2018 dev->mtu = new_mtu;
2019 return 0;
2020 }
2021
2022 imask = sky2_read32(hw, B0_IMSK);
2023 sky2_write32(hw, B0_IMSK, 0);
2024
2025 dev->trans_start = jiffies; /* prevent tx timeout */
2026 netif_stop_queue(dev);
2027 napi_disable(&hw->napi);
2028
2029 synchronize_irq(hw->pdev->irq);
2030
2031 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2032 sky2_set_tx_stfwd(hw, port);
2033
2034 ctl = gma_read16(hw, port, GM_GP_CTRL);
2035 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2036 sky2_rx_stop(sky2);
2037 sky2_rx_clean(sky2);
2038
2039 dev->mtu = new_mtu;
2040
2041 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2042 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2043
2044 if (dev->mtu > ETH_DATA_LEN)
2045 mode |= GM_SMOD_JUMBO_ENA;
2046
2047 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2048
2049 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2050
2051 err = sky2_rx_start(sky2);
2052 sky2_write32(hw, B0_IMSK, imask);
2053
2054 sky2_read32(hw, B0_Y2_SP_LISR);
2055 napi_enable(&hw->napi);
2056
2057 if (err)
2058 dev_close(dev);
2059 else {
2060 gma_write16(hw, port, GM_GP_CTRL, ctl);
2061
2062 netif_wake_queue(dev);
2063 }
2064
2065 return err;
2066 }
2067
2068 /* For small just reuse existing skb for next receive */
2069 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2070 const struct rx_ring_info *re,
2071 unsigned length)
2072 {
2073 struct sk_buff *skb;
2074
2075 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2076 if (likely(skb)) {
2077 skb_reserve(skb, 2);
2078 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2079 length, PCI_DMA_FROMDEVICE);
2080 skb_copy_from_linear_data(re->skb, skb->data, length);
2081 skb->ip_summed = re->skb->ip_summed;
2082 skb->csum = re->skb->csum;
2083 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2084 length, PCI_DMA_FROMDEVICE);
2085 re->skb->ip_summed = CHECKSUM_NONE;
2086 skb_put(skb, length);
2087 }
2088 return skb;
2089 }
2090
2091 /* Adjust length of skb with fragments to match received data */
2092 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2093 unsigned int length)
2094 {
2095 int i, num_frags;
2096 unsigned int size;
2097
2098 /* put header into skb */
2099 size = min(length, hdr_space);
2100 skb->tail += size;
2101 skb->len += size;
2102 length -= size;
2103
2104 num_frags = skb_shinfo(skb)->nr_frags;
2105 for (i = 0; i < num_frags; i++) {
2106 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2107
2108 if (length == 0) {
2109 /* don't need this page */
2110 __free_page(frag->page);
2111 --skb_shinfo(skb)->nr_frags;
2112 } else {
2113 size = min(length, (unsigned) PAGE_SIZE);
2114
2115 frag->size = size;
2116 skb->data_len += size;
2117 skb->truesize += size;
2118 skb->len += size;
2119 length -= size;
2120 }
2121 }
2122 }
2123
2124 /* Normal packet - take skb from ring element and put in a new one */
2125 static struct sk_buff *receive_new(struct sky2_port *sky2,
2126 struct rx_ring_info *re,
2127 unsigned int length)
2128 {
2129 struct sk_buff *skb, *nskb;
2130 unsigned hdr_space = sky2->rx_data_size;
2131
2132 /* Don't be tricky about reusing pages (yet) */
2133 nskb = sky2_rx_alloc(sky2);
2134 if (unlikely(!nskb))
2135 return NULL;
2136
2137 skb = re->skb;
2138 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2139
2140 prefetch(skb->data);
2141 re->skb = nskb;
2142 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2143
2144 if (skb_shinfo(skb)->nr_frags)
2145 skb_put_frags(skb, hdr_space, length);
2146 else
2147 skb_put(skb, length);
2148 return skb;
2149 }
2150
2151 /*
2152 * Receive one packet.
2153 * For larger packets, get new buffer.
2154 */
2155 static struct sk_buff *sky2_receive(struct net_device *dev,
2156 u16 length, u32 status)
2157 {
2158 struct sky2_port *sky2 = netdev_priv(dev);
2159 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2160 struct sk_buff *skb = NULL;
2161 u16 count = (status & GMR_FS_LEN) >> 16;
2162
2163 #ifdef SKY2_VLAN_TAG_USED
2164 /* Account for vlan tag */
2165 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2166 count -= VLAN_HLEN;
2167 #endif
2168
2169 if (unlikely(netif_msg_rx_status(sky2)))
2170 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2171 dev->name, sky2->rx_next, status, length);
2172
2173 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2174 prefetch(sky2->rx_ring + sky2->rx_next);
2175
2176 /* This chip has hardware problems that generates bogus status.
2177 * So do only marginal checking and expect higher level protocols
2178 * to handle crap frames.
2179 */
2180 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2181 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2182 length != count)
2183 goto okay;
2184
2185 if (status & GMR_FS_ANY_ERR)
2186 goto error;
2187
2188 if (!(status & GMR_FS_RX_OK))
2189 goto resubmit;
2190
2191 /* if length reported by DMA does not match PHY, packet was truncated */
2192 if (length != count)
2193 goto len_error;
2194
2195 okay:
2196 if (length < copybreak)
2197 skb = receive_copy(sky2, re, length);
2198 else
2199 skb = receive_new(sky2, re, length);
2200 resubmit:
2201 sky2_rx_submit(sky2, re);
2202
2203 return skb;
2204
2205 len_error:
2206 /* Truncation of overlength packets
2207 causes PHY length to not match MAC length */
2208 ++dev->stats.rx_length_errors;
2209 if (netif_msg_rx_err(sky2) && net_ratelimit())
2210 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2211 dev->name, status, length);
2212 goto resubmit;
2213
2214 error:
2215 ++dev->stats.rx_errors;
2216 if (status & GMR_FS_RX_FF_OV) {
2217 dev->stats.rx_over_errors++;
2218 goto resubmit;
2219 }
2220
2221 if (netif_msg_rx_err(sky2) && net_ratelimit())
2222 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2223 dev->name, status, length);
2224
2225 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2226 dev->stats.rx_length_errors++;
2227 if (status & GMR_FS_FRAGMENT)
2228 dev->stats.rx_frame_errors++;
2229 if (status & GMR_FS_CRC_ERR)
2230 dev->stats.rx_crc_errors++;
2231
2232 goto resubmit;
2233 }
2234
2235 /* Transmit complete */
2236 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2237 {
2238 struct sky2_port *sky2 = netdev_priv(dev);
2239
2240 if (netif_running(dev)) {
2241 netif_tx_lock(dev);
2242 sky2_tx_complete(sky2, last);
2243 netif_tx_unlock(dev);
2244 }
2245 }
2246
2247 /* Process status response ring */
2248 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2249 {
2250 int work_done = 0;
2251 unsigned rx[2] = { 0, 0 };
2252
2253 rmb();
2254 do {
2255 struct sky2_port *sky2;
2256 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2257 unsigned port;
2258 struct net_device *dev;
2259 struct sk_buff *skb;
2260 u32 status;
2261 u16 length;
2262 u8 opcode = le->opcode;
2263
2264 if (!(opcode & HW_OWNER))
2265 break;
2266
2267 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2268
2269 port = le->css & CSS_LINK_BIT;
2270 dev = hw->dev[port];
2271 sky2 = netdev_priv(dev);
2272 length = le16_to_cpu(le->length);
2273 status = le32_to_cpu(le->status);
2274
2275 le->opcode = 0;
2276 switch (opcode & ~HW_OWNER) {
2277 case OP_RXSTAT:
2278 ++rx[port];
2279 skb = sky2_receive(dev, length, status);
2280 if (unlikely(!skb)) {
2281 dev->stats.rx_dropped++;
2282 break;
2283 }
2284
2285 /* This chip reports checksum status differently */
2286 if (hw->flags & SKY2_HW_NEW_LE) {
2287 if (sky2->rx_csum &&
2288 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2289 (le->css & CSS_TCPUDPCSOK))
2290 skb->ip_summed = CHECKSUM_UNNECESSARY;
2291 else
2292 skb->ip_summed = CHECKSUM_NONE;
2293 }
2294
2295 skb->protocol = eth_type_trans(skb, dev);
2296 dev->stats.rx_packets++;
2297 dev->stats.rx_bytes += skb->len;
2298 dev->last_rx = jiffies;
2299
2300 #ifdef SKY2_VLAN_TAG_USED
2301 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2302 vlan_hwaccel_receive_skb(skb,
2303 sky2->vlgrp,
2304 be16_to_cpu(sky2->rx_tag));
2305 } else
2306 #endif
2307 netif_receive_skb(skb);
2308
2309 /* Stop after net poll weight */
2310 if (++work_done >= to_do)
2311 goto exit_loop;
2312 break;
2313
2314 #ifdef SKY2_VLAN_TAG_USED
2315 case OP_RXVLAN:
2316 sky2->rx_tag = length;
2317 break;
2318
2319 case OP_RXCHKSVLAN:
2320 sky2->rx_tag = length;
2321 /* fall through */
2322 #endif
2323 case OP_RXCHKS:
2324 if (!sky2->rx_csum)
2325 break;
2326
2327 /* If this happens then driver assuming wrong format */
2328 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2329 if (net_ratelimit())
2330 printk(KERN_NOTICE "%s: unexpected"
2331 " checksum status\n",
2332 dev->name);
2333 break;
2334 }
2335
2336 /* Both checksum counters are programmed to start at
2337 * the same offset, so unless there is a problem they
2338 * should match. This failure is an early indication that
2339 * hardware receive checksumming won't work.
2340 */
2341 if (likely(status >> 16 == (status & 0xffff))) {
2342 skb = sky2->rx_ring[sky2->rx_next].skb;
2343 skb->ip_summed = CHECKSUM_COMPLETE;
2344 skb->csum = status & 0xffff;
2345 } else {
2346 printk(KERN_NOTICE PFX "%s: hardware receive "
2347 "checksum problem (status = %#x)\n",
2348 dev->name, status);
2349 sky2->rx_csum = 0;
2350 sky2_write32(sky2->hw,
2351 Q_ADDR(rxqaddr[port], Q_CSR),
2352 BMU_DIS_RX_CHKSUM);
2353 }
2354 break;
2355
2356 case OP_TXINDEXLE:
2357 /* TX index reports status for both ports */
2358 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2359 sky2_tx_done(hw->dev[0], status & 0xfff);
2360 if (hw->dev[1])
2361 sky2_tx_done(hw->dev[1],
2362 ((status >> 24) & 0xff)
2363 | (u16)(length & 0xf) << 8);
2364 break;
2365
2366 default:
2367 if (net_ratelimit())
2368 printk(KERN_WARNING PFX
2369 "unknown status opcode 0x%x\n", opcode);
2370 }
2371 } while (hw->st_idx != idx);
2372
2373 /* Fully processed status ring so clear irq */
2374 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2375
2376 exit_loop:
2377 if (rx[0])
2378 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
2379
2380 if (rx[1])
2381 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
2382
2383 return work_done;
2384 }
2385
2386 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2387 {
2388 struct net_device *dev = hw->dev[port];
2389
2390 if (net_ratelimit())
2391 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2392 dev->name, status);
2393
2394 if (status & Y2_IS_PAR_RD1) {
2395 if (net_ratelimit())
2396 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2397 dev->name);
2398 /* Clear IRQ */
2399 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2400 }
2401
2402 if (status & Y2_IS_PAR_WR1) {
2403 if (net_ratelimit())
2404 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2405 dev->name);
2406
2407 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2408 }
2409
2410 if (status & Y2_IS_PAR_MAC1) {
2411 if (net_ratelimit())
2412 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2413 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2414 }
2415
2416 if (status & Y2_IS_PAR_RX1) {
2417 if (net_ratelimit())
2418 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2419 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2420 }
2421
2422 if (status & Y2_IS_TCP_TXA1) {
2423 if (net_ratelimit())
2424 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2425 dev->name);
2426 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2427 }
2428 }
2429
2430 static void sky2_hw_intr(struct sky2_hw *hw)
2431 {
2432 struct pci_dev *pdev = hw->pdev;
2433 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2434 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2435
2436 status &= hwmsk;
2437
2438 if (status & Y2_IS_TIST_OV)
2439 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2440
2441 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2442 u16 pci_err;
2443
2444 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2445 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2446 if (net_ratelimit())
2447 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2448 pci_err);
2449
2450 sky2_pci_write16(hw, PCI_STATUS,
2451 pci_err | PCI_STATUS_ERROR_BITS);
2452 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2453 }
2454
2455 if (status & Y2_IS_PCI_EXP) {
2456 /* PCI-Express uncorrectable Error occurred */
2457 u32 err;
2458
2459 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2460 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2461 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2462 0xfffffffful);
2463 if (net_ratelimit())
2464 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2465
2466 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2467 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2468 }
2469
2470 if (status & Y2_HWE_L1_MASK)
2471 sky2_hw_error(hw, 0, status);
2472 status >>= 8;
2473 if (status & Y2_HWE_L1_MASK)
2474 sky2_hw_error(hw, 1, status);
2475 }
2476
2477 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2478 {
2479 struct net_device *dev = hw->dev[port];
2480 struct sky2_port *sky2 = netdev_priv(dev);
2481 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2482
2483 if (netif_msg_intr(sky2))
2484 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2485 dev->name, status);
2486
2487 if (status & GM_IS_RX_CO_OV)
2488 gma_read16(hw, port, GM_RX_IRQ_SRC);
2489
2490 if (status & GM_IS_TX_CO_OV)
2491 gma_read16(hw, port, GM_TX_IRQ_SRC);
2492
2493 if (status & GM_IS_RX_FF_OR) {
2494 ++dev->stats.rx_fifo_errors;
2495 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2496 }
2497
2498 if (status & GM_IS_TX_FF_UR) {
2499 ++dev->stats.tx_fifo_errors;
2500 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2501 }
2502 }
2503
2504 /* This should never happen it is a bug. */
2505 static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2506 u16 q, unsigned ring_size)
2507 {
2508 struct net_device *dev = hw->dev[port];
2509 struct sky2_port *sky2 = netdev_priv(dev);
2510 unsigned idx;
2511 const u64 *le = (q == Q_R1 || q == Q_R2)
2512 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
2513
2514 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2515 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2516 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2517 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2518
2519 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2520 }
2521
2522 static int sky2_rx_hung(struct net_device *dev)
2523 {
2524 struct sky2_port *sky2 = netdev_priv(dev);
2525 struct sky2_hw *hw = sky2->hw;
2526 unsigned port = sky2->port;
2527 unsigned rxq = rxqaddr[port];
2528 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2529 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2530 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2531 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2532
2533 /* If idle and MAC or PCI is stuck */
2534 if (sky2->check.last == dev->last_rx &&
2535 ((mac_rp == sky2->check.mac_rp &&
2536 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2537 /* Check if the PCI RX hang */
2538 (fifo_rp == sky2->check.fifo_rp &&
2539 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2540 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2541 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2542 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2543 return 1;
2544 } else {
2545 sky2->check.last = dev->last_rx;
2546 sky2->check.mac_rp = mac_rp;
2547 sky2->check.mac_lev = mac_lev;
2548 sky2->check.fifo_rp = fifo_rp;
2549 sky2->check.fifo_lev = fifo_lev;
2550 return 0;
2551 }
2552 }
2553
2554 static void sky2_watchdog(unsigned long arg)
2555 {
2556 struct sky2_hw *hw = (struct sky2_hw *) arg;
2557
2558 /* Check for lost IRQ once a second */
2559 if (sky2_read32(hw, B0_ISRC)) {
2560 napi_schedule(&hw->napi);
2561 } else {
2562 int i, active = 0;
2563
2564 for (i = 0; i < hw->ports; i++) {
2565 struct net_device *dev = hw->dev[i];
2566 if (!netif_running(dev))
2567 continue;
2568 ++active;
2569
2570 /* For chips with Rx FIFO, check if stuck */
2571 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2572 sky2_rx_hung(dev)) {
2573 pr_info(PFX "%s: receiver hang detected\n",
2574 dev->name);
2575 schedule_work(&hw->restart_work);
2576 return;
2577 }
2578 }
2579
2580 if (active == 0)
2581 return;
2582 }
2583
2584 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2585 }
2586
2587 /* Hardware/software error handling */
2588 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2589 {
2590 if (net_ratelimit())
2591 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2592
2593 if (status & Y2_IS_HW_ERR)
2594 sky2_hw_intr(hw);
2595
2596 if (status & Y2_IS_IRQ_MAC1)
2597 sky2_mac_intr(hw, 0);
2598
2599 if (status & Y2_IS_IRQ_MAC2)
2600 sky2_mac_intr(hw, 1);
2601
2602 if (status & Y2_IS_CHK_RX1)
2603 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
2604
2605 if (status & Y2_IS_CHK_RX2)
2606 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
2607
2608 if (status & Y2_IS_CHK_TXA1)
2609 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
2610
2611 if (status & Y2_IS_CHK_TXA2)
2612 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2613 }
2614
2615 static int sky2_poll(struct napi_struct *napi, int work_limit)
2616 {
2617 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2618 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2619 int work_done = 0;
2620 u16 idx;
2621
2622 if (unlikely(status & Y2_IS_ERROR))
2623 sky2_err_intr(hw, status);
2624
2625 if (status & Y2_IS_IRQ_PHY1)
2626 sky2_phy_intr(hw, 0);
2627
2628 if (status & Y2_IS_IRQ_PHY2)
2629 sky2_phy_intr(hw, 1);
2630
2631 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2632 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
2633
2634 if (work_done >= work_limit)
2635 goto done;
2636 }
2637
2638 /* Bug/Errata workaround?
2639 * Need to kick the TX irq moderation timer.
2640 */
2641 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2642 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2643 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2644 }
2645 napi_complete(napi);
2646 sky2_read32(hw, B0_Y2_SP_LISR);
2647 done:
2648
2649 return work_done;
2650 }
2651
2652 static irqreturn_t sky2_intr(int irq, void *dev_id)
2653 {
2654 struct sky2_hw *hw = dev_id;
2655 u32 status;
2656
2657 /* Reading this mask interrupts as side effect */
2658 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2659 if (status == 0 || status == ~0)
2660 return IRQ_NONE;
2661
2662 prefetch(&hw->st_le[hw->st_idx]);
2663
2664 napi_schedule(&hw->napi);
2665
2666 return IRQ_HANDLED;
2667 }
2668
2669 #ifdef CONFIG_NET_POLL_CONTROLLER
2670 static void sky2_netpoll(struct net_device *dev)
2671 {
2672 struct sky2_port *sky2 = netdev_priv(dev);
2673
2674 napi_schedule(&sky2->hw->napi);
2675 }
2676 #endif
2677
2678 /* Chip internal frequency for clock calculations */
2679 static u32 sky2_mhz(const struct sky2_hw *hw)
2680 {
2681 switch (hw->chip_id) {
2682 case CHIP_ID_YUKON_EC:
2683 case CHIP_ID_YUKON_EC_U:
2684 case CHIP_ID_YUKON_EX:
2685 case CHIP_ID_YUKON_SUPR:
2686 return 125;
2687
2688 case CHIP_ID_YUKON_FE:
2689 return 100;
2690
2691 case CHIP_ID_YUKON_FE_P:
2692 return 50;
2693
2694 case CHIP_ID_YUKON_XL:
2695 return 156;
2696
2697 default:
2698 BUG();
2699 }
2700 }
2701
2702 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2703 {
2704 return sky2_mhz(hw) * us;
2705 }
2706
2707 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2708 {
2709 return clk / sky2_mhz(hw);
2710 }
2711
2712
2713 static int __devinit sky2_init(struct sky2_hw *hw)
2714 {
2715 u8 t8;
2716
2717 /* Enable all clocks and check for bad PCI access */
2718 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2719
2720 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2721
2722 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2723 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2724
2725 switch(hw->chip_id) {
2726 case CHIP_ID_YUKON_XL:
2727 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
2728 break;
2729
2730 case CHIP_ID_YUKON_EC_U:
2731 hw->flags = SKY2_HW_GIGABIT
2732 | SKY2_HW_NEWER_PHY
2733 | SKY2_HW_ADV_POWER_CTL;
2734 break;
2735
2736 case CHIP_ID_YUKON_EX:
2737 hw->flags = SKY2_HW_GIGABIT
2738 | SKY2_HW_NEWER_PHY
2739 | SKY2_HW_NEW_LE
2740 | SKY2_HW_ADV_POWER_CTL;
2741
2742 /* New transmit checksum */
2743 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2744 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2745 break;
2746
2747 case CHIP_ID_YUKON_EC:
2748 /* This rev is really old, and requires untested workarounds */
2749 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2750 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2751 return -EOPNOTSUPP;
2752 }
2753 hw->flags = SKY2_HW_GIGABIT;
2754 break;
2755
2756 case CHIP_ID_YUKON_FE:
2757 break;
2758
2759 case CHIP_ID_YUKON_FE_P:
2760 hw->flags = SKY2_HW_NEWER_PHY
2761 | SKY2_HW_NEW_LE
2762 | SKY2_HW_AUTO_TX_SUM
2763 | SKY2_HW_ADV_POWER_CTL;
2764 break;
2765
2766 case CHIP_ID_YUKON_SUPR:
2767 hw->flags = SKY2_HW_GIGABIT
2768 | SKY2_HW_NEWER_PHY
2769 | SKY2_HW_NEW_LE
2770 | SKY2_HW_AUTO_TX_SUM
2771 | SKY2_HW_ADV_POWER_CTL;
2772 break;
2773
2774 default:
2775 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2776 hw->chip_id);
2777 return -EOPNOTSUPP;
2778 }
2779
2780 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2781 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2782 hw->flags |= SKY2_HW_FIBRE_PHY;
2783
2784
2785 hw->ports = 1;
2786 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2787 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2788 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2789 ++hw->ports;
2790 }
2791
2792 return 0;
2793 }
2794
2795 static void sky2_reset(struct sky2_hw *hw)
2796 {
2797 struct pci_dev *pdev = hw->pdev;
2798 u16 status;
2799 int i, cap;
2800 u32 hwe_mask = Y2_HWE_ALL_MASK;
2801
2802 /* disable ASF */
2803 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2804 status = sky2_read16(hw, HCU_CCSR);
2805 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2806 HCU_CCSR_UC_STATE_MSK);
2807 sky2_write16(hw, HCU_CCSR, status);
2808 } else
2809 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2810 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2811
2812 /* do a SW reset */
2813 sky2_write8(hw, B0_CTST, CS_RST_SET);
2814 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2815
2816 /* allow writes to PCI config */
2817 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2818
2819 /* clear PCI errors, if any */
2820 status = sky2_pci_read16(hw, PCI_STATUS);
2821 status |= PCI_STATUS_ERROR_BITS;
2822 sky2_pci_write16(hw, PCI_STATUS, status);
2823
2824 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2825
2826 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2827 if (cap) {
2828 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2829 0xfffffffful);
2830
2831 /* If error bit is stuck on ignore it */
2832 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2833 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
2834 else
2835 hwe_mask |= Y2_IS_PCI_EXP;
2836 }
2837
2838 sky2_power_on(hw);
2839 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2840
2841 for (i = 0; i < hw->ports; i++) {
2842 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2843 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2844
2845 if (hw->chip_id == CHIP_ID_YUKON_EX ||
2846 hw->chip_id == CHIP_ID_YUKON_SUPR)
2847 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2848 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2849 | GMC_BYP_RETR_ON);
2850 }
2851
2852 /* Clear I2C IRQ noise */
2853 sky2_write32(hw, B2_I2C_IRQ, 1);
2854
2855 /* turn off hardware timer (unused) */
2856 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2857 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2858
2859 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2860
2861 /* Turn off descriptor polling */
2862 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2863
2864 /* Turn off receive timestamp */
2865 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2866 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2867
2868 /* enable the Tx Arbiters */
2869 for (i = 0; i < hw->ports; i++)
2870 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2871
2872 /* Initialize ram interface */
2873 for (i = 0; i < hw->ports; i++) {
2874 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2875
2876 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2877 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2878 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2879 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2880 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2881 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2882 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2883 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2884 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2885 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2886 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2887 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2888 }
2889
2890 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
2891
2892 for (i = 0; i < hw->ports; i++)
2893 sky2_gmac_reset(hw, i);
2894
2895 memset(hw->st_le, 0, STATUS_LE_BYTES);
2896 hw->st_idx = 0;
2897
2898 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2899 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2900
2901 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2902 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2903
2904 /* Set the list last index */
2905 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2906
2907 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2908 sky2_write8(hw, STAT_FIFO_WM, 16);
2909
2910 /* set Status-FIFO ISR watermark */
2911 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2912 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2913 else
2914 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2915
2916 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2917 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2918 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2919
2920 /* enable status unit */
2921 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2922
2923 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2924 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2925 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2926 }
2927
2928 static void sky2_restart(struct work_struct *work)
2929 {
2930 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2931 struct net_device *dev;
2932 int i, err;
2933
2934 rtnl_lock();
2935 for (i = 0; i < hw->ports; i++) {
2936 dev = hw->dev[i];
2937 if (netif_running(dev))
2938 sky2_down(dev);
2939 }
2940
2941 napi_disable(&hw->napi);
2942 sky2_write32(hw, B0_IMSK, 0);
2943 sky2_reset(hw);
2944 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2945 napi_enable(&hw->napi);
2946
2947 for (i = 0; i < hw->ports; i++) {
2948 dev = hw->dev[i];
2949 if (netif_running(dev)) {
2950 err = sky2_up(dev);
2951 if (err) {
2952 printk(KERN_INFO PFX "%s: could not restart %d\n",
2953 dev->name, err);
2954 dev_close(dev);
2955 }
2956 }
2957 }
2958
2959 rtnl_unlock();
2960 }
2961
2962 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2963 {
2964 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2965 }
2966
2967 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2968 {
2969 const struct sky2_port *sky2 = netdev_priv(dev);
2970
2971 wol->supported = sky2_wol_supported(sky2->hw);
2972 wol->wolopts = sky2->wol;
2973 }
2974
2975 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2976 {
2977 struct sky2_port *sky2 = netdev_priv(dev);
2978 struct sky2_hw *hw = sky2->hw;
2979
2980 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2981 return -EOPNOTSUPP;
2982
2983 sky2->wol = wol->wolopts;
2984
2985 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
2986 hw->chip_id == CHIP_ID_YUKON_EX ||
2987 hw->chip_id == CHIP_ID_YUKON_FE_P)
2988 sky2_write32(hw, B0_CTST, sky2->wol
2989 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2990
2991 if (!netif_running(dev))
2992 sky2_wol_init(sky2);
2993 return 0;
2994 }
2995
2996 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2997 {
2998 if (sky2_is_copper(hw)) {
2999 u32 modes = SUPPORTED_10baseT_Half
3000 | SUPPORTED_10baseT_Full
3001 | SUPPORTED_100baseT_Half
3002 | SUPPORTED_100baseT_Full
3003 | SUPPORTED_Autoneg | SUPPORTED_TP;
3004
3005 if (hw->flags & SKY2_HW_GIGABIT)
3006 modes |= SUPPORTED_1000baseT_Half
3007 | SUPPORTED_1000baseT_Full;
3008 return modes;
3009 } else
3010 return SUPPORTED_1000baseT_Half
3011 | SUPPORTED_1000baseT_Full
3012 | SUPPORTED_Autoneg
3013 | SUPPORTED_FIBRE;
3014 }
3015
3016 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3017 {
3018 struct sky2_port *sky2 = netdev_priv(dev);
3019 struct sky2_hw *hw = sky2->hw;
3020
3021 ecmd->transceiver = XCVR_INTERNAL;
3022 ecmd->supported = sky2_supported_modes(hw);
3023 ecmd->phy_address = PHY_ADDR_MARV;
3024 if (sky2_is_copper(hw)) {
3025 ecmd->port = PORT_TP;
3026 ecmd->speed = sky2->speed;
3027 } else {
3028 ecmd->speed = SPEED_1000;
3029 ecmd->port = PORT_FIBRE;
3030 }
3031
3032 ecmd->advertising = sky2->advertising;
3033 ecmd->autoneg = sky2->autoneg;
3034 ecmd->duplex = sky2->duplex;
3035 return 0;
3036 }
3037
3038 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3039 {
3040 struct sky2_port *sky2 = netdev_priv(dev);
3041 const struct sky2_hw *hw = sky2->hw;
3042 u32 supported = sky2_supported_modes(hw);
3043
3044 if (ecmd->autoneg == AUTONEG_ENABLE) {
3045 ecmd->advertising = supported;
3046 sky2->duplex = -1;
3047 sky2->speed = -1;
3048 } else {
3049 u32 setting;
3050
3051 switch (ecmd->speed) {
3052 case SPEED_1000:
3053 if (ecmd->duplex == DUPLEX_FULL)
3054 setting = SUPPORTED_1000baseT_Full;
3055 else if (ecmd->duplex == DUPLEX_HALF)
3056 setting = SUPPORTED_1000baseT_Half;
3057 else
3058 return -EINVAL;
3059 break;
3060 case SPEED_100:
3061 if (ecmd->duplex == DUPLEX_FULL)
3062 setting = SUPPORTED_100baseT_Full;
3063 else if (ecmd->duplex == DUPLEX_HALF)
3064 setting = SUPPORTED_100baseT_Half;
3065 else
3066 return -EINVAL;
3067 break;
3068
3069 case SPEED_10:
3070 if (ecmd->duplex == DUPLEX_FULL)
3071 setting = SUPPORTED_10baseT_Full;
3072 else if (ecmd->duplex == DUPLEX_HALF)
3073 setting = SUPPORTED_10baseT_Half;
3074 else
3075 return -EINVAL;
3076 break;
3077 default:
3078 return -EINVAL;
3079 }
3080
3081 if ((setting & supported) == 0)
3082 return -EINVAL;
3083
3084 sky2->speed = ecmd->speed;
3085 sky2->duplex = ecmd->duplex;
3086 }
3087
3088 sky2->autoneg = ecmd->autoneg;
3089 sky2->advertising = ecmd->advertising;
3090
3091 if (netif_running(dev)) {
3092 sky2_phy_reinit(sky2);
3093 sky2_set_multicast(dev);
3094 }
3095
3096 return 0;
3097 }
3098
3099 static void sky2_get_drvinfo(struct net_device *dev,
3100 struct ethtool_drvinfo *info)
3101 {
3102 struct sky2_port *sky2 = netdev_priv(dev);
3103
3104 strcpy(info->driver, DRV_NAME);
3105 strcpy(info->version, DRV_VERSION);
3106 strcpy(info->fw_version, "N/A");
3107 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3108 }
3109
3110 static const struct sky2_stat {
3111 char name[ETH_GSTRING_LEN];
3112 u16 offset;
3113 } sky2_stats[] = {
3114 { "tx_bytes", GM_TXO_OK_HI },
3115 { "rx_bytes", GM_RXO_OK_HI },
3116 { "tx_broadcast", GM_TXF_BC_OK },
3117 { "rx_broadcast", GM_RXF_BC_OK },
3118 { "tx_multicast", GM_TXF_MC_OK },
3119 { "rx_multicast", GM_RXF_MC_OK },
3120 { "tx_unicast", GM_TXF_UC_OK },
3121 { "rx_unicast", GM_RXF_UC_OK },
3122 { "tx_mac_pause", GM_TXF_MPAUSE },
3123 { "rx_mac_pause", GM_RXF_MPAUSE },
3124 { "collisions", GM_TXF_COL },
3125 { "late_collision",GM_TXF_LAT_COL },
3126 { "aborted", GM_TXF_ABO_COL },
3127 { "single_collisions", GM_TXF_SNG_COL },
3128 { "multi_collisions", GM_TXF_MUL_COL },
3129
3130 { "rx_short", GM_RXF_SHT },
3131 { "rx_runt", GM_RXE_FRAG },
3132 { "rx_64_byte_packets", GM_RXF_64B },
3133 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3134 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3135 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3136 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3137 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3138 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3139 { "rx_too_long", GM_RXF_LNG_ERR },
3140 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3141 { "rx_jabber", GM_RXF_JAB_PKT },
3142 { "rx_fcs_error", GM_RXF_FCS_ERR },
3143
3144 { "tx_64_byte_packets", GM_TXF_64B },
3145 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3146 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3147 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3148 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3149 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3150 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3151 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3152 };
3153
3154 static u32 sky2_get_rx_csum(struct net_device *dev)
3155 {
3156 struct sky2_port *sky2 = netdev_priv(dev);
3157
3158 return sky2->rx_csum;
3159 }
3160
3161 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3162 {
3163 struct sky2_port *sky2 = netdev_priv(dev);
3164
3165 sky2->rx_csum = data;
3166
3167 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3168 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3169
3170 return 0;
3171 }
3172
3173 static u32 sky2_get_msglevel(struct net_device *netdev)
3174 {
3175 struct sky2_port *sky2 = netdev_priv(netdev);
3176 return sky2->msg_enable;
3177 }
3178
3179 static int sky2_nway_reset(struct net_device *dev)
3180 {
3181 struct sky2_port *sky2 = netdev_priv(dev);
3182
3183 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
3184 return -EINVAL;
3185
3186 sky2_phy_reinit(sky2);
3187 sky2_set_multicast(dev);
3188
3189 return 0;
3190 }
3191
3192 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3193 {
3194 struct sky2_hw *hw = sky2->hw;
3195 unsigned port = sky2->port;
3196 int i;
3197
3198 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3199 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3200 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3201 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3202
3203 for (i = 2; i < count; i++)
3204 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3205 }
3206
3207 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3208 {
3209 struct sky2_port *sky2 = netdev_priv(netdev);
3210 sky2->msg_enable = value;
3211 }
3212
3213 static int sky2_get_sset_count(struct net_device *dev, int sset)
3214 {
3215 switch (sset) {
3216 case ETH_SS_STATS:
3217 return ARRAY_SIZE(sky2_stats);
3218 default:
3219 return -EOPNOTSUPP;
3220 }
3221 }
3222
3223 static void sky2_get_ethtool_stats(struct net_device *dev,
3224 struct ethtool_stats *stats, u64 * data)
3225 {
3226 struct sky2_port *sky2 = netdev_priv(dev);
3227
3228 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3229 }
3230
3231 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3232 {
3233 int i;
3234
3235 switch (stringset) {
3236 case ETH_SS_STATS:
3237 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3238 memcpy(data + i * ETH_GSTRING_LEN,
3239 sky2_stats[i].name, ETH_GSTRING_LEN);
3240 break;
3241 }
3242 }
3243
3244 static int sky2_set_mac_address(struct net_device *dev, void *p)
3245 {
3246 struct sky2_port *sky2 = netdev_priv(dev);
3247 struct sky2_hw *hw = sky2->hw;
3248 unsigned port = sky2->port;
3249 const struct sockaddr *addr = p;
3250
3251 if (!is_valid_ether_addr(addr->sa_data))
3252 return -EADDRNOTAVAIL;
3253
3254 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3255 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3256 dev->dev_addr, ETH_ALEN);
3257 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3258 dev->dev_addr, ETH_ALEN);
3259
3260 /* virtual address for data */
3261 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3262
3263 /* physical address: used for pause frames */
3264 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3265
3266 return 0;
3267 }
3268
3269 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3270 {
3271 u32 bit;
3272
3273 bit = ether_crc(ETH_ALEN, addr) & 63;
3274 filter[bit >> 3] |= 1 << (bit & 7);
3275 }
3276
3277 static void sky2_set_multicast(struct net_device *dev)
3278 {
3279 struct sky2_port *sky2 = netdev_priv(dev);
3280 struct sky2_hw *hw = sky2->hw;
3281 unsigned port = sky2->port;
3282 struct dev_mc_list *list = dev->mc_list;
3283 u16 reg;
3284 u8 filter[8];
3285 int rx_pause;
3286 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3287
3288 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3289 memset(filter, 0, sizeof(filter));
3290
3291 reg = gma_read16(hw, port, GM_RX_CTRL);
3292 reg |= GM_RXCR_UCF_ENA;
3293
3294 if (dev->flags & IFF_PROMISC) /* promiscuous */
3295 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3296 else if (dev->flags & IFF_ALLMULTI)
3297 memset(filter, 0xff, sizeof(filter));
3298 else if (dev->mc_count == 0 && !rx_pause)
3299 reg &= ~GM_RXCR_MCF_ENA;
3300 else {
3301 int i;
3302 reg |= GM_RXCR_MCF_ENA;
3303
3304 if (rx_pause)
3305 sky2_add_filter(filter, pause_mc_addr);
3306
3307 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3308 sky2_add_filter(filter, list->dmi_addr);
3309 }
3310
3311 gma_write16(hw, port, GM_MC_ADDR_H1,
3312 (u16) filter[0] | ((u16) filter[1] << 8));
3313 gma_write16(hw, port, GM_MC_ADDR_H2,
3314 (u16) filter[2] | ((u16) filter[3] << 8));
3315 gma_write16(hw, port, GM_MC_ADDR_H3,
3316 (u16) filter[4] | ((u16) filter[5] << 8));
3317 gma_write16(hw, port, GM_MC_ADDR_H4,
3318 (u16) filter[6] | ((u16) filter[7] << 8));
3319
3320 gma_write16(hw, port, GM_RX_CTRL, reg);
3321 }
3322
3323 /* Can have one global because blinking is controlled by
3324 * ethtool and that is always under RTNL mutex
3325 */
3326 static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3327 {
3328 struct sky2_hw *hw = sky2->hw;
3329 unsigned port = sky2->port;
3330
3331 spin_lock_bh(&sky2->phy_lock);
3332 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3333 hw->chip_id == CHIP_ID_YUKON_EX ||
3334 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3335 u16 pg;
3336 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3337 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3338
3339 switch (mode) {
3340 case MO_LED_OFF:
3341 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3342 PHY_M_LEDC_LOS_CTRL(8) |
3343 PHY_M_LEDC_INIT_CTRL(8) |
3344 PHY_M_LEDC_STA1_CTRL(8) |
3345 PHY_M_LEDC_STA0_CTRL(8));
3346 break;
3347 case MO_LED_ON:
3348 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3349 PHY_M_LEDC_LOS_CTRL(9) |
3350 PHY_M_LEDC_INIT_CTRL(9) |
3351 PHY_M_LEDC_STA1_CTRL(9) |
3352 PHY_M_LEDC_STA0_CTRL(9));
3353 break;
3354 case MO_LED_BLINK:
3355 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3356 PHY_M_LEDC_LOS_CTRL(0xa) |
3357 PHY_M_LEDC_INIT_CTRL(0xa) |
3358 PHY_M_LEDC_STA1_CTRL(0xa) |
3359 PHY_M_LEDC_STA0_CTRL(0xa));
3360 break;
3361 case MO_LED_NORM:
3362 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3363 PHY_M_LEDC_LOS_CTRL(1) |
3364 PHY_M_LEDC_INIT_CTRL(8) |
3365 PHY_M_LEDC_STA1_CTRL(7) |
3366 PHY_M_LEDC_STA0_CTRL(7));
3367 }
3368
3369 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3370 } else
3371 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3372 PHY_M_LED_MO_DUP(mode) |
3373 PHY_M_LED_MO_10(mode) |
3374 PHY_M_LED_MO_100(mode) |
3375 PHY_M_LED_MO_1000(mode) |
3376 PHY_M_LED_MO_RX(mode) |
3377 PHY_M_LED_MO_TX(mode));
3378
3379 spin_unlock_bh(&sky2->phy_lock);
3380 }
3381
3382 /* blink LED's for finding board */
3383 static int sky2_phys_id(struct net_device *dev, u32 data)
3384 {
3385 struct sky2_port *sky2 = netdev_priv(dev);
3386 unsigned int i;
3387
3388 if (data == 0)
3389 data = UINT_MAX;
3390
3391 for (i = 0; i < data; i++) {
3392 sky2_led(sky2, MO_LED_ON);
3393 if (msleep_interruptible(500))
3394 break;
3395 sky2_led(sky2, MO_LED_OFF);
3396 if (msleep_interruptible(500))
3397 break;
3398 }
3399 sky2_led(sky2, MO_LED_NORM);
3400
3401 return 0;
3402 }
3403
3404 static void sky2_get_pauseparam(struct net_device *dev,
3405 struct ethtool_pauseparam *ecmd)
3406 {
3407 struct sky2_port *sky2 = netdev_priv(dev);
3408
3409 switch (sky2->flow_mode) {
3410 case FC_NONE:
3411 ecmd->tx_pause = ecmd->rx_pause = 0;
3412 break;
3413 case FC_TX:
3414 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3415 break;
3416 case FC_RX:
3417 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3418 break;
3419 case FC_BOTH:
3420 ecmd->tx_pause = ecmd->rx_pause = 1;
3421 }
3422
3423 ecmd->autoneg = sky2->autoneg;
3424 }
3425
3426 static int sky2_set_pauseparam(struct net_device *dev,
3427 struct ethtool_pauseparam *ecmd)
3428 {
3429 struct sky2_port *sky2 = netdev_priv(dev);
3430
3431 sky2->autoneg = ecmd->autoneg;
3432 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3433
3434 if (netif_running(dev))
3435 sky2_phy_reinit(sky2);
3436
3437 return 0;
3438 }
3439
3440 static int sky2_get_coalesce(struct net_device *dev,
3441 struct ethtool_coalesce *ecmd)
3442 {
3443 struct sky2_port *sky2 = netdev_priv(dev);
3444 struct sky2_hw *hw = sky2->hw;
3445
3446 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3447 ecmd->tx_coalesce_usecs = 0;
3448 else {
3449 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3450 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3451 }
3452 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3453
3454 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3455 ecmd->rx_coalesce_usecs = 0;
3456 else {
3457 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3458 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3459 }
3460 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3461
3462 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3463 ecmd->rx_coalesce_usecs_irq = 0;
3464 else {
3465 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3466 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3467 }
3468
3469 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3470
3471 return 0;
3472 }
3473
3474 /* Note: this affect both ports */
3475 static int sky2_set_coalesce(struct net_device *dev,
3476 struct ethtool_coalesce *ecmd)
3477 {
3478 struct sky2_port *sky2 = netdev_priv(dev);
3479 struct sky2_hw *hw = sky2->hw;
3480 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3481
3482 if (ecmd->tx_coalesce_usecs > tmax ||
3483 ecmd->rx_coalesce_usecs > tmax ||
3484 ecmd->rx_coalesce_usecs_irq > tmax)
3485 return -EINVAL;
3486
3487 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3488 return -EINVAL;
3489 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3490 return -EINVAL;
3491 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3492 return -EINVAL;
3493
3494 if (ecmd->tx_coalesce_usecs == 0)
3495 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3496 else {
3497 sky2_write32(hw, STAT_TX_TIMER_INI,
3498 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3499 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3500 }
3501 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3502
3503 if (ecmd->rx_coalesce_usecs == 0)
3504 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3505 else {
3506 sky2_write32(hw, STAT_LEV_TIMER_INI,
3507 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3508 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3509 }
3510 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3511
3512 if (ecmd->rx_coalesce_usecs_irq == 0)
3513 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3514 else {
3515 sky2_write32(hw, STAT_ISR_TIMER_INI,
3516 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3517 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3518 }
3519 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3520 return 0;
3521 }
3522
3523 static void sky2_get_ringparam(struct net_device *dev,
3524 struct ethtool_ringparam *ering)
3525 {
3526 struct sky2_port *sky2 = netdev_priv(dev);
3527
3528 ering->rx_max_pending = RX_MAX_PENDING;
3529 ering->rx_mini_max_pending = 0;
3530 ering->rx_jumbo_max_pending = 0;
3531 ering->tx_max_pending = TX_RING_SIZE - 1;
3532
3533 ering->rx_pending = sky2->rx_pending;
3534 ering->rx_mini_pending = 0;
3535 ering->rx_jumbo_pending = 0;
3536 ering->tx_pending = sky2->tx_pending;
3537 }
3538
3539 static int sky2_set_ringparam(struct net_device *dev,
3540 struct ethtool_ringparam *ering)
3541 {
3542 struct sky2_port *sky2 = netdev_priv(dev);
3543 int err = 0;
3544
3545 if (ering->rx_pending > RX_MAX_PENDING ||
3546 ering->rx_pending < 8 ||
3547 ering->tx_pending < MAX_SKB_TX_LE ||
3548 ering->tx_pending > TX_RING_SIZE - 1)
3549 return -EINVAL;
3550
3551 if (netif_running(dev))
3552 sky2_down(dev);
3553
3554 sky2->rx_pending = ering->rx_pending;
3555 sky2->tx_pending = ering->tx_pending;
3556
3557 if (netif_running(dev)) {
3558 err = sky2_up(dev);
3559 if (err)
3560 dev_close(dev);
3561 }
3562
3563 return err;
3564 }
3565
3566 static int sky2_get_regs_len(struct net_device *dev)
3567 {
3568 return 0x4000;
3569 }
3570
3571 /*
3572 * Returns copy of control register region
3573 * Note: ethtool_get_regs always provides full size (16k) buffer
3574 */
3575 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3576 void *p)
3577 {
3578 const struct sky2_port *sky2 = netdev_priv(dev);
3579 const void __iomem *io = sky2->hw->regs;
3580 unsigned int b;
3581
3582 regs->version = 1;
3583
3584 for (b = 0; b < 128; b++) {
3585 /* This complicated switch statement is to make sure and
3586 * only access regions that are unreserved.
3587 * Some blocks are only valid on dual port cards.
3588 * and block 3 has some special diagnostic registers that
3589 * are poison.
3590 */
3591 switch (b) {
3592 case 3:
3593 /* skip diagnostic ram region */
3594 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3595 break;
3596
3597 /* dual port cards only */
3598 case 5: /* Tx Arbiter 2 */
3599 case 9: /* RX2 */
3600 case 14 ... 15: /* TX2 */
3601 case 17: case 19: /* Ram Buffer 2 */
3602 case 22 ... 23: /* Tx Ram Buffer 2 */
3603 case 25: /* Rx MAC Fifo 1 */
3604 case 27: /* Tx MAC Fifo 2 */
3605 case 31: /* GPHY 2 */
3606 case 40 ... 47: /* Pattern Ram 2 */
3607 case 52: case 54: /* TCP Segmentation 2 */
3608 case 112 ... 116: /* GMAC 2 */
3609 if (sky2->hw->ports == 1)
3610 goto reserved;
3611 /* fall through */
3612 case 0: /* Control */
3613 case 2: /* Mac address */
3614 case 4: /* Tx Arbiter 1 */
3615 case 7: /* PCI express reg */
3616 case 8: /* RX1 */
3617 case 12 ... 13: /* TX1 */
3618 case 16: case 18:/* Rx Ram Buffer 1 */
3619 case 20 ... 21: /* Tx Ram Buffer 1 */
3620 case 24: /* Rx MAC Fifo 1 */
3621 case 26: /* Tx MAC Fifo 1 */
3622 case 28 ... 29: /* Descriptor and status unit */
3623 case 30: /* GPHY 1*/
3624 case 32 ... 39: /* Pattern Ram 1 */
3625 case 48: case 50: /* TCP Segmentation 1 */
3626 case 56 ... 60: /* PCI space */
3627 case 80 ... 84: /* GMAC 1 */
3628 memcpy_fromio(p, io, 128);
3629 break;
3630 default:
3631 reserved:
3632 memset(p, 0, 128);
3633 }
3634
3635 p += 128;
3636 io += 128;
3637 }
3638 }
3639
3640 /* In order to do Jumbo packets on these chips, need to turn off the
3641 * transmit store/forward. Therefore checksum offload won't work.
3642 */
3643 static int no_tx_offload(struct net_device *dev)
3644 {
3645 const struct sky2_port *sky2 = netdev_priv(dev);
3646 const struct sky2_hw *hw = sky2->hw;
3647
3648 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
3649 }
3650
3651 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3652 {
3653 if (data && no_tx_offload(dev))
3654 return -EINVAL;
3655
3656 return ethtool_op_set_tx_csum(dev, data);
3657 }
3658
3659
3660 static int sky2_set_tso(struct net_device *dev, u32 data)
3661 {
3662 if (data && no_tx_offload(dev))
3663 return -EINVAL;
3664
3665 return ethtool_op_set_tso(dev, data);
3666 }
3667
3668 static int sky2_get_eeprom_len(struct net_device *dev)
3669 {
3670 struct sky2_port *sky2 = netdev_priv(dev);
3671 struct sky2_hw *hw = sky2->hw;
3672 u16 reg2;
3673
3674 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3675 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3676 }
3677
3678 static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
3679 {
3680 u32 val;
3681
3682 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3683
3684 do {
3685 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
3686 } while (!(offset & PCI_VPD_ADDR_F));
3687
3688 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3689 return val;
3690 }
3691
3692 static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
3693 {
3694 sky2_pci_write16(hw, cap + PCI_VPD_DATA, val);
3695 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3696 do {
3697 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
3698 } while (offset & PCI_VPD_ADDR_F);
3699 }
3700
3701 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3702 u8 *data)
3703 {
3704 struct sky2_port *sky2 = netdev_priv(dev);
3705 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3706 int length = eeprom->len;
3707 u16 offset = eeprom->offset;
3708
3709 if (!cap)
3710 return -EINVAL;
3711
3712 eeprom->magic = SKY2_EEPROM_MAGIC;
3713
3714 while (length > 0) {
3715 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
3716 int n = min_t(int, length, sizeof(val));
3717
3718 memcpy(data, &val, n);
3719 length -= n;
3720 data += n;
3721 offset += n;
3722 }
3723 return 0;
3724 }
3725
3726 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3727 u8 *data)
3728 {
3729 struct sky2_port *sky2 = netdev_priv(dev);
3730 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3731 int length = eeprom->len;
3732 u16 offset = eeprom->offset;
3733
3734 if (!cap)
3735 return -EINVAL;
3736
3737 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3738 return -EINVAL;
3739
3740 while (length > 0) {
3741 u32 val;
3742 int n = min_t(int, length, sizeof(val));
3743
3744 if (n < sizeof(val))
3745 val = sky2_vpd_read(sky2->hw, cap, offset);
3746 memcpy(&val, data, n);
3747
3748 sky2_vpd_write(sky2->hw, cap, offset, val);
3749
3750 length -= n;
3751 data += n;
3752 offset += n;
3753 }
3754 return 0;
3755 }
3756
3757
3758 static const struct ethtool_ops sky2_ethtool_ops = {
3759 .get_settings = sky2_get_settings,
3760 .set_settings = sky2_set_settings,
3761 .get_drvinfo = sky2_get_drvinfo,
3762 .get_wol = sky2_get_wol,
3763 .set_wol = sky2_set_wol,
3764 .get_msglevel = sky2_get_msglevel,
3765 .set_msglevel = sky2_set_msglevel,
3766 .nway_reset = sky2_nway_reset,
3767 .get_regs_len = sky2_get_regs_len,
3768 .get_regs = sky2_get_regs,
3769 .get_link = ethtool_op_get_link,
3770 .get_eeprom_len = sky2_get_eeprom_len,
3771 .get_eeprom = sky2_get_eeprom,
3772 .set_eeprom = sky2_set_eeprom,
3773 .set_sg = ethtool_op_set_sg,
3774 .set_tx_csum = sky2_set_tx_csum,
3775 .set_tso = sky2_set_tso,
3776 .get_rx_csum = sky2_get_rx_csum,
3777 .set_rx_csum = sky2_set_rx_csum,
3778 .get_strings = sky2_get_strings,
3779 .get_coalesce = sky2_get_coalesce,
3780 .set_coalesce = sky2_set_coalesce,
3781 .get_ringparam = sky2_get_ringparam,
3782 .set_ringparam = sky2_set_ringparam,
3783 .get_pauseparam = sky2_get_pauseparam,
3784 .set_pauseparam = sky2_set_pauseparam,
3785 .phys_id = sky2_phys_id,
3786 .get_sset_count = sky2_get_sset_count,
3787 .get_ethtool_stats = sky2_get_ethtool_stats,
3788 };
3789
3790 #ifdef CONFIG_SKY2_DEBUG
3791
3792 static struct dentry *sky2_debug;
3793
3794 static int sky2_debug_show(struct seq_file *seq, void *v)
3795 {
3796 struct net_device *dev = seq->private;
3797 const struct sky2_port *sky2 = netdev_priv(dev);
3798 struct sky2_hw *hw = sky2->hw;
3799 unsigned port = sky2->port;
3800 unsigned idx, last;
3801 int sop;
3802
3803 if (!netif_running(dev))
3804 return -ENETDOWN;
3805
3806 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3807 sky2_read32(hw, B0_ISRC),
3808 sky2_read32(hw, B0_IMSK),
3809 sky2_read32(hw, B0_Y2_SP_ICR));
3810
3811 napi_disable(&hw->napi);
3812 last = sky2_read16(hw, STAT_PUT_IDX);
3813
3814 if (hw->st_idx == last)
3815 seq_puts(seq, "Status ring (empty)\n");
3816 else {
3817 seq_puts(seq, "Status ring\n");
3818 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3819 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3820 const struct sky2_status_le *le = hw->st_le + idx;
3821 seq_printf(seq, "[%d] %#x %d %#x\n",
3822 idx, le->opcode, le->length, le->status);
3823 }
3824 seq_puts(seq, "\n");
3825 }
3826
3827 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3828 sky2->tx_cons, sky2->tx_prod,
3829 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3830 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3831
3832 /* Dump contents of tx ring */
3833 sop = 1;
3834 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3835 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3836 const struct sky2_tx_le *le = sky2->tx_le + idx;
3837 u32 a = le32_to_cpu(le->addr);
3838
3839 if (sop)
3840 seq_printf(seq, "%u:", idx);
3841 sop = 0;
3842
3843 switch(le->opcode & ~HW_OWNER) {
3844 case OP_ADDR64:
3845 seq_printf(seq, " %#x:", a);
3846 break;
3847 case OP_LRGLEN:
3848 seq_printf(seq, " mtu=%d", a);
3849 break;
3850 case OP_VLAN:
3851 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3852 break;
3853 case OP_TCPLISW:
3854 seq_printf(seq, " csum=%#x", a);
3855 break;
3856 case OP_LARGESEND:
3857 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3858 break;
3859 case OP_PACKET:
3860 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3861 break;
3862 case OP_BUFFER:
3863 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3864 break;
3865 default:
3866 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3867 a, le16_to_cpu(le->length));
3868 }
3869
3870 if (le->ctrl & EOP) {
3871 seq_putc(seq, '\n');
3872 sop = 1;
3873 }
3874 }
3875
3876 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3877 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3878 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3879 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3880
3881 sky2_read32(hw, B0_Y2_SP_LISR);
3882 napi_enable(&hw->napi);
3883 return 0;
3884 }
3885
3886 static int sky2_debug_open(struct inode *inode, struct file *file)
3887 {
3888 return single_open(file, sky2_debug_show, inode->i_private);
3889 }
3890
3891 static const struct file_operations sky2_debug_fops = {
3892 .owner = THIS_MODULE,
3893 .open = sky2_debug_open,
3894 .read = seq_read,
3895 .llseek = seq_lseek,
3896 .release = single_release,
3897 };
3898
3899 /*
3900 * Use network device events to create/remove/rename
3901 * debugfs file entries
3902 */
3903 static int sky2_device_event(struct notifier_block *unused,
3904 unsigned long event, void *ptr)
3905 {
3906 struct net_device *dev = ptr;
3907 struct sky2_port *sky2 = netdev_priv(dev);
3908
3909 if (dev->open != sky2_up || !sky2_debug)
3910 return NOTIFY_DONE;
3911
3912 switch(event) {
3913 case NETDEV_CHANGENAME:
3914 if (sky2->debugfs) {
3915 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
3916 sky2_debug, dev->name);
3917 }
3918 break;
3919
3920 case NETDEV_GOING_DOWN:
3921 if (sky2->debugfs) {
3922 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3923 dev->name);
3924 debugfs_remove(sky2->debugfs);
3925 sky2->debugfs = NULL;
3926 }
3927 break;
3928
3929 case NETDEV_UP:
3930 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
3931 sky2_debug, dev,
3932 &sky2_debug_fops);
3933 if (IS_ERR(sky2->debugfs))
3934 sky2->debugfs = NULL;
3935 }
3936
3937 return NOTIFY_DONE;
3938 }
3939
3940 static struct notifier_block sky2_notifier = {
3941 .notifier_call = sky2_device_event,
3942 };
3943
3944
3945 static __init void sky2_debug_init(void)
3946 {
3947 struct dentry *ent;
3948
3949 ent = debugfs_create_dir("sky2", NULL);
3950 if (!ent || IS_ERR(ent))
3951 return;
3952
3953 sky2_debug = ent;
3954 register_netdevice_notifier(&sky2_notifier);
3955 }
3956
3957 static __exit void sky2_debug_cleanup(void)
3958 {
3959 if (sky2_debug) {
3960 unregister_netdevice_notifier(&sky2_notifier);
3961 debugfs_remove(sky2_debug);
3962 sky2_debug = NULL;
3963 }
3964 }
3965
3966 #else
3967 #define sky2_debug_init()
3968 #define sky2_debug_cleanup()
3969 #endif
3970
3971
3972 /* Initialize network device */
3973 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3974 unsigned port,
3975 int highmem, int wol)
3976 {
3977 struct sky2_port *sky2;
3978 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3979
3980 if (!dev) {
3981 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
3982 return NULL;
3983 }
3984
3985 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3986 dev->irq = hw->pdev->irq;
3987 dev->open = sky2_up;
3988 dev->stop = sky2_down;
3989 dev->do_ioctl = sky2_ioctl;
3990 dev->hard_start_xmit = sky2_xmit_frame;
3991 dev->set_multicast_list = sky2_set_multicast;
3992 dev->set_mac_address = sky2_set_mac_address;
3993 dev->change_mtu = sky2_change_mtu;
3994 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3995 dev->tx_timeout = sky2_tx_timeout;
3996 dev->watchdog_timeo = TX_WATCHDOG;
3997 #ifdef CONFIG_NET_POLL_CONTROLLER
3998 if (port == 0)
3999 dev->poll_controller = sky2_netpoll;
4000 #endif
4001
4002 sky2 = netdev_priv(dev);
4003 sky2->netdev = dev;
4004 sky2->hw = hw;
4005 sky2->msg_enable = netif_msg_init(debug, default_msg);
4006
4007 /* Auto speed and flow control */
4008 sky2->autoneg = AUTONEG_ENABLE;
4009 sky2->flow_mode = FC_BOTH;
4010
4011 sky2->duplex = -1;
4012 sky2->speed = -1;
4013 sky2->advertising = sky2_supported_modes(hw);
4014 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
4015 sky2->wol = wol;
4016
4017 spin_lock_init(&sky2->phy_lock);
4018 sky2->tx_pending = TX_DEF_PENDING;
4019 sky2->rx_pending = RX_DEF_PENDING;
4020
4021 hw->dev[port] = dev;
4022
4023 sky2->port = port;
4024
4025 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
4026 if (highmem)
4027 dev->features |= NETIF_F_HIGHDMA;
4028
4029 #ifdef SKY2_VLAN_TAG_USED
4030 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4031 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4032 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4033 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4034 dev->vlan_rx_register = sky2_vlan_rx_register;
4035 }
4036 #endif
4037
4038 /* read the mac address */
4039 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4040 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4041
4042 return dev;
4043 }
4044
4045 static void __devinit sky2_show_addr(struct net_device *dev)
4046 {
4047 const struct sky2_port *sky2 = netdev_priv(dev);
4048 DECLARE_MAC_BUF(mac);
4049
4050 if (netif_msg_probe(sky2))
4051 printk(KERN_INFO PFX "%s: addr %s\n",
4052 dev->name, print_mac(mac, dev->dev_addr));
4053 }
4054
4055 /* Handle software interrupt used during MSI test */
4056 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4057 {
4058 struct sky2_hw *hw = dev_id;
4059 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4060
4061 if (status == 0)
4062 return IRQ_NONE;
4063
4064 if (status & Y2_IS_IRQ_SW) {
4065 hw->flags |= SKY2_HW_USE_MSI;
4066 wake_up(&hw->msi_wait);
4067 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4068 }
4069 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4070
4071 return IRQ_HANDLED;
4072 }
4073
4074 /* Test interrupt path by forcing a a software IRQ */
4075 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4076 {
4077 struct pci_dev *pdev = hw->pdev;
4078 int err;
4079
4080 init_waitqueue_head (&hw->msi_wait);
4081
4082 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4083
4084 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4085 if (err) {
4086 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4087 return err;
4088 }
4089
4090 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4091 sky2_read8(hw, B0_CTST);
4092
4093 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4094
4095 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4096 /* MSI test failed, go back to INTx mode */
4097 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4098 "switching to INTx mode.\n");
4099
4100 err = -EOPNOTSUPP;
4101 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4102 }
4103
4104 sky2_write32(hw, B0_IMSK, 0);
4105 sky2_read32(hw, B0_IMSK);
4106
4107 free_irq(pdev->irq, hw);
4108
4109 return err;
4110 }
4111
4112 static int __devinit pci_wake_enabled(struct pci_dev *dev)
4113 {
4114 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
4115 u16 value;
4116
4117 if (!pm)
4118 return 0;
4119 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
4120 return 0;
4121 return value & PCI_PM_CTRL_PME_ENABLE;
4122 }
4123
4124 static int __devinit sky2_probe(struct pci_dev *pdev,
4125 const struct pci_device_id *ent)
4126 {
4127 struct net_device *dev;
4128 struct sky2_hw *hw;
4129 int err, using_dac = 0, wol_default;
4130
4131 err = pci_enable_device(pdev);
4132 if (err) {
4133 dev_err(&pdev->dev, "cannot enable PCI device\n");
4134 goto err_out;
4135 }
4136
4137 err = pci_request_regions(pdev, DRV_NAME);
4138 if (err) {
4139 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4140 goto err_out_disable;
4141 }
4142
4143 pci_set_master(pdev);
4144
4145 if (sizeof(dma_addr_t) > sizeof(u32) &&
4146 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
4147 using_dac = 1;
4148 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
4149 if (err < 0) {
4150 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4151 "for consistent allocations\n");
4152 goto err_out_free_regions;
4153 }
4154 } else {
4155 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4156 if (err) {
4157 dev_err(&pdev->dev, "no usable DMA configuration\n");
4158 goto err_out_free_regions;
4159 }
4160 }
4161
4162 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
4163
4164 err = -ENOMEM;
4165 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
4166 if (!hw) {
4167 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4168 goto err_out_free_regions;
4169 }
4170
4171 hw->pdev = pdev;
4172
4173 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4174 if (!hw->regs) {
4175 dev_err(&pdev->dev, "cannot map device registers\n");
4176 goto err_out_free_hw;
4177 }
4178
4179 #ifdef __BIG_ENDIAN
4180 /* The sk98lin vendor driver uses hardware byte swapping but
4181 * this driver uses software swapping.
4182 */
4183 {
4184 u32 reg;
4185 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
4186 reg &= ~PCI_REV_DESC;
4187 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
4188 }
4189 #endif
4190
4191 /* ring for status responses */
4192 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
4193 if (!hw->st_le)
4194 goto err_out_iounmap;
4195
4196 err = sky2_init(hw);
4197 if (err)
4198 goto err_out_iounmap;
4199
4200 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
4201 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
4202 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
4203 hw->chip_id, hw->chip_rev);
4204
4205 sky2_reset(hw);
4206
4207 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4208 if (!dev) {
4209 err = -ENOMEM;
4210 goto err_out_free_pci;
4211 }
4212
4213 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4214 err = sky2_test_msi(hw);
4215 if (err == -EOPNOTSUPP)
4216 pci_disable_msi(pdev);
4217 else if (err)
4218 goto err_out_free_netdev;
4219 }
4220
4221 err = register_netdev(dev);
4222 if (err) {
4223 dev_err(&pdev->dev, "cannot register net device\n");
4224 goto err_out_free_netdev;
4225 }
4226
4227 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4228
4229 err = request_irq(pdev->irq, sky2_intr,
4230 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4231 dev->name, hw);
4232 if (err) {
4233 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4234 goto err_out_unregister;
4235 }
4236 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4237 napi_enable(&hw->napi);
4238
4239 sky2_show_addr(dev);
4240
4241 if (hw->ports > 1) {
4242 struct net_device *dev1;
4243
4244 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4245 if (!dev1)
4246 dev_warn(&pdev->dev, "allocation for second device failed\n");
4247 else if ((err = register_netdev(dev1))) {
4248 dev_warn(&pdev->dev,
4249 "register of second port failed (%d)\n", err);
4250 hw->dev[1] = NULL;
4251 free_netdev(dev1);
4252 } else
4253 sky2_show_addr(dev1);
4254 }
4255
4256 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4257 INIT_WORK(&hw->restart_work, sky2_restart);
4258
4259 pci_set_drvdata(pdev, hw);
4260
4261 return 0;
4262
4263 err_out_unregister:
4264 if (hw->flags & SKY2_HW_USE_MSI)
4265 pci_disable_msi(pdev);
4266 unregister_netdev(dev);
4267 err_out_free_netdev:
4268 free_netdev(dev);
4269 err_out_free_pci:
4270 sky2_write8(hw, B0_CTST, CS_RST_SET);
4271 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4272 err_out_iounmap:
4273 iounmap(hw->regs);
4274 err_out_free_hw:
4275 kfree(hw);
4276 err_out_free_regions:
4277 pci_release_regions(pdev);
4278 err_out_disable:
4279 pci_disable_device(pdev);
4280 err_out:
4281 pci_set_drvdata(pdev, NULL);
4282 return err;
4283 }
4284
4285 static void __devexit sky2_remove(struct pci_dev *pdev)
4286 {
4287 struct sky2_hw *hw = pci_get_drvdata(pdev);
4288 int i;
4289
4290 if (!hw)
4291 return;
4292
4293 del_timer_sync(&hw->watchdog_timer);
4294 cancel_work_sync(&hw->restart_work);
4295
4296 for (i = hw->ports-1; i >= 0; --i)
4297 unregister_netdev(hw->dev[i]);
4298
4299 sky2_write32(hw, B0_IMSK, 0);
4300
4301 sky2_power_aux(hw);
4302
4303 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
4304 sky2_write8(hw, B0_CTST, CS_RST_SET);
4305 sky2_read8(hw, B0_CTST);
4306
4307 free_irq(pdev->irq, hw);
4308 if (hw->flags & SKY2_HW_USE_MSI)
4309 pci_disable_msi(pdev);
4310 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4311 pci_release_regions(pdev);
4312 pci_disable_device(pdev);
4313
4314 for (i = hw->ports-1; i >= 0; --i)
4315 free_netdev(hw->dev[i]);
4316
4317 iounmap(hw->regs);
4318 kfree(hw);
4319
4320 pci_set_drvdata(pdev, NULL);
4321 }
4322
4323 #ifdef CONFIG_PM
4324 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4325 {
4326 struct sky2_hw *hw = pci_get_drvdata(pdev);
4327 int i, wol = 0;
4328
4329 if (!hw)
4330 return 0;
4331
4332 for (i = 0; i < hw->ports; i++) {
4333 struct net_device *dev = hw->dev[i];
4334 struct sky2_port *sky2 = netdev_priv(dev);
4335
4336 if (netif_running(dev))
4337 sky2_down(dev);
4338
4339 if (sky2->wol)
4340 sky2_wol_init(sky2);
4341
4342 wol |= sky2->wol;
4343 }
4344
4345 sky2_write32(hw, B0_IMSK, 0);
4346 napi_disable(&hw->napi);
4347 sky2_power_aux(hw);
4348
4349 pci_save_state(pdev);
4350 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4351 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4352
4353 return 0;
4354 }
4355
4356 static int sky2_resume(struct pci_dev *pdev)
4357 {
4358 struct sky2_hw *hw = pci_get_drvdata(pdev);
4359 int i, err;
4360
4361 if (!hw)
4362 return 0;
4363
4364 err = pci_set_power_state(pdev, PCI_D0);
4365 if (err)
4366 goto out;
4367
4368 err = pci_restore_state(pdev);
4369 if (err)
4370 goto out;
4371
4372 pci_enable_wake(pdev, PCI_D0, 0);
4373
4374 /* Re-enable all clocks */
4375 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4376 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4377 hw->chip_id == CHIP_ID_YUKON_FE_P)
4378 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4379
4380 sky2_reset(hw);
4381 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4382 napi_enable(&hw->napi);
4383
4384 for (i = 0; i < hw->ports; i++) {
4385 struct net_device *dev = hw->dev[i];
4386 if (netif_running(dev)) {
4387 err = sky2_up(dev);
4388 if (err) {
4389 printk(KERN_ERR PFX "%s: could not up: %d\n",
4390 dev->name, err);
4391 dev_close(dev);
4392 goto out;
4393 }
4394 }
4395 }
4396
4397 return 0;
4398 out:
4399 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4400 pci_disable_device(pdev);
4401 return err;
4402 }
4403 #endif
4404
4405 static void sky2_shutdown(struct pci_dev *pdev)
4406 {
4407 struct sky2_hw *hw = pci_get_drvdata(pdev);
4408 int i, wol = 0;
4409
4410 if (!hw)
4411 return;
4412
4413 del_timer_sync(&hw->watchdog_timer);
4414
4415 for (i = 0; i < hw->ports; i++) {
4416 struct net_device *dev = hw->dev[i];
4417 struct sky2_port *sky2 = netdev_priv(dev);
4418
4419 if (sky2->wol) {
4420 wol = 1;
4421 sky2_wol_init(sky2);
4422 }
4423 }
4424
4425 if (wol)
4426 sky2_power_aux(hw);
4427
4428 pci_enable_wake(pdev, PCI_D3hot, wol);
4429 pci_enable_wake(pdev, PCI_D3cold, wol);
4430
4431 pci_disable_device(pdev);
4432 pci_set_power_state(pdev, PCI_D3hot);
4433
4434 }
4435
4436 static struct pci_driver sky2_driver = {
4437 .name = DRV_NAME,
4438 .id_table = sky2_id_table,
4439 .probe = sky2_probe,
4440 .remove = __devexit_p(sky2_remove),
4441 #ifdef CONFIG_PM
4442 .suspend = sky2_suspend,
4443 .resume = sky2_resume,
4444 #endif
4445 .shutdown = sky2_shutdown,
4446 };
4447
4448 static int __init sky2_init_module(void)
4449 {
4450 sky2_debug_init();
4451 return pci_register_driver(&sky2_driver);
4452 }
4453
4454 static void __exit sky2_cleanup_module(void)
4455 {
4456 pci_unregister_driver(&sky2_driver);
4457 sky2_debug_cleanup();
4458 }
4459
4460 module_init(sky2_init_module);
4461 module_exit(sky2_cleanup_module);
4462
4463 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4464 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4465 MODULE_LICENSE("GPL");
4466 MODULE_VERSION(DRV_VERSION);
WRT350N Kernel Patches