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[PATCH] x86-64: adjust inclusion of asm/vsyscall32.h
[wrt350n-kernel.git] / drivers / ata / pata_via.c
blob96b71791d2f48edc8109d606a7a7d76c074df51b
1 /*
2 * pata_via.c - VIA PATA for new ATA layer
3 * (C) 2005-2006 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * Documentation
7 * Most chipset documentation available under NDA only
8 *
9 * VIA version guide
10 * VIA VT82C561 - early design, uses ata_generic currently
11 * VIA VT82C576 - MWDMA, 33Mhz
12 * VIA VT82C586 - MWDMA, 33Mhz
13 * VIA VT82C586a - Added UDMA to 33Mhz
14 * VIA VT82C586b - UDMA33
15 * VIA VT82C596a - Nonfunctional UDMA66
16 * VIA VT82C596b - Working UDMA66
17 * VIA VT82C686 - Nonfunctional UDMA66
18 * VIA VT82C686a - Working UDMA66
19 * VIA VT82C686b - Updated to UDMA100
20 * VIA VT8231 - UDMA100
21 * VIA VT8233 - UDMA100
22 * VIA VT8233a - UDMA133
23 * VIA VT8233c - UDMA100
24 * VIA VT8235 - UDMA133
25 * VIA VT8237 - UDMA133
26 * VIA VT8237S - UDMA133
27 * VIA VT8251 - UDMA133
28 *
29 * Most registers remain compatible across chips. Others start reserved
30 * and acquire sensible semantics if set to 1 (eg cable detect). A few
31 * exceptions exist, notably around the FIFO settings.
32 *
33 * One additional quirk of the VIA design is that like ALi they use few
34 * PCI IDs for a lot of chips.
35 *
36 * Based heavily on:
37 *
38 * Version 3.38
39 *
40 * VIA IDE driver for Linux. Supported southbridges:
41 *
42 * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
43 * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
44 * vt8235, vt8237
45 *
46 * Copyright (c) 2000-2002 Vojtech Pavlik
47 *
48 * Based on the work of:
49 * Michel Aubry
50 * Jeff Garzik
51 * Andre Hedrick
52
53 */
54
55 #include <linux/kernel.h>
56 #include <linux/module.h>
57 #include <linux/pci.h>
58 #include <linux/init.h>
59 #include <linux/blkdev.h>
60 #include <linux/delay.h>
61 #include <scsi/scsi_host.h>
62 #include <linux/libata.h>
63
64 #define DRV_NAME "pata_via"
65 #define DRV_VERSION "0.3.1"
66
67 /*
68 * The following comes directly from Vojtech Pavlik's ide/pci/via82cxxx
69 * driver.
70 */
71
72 enum {
73 VIA_UDMA = 0x007,
74 VIA_UDMA_NONE = 0x000,
75 VIA_UDMA_33 = 0x001,
76 VIA_UDMA_66 = 0x002,
77 VIA_UDMA_100 = 0x003,
78 VIA_UDMA_133 = 0x004,
79 VIA_BAD_PREQ = 0x010, /* Crashes if PREQ# till DDACK# set */
80 VIA_BAD_CLK66 = 0x020, /* 66 MHz clock doesn't work correctly */
81 VIA_SET_FIFO = 0x040, /* Needs to have FIFO split set */
82 VIA_NO_UNMASK = 0x080, /* Doesn't work with IRQ unmasking on */
83 VIA_BAD_ID = 0x100, /* Has wrong vendor ID (0x1107) */
84 VIA_BAD_AST = 0x200, /* Don't touch Address Setup Timing */
85 VIA_NO_ENABLES = 0x400, /* Has no enablebits */
86 };
87
88 /*
89 * VIA SouthBridge chips.
90 */
91
92 static const struct via_isa_bridge {
93 const char *name;
94 u16 id;
95 u8 rev_min;
96 u8 rev_max;
97 u16 flags;
98 } via_isa_bridges[] = {
99 { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
100 { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
101 { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
102 { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST | VIA_NO_ENABLES},
103 { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
104 { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
105 { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
106 { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
107 { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, VIA_UDMA_100 },
108 { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, VIA_UDMA_100 },
109 { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, VIA_UDMA_100 },
110 { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, VIA_UDMA_100 },
111 { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, VIA_UDMA_66 },
112 { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 },
113 { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, VIA_UDMA_66 },
114 { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 },
115 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, VIA_UDMA_33 | VIA_SET_FIFO },
116 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, VIA_UDMA_33 | VIA_SET_FIFO | VIA_BAD_PREQ },
117 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, VIA_UDMA_33 | VIA_SET_FIFO },
118 { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, VIA_UDMA_33 | VIA_SET_FIFO },
119 { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, VIA_UDMA_NONE | VIA_SET_FIFO },
120 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK },
121 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
122 { NULL }
123 };
124
125 /**
126 * via_cable_detect - cable detection
127 * @ap: ATA port
128 *
129 * Perform cable detection. Actually for the VIA case the BIOS
130 * already did this for us. We read the values provided by the
131 * BIOS. If you are using an 8235 in a non-PC configuration you
132 * may need to update this code.
133 *
134 * Hotplug also impacts on this.
135 */
136
137 static int via_cable_detect(struct ata_port *ap) {
138 const struct via_isa_bridge *config = ap->host->private_data;
139 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
140 u32 ata66;
141
142 /* Early chips are 40 wire */
143 if ((config->flags & VIA_UDMA) < VIA_UDMA_66)
144 return ATA_CBL_PATA40;
145 /* UDMA 66 chips have only drive side logic */
146 else if((config->flags & VIA_UDMA) < VIA_UDMA_100)
147 return ATA_CBL_PATA_UNK;
148 /* UDMA 100 or later */
149 pci_read_config_dword(pdev, 0x50, &ata66);
150 /* Check both the drive cable reporting bits, we might not have
151 two drives */
152 if (ata66 & (0x10100000 >> (16 * ap->port_no)))
153 return ATA_CBL_PATA80;
154 return ATA_CBL_PATA40;
155 }
156
157 static int via_pre_reset(struct ata_port *ap)
158 {
159 const struct via_isa_bridge *config = ap->host->private_data;
160
161 if (!(config->flags & VIA_NO_ENABLES)) {
162 static const struct pci_bits via_enable_bits[] = {
163 { 0x40, 1, 0x02, 0x02 },
164 { 0x40, 1, 0x01, 0x01 }
165 };
166 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
167 if (!pci_test_config_bits(pdev, &via_enable_bits[ap->port_no]))
168 return -ENOENT;
169 }
170 return ata_std_prereset(ap);
171 }
172
173
174 /**
175 * via_error_handler - reset for VIA chips
176 * @ap: ATA port
177 *
178 * Handle the reset callback for the later chips with cable detect
179 */
180
181 static void via_error_handler(struct ata_port *ap)
182 {
183 ata_bmdma_drive_eh(ap, via_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
184 }
185
186 /**
187 * via_do_set_mode - set initial PIO mode data
188 * @ap: ATA interface
189 * @adev: ATA device
190 * @mode: ATA mode being programmed
191 * @tdiv: Clocks per PCI clock
192 * @set_ast: Set to program address setup
193 * @udma_type: UDMA mode/format of registers
194 *
195 * Program the VIA registers for DMA and PIO modes. Uses the ata timing
196 * support in order to compute modes.
197 *
198 * FIXME: Hotplug will require we serialize multiple mode changes
199 * on the two channels.
200 */
201
202 static void via_do_set_mode(struct ata_port *ap, struct ata_device *adev, int mode, int tdiv, int set_ast, int udma_type)
203 {
204 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
205 struct ata_device *peer = ata_dev_pair(adev);
206 struct ata_timing t, p;
207 static int via_clock = 33333; /* Bus clock in kHZ - ought to be tunable one day */
208 unsigned long T = 1000000000 / via_clock;
209 unsigned long UT = T/tdiv;
210 int ut;
211 int offset = 3 - (2*ap->port_no) - adev->devno;
212
213
214 /* Calculate the timing values we require */
215 ata_timing_compute(adev, mode, &t, T, UT);
216
217 /* We share 8bit timing so we must merge the constraints */
218 if (peer) {
219 if (peer->pio_mode) {
220 ata_timing_compute(peer, peer->pio_mode, &p, T, UT);
221 ata_timing_merge(&p, &t, &t, ATA_TIMING_8BIT);
222 }
223 }
224
225 /* Address setup is programmable but breaks on UDMA133 setups */
226 if (set_ast) {
227 u8 setup; /* 2 bits per drive */
228 int shift = 2 * offset;
229
230 pci_read_config_byte(pdev, 0x4C, &setup);
231 setup &= ~(3 << shift);
232 setup |= FIT(t.setup, 1, 4) << shift; /* 1,4 or 1,4 - 1 FIXME */
233 pci_write_config_byte(pdev, 0x4C, setup);
234 }
235
236 /* Load the PIO mode bits */
237 pci_write_config_byte(pdev, 0x4F - ap->port_no,
238 ((FIT(t.act8b, 1, 16) - 1) << 4) | (FIT(t.rec8b, 1, 16) - 1));
239 pci_write_config_byte(pdev, 0x48 + offset,
240 ((FIT(t.active, 1, 16) - 1) << 4) | (FIT(t.recover, 1, 16) - 1));
241
242 /* Load the UDMA bits according to type */
243 switch(udma_type) {
244 default:
245 /* BUG() ? */
246 /* fall through */
247 case 33:
248 ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 5) - 2)) : 0x03;
249 break;
250 case 66:
251 ut = t.udma ? (0xe8 | (FIT(t.udma, 2, 9) - 2)) : 0x0f;
252 break;
253 case 100:
254 ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 9) - 2)) : 0x07;
255 break;
256 case 133:
257 ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 9) - 2)) : 0x07;
258 break;
259 }
260 /* Set UDMA unless device is not UDMA capable */
261 if (udma_type)
262 pci_write_config_byte(pdev, 0x50 + offset, ut);
263 }
264
265 static void via_set_piomode(struct ata_port *ap, struct ata_device *adev)
266 {
267 const struct via_isa_bridge *config = ap->host->private_data;
268 int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
269 int mode = config->flags & VIA_UDMA;
270 static u8 tclock[5] = { 1, 1, 2, 3, 4 };
271 static u8 udma[5] = { 0, 33, 66, 100, 133 };
272
273 via_do_set_mode(ap, adev, adev->pio_mode, tclock[mode], set_ast, udma[mode]);
274 }
275
276 static void via_set_dmamode(struct ata_port *ap, struct ata_device *adev)
277 {
278 const struct via_isa_bridge *config = ap->host->private_data;
279 int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
280 int mode = config->flags & VIA_UDMA;
281 static u8 tclock[5] = { 1, 1, 2, 3, 4 };
282 static u8 udma[5] = { 0, 33, 66, 100, 133 };
283
284 via_do_set_mode(ap, adev, adev->dma_mode, tclock[mode], set_ast, udma[mode]);
285 }
286
287 static struct scsi_host_template via_sht = {
288 .module = THIS_MODULE,
289 .name = DRV_NAME,
290 .ioctl = ata_scsi_ioctl,
291 .queuecommand = ata_scsi_queuecmd,
292 .can_queue = ATA_DEF_QUEUE,
293 .this_id = ATA_SHT_THIS_ID,
294 .sg_tablesize = LIBATA_MAX_PRD,
295 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
296 .emulated = ATA_SHT_EMULATED,
297 .use_clustering = ATA_SHT_USE_CLUSTERING,
298 .proc_name = DRV_NAME,
299 .dma_boundary = ATA_DMA_BOUNDARY,
300 .slave_configure = ata_scsi_slave_config,
301 .slave_destroy = ata_scsi_slave_destroy,
302 .bios_param = ata_std_bios_param,
303 #ifdef CONFIG_PM
304 .resume = ata_scsi_device_resume,
305 .suspend = ata_scsi_device_suspend,
306 #endif
307 };
308
309 static struct ata_port_operations via_port_ops = {
310 .port_disable = ata_port_disable,
311 .set_piomode = via_set_piomode,
312 .set_dmamode = via_set_dmamode,
313 .mode_filter = ata_pci_default_filter,
314
315 .tf_load = ata_tf_load,
316 .tf_read = ata_tf_read,
317 .check_status = ata_check_status,
318 .exec_command = ata_exec_command,
319 .dev_select = ata_std_dev_select,
320
321 .freeze = ata_bmdma_freeze,
322 .thaw = ata_bmdma_thaw,
323 .error_handler = via_error_handler,
324 .post_internal_cmd = ata_bmdma_post_internal_cmd,
325 .cable_detect = via_cable_detect,
326
327 .bmdma_setup = ata_bmdma_setup,
328 .bmdma_start = ata_bmdma_start,
329 .bmdma_stop = ata_bmdma_stop,
330 .bmdma_status = ata_bmdma_status,
331
332 .qc_prep = ata_qc_prep,
333 .qc_issue = ata_qc_issue_prot,
334
335 .data_xfer = ata_data_xfer,
336
337 .irq_handler = ata_interrupt,
338 .irq_clear = ata_bmdma_irq_clear,
339 .irq_on = ata_irq_on,
340 .irq_ack = ata_irq_ack,
341
342 .port_start = ata_port_start,
343 };
344
345 static struct ata_port_operations via_port_ops_noirq = {
346 .port_disable = ata_port_disable,
347 .set_piomode = via_set_piomode,
348 .set_dmamode = via_set_dmamode,
349 .mode_filter = ata_pci_default_filter,
350
351 .tf_load = ata_tf_load,
352 .tf_read = ata_tf_read,
353 .check_status = ata_check_status,
354 .exec_command = ata_exec_command,
355 .dev_select = ata_std_dev_select,
356
357 .freeze = ata_bmdma_freeze,
358 .thaw = ata_bmdma_thaw,
359 .error_handler = via_error_handler,
360 .post_internal_cmd = ata_bmdma_post_internal_cmd,
361 .cable_detect = via_cable_detect,
362
363 .bmdma_setup = ata_bmdma_setup,
364 .bmdma_start = ata_bmdma_start,
365 .bmdma_stop = ata_bmdma_stop,
366 .bmdma_status = ata_bmdma_status,
367
368 .qc_prep = ata_qc_prep,
369 .qc_issue = ata_qc_issue_prot,
370
371 .data_xfer = ata_data_xfer_noirq,
372
373 .irq_handler = ata_interrupt,
374 .irq_clear = ata_bmdma_irq_clear,
375 .irq_on = ata_irq_on,
376 .irq_ack = ata_irq_ack,
377
378 .port_start = ata_port_start,
379 };
380
381 /**
382 * via_config_fifo - set up the FIFO
383 * @pdev: PCI device
384 * @flags: configuration flags
385 *
386 * Set the FIFO properties for this device if neccessary. Used both on
387 * set up and on and the resume path
388 */
389
390 static void via_config_fifo(struct pci_dev *pdev, unsigned int flags)
391 {
392 u8 enable;
393
394 /* 0x40 low bits indicate enabled channels */
395 pci_read_config_byte(pdev, 0x40 , &enable);
396 enable &= 3;
397
398 if (flags & VIA_SET_FIFO) {
399 static const u8 fifo_setting[4] = {0x00, 0x60, 0x00, 0x20};
400 u8 fifo;
401
402 pci_read_config_byte(pdev, 0x43, &fifo);
403
404 /* Clear PREQ# until DDACK# for errata */
405 if (flags & VIA_BAD_PREQ)
406 fifo &= 0x7F;
407 else
408 fifo &= 0x9f;
409 /* Turn on FIFO for enabled channels */
410 fifo |= fifo_setting[enable];
411 pci_write_config_byte(pdev, 0x43, fifo);
412 }
413 }
414
415 /**
416 * via_init_one - discovery callback
417 * @pdev: PCI device
418 * @id: PCI table info
419 *
420 * A VIA IDE interface has been discovered. Figure out what revision
421 * and perform configuration work before handing it to the ATA layer
422 */
423
424 static int via_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
425 {
426 /* Early VIA without UDMA support */
427 static struct ata_port_info via_mwdma_info = {
428 .sht = &via_sht,
429 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SETXFER_POLLING,
430 .pio_mask = 0x1f,
431 .mwdma_mask = 0x07,
432 .port_ops = &via_port_ops
433 };
434 /* Ditto with IRQ masking required */
435 static struct ata_port_info via_mwdma_info_borked = {
436 .sht = &via_sht,
437 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SETXFER_POLLING,
438 .pio_mask = 0x1f,
439 .mwdma_mask = 0x07,
440 .port_ops = &via_port_ops_noirq,
441 };
442 /* VIA UDMA 33 devices (and borked 66) */
443 static struct ata_port_info via_udma33_info = {
444 .sht = &via_sht,
445 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SETXFER_POLLING,
446 .pio_mask = 0x1f,
447 .mwdma_mask = 0x07,
448 .udma_mask = 0x7,
449 .port_ops = &via_port_ops
450 };
451 /* VIA UDMA 66 devices */
452 static struct ata_port_info via_udma66_info = {
453 .sht = &via_sht,
454 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SETXFER_POLLING,
455 .pio_mask = 0x1f,
456 .mwdma_mask = 0x07,
457 .udma_mask = 0x1f,
458 .port_ops = &via_port_ops
459 };
460 /* VIA UDMA 100 devices */
461 static struct ata_port_info via_udma100_info = {
462 .sht = &via_sht,
463 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SETXFER_POLLING,
464 .pio_mask = 0x1f,
465 .mwdma_mask = 0x07,
466 .udma_mask = 0x3f,
467 .port_ops = &via_port_ops
468 };
469 /* UDMA133 with bad AST (All current 133) */
470 static struct ata_port_info via_udma133_info = {
471 .sht = &via_sht,
472 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SETXFER_POLLING,
473 .pio_mask = 0x1f,
474 .mwdma_mask = 0x07,
475 .udma_mask = 0x7f, /* FIXME: should check north bridge */
476 .port_ops = &via_port_ops
477 };
478 struct ata_port_info *port_info[2], *type;
479 struct pci_dev *isa = NULL;
480 const struct via_isa_bridge *config;
481 static int printed_version;
482 u8 t;
483 u8 enable;
484 u32 timing;
485
486 if (!printed_version++)
487 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
488
489 /* To find out how the IDE will behave and what features we
490 actually have to look at the bridge not the IDE controller */
491 for (config = via_isa_bridges; config->id; config++)
492 if ((isa = pci_get_device(PCI_VENDOR_ID_VIA +
493 !!(config->flags & VIA_BAD_ID),
494 config->id, NULL))) {
495
496 pci_read_config_byte(isa, PCI_REVISION_ID, &t);
497 if (t >= config->rev_min &&
498 t <= config->rev_max)
499 break;
500 pci_dev_put(isa);
501 }
502
503 if (!config->id) {
504 printk(KERN_WARNING "via: Unknown VIA SouthBridge, disabling.\n");
505 return -ENODEV;
506 }
507 pci_dev_put(isa);
508
509 /* 0x40 low bits indicate enabled channels */
510 pci_read_config_byte(pdev, 0x40 , &enable);
511 enable &= 3;
512 if (enable == 0) {
513 return -ENODEV;
514 }
515
516 /* Initialise the FIFO for the enabled channels. */
517 via_config_fifo(pdev, config->flags);
518
519 /* Clock set up */
520 switch(config->flags & VIA_UDMA) {
521 case VIA_UDMA_NONE:
522 if (config->flags & VIA_NO_UNMASK)
523 type = &via_mwdma_info_borked;
524 else
525 type = &via_mwdma_info;
526 break;
527 case VIA_UDMA_33:
528 type = &via_udma33_info;
529 break;
530 case VIA_UDMA_66:
531 type = &via_udma66_info;
532 /* The 66 MHz devices require we enable the clock */
533 pci_read_config_dword(pdev, 0x50, &timing);
534 timing |= 0x80008;
535 pci_write_config_dword(pdev, 0x50, timing);
536 break;
537 case VIA_UDMA_100:
538 type = &via_udma100_info;
539 break;
540 case VIA_UDMA_133:
541 type = &via_udma133_info;
542 break;
543 default:
544 WARN_ON(1);
545 return -ENODEV;
546 }
547
548 if (config->flags & VIA_BAD_CLK66) {
549 /* Disable the 66MHz clock on problem devices */
550 pci_read_config_dword(pdev, 0x50, &timing);
551 timing &= ~0x80008;
552 pci_write_config_dword(pdev, 0x50, timing);
553 }
554
555 /* We have established the device type, now fire it up */
556 type->private_data = (void *)config;
557
558 port_info[0] = port_info[1] = type;
559 return ata_pci_init_one(pdev, port_info, 2);
560 }
561
562 #ifdef CONFIG_PM
563 /**
564 * via_reinit_one - reinit after resume
565 * @pdev; PCI device
566 *
567 * Called when the VIA PATA device is resumed. We must then
568 * reconfigure the fifo and other setup we may have altered. In
569 * addition the kernel needs to have the resume methods on PCI
570 * quirk supported.
571 */
572
573 static int via_reinit_one(struct pci_dev *pdev)
574 {
575 u32 timing;
576 struct ata_host *host = dev_get_drvdata(&pdev->dev);
577 const struct via_isa_bridge *config = host->private_data;
578
579 via_config_fifo(pdev, config->flags);
580
581 if ((config->flags & VIA_UDMA) == VIA_UDMA_66) {
582 /* The 66 MHz devices require we enable the clock */
583 pci_read_config_dword(pdev, 0x50, &timing);
584 timing |= 0x80008;
585 pci_write_config_dword(pdev, 0x50, timing);
586 }
587 if (config->flags & VIA_BAD_CLK66) {
588 /* Disable the 66MHz clock on problem devices */
589 pci_read_config_dword(pdev, 0x50, &timing);
590 timing &= ~0x80008;
591 pci_write_config_dword(pdev, 0x50, timing);
592 }
593 return ata_pci_device_resume(pdev);
594 }
595 #endif
596
597 static const struct pci_device_id via[] = {
598 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C576_1), },
599 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C586_1), },
600 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6410), },
601 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_SATA_EIDE), },
602
603 { },
604 };
605
606 static struct pci_driver via_pci_driver = {
607 .name = DRV_NAME,
608 .id_table = via,
609 .probe = via_init_one,
610 .remove = ata_pci_remove_one,
611 #ifdef CONFIG_PM
612 .suspend = ata_pci_device_suspend,
613 .resume = via_reinit_one,
614 #endif
615 };
616
617 static int __init via_init(void)
618 {
619 return pci_register_driver(&via_pci_driver);
620 }
621
622 static void __exit via_exit(void)
623 {
624 pci_unregister_driver(&via_pci_driver);
625 }
626
627 MODULE_AUTHOR("Alan Cox");
628 MODULE_DESCRIPTION("low-level driver for VIA PATA");
629 MODULE_LICENSE("GPL");
630 MODULE_DEVICE_TABLE(pci, via);
631 MODULE_VERSION(DRV_VERSION);
632
633 module_init(via_init);
634 module_exit(via_exit);
WRT350N Kernel Patches