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[PATCH] x86-64: adjust inclusion of asm/vsyscall32.h
[wrt350n-kernel.git] / drivers / ata / sata_mv.c
blobcb9b9ac12b4c1cf3689757bafe9be68f46f59ab5
1 /*
2 * sata_mv.c - Marvell SATA support
3 *
4 * Copyright 2005: EMC Corporation, all rights reserved.
5 * Copyright 2005 Red Hat, Inc. All rights reserved.
6 *
7 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <linux/init.h>
28 #include <linux/blkdev.h>
29 #include <linux/delay.h>
30 #include <linux/interrupt.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/device.h>
33 #include <scsi/scsi_host.h>
34 #include <scsi/scsi_cmnd.h>
35 #include <linux/libata.h>
36
37 #define DRV_NAME "sata_mv"
38 #define DRV_VERSION "0.8"
39
40 enum {
41 /* BAR's are enumerated in terms of pci_resource_start() terms */
42 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
43 MV_IO_BAR = 2, /* offset 0x18: IO space */
44 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
45
46 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
47 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
48
49 MV_PCI_REG_BASE = 0,
50 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
51 MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
52 MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
53 MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
54 MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
55 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
56
57 MV_SATAHC0_REG_BASE = 0x20000,
58 MV_FLASH_CTL = 0x1046c,
59 MV_GPIO_PORT_CTL = 0x104f0,
60 MV_RESET_CFG = 0x180d8,
61
62 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
63 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
64 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
65 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
66
67 MV_USE_Q_DEPTH = ATA_DEF_QUEUE,
68
69 MV_MAX_Q_DEPTH = 32,
70 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
71
72 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
73 * CRPB needs alignment on a 256B boundary. Size == 256B
74 * SG count of 176 leads to MV_PORT_PRIV_DMA_SZ == 4KB
75 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
76 */
77 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
78 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
79 MV_MAX_SG_CT = 176,
80 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
81 MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ),
82
83 MV_PORTS_PER_HC = 4,
84 /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */
85 MV_PORT_HC_SHIFT = 2,
86 /* == (port % MV_PORTS_PER_HC) to determine hard port from 0-7 port */
87 MV_PORT_MASK = 3,
88
89 /* Host Flags */
90 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
91 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
92 MV_COMMON_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
93 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
94 ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING),
95 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
96
97 CRQB_FLAG_READ = (1 << 0),
98 CRQB_TAG_SHIFT = 1,
99 CRQB_CMD_ADDR_SHIFT = 8,
100 CRQB_CMD_CS = (0x2 << 11),
101 CRQB_CMD_LAST = (1 << 15),
102
103 CRPB_FLAG_STATUS_SHIFT = 8,
104
105 EPRD_FLAG_END_OF_TBL = (1 << 31),
106
107 /* PCI interface registers */
108
109 PCI_COMMAND_OFS = 0xc00,
110
111 PCI_MAIN_CMD_STS_OFS = 0xd30,
112 STOP_PCI_MASTER = (1 << 2),
113 PCI_MASTER_EMPTY = (1 << 3),
114 GLOB_SFT_RST = (1 << 4),
115
116 MV_PCI_MODE = 0xd00,
117 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
118 MV_PCI_DISC_TIMER = 0xd04,
119 MV_PCI_MSI_TRIGGER = 0xc38,
120 MV_PCI_SERR_MASK = 0xc28,
121 MV_PCI_XBAR_TMOUT = 0x1d04,
122 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
123 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
124 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
125 MV_PCI_ERR_COMMAND = 0x1d50,
126
127 PCI_IRQ_CAUSE_OFS = 0x1d58,
128 PCI_IRQ_MASK_OFS = 0x1d5c,
129 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
130
131 HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
132 HC_MAIN_IRQ_MASK_OFS = 0x1d64,
133 PORT0_ERR = (1 << 0), /* shift by port # */
134 PORT0_DONE = (1 << 1), /* shift by port # */
135 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
136 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
137 PCI_ERR = (1 << 18),
138 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
139 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
140 PORTS_0_3_COAL_DONE = (1 << 8),
141 PORTS_4_7_COAL_DONE = (1 << 17),
142 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
143 GPIO_INT = (1 << 22),
144 SELF_INT = (1 << 23),
145 TWSI_INT = (1 << 24),
146 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
147 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
148 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
149 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
150 HC_MAIN_RSVD),
151 HC_MAIN_MASKED_IRQS_5 = (PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
152 HC_MAIN_RSVD_5),
153
154 /* SATAHC registers */
155 HC_CFG_OFS = 0,
156
157 HC_IRQ_CAUSE_OFS = 0x14,
158 CRPB_DMA_DONE = (1 << 0), /* shift by port # */
159 HC_IRQ_COAL = (1 << 4), /* IRQ coalescing */
160 DEV_IRQ = (1 << 8), /* shift by port # */
161
162 /* Shadow block registers */
163 SHD_BLK_OFS = 0x100,
164 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
165
166 /* SATA registers */
167 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
168 SATA_ACTIVE_OFS = 0x350,
169 PHY_MODE3 = 0x310,
170 PHY_MODE4 = 0x314,
171 PHY_MODE2 = 0x330,
172 MV5_PHY_MODE = 0x74,
173 MV5_LT_MODE = 0x30,
174 MV5_PHY_CTL = 0x0C,
175 SATA_INTERFACE_CTL = 0x050,
176
177 MV_M2_PREAMP_MASK = 0x7e0,
178
179 /* Port registers */
180 EDMA_CFG_OFS = 0,
181 EDMA_CFG_Q_DEPTH = 0, /* queueing disabled */
182 EDMA_CFG_NCQ = (1 << 5),
183 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
184 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
185 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
186
187 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
188 EDMA_ERR_IRQ_MASK_OFS = 0xc,
189 EDMA_ERR_D_PAR = (1 << 0),
190 EDMA_ERR_PRD_PAR = (1 << 1),
191 EDMA_ERR_DEV = (1 << 2),
192 EDMA_ERR_DEV_DCON = (1 << 3),
193 EDMA_ERR_DEV_CON = (1 << 4),
194 EDMA_ERR_SERR = (1 << 5),
195 EDMA_ERR_SELF_DIS = (1 << 7),
196 EDMA_ERR_BIST_ASYNC = (1 << 8),
197 EDMA_ERR_CRBQ_PAR = (1 << 9),
198 EDMA_ERR_CRPB_PAR = (1 << 10),
199 EDMA_ERR_INTRL_PAR = (1 << 11),
200 EDMA_ERR_IORDY = (1 << 12),
201 EDMA_ERR_LNK_CTRL_RX = (0xf << 13),
202 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15),
203 EDMA_ERR_LNK_DATA_RX = (0xf << 17),
204 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21),
205 EDMA_ERR_LNK_DATA_TX = (0x1f << 26),
206 EDMA_ERR_TRANS_PROTO = (1 << 31),
207 EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
208 EDMA_ERR_DEV_DCON | EDMA_ERR_CRBQ_PAR |
209 EDMA_ERR_CRPB_PAR | EDMA_ERR_INTRL_PAR |
210 EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 |
211 EDMA_ERR_LNK_DATA_RX |
212 EDMA_ERR_LNK_DATA_TX |
213 EDMA_ERR_TRANS_PROTO),
214
215 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
216 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
217
218 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
219 EDMA_REQ_Q_PTR_SHIFT = 5,
220
221 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
222 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
223 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
224 EDMA_RSP_Q_PTR_SHIFT = 3,
225
226 EDMA_CMD_OFS = 0x28,
227 EDMA_EN = (1 << 0),
228 EDMA_DS = (1 << 1),
229 ATA_RST = (1 << 2),
230
231 EDMA_IORDY_TMOUT = 0x34,
232 EDMA_ARB_CFG = 0x38,
233
234 /* Host private flags (hp_flags) */
235 MV_HP_FLAG_MSI = (1 << 0),
236 MV_HP_ERRATA_50XXB0 = (1 << 1),
237 MV_HP_ERRATA_50XXB2 = (1 << 2),
238 MV_HP_ERRATA_60X1B2 = (1 << 3),
239 MV_HP_ERRATA_60X1C0 = (1 << 4),
240 MV_HP_ERRATA_XX42A0 = (1 << 5),
241 MV_HP_50XX = (1 << 6),
242 MV_HP_GEN_IIE = (1 << 7),
243
244 /* Port private flags (pp_flags) */
245 MV_PP_FLAG_EDMA_EN = (1 << 0),
246 MV_PP_FLAG_EDMA_DS_ACT = (1 << 1),
247 };
248
249 #define IS_50XX(hpriv) ((hpriv)->hp_flags & MV_HP_50XX)
250 #define IS_60XX(hpriv) (((hpriv)->hp_flags & MV_HP_50XX) == 0)
251 #define IS_GEN_I(hpriv) IS_50XX(hpriv)
252 #define IS_GEN_II(hpriv) IS_60XX(hpriv)
253 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
254
255 enum {
256 MV_DMA_BOUNDARY = 0xffffffffU,
257
258 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
259
260 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
261 };
262
263 enum chip_type {
264 chip_504x,
265 chip_508x,
266 chip_5080,
267 chip_604x,
268 chip_608x,
269 chip_6042,
270 chip_7042,
271 };
272
273 /* Command ReQuest Block: 32B */
274 struct mv_crqb {
275 __le32 sg_addr;
276 __le32 sg_addr_hi;
277 __le16 ctrl_flags;
278 __le16 ata_cmd[11];
279 };
280
281 struct mv_crqb_iie {
282 __le32 addr;
283 __le32 addr_hi;
284 __le32 flags;
285 __le32 len;
286 __le32 ata_cmd[4];
287 };
288
289 /* Command ResPonse Block: 8B */
290 struct mv_crpb {
291 __le16 id;
292 __le16 flags;
293 __le32 tmstmp;
294 };
295
296 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
297 struct mv_sg {
298 __le32 addr;
299 __le32 flags_size;
300 __le32 addr_hi;
301 __le32 reserved;
302 };
303
304 struct mv_port_priv {
305 struct mv_crqb *crqb;
306 dma_addr_t crqb_dma;
307 struct mv_crpb *crpb;
308 dma_addr_t crpb_dma;
309 struct mv_sg *sg_tbl;
310 dma_addr_t sg_tbl_dma;
311 u32 pp_flags;
312 };
313
314 struct mv_port_signal {
315 u32 amps;
316 u32 pre;
317 };
318
319 struct mv_host_priv;
320 struct mv_hw_ops {
321 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
322 unsigned int port);
323 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
324 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
325 void __iomem *mmio);
326 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
327 unsigned int n_hc);
328 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
329 void (*reset_bus)(struct pci_dev *pdev, void __iomem *mmio);
330 };
331
332 struct mv_host_priv {
333 u32 hp_flags;
334 struct mv_port_signal signal[8];
335 const struct mv_hw_ops *ops;
336 };
337
338 static void mv_irq_clear(struct ata_port *ap);
339 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
340 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
341 static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
342 static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
343 static void mv_phy_reset(struct ata_port *ap);
344 static void __mv_phy_reset(struct ata_port *ap, int can_sleep);
345 static int mv_port_start(struct ata_port *ap);
346 static void mv_port_stop(struct ata_port *ap);
347 static void mv_qc_prep(struct ata_queued_cmd *qc);
348 static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
349 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
350 static void mv_eng_timeout(struct ata_port *ap);
351 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
352
353 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
354 unsigned int port);
355 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
356 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
357 void __iomem *mmio);
358 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
359 unsigned int n_hc);
360 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
361 static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio);
362
363 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
364 unsigned int port);
365 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
366 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
367 void __iomem *mmio);
368 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
369 unsigned int n_hc);
370 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
371 static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio);
372 static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
373 unsigned int port_no);
374 static void mv_stop_and_reset(struct ata_port *ap);
375
376 static struct scsi_host_template mv_sht = {
377 .module = THIS_MODULE,
378 .name = DRV_NAME,
379 .ioctl = ata_scsi_ioctl,
380 .queuecommand = ata_scsi_queuecmd,
381 .can_queue = MV_USE_Q_DEPTH,
382 .this_id = ATA_SHT_THIS_ID,
383 .sg_tablesize = MV_MAX_SG_CT,
384 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
385 .emulated = ATA_SHT_EMULATED,
386 .use_clustering = 1,
387 .proc_name = DRV_NAME,
388 .dma_boundary = MV_DMA_BOUNDARY,
389 .slave_configure = ata_scsi_slave_config,
390 .slave_destroy = ata_scsi_slave_destroy,
391 .bios_param = ata_std_bios_param,
392 };
393
394 static const struct ata_port_operations mv5_ops = {
395 .port_disable = ata_port_disable,
396
397 .tf_load = ata_tf_load,
398 .tf_read = ata_tf_read,
399 .check_status = ata_check_status,
400 .exec_command = ata_exec_command,
401 .dev_select = ata_std_dev_select,
402
403 .phy_reset = mv_phy_reset,
404 .cable_detect = ata_cable_sata,
405
406 .qc_prep = mv_qc_prep,
407 .qc_issue = mv_qc_issue,
408 .data_xfer = ata_data_xfer,
409
410 .eng_timeout = mv_eng_timeout,
411
412 .irq_clear = mv_irq_clear,
413 .irq_on = ata_irq_on,
414 .irq_ack = ata_irq_ack,
415
416 .scr_read = mv5_scr_read,
417 .scr_write = mv5_scr_write,
418
419 .port_start = mv_port_start,
420 .port_stop = mv_port_stop,
421 };
422
423 static const struct ata_port_operations mv6_ops = {
424 .port_disable = ata_port_disable,
425
426 .tf_load = ata_tf_load,
427 .tf_read = ata_tf_read,
428 .check_status = ata_check_status,
429 .exec_command = ata_exec_command,
430 .dev_select = ata_std_dev_select,
431
432 .phy_reset = mv_phy_reset,
433 .cable_detect = ata_cable_sata,
434
435 .qc_prep = mv_qc_prep,
436 .qc_issue = mv_qc_issue,
437 .data_xfer = ata_data_xfer,
438
439 .eng_timeout = mv_eng_timeout,
440
441 .irq_clear = mv_irq_clear,
442 .irq_on = ata_irq_on,
443 .irq_ack = ata_irq_ack,
444
445 .scr_read = mv_scr_read,
446 .scr_write = mv_scr_write,
447
448 .port_start = mv_port_start,
449 .port_stop = mv_port_stop,
450 };
451
452 static const struct ata_port_operations mv_iie_ops = {
453 .port_disable = ata_port_disable,
454
455 .tf_load = ata_tf_load,
456 .tf_read = ata_tf_read,
457 .check_status = ata_check_status,
458 .exec_command = ata_exec_command,
459 .dev_select = ata_std_dev_select,
460
461 .phy_reset = mv_phy_reset,
462 .cable_detect = ata_cable_sata,
463
464 .qc_prep = mv_qc_prep_iie,
465 .qc_issue = mv_qc_issue,
466 .data_xfer = ata_data_xfer,
467
468 .eng_timeout = mv_eng_timeout,
469
470 .irq_clear = mv_irq_clear,
471 .irq_on = ata_irq_on,
472 .irq_ack = ata_irq_ack,
473
474 .scr_read = mv_scr_read,
475 .scr_write = mv_scr_write,
476
477 .port_start = mv_port_start,
478 .port_stop = mv_port_stop,
479 };
480
481 static const struct ata_port_info mv_port_info[] = {
482 { /* chip_504x */
483 .flags = MV_COMMON_FLAGS,
484 .pio_mask = 0x1f, /* pio0-4 */
485 .udma_mask = 0x7f, /* udma0-6 */
486 .port_ops = &mv5_ops,
487 },
488 { /* chip_508x */
489 .flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
490 .pio_mask = 0x1f, /* pio0-4 */
491 .udma_mask = 0x7f, /* udma0-6 */
492 .port_ops = &mv5_ops,
493 },
494 { /* chip_5080 */
495 .flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
496 .pio_mask = 0x1f, /* pio0-4 */
497 .udma_mask = 0x7f, /* udma0-6 */
498 .port_ops = &mv5_ops,
499 },
500 { /* chip_604x */
501 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
502 .pio_mask = 0x1f, /* pio0-4 */
503 .udma_mask = 0x7f, /* udma0-6 */
504 .port_ops = &mv6_ops,
505 },
506 { /* chip_608x */
507 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS |
508 MV_FLAG_DUAL_HC),
509 .pio_mask = 0x1f, /* pio0-4 */
510 .udma_mask = 0x7f, /* udma0-6 */
511 .port_ops = &mv6_ops,
512 },
513 { /* chip_6042 */
514 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
515 .pio_mask = 0x1f, /* pio0-4 */
516 .udma_mask = 0x7f, /* udma0-6 */
517 .port_ops = &mv_iie_ops,
518 },
519 { /* chip_7042 */
520 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
521 .pio_mask = 0x1f, /* pio0-4 */
522 .udma_mask = 0x7f, /* udma0-6 */
523 .port_ops = &mv_iie_ops,
524 },
525 };
526
527 static const struct pci_device_id mv_pci_tbl[] = {
528 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
529 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
530 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
531 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
532
533 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
534 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
535 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
536 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
537 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
538
539 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
540
541 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
542
543 /* add Marvell 7042 support */
544 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
545
546 { } /* terminate list */
547 };
548
549 static struct pci_driver mv_pci_driver = {
550 .name = DRV_NAME,
551 .id_table = mv_pci_tbl,
552 .probe = mv_init_one,
553 .remove = ata_pci_remove_one,
554 };
555
556 static const struct mv_hw_ops mv5xxx_ops = {
557 .phy_errata = mv5_phy_errata,
558 .enable_leds = mv5_enable_leds,
559 .read_preamp = mv5_read_preamp,
560 .reset_hc = mv5_reset_hc,
561 .reset_flash = mv5_reset_flash,
562 .reset_bus = mv5_reset_bus,
563 };
564
565 static const struct mv_hw_ops mv6xxx_ops = {
566 .phy_errata = mv6_phy_errata,
567 .enable_leds = mv6_enable_leds,
568 .read_preamp = mv6_read_preamp,
569 .reset_hc = mv6_reset_hc,
570 .reset_flash = mv6_reset_flash,
571 .reset_bus = mv_reset_pci_bus,
572 };
573
574 /*
575 * module options
576 */
577 static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
578
579
580 /* move to PCI layer or libata core? */
581 static int pci_go_64(struct pci_dev *pdev)
582 {
583 int rc;
584
585 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
586 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
587 if (rc) {
588 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
589 if (rc) {
590 dev_printk(KERN_ERR, &pdev->dev,
591 "64-bit DMA enable failed\n");
592 return rc;
593 }
594 }
595 } else {
596 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
597 if (rc) {
598 dev_printk(KERN_ERR, &pdev->dev,
599 "32-bit DMA enable failed\n");
600 return rc;
601 }
602 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
603 if (rc) {
604 dev_printk(KERN_ERR, &pdev->dev,
605 "32-bit consistent DMA enable failed\n");
606 return rc;
607 }
608 }
609
610 return rc;
611 }
612
613 /*
614 * Functions
615 */
616
617 static inline void writelfl(unsigned long data, void __iomem *addr)
618 {
619 writel(data, addr);
620 (void) readl(addr); /* flush to avoid PCI posted write */
621 }
622
623 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
624 {
625 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
626 }
627
628 static inline unsigned int mv_hc_from_port(unsigned int port)
629 {
630 return port >> MV_PORT_HC_SHIFT;
631 }
632
633 static inline unsigned int mv_hardport_from_port(unsigned int port)
634 {
635 return port & MV_PORT_MASK;
636 }
637
638 static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
639 unsigned int port)
640 {
641 return mv_hc_base(base, mv_hc_from_port(port));
642 }
643
644 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
645 {
646 return mv_hc_base_from_port(base, port) +
647 MV_SATAHC_ARBTR_REG_SZ +
648 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
649 }
650
651 static inline void __iomem *mv_ap_base(struct ata_port *ap)
652 {
653 return mv_port_base(ap->host->iomap[MV_PRIMARY_BAR], ap->port_no);
654 }
655
656 static inline int mv_get_hc_count(unsigned long port_flags)
657 {
658 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
659 }
660
661 static void mv_irq_clear(struct ata_port *ap)
662 {
663 }
664
665 /**
666 * mv_start_dma - Enable eDMA engine
667 * @base: port base address
668 * @pp: port private data
669 *
670 * Verify the local cache of the eDMA state is accurate with a
671 * WARN_ON.
672 *
673 * LOCKING:
674 * Inherited from caller.
675 */
676 static void mv_start_dma(void __iomem *base, struct mv_port_priv *pp)
677 {
678 if (!(MV_PP_FLAG_EDMA_EN & pp->pp_flags)) {
679 writelfl(EDMA_EN, base + EDMA_CMD_OFS);
680 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
681 }
682 WARN_ON(!(EDMA_EN & readl(base + EDMA_CMD_OFS)));
683 }
684
685 /**
686 * mv_stop_dma - Disable eDMA engine
687 * @ap: ATA channel to manipulate
688 *
689 * Verify the local cache of the eDMA state is accurate with a
690 * WARN_ON.
691 *
692 * LOCKING:
693 * Inherited from caller.
694 */
695 static void mv_stop_dma(struct ata_port *ap)
696 {
697 void __iomem *port_mmio = mv_ap_base(ap);
698 struct mv_port_priv *pp = ap->private_data;
699 u32 reg;
700 int i;
701
702 if (MV_PP_FLAG_EDMA_EN & pp->pp_flags) {
703 /* Disable EDMA if active. The disable bit auto clears.
704 */
705 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
706 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
707 } else {
708 WARN_ON(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS));
709 }
710
711 /* now properly wait for the eDMA to stop */
712 for (i = 1000; i > 0; i--) {
713 reg = readl(port_mmio + EDMA_CMD_OFS);
714 if (!(EDMA_EN & reg)) {
715 break;
716 }
717 udelay(100);
718 }
719
720 if (EDMA_EN & reg) {
721 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
722 /* FIXME: Consider doing a reset here to recover */
723 }
724 }
725
726 #ifdef ATA_DEBUG
727 static void mv_dump_mem(void __iomem *start, unsigned bytes)
728 {
729 int b, w;
730 for (b = 0; b < bytes; ) {
731 DPRINTK("%p: ", start + b);
732 for (w = 0; b < bytes && w < 4; w++) {
733 printk("%08x ",readl(start + b));
734 b += sizeof(u32);
735 }
736 printk("\n");
737 }
738 }
739 #endif
740
741 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
742 {
743 #ifdef ATA_DEBUG
744 int b, w;
745 u32 dw;
746 for (b = 0; b < bytes; ) {
747 DPRINTK("%02x: ", b);
748 for (w = 0; b < bytes && w < 4; w++) {
749 (void) pci_read_config_dword(pdev,b,&dw);
750 printk("%08x ",dw);
751 b += sizeof(u32);
752 }
753 printk("\n");
754 }
755 #endif
756 }
757 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
758 struct pci_dev *pdev)
759 {
760 #ifdef ATA_DEBUG
761 void __iomem *hc_base = mv_hc_base(mmio_base,
762 port >> MV_PORT_HC_SHIFT);
763 void __iomem *port_base;
764 int start_port, num_ports, p, start_hc, num_hcs, hc;
765
766 if (0 > port) {
767 start_hc = start_port = 0;
768 num_ports = 8; /* shld be benign for 4 port devs */
769 num_hcs = 2;
770 } else {
771 start_hc = port >> MV_PORT_HC_SHIFT;
772 start_port = port;
773 num_ports = num_hcs = 1;
774 }
775 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
776 num_ports > 1 ? num_ports - 1 : start_port);
777
778 if (NULL != pdev) {
779 DPRINTK("PCI config space regs:\n");
780 mv_dump_pci_cfg(pdev, 0x68);
781 }
782 DPRINTK("PCI regs:\n");
783 mv_dump_mem(mmio_base+0xc00, 0x3c);
784 mv_dump_mem(mmio_base+0xd00, 0x34);
785 mv_dump_mem(mmio_base+0xf00, 0x4);
786 mv_dump_mem(mmio_base+0x1d00, 0x6c);
787 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
788 hc_base = mv_hc_base(mmio_base, hc);
789 DPRINTK("HC regs (HC %i):\n", hc);
790 mv_dump_mem(hc_base, 0x1c);
791 }
792 for (p = start_port; p < start_port + num_ports; p++) {
793 port_base = mv_port_base(mmio_base, p);
794 DPRINTK("EDMA regs (port %i):\n",p);
795 mv_dump_mem(port_base, 0x54);
796 DPRINTK("SATA regs (port %i):\n",p);
797 mv_dump_mem(port_base+0x300, 0x60);
798 }
799 #endif
800 }
801
802 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
803 {
804 unsigned int ofs;
805
806 switch (sc_reg_in) {
807 case SCR_STATUS:
808 case SCR_CONTROL:
809 case SCR_ERROR:
810 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
811 break;
812 case SCR_ACTIVE:
813 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
814 break;
815 default:
816 ofs = 0xffffffffU;
817 break;
818 }
819 return ofs;
820 }
821
822 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
823 {
824 unsigned int ofs = mv_scr_offset(sc_reg_in);
825
826 if (0xffffffffU != ofs)
827 return readl(mv_ap_base(ap) + ofs);
828 else
829 return (u32) ofs;
830 }
831
832 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
833 {
834 unsigned int ofs = mv_scr_offset(sc_reg_in);
835
836 if (0xffffffffU != ofs)
837 writelfl(val, mv_ap_base(ap) + ofs);
838 }
839
840 static void mv_edma_cfg(struct mv_host_priv *hpriv, void __iomem *port_mmio)
841 {
842 u32 cfg = readl(port_mmio + EDMA_CFG_OFS);
843
844 /* set up non-NCQ EDMA configuration */
845 cfg &= ~(1 << 9); /* disable equeue */
846
847 if (IS_GEN_I(hpriv)) {
848 cfg &= ~0x1f; /* clear queue depth */
849 cfg |= (1 << 8); /* enab config burst size mask */
850 }
851
852 else if (IS_GEN_II(hpriv)) {
853 cfg &= ~0x1f; /* clear queue depth */
854 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
855 cfg &= ~(EDMA_CFG_NCQ | EDMA_CFG_NCQ_GO_ON_ERR); /* clear NCQ */
856 }
857
858 else if (IS_GEN_IIE(hpriv)) {
859 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
860 cfg |= (1 << 22); /* enab 4-entry host queue cache */
861 cfg &= ~(1 << 19); /* dis 128-entry queue (for now?) */
862 cfg |= (1 << 18); /* enab early completion */
863 cfg |= (1 << 17); /* enab cut-through (dis stor&forwrd) */
864 cfg &= ~(1 << 16); /* dis FIS-based switching (for now) */
865 cfg &= ~(EDMA_CFG_NCQ | EDMA_CFG_NCQ_GO_ON_ERR); /* clear NCQ */
866 }
867
868 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
869 }
870
871 /**
872 * mv_port_start - Port specific init/start routine.
873 * @ap: ATA channel to manipulate
874 *
875 * Allocate and point to DMA memory, init port private memory,
876 * zero indices.
877 *
878 * LOCKING:
879 * Inherited from caller.
880 */
881 static int mv_port_start(struct ata_port *ap)
882 {
883 struct device *dev = ap->host->dev;
884 struct mv_host_priv *hpriv = ap->host->private_data;
885 struct mv_port_priv *pp;
886 void __iomem *port_mmio = mv_ap_base(ap);
887 void *mem;
888 dma_addr_t mem_dma;
889 int rc;
890
891 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
892 if (!pp)
893 return -ENOMEM;
894
895 mem = dmam_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma,
896 GFP_KERNEL);
897 if (!mem)
898 return -ENOMEM;
899 memset(mem, 0, MV_PORT_PRIV_DMA_SZ);
900
901 rc = ata_pad_alloc(ap, dev);
902 if (rc)
903 return rc;
904
905 /* First item in chunk of DMA memory:
906 * 32-slot command request table (CRQB), 32 bytes each in size
907 */
908 pp->crqb = mem;
909 pp->crqb_dma = mem_dma;
910 mem += MV_CRQB_Q_SZ;
911 mem_dma += MV_CRQB_Q_SZ;
912
913 /* Second item:
914 * 32-slot command response table (CRPB), 8 bytes each in size
915 */
916 pp->crpb = mem;
917 pp->crpb_dma = mem_dma;
918 mem += MV_CRPB_Q_SZ;
919 mem_dma += MV_CRPB_Q_SZ;
920
921 /* Third item:
922 * Table of scatter-gather descriptors (ePRD), 16 bytes each
923 */
924 pp->sg_tbl = mem;
925 pp->sg_tbl_dma = mem_dma;
926
927 mv_edma_cfg(hpriv, port_mmio);
928
929 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
930 writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK,
931 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
932
933 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
934 writelfl(pp->crqb_dma & 0xffffffff,
935 port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
936 else
937 writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
938
939 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
940
941 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
942 writelfl(pp->crpb_dma & 0xffffffff,
943 port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
944 else
945 writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
946
947 writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK,
948 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
949
950 /* Don't turn on EDMA here...do it before DMA commands only. Else
951 * we'll be unable to send non-data, PIO, etc due to restricted access
952 * to shadow regs.
953 */
954 ap->private_data = pp;
955 return 0;
956 }
957
958 /**
959 * mv_port_stop - Port specific cleanup/stop routine.
960 * @ap: ATA channel to manipulate
961 *
962 * Stop DMA, cleanup port memory.
963 *
964 * LOCKING:
965 * This routine uses the host lock to protect the DMA stop.
966 */
967 static void mv_port_stop(struct ata_port *ap)
968 {
969 unsigned long flags;
970
971 spin_lock_irqsave(&ap->host->lock, flags);
972 mv_stop_dma(ap);
973 spin_unlock_irqrestore(&ap->host->lock, flags);
974 }
975
976 /**
977 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
978 * @qc: queued command whose SG list to source from
979 *
980 * Populate the SG list and mark the last entry.
981 *
982 * LOCKING:
983 * Inherited from caller.
984 */
985 static unsigned int mv_fill_sg(struct ata_queued_cmd *qc)
986 {
987 struct mv_port_priv *pp = qc->ap->private_data;
988 unsigned int n_sg = 0;
989 struct scatterlist *sg;
990 struct mv_sg *mv_sg;
991
992 mv_sg = pp->sg_tbl;
993 ata_for_each_sg(sg, qc) {
994 dma_addr_t addr = sg_dma_address(sg);
995 u32 sg_len = sg_dma_len(sg);
996
997 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
998 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
999 mv_sg->flags_size = cpu_to_le32(sg_len & 0xffff);
1000
1001 if (ata_sg_is_last(sg, qc))
1002 mv_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
1003
1004 mv_sg++;
1005 n_sg++;
1006 }
1007
1008 return n_sg;
1009 }
1010
1011 static inline unsigned mv_inc_q_index(unsigned index)
1012 {
1013 return (index + 1) & MV_MAX_Q_DEPTH_MASK;
1014 }
1015
1016 static inline void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
1017 {
1018 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
1019 (last ? CRQB_CMD_LAST : 0);
1020 *cmdw = cpu_to_le16(tmp);
1021 }
1022
1023 /**
1024 * mv_qc_prep - Host specific command preparation.
1025 * @qc: queued command to prepare
1026 *
1027 * This routine simply redirects to the general purpose routine
1028 * if command is not DMA. Else, it handles prep of the CRQB
1029 * (command request block), does some sanity checking, and calls
1030 * the SG load routine.
1031 *
1032 * LOCKING:
1033 * Inherited from caller.
1034 */
1035 static void mv_qc_prep(struct ata_queued_cmd *qc)
1036 {
1037 struct ata_port *ap = qc->ap;
1038 struct mv_port_priv *pp = ap->private_data;
1039 __le16 *cw;
1040 struct ata_taskfile *tf;
1041 u16 flags = 0;
1042 unsigned in_index;
1043
1044 if (ATA_PROT_DMA != qc->tf.protocol)
1045 return;
1046
1047 /* Fill in command request block
1048 */
1049 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1050 flags |= CRQB_FLAG_READ;
1051 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1052 flags |= qc->tag << CRQB_TAG_SHIFT;
1053
1054 /* get current queue index from hardware */
1055 in_index = (readl(mv_ap_base(ap) + EDMA_REQ_Q_IN_PTR_OFS)
1056 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1057
1058 pp->crqb[in_index].sg_addr =
1059 cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
1060 pp->crqb[in_index].sg_addr_hi =
1061 cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
1062 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
1063
1064 cw = &pp->crqb[in_index].ata_cmd[0];
1065 tf = &qc->tf;
1066
1067 /* Sadly, the CRQB cannot accomodate all registers--there are
1068 * only 11 bytes...so we must pick and choose required
1069 * registers based on the command. So, we drop feature and
1070 * hob_feature for [RW] DMA commands, but they are needed for
1071 * NCQ. NCQ will drop hob_nsect.
1072 */
1073 switch (tf->command) {
1074 case ATA_CMD_READ:
1075 case ATA_CMD_READ_EXT:
1076 case ATA_CMD_WRITE:
1077 case ATA_CMD_WRITE_EXT:
1078 case ATA_CMD_WRITE_FUA_EXT:
1079 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1080 break;
1081 #ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */
1082 case ATA_CMD_FPDMA_READ:
1083 case ATA_CMD_FPDMA_WRITE:
1084 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
1085 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1086 break;
1087 #endif /* FIXME: remove this line when NCQ added */
1088 default:
1089 /* The only other commands EDMA supports in non-queued and
1090 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1091 * of which are defined/used by Linux. If we get here, this
1092 * driver needs work.
1093 *
1094 * FIXME: modify libata to give qc_prep a return value and
1095 * return error here.
1096 */
1097 BUG_ON(tf->command);
1098 break;
1099 }
1100 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1101 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1102 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1103 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1104 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1105 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1106 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1107 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1108 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1109
1110 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1111 return;
1112 mv_fill_sg(qc);
1113 }
1114
1115 /**
1116 * mv_qc_prep_iie - Host specific command preparation.
1117 * @qc: queued command to prepare
1118 *
1119 * This routine simply redirects to the general purpose routine
1120 * if command is not DMA. Else, it handles prep of the CRQB
1121 * (command request block), does some sanity checking, and calls
1122 * the SG load routine.
1123 *
1124 * LOCKING:
1125 * Inherited from caller.
1126 */
1127 static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1128 {
1129 struct ata_port *ap = qc->ap;
1130 struct mv_port_priv *pp = ap->private_data;
1131 struct mv_crqb_iie *crqb;
1132 struct ata_taskfile *tf;
1133 unsigned in_index;
1134 u32 flags = 0;
1135
1136 if (ATA_PROT_DMA != qc->tf.protocol)
1137 return;
1138
1139 /* Fill in Gen IIE command request block
1140 */
1141 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1142 flags |= CRQB_FLAG_READ;
1143
1144 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1145 flags |= qc->tag << CRQB_TAG_SHIFT;
1146
1147 /* get current queue index from hardware */
1148 in_index = (readl(mv_ap_base(ap) + EDMA_REQ_Q_IN_PTR_OFS)
1149 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1150
1151 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
1152 crqb->addr = cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
1153 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
1154 crqb->flags = cpu_to_le32(flags);
1155
1156 tf = &qc->tf;
1157 crqb->ata_cmd[0] = cpu_to_le32(
1158 (tf->command << 16) |
1159 (tf->feature << 24)
1160 );
1161 crqb->ata_cmd[1] = cpu_to_le32(
1162 (tf->lbal << 0) |
1163 (tf->lbam << 8) |
1164 (tf->lbah << 16) |
1165 (tf->device << 24)
1166 );
1167 crqb->ata_cmd[2] = cpu_to_le32(
1168 (tf->hob_lbal << 0) |
1169 (tf->hob_lbam << 8) |
1170 (tf->hob_lbah << 16) |
1171 (tf->hob_feature << 24)
1172 );
1173 crqb->ata_cmd[3] = cpu_to_le32(
1174 (tf->nsect << 0) |
1175 (tf->hob_nsect << 8)
1176 );
1177
1178 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1179 return;
1180 mv_fill_sg(qc);
1181 }
1182
1183 /**
1184 * mv_qc_issue - Initiate a command to the host
1185 * @qc: queued command to start
1186 *
1187 * This routine simply redirects to the general purpose routine
1188 * if command is not DMA. Else, it sanity checks our local
1189 * caches of the request producer/consumer indices then enables
1190 * DMA and bumps the request producer index.
1191 *
1192 * LOCKING:
1193 * Inherited from caller.
1194 */
1195 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
1196 {
1197 void __iomem *port_mmio = mv_ap_base(qc->ap);
1198 struct mv_port_priv *pp = qc->ap->private_data;
1199 unsigned in_index;
1200 u32 in_ptr;
1201
1202 if (ATA_PROT_DMA != qc->tf.protocol) {
1203 /* We're about to send a non-EDMA capable command to the
1204 * port. Turn off EDMA so there won't be problems accessing
1205 * shadow block, etc registers.
1206 */
1207 mv_stop_dma(qc->ap);
1208 return ata_qc_issue_prot(qc);
1209 }
1210
1211 in_ptr = readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1212 in_index = (in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1213
1214 /* until we do queuing, the queue should be empty at this point */
1215 WARN_ON(in_index != ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS)
1216 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
1217
1218 in_index = mv_inc_q_index(in_index); /* now incr producer index */
1219
1220 mv_start_dma(port_mmio, pp);
1221
1222 /* and write the request in pointer to kick the EDMA to life */
1223 in_ptr &= EDMA_REQ_Q_BASE_LO_MASK;
1224 in_ptr |= in_index << EDMA_REQ_Q_PTR_SHIFT;
1225 writelfl(in_ptr, port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1226
1227 return 0;
1228 }
1229
1230 /**
1231 * mv_get_crpb_status - get status from most recently completed cmd
1232 * @ap: ATA channel to manipulate
1233 *
1234 * This routine is for use when the port is in DMA mode, when it
1235 * will be using the CRPB (command response block) method of
1236 * returning command completion information. We check indices
1237 * are good, grab status, and bump the response consumer index to
1238 * prove that we're up to date.
1239 *
1240 * LOCKING:
1241 * Inherited from caller.
1242 */
1243 static u8 mv_get_crpb_status(struct ata_port *ap)
1244 {
1245 void __iomem *port_mmio = mv_ap_base(ap);
1246 struct mv_port_priv *pp = ap->private_data;
1247 unsigned out_index;
1248 u32 out_ptr;
1249 u8 ata_status;
1250
1251 out_ptr = readl(port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1252 out_index = (out_ptr >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1253
1254 ata_status = le16_to_cpu(pp->crpb[out_index].flags)
1255 >> CRPB_FLAG_STATUS_SHIFT;
1256
1257 /* increment our consumer index... */
1258 out_index = mv_inc_q_index(out_index);
1259
1260 /* and, until we do NCQ, there should only be 1 CRPB waiting */
1261 WARN_ON(out_index != ((readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
1262 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
1263
1264 /* write out our inc'd consumer index so EDMA knows we're caught up */
1265 out_ptr &= EDMA_RSP_Q_BASE_LO_MASK;
1266 out_ptr |= out_index << EDMA_RSP_Q_PTR_SHIFT;
1267 writelfl(out_ptr, port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1268
1269 /* Return ATA status register for completed CRPB */
1270 return ata_status;
1271 }
1272
1273 /**
1274 * mv_err_intr - Handle error interrupts on the port
1275 * @ap: ATA channel to manipulate
1276 * @reset_allowed: bool: 0 == don't trigger from reset here
1277 *
1278 * In most cases, just clear the interrupt and move on. However,
1279 * some cases require an eDMA reset, which is done right before
1280 * the COMRESET in mv_phy_reset(). The SERR case requires a
1281 * clear of pending errors in the SATA SERROR register. Finally,
1282 * if the port disabled DMA, update our cached copy to match.
1283 *
1284 * LOCKING:
1285 * Inherited from caller.
1286 */
1287 static void mv_err_intr(struct ata_port *ap, int reset_allowed)
1288 {
1289 void __iomem *port_mmio = mv_ap_base(ap);
1290 u32 edma_err_cause, serr = 0;
1291
1292 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1293
1294 if (EDMA_ERR_SERR & edma_err_cause) {
1295 sata_scr_read(ap, SCR_ERROR, &serr);
1296 sata_scr_write_flush(ap, SCR_ERROR, serr);
1297 }
1298 if (EDMA_ERR_SELF_DIS & edma_err_cause) {
1299 struct mv_port_priv *pp = ap->private_data;
1300 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1301 }
1302 DPRINTK(KERN_ERR "ata%u: port error; EDMA err cause: 0x%08x "
1303 "SERR: 0x%08x\n", ap->print_id, edma_err_cause, serr);
1304
1305 /* Clear EDMA now that SERR cleanup done */
1306 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1307
1308 /* check for fatal here and recover if needed */
1309 if (reset_allowed && (EDMA_ERR_FATAL & edma_err_cause))
1310 mv_stop_and_reset(ap);
1311 }
1312
1313 /**
1314 * mv_host_intr - Handle all interrupts on the given host controller
1315 * @host: host specific structure
1316 * @relevant: port error bits relevant to this host controller
1317 * @hc: which host controller we're to look at
1318 *
1319 * Read then write clear the HC interrupt status then walk each
1320 * port connected to the HC and see if it needs servicing. Port
1321 * success ints are reported in the HC interrupt status reg, the
1322 * port error ints are reported in the higher level main
1323 * interrupt status register and thus are passed in via the
1324 * 'relevant' argument.
1325 *
1326 * LOCKING:
1327 * Inherited from caller.
1328 */
1329 static void mv_host_intr(struct ata_host *host, u32 relevant, unsigned int hc)
1330 {
1331 void __iomem *mmio = host->iomap[MV_PRIMARY_BAR];
1332 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1333 struct ata_queued_cmd *qc;
1334 u32 hc_irq_cause;
1335 int shift, port, port0, hard_port, handled;
1336 unsigned int err_mask;
1337
1338 if (hc == 0)
1339 port0 = 0;
1340 else
1341 port0 = MV_PORTS_PER_HC;
1342
1343 /* we'll need the HC success int register in most cases */
1344 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
1345 if (hc_irq_cause)
1346 writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
1347
1348 VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n",
1349 hc,relevant,hc_irq_cause);
1350
1351 for (port = port0; port < port0 + MV_PORTS_PER_HC; port++) {
1352 u8 ata_status = 0;
1353 struct ata_port *ap = host->ports[port];
1354 struct mv_port_priv *pp = ap->private_data;
1355
1356 hard_port = mv_hardport_from_port(port); /* range 0..3 */
1357 handled = 0; /* ensure ata_status is set if handled++ */
1358
1359 /* Note that DEV_IRQ might happen spuriously during EDMA,
1360 * and should be ignored in such cases.
1361 * The cause of this is still under investigation.
1362 */
1363 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1364 /* EDMA: check for response queue interrupt */
1365 if ((CRPB_DMA_DONE << hard_port) & hc_irq_cause) {
1366 ata_status = mv_get_crpb_status(ap);
1367 handled = 1;
1368 }
1369 } else {
1370 /* PIO: check for device (drive) interrupt */
1371 if ((DEV_IRQ << hard_port) & hc_irq_cause) {
1372 ata_status = readb(ap->ioaddr.status_addr);
1373 handled = 1;
1374 /* ignore spurious intr if drive still BUSY */
1375 if (ata_status & ATA_BUSY) {
1376 ata_status = 0;
1377 handled = 0;
1378 }
1379 }
1380 }
1381
1382 if (ap && (ap->flags & ATA_FLAG_DISABLED))
1383 continue;
1384
1385 err_mask = ac_err_mask(ata_status);
1386
1387 shift = port << 1; /* (port * 2) */
1388 if (port >= MV_PORTS_PER_HC) {
1389 shift++; /* skip bit 8 in the HC Main IRQ reg */
1390 }
1391 if ((PORT0_ERR << shift) & relevant) {
1392 mv_err_intr(ap, 1);
1393 err_mask |= AC_ERR_OTHER;
1394 handled = 1;
1395 }
1396
1397 if (handled) {
1398 qc = ata_qc_from_tag(ap, ap->active_tag);
1399 if (qc && (qc->flags & ATA_QCFLAG_ACTIVE)) {
1400 VPRINTK("port %u IRQ found for qc, "
1401 "ata_status 0x%x\n", port,ata_status);
1402 /* mark qc status appropriately */
1403 if (!(qc->tf.flags & ATA_TFLAG_POLLING)) {
1404 qc->err_mask |= err_mask;
1405 ata_qc_complete(qc);
1406 }
1407 }
1408 }
1409 }
1410 VPRINTK("EXIT\n");
1411 }
1412
1413 /**
1414 * mv_interrupt -
1415 * @irq: unused
1416 * @dev_instance: private data; in this case the host structure
1417 * @regs: unused
1418 *
1419 * Read the read only register to determine if any host
1420 * controllers have pending interrupts. If so, call lower level
1421 * routine to handle. Also check for PCI errors which are only
1422 * reported here.
1423 *
1424 * LOCKING:
1425 * This routine holds the host lock while processing pending
1426 * interrupts.
1427 */
1428 static irqreturn_t mv_interrupt(int irq, void *dev_instance)
1429 {
1430 struct ata_host *host = dev_instance;
1431 unsigned int hc, handled = 0, n_hcs;
1432 void __iomem *mmio = host->iomap[MV_PRIMARY_BAR];
1433 struct mv_host_priv *hpriv;
1434 u32 irq_stat;
1435
1436 irq_stat = readl(mmio + HC_MAIN_IRQ_CAUSE_OFS);
1437
1438 /* check the cases where we either have nothing pending or have read
1439 * a bogus register value which can indicate HW removal or PCI fault
1440 */
1441 if (!irq_stat || (0xffffffffU == irq_stat))
1442 return IRQ_NONE;
1443
1444 n_hcs = mv_get_hc_count(host->ports[0]->flags);
1445 spin_lock(&host->lock);
1446
1447 for (hc = 0; hc < n_hcs; hc++) {
1448 u32 relevant = irq_stat & (HC0_IRQ_PEND << (hc * HC_SHIFT));
1449 if (relevant) {
1450 mv_host_intr(host, relevant, hc);
1451 handled++;
1452 }
1453 }
1454
1455 hpriv = host->private_data;
1456 if (IS_60XX(hpriv)) {
1457 /* deal with the interrupt coalescing bits */
1458 if (irq_stat & (TRAN_LO_DONE | TRAN_HI_DONE | PORTS_0_7_COAL_DONE)) {
1459 writelfl(0, mmio + MV_IRQ_COAL_CAUSE_LO);
1460 writelfl(0, mmio + MV_IRQ_COAL_CAUSE_HI);
1461 writelfl(0, mmio + MV_IRQ_COAL_CAUSE);
1462 }
1463 }
1464
1465 if (PCI_ERR & irq_stat) {
1466 printk(KERN_ERR DRV_NAME ": PCI ERROR; PCI IRQ cause=0x%08x\n",
1467 readl(mmio + PCI_IRQ_CAUSE_OFS));
1468
1469 DPRINTK("All regs @ PCI error\n");
1470 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
1471
1472 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
1473 handled++;
1474 }
1475 spin_unlock(&host->lock);
1476
1477 return IRQ_RETVAL(handled);
1478 }
1479
1480 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
1481 {
1482 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
1483 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
1484
1485 return hc_mmio + ofs;
1486 }
1487
1488 static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
1489 {
1490 unsigned int ofs;
1491
1492 switch (sc_reg_in) {
1493 case SCR_STATUS:
1494 case SCR_ERROR:
1495 case SCR_CONTROL:
1496 ofs = sc_reg_in * sizeof(u32);
1497 break;
1498 default:
1499 ofs = 0xffffffffU;
1500 break;
1501 }
1502 return ofs;
1503 }
1504
1505 static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
1506 {
1507 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
1508 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
1509 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1510
1511 if (ofs != 0xffffffffU)
1512 return readl(addr + ofs);
1513 else
1514 return (u32) ofs;
1515 }
1516
1517 static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
1518 {
1519 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
1520 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
1521 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1522
1523 if (ofs != 0xffffffffU)
1524 writelfl(val, addr + ofs);
1525 }
1526
1527 static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio)
1528 {
1529 u8 rev_id;
1530 int early_5080;
1531
1532 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
1533
1534 early_5080 = (pdev->device == 0x5080) && (rev_id == 0);
1535
1536 if (!early_5080) {
1537 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1538 tmp |= (1 << 0);
1539 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1540 }
1541
1542 mv_reset_pci_bus(pdev, mmio);
1543 }
1544
1545 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1546 {
1547 writel(0x0fcfffff, mmio + MV_FLASH_CTL);
1548 }
1549
1550 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
1551 void __iomem *mmio)
1552 {
1553 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
1554 u32 tmp;
1555
1556 tmp = readl(phy_mmio + MV5_PHY_MODE);
1557
1558 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
1559 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
1560 }
1561
1562 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1563 {
1564 u32 tmp;
1565
1566 writel(0, mmio + MV_GPIO_PORT_CTL);
1567
1568 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
1569
1570 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1571 tmp |= ~(1 << 0);
1572 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1573 }
1574
1575 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1576 unsigned int port)
1577 {
1578 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
1579 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
1580 u32 tmp;
1581 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
1582
1583 if (fix_apm_sq) {
1584 tmp = readl(phy_mmio + MV5_LT_MODE);
1585 tmp |= (1 << 19);
1586 writel(tmp, phy_mmio + MV5_LT_MODE);
1587
1588 tmp = readl(phy_mmio + MV5_PHY_CTL);
1589 tmp &= ~0x3;
1590 tmp |= 0x1;
1591 writel(tmp, phy_mmio + MV5_PHY_CTL);
1592 }
1593
1594 tmp = readl(phy_mmio + MV5_PHY_MODE);
1595 tmp &= ~mask;
1596 tmp |= hpriv->signal[port].pre;
1597 tmp |= hpriv->signal[port].amps;
1598 writel(tmp, phy_mmio + MV5_PHY_MODE);
1599 }
1600
1601
1602 #undef ZERO
1603 #define ZERO(reg) writel(0, port_mmio + (reg))
1604 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
1605 unsigned int port)
1606 {
1607 void __iomem *port_mmio = mv_port_base(mmio, port);
1608
1609 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
1610
1611 mv_channel_reset(hpriv, mmio, port);
1612
1613 ZERO(0x028); /* command */
1614 writel(0x11f, port_mmio + EDMA_CFG_OFS);
1615 ZERO(0x004); /* timer */
1616 ZERO(0x008); /* irq err cause */
1617 ZERO(0x00c); /* irq err mask */
1618 ZERO(0x010); /* rq bah */
1619 ZERO(0x014); /* rq inp */
1620 ZERO(0x018); /* rq outp */
1621 ZERO(0x01c); /* respq bah */
1622 ZERO(0x024); /* respq outp */
1623 ZERO(0x020); /* respq inp */
1624 ZERO(0x02c); /* test control */
1625 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
1626 }
1627 #undef ZERO
1628
1629 #define ZERO(reg) writel(0, hc_mmio + (reg))
1630 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1631 unsigned int hc)
1632 {
1633 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1634 u32 tmp;
1635
1636 ZERO(0x00c);
1637 ZERO(0x010);
1638 ZERO(0x014);
1639 ZERO(0x018);
1640
1641 tmp = readl(hc_mmio + 0x20);
1642 tmp &= 0x1c1c1c1c;
1643 tmp |= 0x03030303;
1644 writel(tmp, hc_mmio + 0x20);
1645 }
1646 #undef ZERO
1647
1648 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1649 unsigned int n_hc)
1650 {
1651 unsigned int hc, port;
1652
1653 for (hc = 0; hc < n_hc; hc++) {
1654 for (port = 0; port < MV_PORTS_PER_HC; port++)
1655 mv5_reset_hc_port(hpriv, mmio,
1656 (hc * MV_PORTS_PER_HC) + port);
1657
1658 mv5_reset_one_hc(hpriv, mmio, hc);
1659 }
1660
1661 return 0;
1662 }
1663
1664 #undef ZERO
1665 #define ZERO(reg) writel(0, mmio + (reg))
1666 static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio)
1667 {
1668 u32 tmp;
1669
1670 tmp = readl(mmio + MV_PCI_MODE);
1671 tmp &= 0xff00ffff;
1672 writel(tmp, mmio + MV_PCI_MODE);
1673
1674 ZERO(MV_PCI_DISC_TIMER);
1675 ZERO(MV_PCI_MSI_TRIGGER);
1676 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
1677 ZERO(HC_MAIN_IRQ_MASK_OFS);
1678 ZERO(MV_PCI_SERR_MASK);
1679 ZERO(PCI_IRQ_CAUSE_OFS);
1680 ZERO(PCI_IRQ_MASK_OFS);
1681 ZERO(MV_PCI_ERR_LOW_ADDRESS);
1682 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
1683 ZERO(MV_PCI_ERR_ATTRIBUTE);
1684 ZERO(MV_PCI_ERR_COMMAND);
1685 }
1686 #undef ZERO
1687
1688 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1689 {
1690 u32 tmp;
1691
1692 mv5_reset_flash(hpriv, mmio);
1693
1694 tmp = readl(mmio + MV_GPIO_PORT_CTL);
1695 tmp &= 0x3;
1696 tmp |= (1 << 5) | (1 << 6);
1697 writel(tmp, mmio + MV_GPIO_PORT_CTL);
1698 }
1699
1700 /**
1701 * mv6_reset_hc - Perform the 6xxx global soft reset
1702 * @mmio: base address of the HBA
1703 *
1704 * This routine only applies to 6xxx parts.
1705 *
1706 * LOCKING:
1707 * Inherited from caller.
1708 */
1709 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1710 unsigned int n_hc)
1711 {
1712 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
1713 int i, rc = 0;
1714 u32 t;
1715
1716 /* Following procedure defined in PCI "main command and status
1717 * register" table.
1718 */
1719 t = readl(reg);
1720 writel(t | STOP_PCI_MASTER, reg);
1721
1722 for (i = 0; i < 1000; i++) {
1723 udelay(1);
1724 t = readl(reg);
1725 if (PCI_MASTER_EMPTY & t) {
1726 break;
1727 }
1728 }
1729 if (!(PCI_MASTER_EMPTY & t)) {
1730 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
1731 rc = 1;
1732 goto done;
1733 }
1734
1735 /* set reset */
1736 i = 5;
1737 do {
1738 writel(t | GLOB_SFT_RST, reg);
1739 t = readl(reg);
1740 udelay(1);
1741 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
1742
1743 if (!(GLOB_SFT_RST & t)) {
1744 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
1745 rc = 1;
1746 goto done;
1747 }
1748
1749 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
1750 i = 5;
1751 do {
1752 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
1753 t = readl(reg);
1754 udelay(1);
1755 } while ((GLOB_SFT_RST & t) && (i-- > 0));
1756
1757 if (GLOB_SFT_RST & t) {
1758 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
1759 rc = 1;
1760 }
1761 done:
1762 return rc;
1763 }
1764
1765 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
1766 void __iomem *mmio)
1767 {
1768 void __iomem *port_mmio;
1769 u32 tmp;
1770
1771 tmp = readl(mmio + MV_RESET_CFG);
1772 if ((tmp & (1 << 0)) == 0) {
1773 hpriv->signal[idx].amps = 0x7 << 8;
1774 hpriv->signal[idx].pre = 0x1 << 5;
1775 return;
1776 }
1777
1778 port_mmio = mv_port_base(mmio, idx);
1779 tmp = readl(port_mmio + PHY_MODE2);
1780
1781 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
1782 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
1783 }
1784
1785 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1786 {
1787 writel(0x00000060, mmio + MV_GPIO_PORT_CTL);
1788 }
1789
1790 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1791 unsigned int port)
1792 {
1793 void __iomem *port_mmio = mv_port_base(mmio, port);
1794
1795 u32 hp_flags = hpriv->hp_flags;
1796 int fix_phy_mode2 =
1797 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1798 int fix_phy_mode4 =
1799 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1800 u32 m2, tmp;
1801
1802 if (fix_phy_mode2) {
1803 m2 = readl(port_mmio + PHY_MODE2);
1804 m2 &= ~(1 << 16);
1805 m2 |= (1 << 31);
1806 writel(m2, port_mmio + PHY_MODE2);
1807
1808 udelay(200);
1809
1810 m2 = readl(port_mmio + PHY_MODE2);
1811 m2 &= ~((1 << 16) | (1 << 31));
1812 writel(m2, port_mmio + PHY_MODE2);
1813
1814 udelay(200);
1815 }
1816
1817 /* who knows what this magic does */
1818 tmp = readl(port_mmio + PHY_MODE3);
1819 tmp &= ~0x7F800000;
1820 tmp |= 0x2A800000;
1821 writel(tmp, port_mmio + PHY_MODE3);
1822
1823 if (fix_phy_mode4) {
1824 u32 m4;
1825
1826 m4 = readl(port_mmio + PHY_MODE4);
1827
1828 if (hp_flags & MV_HP_ERRATA_60X1B2)
1829 tmp = readl(port_mmio + 0x310);
1830
1831 m4 = (m4 & ~(1 << 1)) | (1 << 0);
1832
1833 writel(m4, port_mmio + PHY_MODE4);
1834
1835 if (hp_flags & MV_HP_ERRATA_60X1B2)
1836 writel(tmp, port_mmio + 0x310);
1837 }
1838
1839 /* Revert values of pre-emphasis and signal amps to the saved ones */
1840 m2 = readl(port_mmio + PHY_MODE2);
1841
1842 m2 &= ~MV_M2_PREAMP_MASK;
1843 m2 |= hpriv->signal[port].amps;
1844 m2 |= hpriv->signal[port].pre;
1845 m2 &= ~(1 << 16);
1846
1847 /* according to mvSata 3.6.1, some IIE values are fixed */
1848 if (IS_GEN_IIE(hpriv)) {
1849 m2 &= ~0xC30FF01F;
1850 m2 |= 0x0000900F;
1851 }
1852
1853 writel(m2, port_mmio + PHY_MODE2);
1854 }
1855
1856 static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
1857 unsigned int port_no)
1858 {
1859 void __iomem *port_mmio = mv_port_base(mmio, port_no);
1860
1861 writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);
1862
1863 if (IS_60XX(hpriv)) {
1864 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
1865 ifctl |= (1 << 7); /* enable gen2i speed */
1866 ifctl = (ifctl & 0xfff) | 0x9b1000; /* from chip spec */
1867 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
1868 }
1869
1870 udelay(25); /* allow reset propagation */
1871
1872 /* Spec never mentions clearing the bit. Marvell's driver does
1873 * clear the bit, however.
1874 */
1875 writelfl(0, port_mmio + EDMA_CMD_OFS);
1876
1877 hpriv->ops->phy_errata(hpriv, mmio, port_no);
1878
1879 if (IS_50XX(hpriv))
1880 mdelay(1);
1881 }
1882
1883 static void mv_stop_and_reset(struct ata_port *ap)
1884 {
1885 struct mv_host_priv *hpriv = ap->host->private_data;
1886 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
1887
1888 mv_stop_dma(ap);
1889
1890 mv_channel_reset(hpriv, mmio, ap->port_no);
1891
1892 __mv_phy_reset(ap, 0);
1893 }
1894
1895 static inline void __msleep(unsigned int msec, int can_sleep)
1896 {
1897 if (can_sleep)
1898 msleep(msec);
1899 else
1900 mdelay(msec);
1901 }
1902
1903 /**
1904 * __mv_phy_reset - Perform eDMA reset followed by COMRESET
1905 * @ap: ATA channel to manipulate
1906 *
1907 * Part of this is taken from __sata_phy_reset and modified to
1908 * not sleep since this routine gets called from interrupt level.
1909 *
1910 * LOCKING:
1911 * Inherited from caller. This is coded to safe to call at
1912 * interrupt level, i.e. it does not sleep.
1913 */
1914 static void __mv_phy_reset(struct ata_port *ap, int can_sleep)
1915 {
1916 struct mv_port_priv *pp = ap->private_data;
1917 struct mv_host_priv *hpriv = ap->host->private_data;
1918 void __iomem *port_mmio = mv_ap_base(ap);
1919 struct ata_taskfile tf;
1920 struct ata_device *dev = &ap->device[0];
1921 unsigned long timeout;
1922 int retry = 5;
1923 u32 sstatus;
1924
1925 VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio);
1926
1927 DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x "
1928 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1929 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1930
1931 /* Issue COMRESET via SControl */
1932 comreset_retry:
1933 sata_scr_write_flush(ap, SCR_CONTROL, 0x301);
1934 __msleep(1, can_sleep);
1935
1936 sata_scr_write_flush(ap, SCR_CONTROL, 0x300);
1937 __msleep(20, can_sleep);
1938
1939 timeout = jiffies + msecs_to_jiffies(200);
1940 do {
1941 sata_scr_read(ap, SCR_STATUS, &sstatus);
1942 if (((sstatus & 0x3) == 3) || ((sstatus & 0x3) == 0))
1943 break;
1944
1945 __msleep(1, can_sleep);
1946 } while (time_before(jiffies, timeout));
1947
1948 /* work around errata */
1949 if (IS_60XX(hpriv) &&
1950 (sstatus != 0x0) && (sstatus != 0x113) && (sstatus != 0x123) &&
1951 (retry-- > 0))
1952 goto comreset_retry;
1953
1954 DPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x "
1955 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1956 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1957
1958 if (ata_port_online(ap)) {
1959 ata_port_probe(ap);
1960 } else {
1961 sata_scr_read(ap, SCR_STATUS, &sstatus);
1962 ata_port_printk(ap, KERN_INFO,
1963 "no device found (phy stat %08x)\n", sstatus);
1964 ata_port_disable(ap);
1965 return;
1966 }
1967
1968 /* even after SStatus reflects that device is ready,
1969 * it seems to take a while for link to be fully
1970 * established (and thus Status no longer 0x80/0x7F),
1971 * so we poll a bit for that, here.
1972 */
1973 retry = 20;
1974 while (1) {
1975 u8 drv_stat = ata_check_status(ap);
1976 if ((drv_stat != 0x80) && (drv_stat != 0x7f))
1977 break;
1978 __msleep(500, can_sleep);
1979 if (retry-- <= 0)
1980 break;
1981 }
1982
1983 tf.lbah = readb(ap->ioaddr.lbah_addr);
1984 tf.lbam = readb(ap->ioaddr.lbam_addr);
1985 tf.lbal = readb(ap->ioaddr.lbal_addr);
1986 tf.nsect = readb(ap->ioaddr.nsect_addr);
1987
1988 dev->class = ata_dev_classify(&tf);
1989 if (!ata_dev_enabled(dev)) {
1990 VPRINTK("Port disabled post-sig: No device present.\n");
1991 ata_port_disable(ap);
1992 }
1993
1994 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1995
1996 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1997
1998 VPRINTK("EXIT\n");
1999 }
2000
2001 static void mv_phy_reset(struct ata_port *ap)
2002 {
2003 __mv_phy_reset(ap, 1);
2004 }
2005
2006 /**
2007 * mv_eng_timeout - Routine called by libata when SCSI times out I/O
2008 * @ap: ATA channel to manipulate
2009 *
2010 * Intent is to clear all pending error conditions, reset the
2011 * chip/bus, fail the command, and move on.
2012 *
2013 * LOCKING:
2014 * This routine holds the host lock while failing the command.
2015 */
2016 static void mv_eng_timeout(struct ata_port *ap)
2017 {
2018 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
2019 struct ata_queued_cmd *qc;
2020 unsigned long flags;
2021
2022 ata_port_printk(ap, KERN_ERR, "Entering mv_eng_timeout\n");
2023 DPRINTK("All regs @ start of eng_timeout\n");
2024 mv_dump_all_regs(mmio, ap->port_no, to_pci_dev(ap->host->dev));
2025
2026 qc = ata_qc_from_tag(ap, ap->active_tag);
2027 printk(KERN_ERR "mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n",
2028 mmio, ap, qc, qc->scsicmd, &qc->scsicmd->cmnd);
2029
2030 spin_lock_irqsave(&ap->host->lock, flags);
2031 mv_err_intr(ap, 0);
2032 mv_stop_and_reset(ap);
2033 spin_unlock_irqrestore(&ap->host->lock, flags);
2034
2035 WARN_ON(!(qc->flags & ATA_QCFLAG_ACTIVE));
2036 if (qc->flags & ATA_QCFLAG_ACTIVE) {
2037 qc->err_mask |= AC_ERR_TIMEOUT;
2038 ata_eh_qc_complete(qc);
2039 }
2040 }
2041
2042 /**
2043 * mv_port_init - Perform some early initialization on a single port.
2044 * @port: libata data structure storing shadow register addresses
2045 * @port_mmio: base address of the port
2046 *
2047 * Initialize shadow register mmio addresses, clear outstanding
2048 * interrupts on the port, and unmask interrupts for the future
2049 * start of the port.
2050 *
2051 * LOCKING:
2052 * Inherited from caller.
2053 */
2054 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
2055 {
2056 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
2057 unsigned serr_ofs;
2058
2059 /* PIO related setup
2060 */
2061 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
2062 port->error_addr =
2063 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
2064 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
2065 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
2066 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
2067 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
2068 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
2069 port->status_addr =
2070 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
2071 /* special case: control/altstatus doesn't have ATA_REG_ address */
2072 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
2073
2074 /* unused: */
2075 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
2076
2077 /* Clear any currently outstanding port interrupt conditions */
2078 serr_ofs = mv_scr_offset(SCR_ERROR);
2079 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
2080 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2081
2082 /* unmask all EDMA error interrupts */
2083 writelfl(~0, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
2084
2085 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
2086 readl(port_mmio + EDMA_CFG_OFS),
2087 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
2088 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
2089 }
2090
2091 static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
2092 {
2093 struct pci_dev *pdev = to_pci_dev(host->dev);
2094 struct mv_host_priv *hpriv = host->private_data;
2095 u8 rev_id;
2096 u32 hp_flags = hpriv->hp_flags;
2097
2098 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
2099
2100 switch(board_idx) {
2101 case chip_5080:
2102 hpriv->ops = &mv5xxx_ops;
2103 hp_flags |= MV_HP_50XX;
2104
2105 switch (rev_id) {
2106 case 0x1:
2107 hp_flags |= MV_HP_ERRATA_50XXB0;
2108 break;
2109 case 0x3:
2110 hp_flags |= MV_HP_ERRATA_50XXB2;
2111 break;
2112 default:
2113 dev_printk(KERN_WARNING, &pdev->dev,
2114 "Applying 50XXB2 workarounds to unknown rev\n");
2115 hp_flags |= MV_HP_ERRATA_50XXB2;
2116 break;
2117 }
2118 break;
2119
2120 case chip_504x:
2121 case chip_508x:
2122 hpriv->ops = &mv5xxx_ops;
2123 hp_flags |= MV_HP_50XX;
2124
2125 switch (rev_id) {
2126 case 0x0:
2127 hp_flags |= MV_HP_ERRATA_50XXB0;
2128 break;
2129 case 0x3:
2130 hp_flags |= MV_HP_ERRATA_50XXB2;
2131 break;
2132 default:
2133 dev_printk(KERN_WARNING, &pdev->dev,
2134 "Applying B2 workarounds to unknown rev\n");
2135 hp_flags |= MV_HP_ERRATA_50XXB2;
2136 break;
2137 }
2138 break;
2139
2140 case chip_604x:
2141 case chip_608x:
2142 hpriv->ops = &mv6xxx_ops;
2143
2144 switch (rev_id) {
2145 case 0x7:
2146 hp_flags |= MV_HP_ERRATA_60X1B2;
2147 break;
2148 case 0x9:
2149 hp_flags |= MV_HP_ERRATA_60X1C0;
2150 break;
2151 default:
2152 dev_printk(KERN_WARNING, &pdev->dev,
2153 "Applying B2 workarounds to unknown rev\n");
2154 hp_flags |= MV_HP_ERRATA_60X1B2;
2155 break;
2156 }
2157 break;
2158
2159 case chip_7042:
2160 case chip_6042:
2161 hpriv->ops = &mv6xxx_ops;
2162
2163 hp_flags |= MV_HP_GEN_IIE;
2164
2165 switch (rev_id) {
2166 case 0x0:
2167 hp_flags |= MV_HP_ERRATA_XX42A0;
2168 break;
2169 case 0x1:
2170 hp_flags |= MV_HP_ERRATA_60X1C0;
2171 break;
2172 default:
2173 dev_printk(KERN_WARNING, &pdev->dev,
2174 "Applying 60X1C0 workarounds to unknown rev\n");
2175 hp_flags |= MV_HP_ERRATA_60X1C0;
2176 break;
2177 }
2178 break;
2179
2180 default:
2181 printk(KERN_ERR DRV_NAME ": BUG: invalid board index %u\n", board_idx);
2182 return 1;
2183 }
2184
2185 hpriv->hp_flags = hp_flags;
2186
2187 return 0;
2188 }
2189
2190 /**
2191 * mv_init_host - Perform some early initialization of the host.
2192 * @host: ATA host to initialize
2193 * @board_idx: controller index
2194 *
2195 * If possible, do an early global reset of the host. Then do
2196 * our port init and clear/unmask all/relevant host interrupts.
2197 *
2198 * LOCKING:
2199 * Inherited from caller.
2200 */
2201 static int mv_init_host(struct ata_host *host, unsigned int board_idx)
2202 {
2203 int rc = 0, n_hc, port, hc;
2204 struct pci_dev *pdev = to_pci_dev(host->dev);
2205 void __iomem *mmio = host->iomap[MV_PRIMARY_BAR];
2206 struct mv_host_priv *hpriv = host->private_data;
2207
2208 /* global interrupt mask */
2209 writel(0, mmio + HC_MAIN_IRQ_MASK_OFS);
2210
2211 rc = mv_chip_id(host, board_idx);
2212 if (rc)
2213 goto done;
2214
2215 n_hc = mv_get_hc_count(host->ports[0]->flags);
2216
2217 for (port = 0; port < host->n_ports; port++)
2218 hpriv->ops->read_preamp(hpriv, port, mmio);
2219
2220 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
2221 if (rc)
2222 goto done;
2223
2224 hpriv->ops->reset_flash(hpriv, mmio);
2225 hpriv->ops->reset_bus(pdev, mmio);
2226 hpriv->ops->enable_leds(hpriv, mmio);
2227
2228 for (port = 0; port < host->n_ports; port++) {
2229 if (IS_60XX(hpriv)) {
2230 void __iomem *port_mmio = mv_port_base(mmio, port);
2231
2232 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
2233 ifctl |= (1 << 7); /* enable gen2i speed */
2234 ifctl = (ifctl & 0xfff) | 0x9b1000; /* from chip spec */
2235 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
2236 }
2237
2238 hpriv->ops->phy_errata(hpriv, mmio, port);
2239 }
2240
2241 for (port = 0; port < host->n_ports; port++) {
2242 void __iomem *port_mmio = mv_port_base(mmio, port);
2243 mv_port_init(&host->ports[port]->ioaddr, port_mmio);
2244 }
2245
2246 for (hc = 0; hc < n_hc; hc++) {
2247 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2248
2249 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
2250 "(before clear)=0x%08x\n", hc,
2251 readl(hc_mmio + HC_CFG_OFS),
2252 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
2253
2254 /* Clear any currently outstanding hc interrupt conditions */
2255 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
2256 }
2257
2258 /* Clear any currently outstanding host interrupt conditions */
2259 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
2260
2261 /* and unmask interrupt generation for host regs */
2262 writelfl(PCI_UNMASK_ALL_IRQS, mmio + PCI_IRQ_MASK_OFS);
2263
2264 if (IS_50XX(hpriv))
2265 writelfl(~HC_MAIN_MASKED_IRQS_5, mmio + HC_MAIN_IRQ_MASK_OFS);
2266 else
2267 writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS);
2268
2269 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
2270 "PCI int cause/mask=0x%08x/0x%08x\n",
2271 readl(mmio + HC_MAIN_IRQ_CAUSE_OFS),
2272 readl(mmio + HC_MAIN_IRQ_MASK_OFS),
2273 readl(mmio + PCI_IRQ_CAUSE_OFS),
2274 readl(mmio + PCI_IRQ_MASK_OFS));
2275
2276 done:
2277 return rc;
2278 }
2279
2280 /**
2281 * mv_print_info - Dump key info to kernel log for perusal.
2282 * @host: ATA host to print info about
2283 *
2284 * FIXME: complete this.
2285 *
2286 * LOCKING:
2287 * Inherited from caller.
2288 */
2289 static void mv_print_info(struct ata_host *host)
2290 {
2291 struct pci_dev *pdev = to_pci_dev(host->dev);
2292 struct mv_host_priv *hpriv = host->private_data;
2293 u8 rev_id, scc;
2294 const char *scc_s;
2295
2296 /* Use this to determine the HW stepping of the chip so we know
2297 * what errata to workaround
2298 */
2299 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
2300
2301 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
2302 if (scc == 0)
2303 scc_s = "SCSI";
2304 else if (scc == 0x01)
2305 scc_s = "RAID";
2306 else
2307 scc_s = "unknown";
2308
2309 dev_printk(KERN_INFO, &pdev->dev,
2310 "%u slots %u ports %s mode IRQ via %s\n",
2311 (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
2312 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
2313 }
2314
2315 /**
2316 * mv_init_one - handle a positive probe of a Marvell host
2317 * @pdev: PCI device found
2318 * @ent: PCI device ID entry for the matched host
2319 *
2320 * LOCKING:
2321 * Inherited from caller.
2322 */
2323 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2324 {
2325 static int printed_version = 0;
2326 unsigned int board_idx = (unsigned int)ent->driver_data;
2327 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
2328 struct ata_host *host;
2329 struct mv_host_priv *hpriv;
2330 int n_ports, rc;
2331
2332 if (!printed_version++)
2333 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
2334
2335 /* allocate host */
2336 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
2337
2338 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
2339 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
2340 if (!host || !hpriv)
2341 return -ENOMEM;
2342 host->private_data = hpriv;
2343
2344 /* acquire resources */
2345 rc = pcim_enable_device(pdev);
2346 if (rc)
2347 return rc;
2348
2349 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
2350 if (rc == -EBUSY)
2351 pcim_pin_device(pdev);
2352 if (rc)
2353 return rc;
2354 host->iomap = pcim_iomap_table(pdev);
2355
2356 rc = pci_go_64(pdev);
2357 if (rc)
2358 return rc;
2359
2360 /* initialize adapter */
2361 rc = mv_init_host(host, board_idx);
2362 if (rc)
2363 return rc;
2364
2365 /* Enable interrupts */
2366 if (msi && pci_enable_msi(pdev))
2367 pci_intx(pdev, 1);
2368
2369 mv_dump_pci_cfg(pdev, 0x68);
2370 mv_print_info(host);
2371
2372 pci_set_master(pdev);
2373 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
2374 &mv_sht);
2375 }
2376
2377 static int __init mv_init(void)
2378 {
2379 return pci_register_driver(&mv_pci_driver);
2380 }
2381
2382 static void __exit mv_exit(void)
2383 {
2384 pci_unregister_driver(&mv_pci_driver);
2385 }
2386
2387 MODULE_AUTHOR("Brett Russ");
2388 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
2389 MODULE_LICENSE("GPL");
2390 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
2391 MODULE_VERSION(DRV_VERSION);
2392
2393 module_param(msi, int, 0444);
2394 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
2395
2396 module_init(mv_init);
2397 module_exit(mv_exit);
WRT350N Kernel Patches