drivers/scsi/qla2xxx/qla_fw.h

   1 /*
   2  * QLogic Fibre Channel HBA Driver
   3  * Copyright (c)  2003-2005 QLogic Corporation
   4  *
   5  * See LICENSE.qla2xxx for copyright and licensing details.
   6  */
   7 #ifndef __QLA_FW_H
   8 #define __QLA_FW_H
   9
  10 #define MBS_CHECKSUM_ERROR      0x4010
  11
  12 /*
  13  * Firmware Options.
  14  */
  15 #define FO1_ENABLE_PUREX        BIT_10
  16 #define FO1_DISABLE_LED_CTRL    BIT_6
  17 #define FO2_ENABLE_SEL_CLASS2   BIT_5
  18 #define FO3_NO_ABTS_ON_LINKDOWN BIT_14
  19
  20 /*
  21  * Port Database structure definition for ISP 24xx.
  22  */
  23 #define PDO_FORCE_ADISC         BIT_1
  24 #define PDO_FORCE_PLOGI         BIT_0
  25
  26
  27 #define PORT_DATABASE_24XX_SIZE         64
  28 struct port_database_24xx {
  29         uint16_t flags;
  30 #define PDF_TASK_RETRY_ID       BIT_14
  31 #define PDF_FC_TAPE             BIT_7
  32 #define PDF_ACK0_CAPABLE        BIT_6
  33 #define PDF_FCP2_CONF           BIT_5
  34 #define PDF_CLASS_2             BIT_4
  35 #define PDF_HARD_ADDR           BIT_1
  36
  37         uint8_t current_login_state;
  38         uint8_t last_login_state;
  39 #define PDS_PLOGI_PENDING       0x03
  40 #define PDS_PLOGI_COMPLETE      0x04
  41 #define PDS_PRLI_PENDING        0x05
  42 #define PDS_PRLI_COMPLETE       0x06
  43 #define PDS_PORT_UNAVAILABLE    0x07
  44 #define PDS_PRLO_PENDING        0x09
  45 #define PDS_LOGO_PENDING        0x11
  46 #define PDS_PRLI2_PENDING       0x12
  47
  48         uint8_t hard_address[3];
  49         uint8_t reserved_1;
  50
  51         uint8_t port_id[3];
  52         uint8_t sequence_id;
  53
  54         uint16_t port_timer;
  55
  56         uint16_t nport_handle;                  /* N_PORT handle. */
  57
  58         uint16_t receive_data_size;
  59         uint16_t reserved_2;
  60
  61         uint8_t prli_svc_param_word_0[2];       /* Big endian */
  62                                                 /* Bits 15-0 of word 0 */
  63         uint8_t prli_svc_param_word_3[2];       /* Big endian */
  64                                                 /* Bits 15-0 of word 3 */
  65
  66         uint8_t port_name[WWN_SIZE];
  67         uint8_t node_name[WWN_SIZE];
  68
  69         uint8_t reserved_3[24];
  70 };
  71
  72 struct nvram_24xx {
  73         /* NVRAM header. */
  74         uint8_t id[4];
  75         uint16_t nvram_version;
  76         uint16_t reserved_0;
  77
  78         /* Firmware Initialization Control Block. */
  79         uint16_t version;
  80         uint16_t reserved_1;
  81         uint16_t frame_payload_size;
  82         uint16_t execution_throttle;
  83         uint16_t exchange_count;
  84         uint16_t hard_address;
  85
  86         uint8_t port_name[WWN_SIZE];
  87         uint8_t node_name[WWN_SIZE];
  88
  89         uint16_t login_retry_count;
  90         uint16_t link_down_on_nos;
  91         uint16_t interrupt_delay_timer;
  92         uint16_t login_timeout;
  93
  94         uint32_t firmware_options_1;
  95         uint32_t firmware_options_2;
  96         uint32_t firmware_options_3;
  97
  98         /* Offset 56. */
  99
 100         /*
 101          * BIT 0     = Control Enable
 102          * BIT 1-15  =
 103          *
 104          * BIT 0-7   = Reserved
 105          * BIT 8-10  = Output Swing 1G
 106          * BIT 11-13 = Output Emphasis 1G
 107          * BIT 14-15 = Reserved
 108          *
 109          * BIT 0-7   = Reserved
 110          * BIT 8-10  = Output Swing 2G
 111          * BIT 11-13 = Output Emphasis 2G
 112          * BIT 14-15 = Reserved
 113          *
 114          * BIT 0-7   = Reserved
 115          * BIT 8-10  = Output Swing 4G
 116          * BIT 11-13 = Output Emphasis 4G
 117          * BIT 14-15 = Reserved
 118          */
 119         uint16_t seriallink_options[4];
 120
 121         uint16_t reserved_2[16];
 122
 123         /* Offset 96. */
 124         uint16_t reserved_3[16];
 125
 126         /* PCIe table entries. */
 127         uint16_t reserved_4[16];
 128
 129         /* Offset 160. */
 130         uint16_t reserved_5[16];
 131
 132         /* Offset 192. */
 133         uint16_t reserved_6[16];
 134
 135         /* Offset 224. */
 136         uint16_t reserved_7[16];
 137
 138         /*
 139          * BIT 0  = Enable spinup delay
 140          * BIT 1  = Disable BIOS
 141          * BIT 2  = Enable Memory Map BIOS
 142          * BIT 3  = Enable Selectable Boot
 143          * BIT 4  = Disable RISC code load
 144          * BIT 5  = Disable Serdes
 145          * BIT 6  =
 146          * BIT 7  =
 147          *
 148          * BIT 8  =
 149          * BIT 9  =
 150          * BIT 10 = Enable lip full login
 151          * BIT 11 = Enable target reset
 152          * BIT 12 =
 153          * BIT 13 =
 154          * BIT 14 =
 155          * BIT 15 = Enable alternate WWN
 156          *
 157          * BIT 16-31 =
 158          */
 159         uint32_t host_p;
 160
 161         uint8_t alternate_port_name[WWN_SIZE];
 162         uint8_t alternate_node_name[WWN_SIZE];
 163
 164         uint8_t boot_port_name[WWN_SIZE];
 165         uint16_t boot_lun_number;
 166         uint16_t reserved_8;
 167
 168         uint8_t alt1_boot_port_name[WWN_SIZE];
 169         uint16_t alt1_boot_lun_number;
 170         uint16_t reserved_9;
 171
 172         uint8_t alt2_boot_port_name[WWN_SIZE];
 173         uint16_t alt2_boot_lun_number;
 174         uint16_t reserved_10;
 175
 176         uint8_t alt3_boot_port_name[WWN_SIZE];
 177         uint16_t alt3_boot_lun_number;
 178         uint16_t reserved_11;
 179
 180         /*
 181          * BIT 0 = Selective Login
 182          * BIT 1 = Alt-Boot Enable
 183          * BIT 2 = Reserved
 184          * BIT 3 = Boot Order List
 185          * BIT 4 = Reserved
 186          * BIT 5 = Selective LUN
 187          * BIT 6 = Reserved
 188          * BIT 7-31 =
 189          */
 190         uint32_t efi_parameters;
 191
 192         uint8_t reset_delay;
 193         uint8_t reserved_12;
 194         uint16_t reserved_13;
 195
 196         uint16_t boot_id_number;
 197         uint16_t reserved_14;
 198
 199         uint16_t max_luns_per_target;
 200         uint16_t reserved_15;
 201
 202         uint16_t port_down_retry_count;
 203         uint16_t link_down_timeout;
 204
 205         /* FCode parameters. */
 206         uint16_t fcode_parameter;
 207
 208         uint16_t reserved_16[3];
 209
 210         /* Offset 352. */
 211         uint8_t prev_drv_ver_major;
 212         uint8_t prev_drv_ver_submajob;
 213         uint8_t prev_drv_ver_minor;
 214         uint8_t prev_drv_ver_subminor;
 215
 216         uint16_t prev_bios_ver_major;
 217         uint16_t prev_bios_ver_minor;
 218
 219         uint16_t prev_efi_ver_major;
 220         uint16_t prev_efi_ver_minor;
 221
 222         uint16_t prev_fw_ver_major;
 223         uint8_t prev_fw_ver_minor;
 224         uint8_t prev_fw_ver_subminor;
 225
 226         uint16_t reserved_17[8];
 227
 228         /* Offset 384. */
 229         uint16_t reserved_18[16];
 230
 231         /* Offset 416. */
 232         uint16_t reserved_19[16];
 233
 234         /* Offset 448. */
 235         uint16_t reserved_20[16];
 236
 237         /* Offset 480. */
 238         uint8_t model_name[16];
 239
 240         uint16_t reserved_21[2];
 241
 242         /* Offset 500. */
 243         /* HW Parameter Block. */
 244         uint16_t pcie_table_sig;
 245         uint16_t pcie_table_offset;
 246
 247         uint16_t subsystem_vendor_id;
 248         uint16_t subsystem_device_id;
 249
 250         uint32_t checksum;
 251 };
 252
 253 /*
 254  * ISP Initialization Control Block.
 255  * Little endian except where noted.
 256  */
 257 #define ICB_VERSION 1
 258 struct init_cb_24xx {
 259         uint16_t version;
 260         uint16_t reserved_1;
 261
 262         uint16_t frame_payload_size;
 263         uint16_t execution_throttle;
 264         uint16_t exchange_count;
 265
 266         uint16_t hard_address;
 267
 268         uint8_t port_name[WWN_SIZE];            /* Big endian. */
 269         uint8_t node_name[WWN_SIZE];            /* Big endian. */
 270
 271         uint16_t response_q_inpointer;
 272         uint16_t request_q_outpointer;
 273
 274         uint16_t login_retry_count;
 275
 276         uint16_t prio_request_q_outpointer;
 277
 278         uint16_t response_q_length;
 279         uint16_t request_q_length;
 280
 281         uint16_t link_down_on_nos;              /* Milliseconds. */
 282
 283         uint16_t prio_request_q_length;
 284
 285         uint32_t request_q_address[2];
 286         uint32_t response_q_address[2];
 287         uint32_t prio_request_q_address[2];
 288
 289         uint8_t reserved_2[8];
 290
 291         uint16_t atio_q_inpointer;
 292         uint16_t atio_q_length;
 293         uint32_t atio_q_address[2];
 294
 295         uint16_t interrupt_delay_timer;         /* 100us increments. */
 296         uint16_t login_timeout;
 297
 298         /*
 299          * BIT 0  = Enable Hard Loop Id
 300          * BIT 1  = Enable Fairness
 301          * BIT 2  = Enable Full-Duplex
 302          * BIT 3  = Reserved
 303          * BIT 4  = Enable Target Mode
 304          * BIT 5  = Disable Initiator Mode
 305          * BIT 6  = Reserved
 306          * BIT 7  = Reserved
 307          *
 308          * BIT 8  = Reserved
 309          * BIT 9  = Non Participating LIP
 310          * BIT 10 = Descending Loop ID Search
 311          * BIT 11 = Acquire Loop ID in LIPA
 312          * BIT 12 = Reserved
 313          * BIT 13 = Full Login after LIP
 314          * BIT 14 = Node Name Option
 315          * BIT 15-31 = Reserved
 316          */
 317         uint32_t firmware_options_1;
 318
 319         /*
 320          * BIT 0  = Operation Mode bit 0
 321          * BIT 1  = Operation Mode bit 1
 322          * BIT 2  = Operation Mode bit 2
 323          * BIT 3  = Operation Mode bit 3
 324          * BIT 4  = Connection Options bit 0
 325          * BIT 5  = Connection Options bit 1
 326          * BIT 6  = Connection Options bit 2
 327          * BIT 7  = Enable Non part on LIHA failure
 328          *
 329          * BIT 8  = Enable Class 2
 330          * BIT 9  = Enable ACK0
 331          * BIT 10 = Reserved
 332          * BIT 11 = Enable FC-SP Security
 333          * BIT 12 = FC Tape Enable
 334          * BIT 13-31 = Reserved
 335          */
 336         uint32_t firmware_options_2;
 337
 338         /*
 339          * BIT 0  = Reserved
 340          * BIT 1  = Soft ID only
 341          * BIT 2  = Reserved
 342          * BIT 3  = Reserved
 343          * BIT 4  = FCP RSP Payload bit 0
 344          * BIT 5  = FCP RSP Payload bit 1
 345          * BIT 6  = Enable Receive Out-of-Order data frame handling
 346          * BIT 7  = Disable Automatic PLOGI on Local Loop
 347          *
 348          * BIT 8  = Reserved
 349          * BIT 9  = Enable Out-of-Order FCP_XFER_RDY relative offset handling
 350          * BIT 10 = Reserved
 351          * BIT 11 = Reserved
 352          * BIT 12 = Reserved
 353          * BIT 13 = Data Rate bit 0
 354          * BIT 14 = Data Rate bit 1
 355          * BIT 15 = Data Rate bit 2
 356          * BIT 16-31 = Reserved
 357          */
 358         uint32_t firmware_options_3;
 359
 360         uint8_t  reserved_3[24];
 361 };
 362
 363 /*
 364  * ISP queue - command entry structure definition.
 365  */
 366 #define COMMAND_TYPE_6  0x48            /* Command Type 6 entry */
 367 struct cmd_type_6 {
 368         uint8_t entry_type;             /* Entry type. */
 369         uint8_t entry_count;            /* Entry count. */
 370         uint8_t sys_define;             /* System defined. */
 371         uint8_t entry_status;           /* Entry Status. */
 372
 373         uint32_t handle;                /* System handle. */
 374
 375         uint16_t nport_handle;          /* N_PORT handle. */
 376         uint16_t timeout;               /* Command timeout. */
 377
 378         uint16_t dseg_count;            /* Data segment count. */
 379
 380         uint16_t fcp_rsp_dsd_len;       /* FCP_RSP DSD length. */
 381
 382         struct scsi_lun lun;            /* FCP LUN (BE). */
 383
 384         uint16_t control_flags;         /* Control flags. */
 385 #define CF_DATA_SEG_DESCR_ENABLE        BIT_2
 386 #define CF_READ_DATA                    BIT_1
 387 #define CF_WRITE_DATA                   BIT_0
 388
 389         uint16_t fcp_cmnd_dseg_len;             /* Data segment length. */
 390         uint32_t fcp_cmnd_dseg_address[2];      /* Data segment address. */
 391
 392         uint32_t fcp_rsp_dseg_address[2];       /* Data segment address. */
 393
 394         uint32_t byte_count;            /* Total byte count. */
 395
 396         uint8_t port_id[3];             /* PortID of destination port. */
 397         uint8_t vp_index;
 398
 399         uint32_t fcp_data_dseg_address[2];      /* Data segment address. */
 400         uint16_t fcp_data_dseg_len;             /* Data segment length. */
 401         uint16_t reserved_1;                    /* MUST be set to 0. */
 402 };
 403
 404 #define COMMAND_TYPE_7  0x18            /* Command Type 7 entry */
 405 struct cmd_type_7 {
 406         uint8_t entry_type;             /* Entry type. */
 407         uint8_t entry_count;            /* Entry count. */
 408         uint8_t sys_define;             /* System defined. */
 409         uint8_t entry_status;           /* Entry Status. */
 410
 411         uint32_t handle;                /* System handle. */
 412
 413         uint16_t nport_handle;          /* N_PORT handle. */
 414         uint16_t timeout;               /* Command timeout. */
 415 #define FW_MAX_TIMEOUT          0x1999
 416
 417         uint16_t dseg_count;            /* Data segment count. */
 418         uint16_t reserved_1;
 419
 420         struct scsi_lun lun;            /* FCP LUN (BE). */
 421
 422         uint16_t task_mgmt_flags;       /* Task management flags. */
 423 #define TMF_CLEAR_ACA           BIT_14
 424 #define TMF_TARGET_RESET        BIT_13
 425 #define TMF_LUN_RESET           BIT_12
 426 #define TMF_CLEAR_TASK_SET      BIT_10
 427 #define TMF_ABORT_TASK_SET      BIT_9
 428 #define TMF_READ_DATA           BIT_1
 429 #define TMF_WRITE_DATA          BIT_0
 430
 431         uint8_t task;
 432 #define TSK_SIMPLE              0
 433 #define TSK_HEAD_OF_QUEUE       1
 434 #define TSK_ORDERED             2
 435 #define TSK_ACA                 4
 436 #define TSK_UNTAGGED            5
 437
 438         uint8_t crn;
 439
 440         uint8_t fcp_cdb[MAX_CMDSZ];     /* SCSI command words. */
 441         uint32_t byte_count;            /* Total byte count. */
 442
 443         uint8_t port_id[3];             /* PortID of destination port. */
 444         uint8_t vp_index;
 445
 446         uint32_t dseg_0_address[2];     /* Data segment 0 address. */
 447         uint32_t dseg_0_len;            /* Data segment 0 length. */
 448 };
 449
 450 /*
 451  * ISP queue - status entry structure definition.
 452  */
 453 #define STATUS_TYPE     0x03            /* Status entry. */
 454 struct sts_entry_24xx {
 455         uint8_t entry_type;             /* Entry type. */
 456         uint8_t entry_count;            /* Entry count. */
 457         uint8_t sys_define;             /* System defined. */
 458         uint8_t entry_status;           /* Entry Status. */
 459
 460         uint32_t handle;                /* System handle. */
 461
 462         uint16_t comp_status;           /* Completion status. */
 463         uint16_t ox_id;                 /* OX_ID used by the firmware. */
 464
 465         uint32_t residual_len;          /* FW calc residual transfer length. */
 466
 467         uint16_t reserved_1;
 468         uint16_t state_flags;           /* State flags. */
 469 #define SF_TRANSFERRED_DATA     BIT_11
 470 #define SF_FCP_RSP_DMA          BIT_0
 471
 472         uint16_t reserved_2;
 473         uint16_t scsi_status;           /* SCSI status. */
 474 #define SS_CONFIRMATION_REQ             BIT_12
 475
 476         uint32_t rsp_residual_count;    /* FCP RSP residual count. */
 477
 478         uint32_t sense_len;             /* FCP SENSE length. */
 479         uint32_t rsp_data_len;          /* FCP response data length. */
 480
 481         uint8_t data[28];               /* FCP response/sense information. */
 482 };
 483
 484 /*
 485  * Status entry completion status
 486  */
 487 #define CS_DATA_REASSEMBLY_ERROR 0x11   /* Data Reassembly Error.. */
 488 #define CS_ABTS_BY_TARGET       0x13    /* Target send ABTS to abort IOCB. */
 489 #define CS_FW_RESOURCE          0x2C    /* Firmware Resource Unavailable. */
 490 #define CS_TASK_MGMT_OVERRUN    0x30    /* Task management overrun (8+). */
 491 #define CS_ABORT_BY_TARGET      0x47    /* Abort By Target. */
 492
 493 /*
 494  * ISP queue - marker entry structure definition.
 495  */
 496 #define MARKER_TYPE     0x04            /* Marker entry. */
 497 struct mrk_entry_24xx {
 498         uint8_t entry_type;             /* Entry type. */
 499         uint8_t entry_count;            /* Entry count. */
 500         uint8_t handle_count;           /* Handle count. */
 501         uint8_t entry_status;           /* Entry Status. */
 502
 503         uint32_t handle;                /* System handle. */
 504
 505         uint16_t nport_handle;          /* N_PORT handle. */
 506
 507         uint8_t modifier;               /* Modifier (7-0). */
 508 #define MK_SYNC_ID_LUN  0               /* Synchronize ID/LUN */
 509 #define MK_SYNC_ID      1               /* Synchronize ID */
 510 #define MK_SYNC_ALL     2               /* Synchronize all ID/LUN */
 511         uint8_t reserved_1;
 512
 513         uint8_t reserved_2;
 514         uint8_t vp_index;
 515
 516         uint16_t reserved_3;
 517
 518         uint8_t lun[8];                 /* FCP LUN (BE). */
 519         uint8_t reserved_4[40];
 520 };
 521
 522 /*
 523  * ISP queue - CT Pass-Through entry structure definition.
 524  */
 525 #define CT_IOCB_TYPE            0x29    /* CT Pass-Through IOCB entry */
 526 struct ct_entry_24xx {
 527         uint8_t entry_type;             /* Entry type. */
 528         uint8_t entry_count;            /* Entry count. */
 529         uint8_t sys_define;             /* System Defined. */
 530         uint8_t entry_status;           /* Entry Status. */
 531
 532         uint32_t handle;                /* System handle. */
 533
 534         uint16_t comp_status;           /* Completion status. */
 535
 536         uint16_t nport_handle;          /* N_PORT handle. */
 537
 538         uint16_t cmd_dsd_count;
 539
 540         uint8_t vp_index;
 541         uint8_t reserved_1;
 542
 543         uint16_t timeout;               /* Command timeout. */
 544         uint16_t reserved_2;
 545
 546         uint16_t rsp_dsd_count;
 547
 548         uint8_t reserved_3[10];
 549
 550         uint32_t rsp_byte_count;
 551         uint32_t cmd_byte_count;
 552
 553         uint32_t dseg_0_address[2];     /* Data segment 0 address. */
 554         uint32_t dseg_0_len;            /* Data segment 0 length. */
 555         uint32_t dseg_1_address[2];     /* Data segment 1 address. */
 556         uint32_t dseg_1_len;            /* Data segment 1 length. */
 557 };
 558
 559 /*
 560  * ISP queue - ELS Pass-Through entry structure definition.
 561  */
 562 #define ELS_IOCB_TYPE           0x53    /* ELS Pass-Through IOCB entry */
 563 struct els_entry_24xx {
 564         uint8_t entry_type;             /* Entry type. */
 565         uint8_t entry_count;            /* Entry count. */
 566         uint8_t sys_define;             /* System Defined. */
 567         uint8_t entry_status;           /* Entry Status. */
 568
 569         uint32_t handle;                /* System handle. */
 570
 571         uint16_t reserved_1;
 572
 573         uint16_t nport_handle;          /* N_PORT handle. */
 574
 575         uint16_t tx_dsd_count;
 576
 577         uint8_t vp_index;
 578         uint8_t sof_type;
 579 #define EST_SOFI3               (1 << 4)
 580 #define EST_SOFI2               (3 << 4)
 581
 582         uint32_t rx_xchg_address[2];    /* Receive exchange address. */
 583         uint16_t rx_dsd_count;
 584
 585         uint8_t opcode;
 586         uint8_t reserved_2;
 587
 588         uint8_t port_id[3];
 589         uint8_t reserved_3;
 590
 591         uint16_t reserved_4;
 592
 593         uint16_t control_flags;         /* Control flags. */
 594 #define ECF_PAYLOAD_DESCR_MASK  (BIT_15|BIT_14|BIT_13)
 595 #define EPD_ELS_COMMAND         (0 << 13)
 596 #define EPD_ELS_ACC             (1 << 13)
 597 #define EPD_ELS_RJT             (2 << 13)
 598 #define EPD_RX_XCHG             (3 << 13)
 599 #define ECF_CLR_PASSTHRU_PEND   BIT_12
 600 #define ECF_INCL_FRAME_HDR      BIT_11
 601
 602         uint32_t rx_byte_count;
 603         uint32_t tx_byte_count;
 604
 605         uint32_t tx_address[2];         /* Data segment 0 address. */
 606         uint32_t tx_len;                /* Data segment 0 length. */
 607         uint32_t rx_address[2];         /* Data segment 1 address. */
 608         uint32_t rx_len;                /* Data segment 1 length. */
 609 };
 610
 611 /*
 612  * ISP queue - Mailbox Command entry structure definition.
 613  */
 614 #define MBX_IOCB_TYPE   0x39
 615 struct mbx_entry_24xx {
 616         uint8_t entry_type;             /* Entry type. */
 617         uint8_t entry_count;            /* Entry count. */
 618         uint8_t handle_count;           /* Handle count. */
 619         uint8_t entry_status;           /* Entry Status. */
 620
 621         uint32_t handle;                /* System handle. */
 622
 623         uint16_t mbx[28];
 624 };
 625
 626
 627 #define LOGINOUT_PORT_IOCB_TYPE 0x52    /* Login/Logout Port entry. */
 628 struct logio_entry_24xx {
 629         uint8_t entry_type;             /* Entry type. */
 630         uint8_t entry_count;            /* Entry count. */
 631         uint8_t sys_define;             /* System defined. */
 632         uint8_t entry_status;           /* Entry Status. */
 633
 634         uint32_t handle;                /* System handle. */
 635
 636         uint16_t comp_status;           /* Completion status. */
 637 #define CS_LOGIO_ERROR          0x31    /* Login/Logout IOCB error. */
 638
 639         uint16_t nport_handle;          /* N_PORT handle. */
 640
 641         uint16_t control_flags;         /* Control flags. */
 642                                         /* Modifiers. */
 643 #define LCF_FCP2_OVERRIDE       BIT_9   /* Set/Reset word 3 of PRLI. */
 644 #define LCF_CLASS_2             BIT_8   /* Enable class 2 during PLOGI. */
 645 #define LCF_FREE_NPORT          BIT_7   /* Release NPORT handle after LOGO. */
 646 #define LCF_EXPL_LOGO           BIT_6   /* Perform an explicit LOGO. */
 647 #define LCF_SKIP_PRLI           BIT_5   /* Skip PRLI after PLOGI. */
 648 #define LCF_IMPL_LOGO_ALL       BIT_5   /* Implicit LOGO to all ports. */
 649 #define LCF_COND_PLOGI          BIT_4   /* PLOGI only if not logged-in. */
 650 #define LCF_IMPL_LOGO           BIT_4   /* Perform an implicit LOGO. */
 651 #define LCF_IMPL_PRLO           BIT_4   /* Perform an implicit PRLO. */
 652                                         /* Commands. */
 653 #define LCF_COMMAND_PLOGI       0x00    /* PLOGI. */
 654 #define LCF_COMMAND_PRLI        0x01    /* PRLI. */
 655 #define LCF_COMMAND_PDISC       0x02    /* PDISC. */
 656 #define LCF_COMMAND_ADISC       0x03    /* ADISC. */
 657 #define LCF_COMMAND_LOGO        0x08    /* LOGO. */
 658 #define LCF_COMMAND_PRLO        0x09    /* PRLO. */
 659 #define LCF_COMMAND_TPRLO       0x0A    /* TPRLO. */
 660
 661         uint8_t vp_index;
 662         uint8_t reserved_1;
 663
 664         uint8_t port_id[3];             /* PortID of destination port. */
 665
 666         uint8_t rsp_size;               /* Response size in 32bit words. */
 667
 668         uint32_t io_parameter[11];      /* General I/O parameters. */
 669 #define LSC_SCODE_NOLINK        0x01
 670 #define LSC_SCODE_NOIOCB        0x02
 671 #define LSC_SCODE_NOXCB         0x03
 672 #define LSC_SCODE_CMD_FAILED    0x04
 673 #define LSC_SCODE_NOFABRIC      0x05
 674 #define LSC_SCODE_FW_NOT_READY  0x07
 675 #define LSC_SCODE_NOT_LOGGED_IN 0x09
 676 #define LSC_SCODE_NOPCB         0x0A
 677
 678 #define LSC_SCODE_ELS_REJECT    0x18
 679 #define LSC_SCODE_CMD_PARAM_ERR 0x19
 680 #define LSC_SCODE_PORTID_USED   0x1A
 681 #define LSC_SCODE_NPORT_USED    0x1B
 682 #define LSC_SCODE_NONPORT       0x1C
 683 #define LSC_SCODE_LOGGED_IN     0x1D
 684 #define LSC_SCODE_NOFLOGI_ACC   0x1F
 685 };
 686
 687 #define TSK_MGMT_IOCB_TYPE      0x14
 688 struct tsk_mgmt_entry {
 689         uint8_t entry_type;             /* Entry type. */
 690         uint8_t entry_count;            /* Entry count. */
 691         uint8_t handle_count;           /* Handle count. */
 692         uint8_t entry_status;           /* Entry Status. */
 693
 694         uint32_t handle;                /* System handle. */
 695
 696         uint16_t nport_handle;          /* N_PORT handle. */
 697
 698         uint16_t reserved_1;
 699
 700         uint16_t delay;                 /* Activity delay in seconds. */
 701
 702         uint16_t timeout;               /* Command timeout. */
 703
 704         uint8_t lun[8];                 /* FCP LUN (BE). */
 705
 706         uint32_t control_flags;         /* Control Flags. */
 707 #define TCF_NOTMCMD_TO_TARGET   BIT_31
 708 #define TCF_LUN_RESET           BIT_4
 709 #define TCF_ABORT_TASK_SET      BIT_3
 710 #define TCF_CLEAR_TASK_SET      BIT_2
 711 #define TCF_TARGET_RESET        BIT_1
 712 #define TCF_CLEAR_ACA           BIT_0
 713
 714         uint8_t reserved_2[20];
 715
 716         uint8_t port_id[3];             /* PortID of destination port. */
 717         uint8_t vp_index;
 718
 719         uint8_t reserved_3[12];
 720 };
 721
 722 #define ABORT_IOCB_TYPE 0x33
 723 struct abort_entry_24xx {
 724         uint8_t entry_type;             /* Entry type. */
 725         uint8_t entry_count;            /* Entry count. */
 726         uint8_t handle_count;           /* Handle count. */
 727         uint8_t entry_status;           /* Entry Status. */
 728
 729         uint32_t handle;                /* System handle. */
 730
 731         uint16_t nport_handle;          /* N_PORT handle. */
 732                                         /* or Completion status. */
 733
 734         uint16_t options;               /* Options. */
 735 #define AOF_NO_ABTS             BIT_0   /* Do not send any ABTS. */
 736
 737         uint32_t handle_to_abort;       /* System handle to abort. */
 738
 739         uint8_t reserved_1[32];
 740
 741         uint8_t port_id[3];             /* PortID of destination port. */
 742         uint8_t vp_index;
 743
 744         uint8_t reserved_2[12];
 745 };
 746
 747 /*
 748  * ISP I/O Register Set structure definitions.
 749  */
 750 struct device_reg_24xx {
 751         uint32_t flash_addr;            /* Flash/NVRAM BIOS address. */
 752 #define FARX_DATA_FLAG  BIT_31
 753 #define FARX_ACCESS_FLASH_CONF  0x7FFD0000
 754 #define FARX_ACCESS_FLASH_DATA  0x7FF00000
 755 #define FARX_ACCESS_NVRAM_CONF  0x7FFF0000
 756 #define FARX_ACCESS_NVRAM_DATA  0x7FFE0000
 757
 758 #define FA_NVRAM_FUNC0_ADDR     0x80
 759 #define FA_NVRAM_FUNC1_ADDR     0x180
 760
 761 #define FA_NVRAM_VPD_SIZE       0x200
 762 #define FA_NVRAM_VPD0_ADDR      0x00
 763 #define FA_NVRAM_VPD1_ADDR      0x100
 764                                         /*
 765                                          * RISC code begins at offset 512KB
 766                                          * within flash. Consisting of two
 767                                          * contiguous RISC code segments.
 768                                          */
 769 #define FA_RISC_CODE_ADDR       0x20000
 770 #define FA_RISC_CODE_SEGMENTS   2
 771
 772         uint32_t flash_data;            /* Flash/NVRAM BIOS data. */
 773
 774         uint32_t ctrl_status;           /* Control/Status. */
 775 #define CSRX_FLASH_ACCESS_ERROR BIT_18  /* Flash/NVRAM Access Error. */
 776 #define CSRX_DMA_ACTIVE         BIT_17  /* DMA Active status. */
 777 #define CSRX_DMA_SHUTDOWN       BIT_16  /* DMA Shutdown control status. */
 778 #define CSRX_FUNCTION           BIT_15  /* Function number. */
 779                                         /* PCI-X Bus Mode. */
 780 #define CSRX_PCIX_BUS_MODE_MASK (BIT_11|BIT_10|BIT_9|BIT_8)
 781 #define PBM_PCI_33MHZ           (0 << 8)
 782 #define PBM_PCIX_M1_66MHZ       (1 << 8)
 783 #define PBM_PCIX_M1_100MHZ      (2 << 8)
 784 #define PBM_PCIX_M1_133MHZ      (3 << 8)
 785 #define PBM_PCIX_M2_66MHZ       (5 << 8)
 786 #define PBM_PCIX_M2_100MHZ      (6 << 8)
 787 #define PBM_PCIX_M2_133MHZ      (7 << 8)
 788 #define PBM_PCI_66MHZ           (8 << 8)
 789                                         /* Max Write Burst byte count. */
 790 #define CSRX_MAX_WRT_BURST_MASK (BIT_5|BIT_4)
 791 #define MWB_512_BYTES           (0 << 4)
 792 #define MWB_1024_BYTES          (1 << 4)
 793 #define MWB_2048_BYTES          (2 << 4)
 794 #define MWB_4096_BYTES          (3 << 4)
 795
 796 #define CSRX_64BIT_SLOT         BIT_2   /* PCI 64-Bit Bus Slot. */
 797 #define CSRX_FLASH_ENABLE       BIT_1   /* Flash BIOS Read/Write enable. */
 798 #define CSRX_ISP_SOFT_RESET     BIT_0   /* ISP soft reset. */
 799
 800         uint32_t ictrl;                 /* Interrupt control. */
 801 #define ICRX_EN_RISC_INT        BIT_3   /* Enable RISC interrupts on PCI. */
 802
 803         uint32_t istatus;               /* Interrupt status. */
 804 #define ISRX_RISC_INT           BIT_3   /* RISC interrupt. */
 805
 806         uint32_t unused_1[2];           /* Gap. */
 807
 808                                         /* Request Queue. */
 809         uint32_t req_q_in;              /*  In-Pointer. */
 810         uint32_t req_q_out;             /*  Out-Pointer. */
 811                                         /* Response Queue. */
 812         uint32_t rsp_q_in;              /*  In-Pointer. */
 813         uint32_t rsp_q_out;             /*  Out-Pointer. */
 814                                         /* Priority Request Queue. */
 815         uint32_t preq_q_in;             /*  In-Pointer. */
 816         uint32_t preq_q_out;            /*  Out-Pointer. */
 817
 818         uint32_t unused_2[2];           /* Gap. */
 819
 820                                         /* ATIO Queue. */
 821         uint32_t atio_q_in;             /*  In-Pointer. */
 822         uint32_t atio_q_out;            /*  Out-Pointer. */
 823
 824         uint32_t host_status;
 825 #define HSRX_RISC_INT           BIT_15  /* RISC to Host interrupt. */
 826 #define HSRX_RISC_PAUSED        BIT_8   /* RISC Paused. */
 827
 828         uint32_t hccr;                  /* Host command & control register. */
 829                                         /* HCCR statuses. */
 830 #define HCCRX_HOST_INT          BIT_6   /* Host to RISC interrupt bit. */
 831 #define HCCRX_RISC_RESET        BIT_5   /* RISC Reset mode bit. */
 832 #define HCCRX_RISC_PAUSE        BIT_4   /* RISC Pause mode bit. */
 833                                         /* HCCR commands. */
 834                                         /* NOOP. */
 835 #define HCCRX_NOOP              0x00000000
 836                                         /* Set RISC Reset. */
 837 #define HCCRX_SET_RISC_RESET    0x10000000
 838                                         /* Clear RISC Reset. */
 839 #define HCCRX_CLR_RISC_RESET    0x20000000
 840                                         /* Set RISC Pause. */
 841 #define HCCRX_SET_RISC_PAUSE    0x30000000
 842                                         /* Releases RISC Pause. */
 843 #define HCCRX_REL_RISC_PAUSE    0x40000000
 844                                         /* Set HOST to RISC interrupt. */
 845 #define HCCRX_SET_HOST_INT      0x50000000
 846                                         /* Clear HOST to RISC interrupt. */
 847 #define HCCRX_CLR_HOST_INT      0x60000000
 848                                         /* Clear RISC to PCI interrupt. */
 849 #define HCCRX_CLR_RISC_INT      0xA0000000
 850
 851         uint32_t gpiod;                 /* GPIO Data register. */
 852                                         /* LED update mask. */
 853 #define GPDX_LED_UPDATE_MASK    (BIT_20|BIT_19|BIT_18)
 854                                         /* Data update mask. */
 855 #define GPDX_DATA_UPDATE_MASK   (BIT_17|BIT_16)
 856                                         /* LED control mask. */
 857 #define GPDX_LED_COLOR_MASK     (BIT_4|BIT_3|BIT_2)
 858                                         /* LED bit values. Color names as
 859                                          * referenced in fw spec.
 860                                          */
 861 #define GPDX_LED_YELLOW_ON      BIT_2
 862 #define GPDX_LED_GREEN_ON       BIT_3
 863 #define GPDX_LED_AMBER_ON       BIT_4
 864                                         /* Data in/out. */
 865 #define GPDX_DATA_INOUT         (BIT_1|BIT_0)
 866
 867         uint32_t gpioe;                 /* GPIO Enable register. */
 868                                         /* Enable update mask. */
 869 #define GPEX_ENABLE_UPDATE_MASK (BIT_17|BIT_16)
 870                                         /* Enable. */
 871 #define GPEX_ENABLE             (BIT_1|BIT_0)
 872
 873         uint32_t iobase_addr;           /* I/O Bus Base Address register. */
 874
 875         uint32_t unused_3[10];          /* Gap. */
 876
 877         uint16_t mailbox0;
 878         uint16_t mailbox1;
 879         uint16_t mailbox2;
 880         uint16_t mailbox3;
 881         uint16_t mailbox4;
 882         uint16_t mailbox5;
 883         uint16_t mailbox6;
 884         uint16_t mailbox7;
 885         uint16_t mailbox8;
 886         uint16_t mailbox9;
 887         uint16_t mailbox10;
 888         uint16_t mailbox11;
 889         uint16_t mailbox12;
 890         uint16_t mailbox13;
 891         uint16_t mailbox14;
 892         uint16_t mailbox15;
 893         uint16_t mailbox16;
 894         uint16_t mailbox17;
 895         uint16_t mailbox18;
 896         uint16_t mailbox19;
 897         uint16_t mailbox20;
 898         uint16_t mailbox21;
 899         uint16_t mailbox22;
 900         uint16_t mailbox23;
 901         uint16_t mailbox24;
 902         uint16_t mailbox25;
 903         uint16_t mailbox26;
 904         uint16_t mailbox27;
 905         uint16_t mailbox28;
 906         uint16_t mailbox29;
 907         uint16_t mailbox30;
 908         uint16_t mailbox31;
 909 };
 910
 911 /* MID Support ***************************************************************/
 912
 913 #define MAX_MID_VPS     125
 914
 915 struct mid_conf_entry_24xx {
 916         uint16_t reserved_1;
 917
 918         /*
 919          * BIT 0  = Enable Hard Loop Id
 920          * BIT 1  = Acquire Loop ID in LIPA
 921          * BIT 2  = ID not Acquired
 922          * BIT 3  = Enable VP
 923          * BIT 4  = Enable Initiator Mode
 924          * BIT 5  = Disable Target Mode
 925          * BIT 6-7 = Reserved
 926          */
 927         uint8_t options;
 928
 929         uint8_t hard_address;
 930
 931         uint8_t port_name[WWN_SIZE];
 932         uint8_t node_name[WWN_SIZE];
 933 };
 934
 935 struct mid_init_cb_24xx {
 936         struct init_cb_24xx init_cb;
 937
 938         uint16_t count;
 939         uint16_t options;
 940
 941         struct mid_conf_entry_24xx entries[MAX_MID_VPS];
 942 };
 943
 944
 945 struct mid_db_entry_24xx {
 946         uint16_t status;
 947 #define MDBS_NON_PARTIC         BIT_3
 948 #define MDBS_ID_ACQUIRED        BIT_1
 949 #define MDBS_ENABLED            BIT_0
 950
 951         uint8_t options;
 952         uint8_t hard_address;
 953
 954         uint8_t port_name[WWN_SIZE];
 955         uint8_t node_name[WWN_SIZE];
 956
 957         uint8_t port_id[3];
 958         uint8_t reserved_1;
 959 };
 960
 961 struct mid_db_24xx {
 962         struct mid_db_entry_24xx entries[MAX_MID_VPS];
 963 };
 964
 965 #define VP_CTRL_IOCB_TYPE       0x30    /* Vitual Port Control entry. */
 966 struct vp_ctrl_entry_24xx {
 967         uint8_t entry_type;             /* Entry type. */
 968         uint8_t entry_count;            /* Entry count. */
 969         uint8_t sys_define;             /* System defined. */
 970         uint8_t entry_status;           /* Entry Status. */
 971
 972         uint32_t handle;                /* System handle. */
 973
 974         uint16_t vp_idx_failed;
 975
 976         uint16_t comp_status;           /* Completion status. */
 977 #define CS_VCE_ACQ_ID_ERROR     0x02    /* Error while acquireing ID. */
 978 #define CS_VCE_BUSY             0x05    /* Firmware not ready to accept cmd. */
 979
 980         uint16_t command;
 981 #define VCE_COMMAND_ENABLE_VPS  0x00    /* Enable VPs. */
 982 #define VCE_COMMAND_DISABLE_VPS 0x08    /* Disable VPs. */
 983 #define VCE_COMMAND_DISABLE_VPS_REINIT  0x09 /* Disable VPs and reinit link. */
 984 #define VCE_COMMAND_DISABLE_VPS_LOGO    0x0a /* Disable VPs and LOGO ports. */
 985
 986         uint16_t vp_count;
 987
 988         uint8_t vp_idx_map[16];
 989
 990         uint8_t reserved_4[32];
 991 };
 992
 993 #define VP_CONFIG_IOCB_TYPE     0x31    /* Vitual Port Config entry. */
 994 struct vp_config_entry_24xx {
 995         uint8_t entry_type;             /* Entry type. */
 996         uint8_t entry_count;            /* Entry count. */
 997         uint8_t sys_define;             /* System defined. */
 998         uint8_t entry_status;           /* Entry Status. */
 999
1000         uint32_t handle;                /* System handle. */
1001
1002         uint16_t reserved_1;
1003
1004         uint16_t comp_status;           /* Completion status. */
1005 #define CS_VCT_STS_ERROR        0x01    /* Specified VPs were not disabled. */
1006 #define CS_VCT_CNT_ERROR        0x02    /* Invalid VP count. */
1007 #define CS_VCT_ERROR            0x03    /* Unknown error. */
1008 #define CS_VCT_IDX_ERROR        0x02    /* Invalid VP index. */
1009 #define CS_VCT_BUSY             0x05    /* Firmware not ready to accept cmd. */
1010
1011         uint8_t command;
1012 #define VCT_COMMAND_MOD_VPS     0x00    /* Enable VPs. */
1013 #define VCT_COMMAND_MOD_ENABLE_VPS 0x08 /* Disable VPs. */
1014
1015         uint8_t vp_count;
1016
1017         uint8_t vp_idx1;
1018         uint8_t vp_idx2;
1019
1020         uint8_t options_idx1;
1021         uint8_t hard_address_idx1;
1022         uint16_t reserved_2;
1023         uint8_t port_name_idx1[WWN_SIZE];
1024         uint8_t node_name_idx1[WWN_SIZE];
1025
1026         uint8_t options_idx2;
1027         uint8_t hard_address_idx2;
1028         uint16_t reserved_3;
1029         uint8_t port_name_idx2[WWN_SIZE];
1030         uint8_t node_name_idx2[WWN_SIZE];
1031
1032         uint8_t reserved_4[8];
1033 };
1034
1035 #define VP_RPT_ID_IOCB_TYPE     0x32    /* Report ID Acquisition entry. */
1036 struct vp_rpt_id_entry_24xx {
1037         uint8_t entry_type;             /* Entry type. */
1038         uint8_t entry_count;            /* Entry count. */
1039         uint8_t sys_define;             /* System defined. */
1040         uint8_t entry_status;           /* Entry Status. */
1041
1042         uint32_t handle;                /* System handle. */
1043
1044         uint16_t vp_count;              /* Format 0 -- | VP setup | VP acq |. */
1045                                         /* Format 1 -- | VP count |. */
1046         uint16_t vp_idx;                /* Format 0 -- Reserved. */
1047                                         /* Format 1 -- VP status and index. */
1048
1049         uint8_t port_id[3];
1050         uint8_t format;
1051
1052         uint8_t vp_idx_map[16];
1053
1054         uint8_t reserved_4[32];
1055 };
1056
1057 /* END MID Support ***********************************************************/
1058 #endif