?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[IPV4]: Use ctl paths to register devinet sysctls
[wrt350n-kernel.git] / drivers / ata / sata_fsl.c
blob922d7b2efba8cf50b6d2a1b8bb144630474623e1
1 /*
2 * drivers/ata/sata_fsl.c
3 *
4 * Freescale 3.0Gbps SATA device driver
5 *
6 * Author: Ashish Kalra <ashish.kalra@freescale.com>
7 * Li Yang <leoli@freescale.com>
8 *
9 * Copyright (c) 2006-2007 Freescale Semiconductor, Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 */
17
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21
22 #include <scsi/scsi_host.h>
23 #include <scsi/scsi_cmnd.h>
24 #include <linux/libata.h>
25 #include <asm/io.h>
26 #include <linux/of_platform.h>
27
28 /* Controller information */
29 enum {
30 SATA_FSL_QUEUE_DEPTH = 16,
31 SATA_FSL_MAX_PRD = 63,
32 SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1,
33 SATA_FSL_MAX_PRD_DIRECT = 16, /* Direct PRDT entries */
34
35 SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
36 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
37 ATA_FLAG_NCQ),
38 SATA_FSL_HOST_LFLAGS = ATA_LFLAG_SKIP_D2H_BSY,
39
40 SATA_FSL_MAX_CMDS = SATA_FSL_QUEUE_DEPTH,
41 SATA_FSL_CMD_HDR_SIZE = 16, /* 4 DWORDS */
42 SATA_FSL_CMD_SLOT_SIZE = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE),
43
44 /*
45 * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and
46 * chained indirect PRDEs upto a max count of 63.
47 * We are allocating an array of 63 PRDEs contigiously, but PRDE#15 will
48 * be setup as an indirect descriptor, pointing to it's next
49 * (contigious) PRDE. Though chained indirect PRDE arrays are
50 * supported,it will be more efficient to use a direct PRDT and
51 * a single chain/link to indirect PRDE array/PRDT.
52 */
53
54 SATA_FSL_CMD_DESC_CFIS_SZ = 32,
55 SATA_FSL_CMD_DESC_SFIS_SZ = 32,
56 SATA_FSL_CMD_DESC_ACMD_SZ = 16,
57 SATA_FSL_CMD_DESC_RSRVD = 16,
58
59 SATA_FSL_CMD_DESC_SIZE = (SATA_FSL_CMD_DESC_CFIS_SZ +
60 SATA_FSL_CMD_DESC_SFIS_SZ +
61 SATA_FSL_CMD_DESC_ACMD_SZ +
62 SATA_FSL_CMD_DESC_RSRVD +
63 SATA_FSL_MAX_PRD * 16),
64
65 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT =
66 (SATA_FSL_CMD_DESC_CFIS_SZ +
67 SATA_FSL_CMD_DESC_SFIS_SZ +
68 SATA_FSL_CMD_DESC_ACMD_SZ +
69 SATA_FSL_CMD_DESC_RSRVD),
70
71 SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS),
72 SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE +
73 SATA_FSL_CMD_DESC_AR_SZ),
74
75 /*
76 * MPC8315 has two SATA controllers, SATA1 & SATA2
77 * (one port per controller)
78 * MPC837x has 2/4 controllers, one port per controller
79 */
80
81 SATA_FSL_MAX_PORTS = 1,
82
83 SATA_FSL_IRQ_FLAG = IRQF_SHARED,
84 };
85
86 /*
87 * Host Controller command register set - per port
88 */
89 enum {
90 CQ = 0,
91 CA = 8,
92 CC = 0x10,
93 CE = 0x18,
94 DE = 0x20,
95 CHBA = 0x24,
96 HSTATUS = 0x28,
97 HCONTROL = 0x2C,
98 CQPMP = 0x30,
99 SIGNATURE = 0x34,
100 ICC = 0x38,
101
102 /*
103 * Host Status Register (HStatus) bitdefs
104 */
105 ONLINE = (1 << 31),
106 GOING_OFFLINE = (1 << 30),
107 BIST_ERR = (1 << 29),
108
109 FATAL_ERR_HC_MASTER_ERR = (1 << 18),
110 FATAL_ERR_PARITY_ERR_TX = (1 << 17),
111 FATAL_ERR_PARITY_ERR_RX = (1 << 16),
112 FATAL_ERR_DATA_UNDERRUN = (1 << 13),
113 FATAL_ERR_DATA_OVERRUN = (1 << 12),
114 FATAL_ERR_CRC_ERR_TX = (1 << 11),
115 FATAL_ERR_CRC_ERR_RX = (1 << 10),
116 FATAL_ERR_FIFO_OVRFL_TX = (1 << 9),
117 FATAL_ERR_FIFO_OVRFL_RX = (1 << 8),
118
119 FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR |
120 FATAL_ERR_PARITY_ERR_TX |
121 FATAL_ERR_PARITY_ERR_RX |
122 FATAL_ERR_DATA_UNDERRUN |
123 FATAL_ERR_DATA_OVERRUN |
124 FATAL_ERR_CRC_ERR_TX |
125 FATAL_ERR_CRC_ERR_RX |
126 FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX,
127
128 INT_ON_FATAL_ERR = (1 << 5),
129 INT_ON_PHYRDY_CHG = (1 << 4),
130
131 INT_ON_SIGNATURE_UPDATE = (1 << 3),
132 INT_ON_SNOTIFY_UPDATE = (1 << 2),
133 INT_ON_SINGL_DEVICE_ERR = (1 << 1),
134 INT_ON_CMD_COMPLETE = 1,
135
136 INT_ON_ERROR = INT_ON_FATAL_ERR |
137 INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR,
138
139 /*
140 * Host Control Register (HControl) bitdefs
141 */
142 HCONTROL_ONLINE_PHY_RST = (1 << 31),
143 HCONTROL_FORCE_OFFLINE = (1 << 30),
144 HCONTROL_PARITY_PROT_MOD = (1 << 14),
145 HCONTROL_DPATH_PARITY = (1 << 12),
146 HCONTROL_SNOOP_ENABLE = (1 << 10),
147 HCONTROL_PMP_ATTACHED = (1 << 9),
148 HCONTROL_COPYOUT_STATFIS = (1 << 8),
149 IE_ON_FATAL_ERR = (1 << 5),
150 IE_ON_PHYRDY_CHG = (1 << 4),
151 IE_ON_SIGNATURE_UPDATE = (1 << 3),
152 IE_ON_SNOTIFY_UPDATE = (1 << 2),
153 IE_ON_SINGL_DEVICE_ERR = (1 << 1),
154 IE_ON_CMD_COMPLETE = 1,
155
156 DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG |
157 IE_ON_SIGNATURE_UPDATE |
158 IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE,
159
160 EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31),
161 DATA_SNOOP_ENABLE = (1 << 22),
162 };
163
164 /*
165 * SATA Superset Registers
166 */
167 enum {
168 SSTATUS = 0,
169 SERROR = 4,
170 SCONTROL = 8,
171 SNOTIFY = 0xC,
172 };
173
174 /*
175 * Control Status Register Set
176 */
177 enum {
178 TRANSCFG = 0,
179 TRANSSTATUS = 4,
180 LINKCFG = 8,
181 LINKCFG1 = 0xC,
182 LINKCFG2 = 0x10,
183 LINKSTATUS = 0x14,
184 LINKSTATUS1 = 0x18,
185 PHYCTRLCFG = 0x1C,
186 COMMANDSTAT = 0x20,
187 };
188
189 /* PHY (link-layer) configuration control */
190 enum {
191 PHY_BIST_ENABLE = 0x01,
192 };
193
194 /*
195 * Command Header Table entry, i.e, command slot
196 * 4 Dwords per command slot, command header size == 64 Dwords.
197 */
198 struct cmdhdr_tbl_entry {
199 u32 cda;
200 u32 prde_fis_len;
201 u32 ttl;
202 u32 desc_info;
203 };
204
205 /*
206 * Description information bitdefs
207 */
208 enum {
209 VENDOR_SPECIFIC_BIST = (1 << 10),
210 CMD_DESC_SNOOP_ENABLE = (1 << 9),
211 FPDMA_QUEUED_CMD = (1 << 8),
212 SRST_CMD = (1 << 7),
213 BIST = (1 << 6),
214 ATAPI_CMD = (1 << 5),
215 };
216
217 /*
218 * Command Descriptor
219 */
220 struct command_desc {
221 u8 cfis[8 * 4];
222 u8 sfis[8 * 4];
223 u8 acmd[4 * 4];
224 u8 fill[4 * 4];
225 u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4];
226 u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4];
227 };
228
229 /*
230 * Physical region table descriptor(PRD)
231 */
232
233 struct prde {
234 u32 dba;
235 u8 fill[2 * 4];
236 u32 ddc_and_ext;
237 };
238
239 /*
240 * ata_port private data
241 * This is our per-port instance data.
242 */
243 struct sata_fsl_port_priv {
244 struct cmdhdr_tbl_entry *cmdslot;
245 dma_addr_t cmdslot_paddr;
246 struct command_desc *cmdentry;
247 dma_addr_t cmdentry_paddr;
248
249 /*
250 * SATA FSL controller has a Status FIS which should contain the
251 * received D2H FIS & taskfile registers. This SFIS is present in
252 * the command descriptor, and to have a ready reference to it,
253 * we are caching it here, quite similar to what is done in H/W on
254 * AHCI compliant devices by copying taskfile fields to a 32-bit
255 * register.
256 */
257
258 struct ata_taskfile tf;
259 };
260
261 /*
262 * ata_port->host_set private data
263 */
264 struct sata_fsl_host_priv {
265 void __iomem *hcr_base;
266 void __iomem *ssr_base;
267 void __iomem *csr_base;
268 int irq;
269 };
270
271 static inline unsigned int sata_fsl_tag(unsigned int tag,
272 void __iomem *hcr_base)
273 {
274 /* We let libATA core do actual (queue) tag allocation */
275
276 /* all non NCQ/queued commands should have tag#0 */
277 if (ata_tag_internal(tag)) {
278 DPRINTK("mapping internal cmds to tag#0\n");
279 return 0;
280 }
281
282 if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) {
283 DPRINTK("tag %d invalid : out of range\n", tag);
284 return 0;
285 }
286
287 if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) {
288 DPRINTK("tag %d invalid : in use!!\n", tag);
289 return 0;
290 }
291
292 return tag;
293 }
294
295 static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp,
296 unsigned int tag, u32 desc_info,
297 u32 data_xfer_len, u8 num_prde,
298 u8 fis_len)
299 {
300 dma_addr_t cmd_descriptor_address;
301
302 cmd_descriptor_address = pp->cmdentry_paddr +
303 tag * SATA_FSL_CMD_DESC_SIZE;
304
305 /* NOTE: both data_xfer_len & fis_len are Dword counts */
306
307 pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address);
308 pp->cmdslot[tag].prde_fis_len =
309 cpu_to_le32((num_prde << 16) | (fis_len << 2));
310 pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03);
311 pp->cmdslot[tag].desc_info = cpu_to_le32(desc_info | (tag & 0x1F));
312
313 VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n",
314 pp->cmdslot[tag].cda,
315 pp->cmdslot[tag].prde_fis_len,
316 pp->cmdslot[tag].ttl, pp->cmdslot[tag].desc_info);
317
318 }
319
320 static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc,
321 u32 *ttl, dma_addr_t cmd_desc_paddr)
322 {
323 struct scatterlist *sg;
324 unsigned int num_prde = 0;
325 u32 ttl_dwords = 0;
326
327 /*
328 * NOTE : direct & indirect prdt's are contigiously allocated
329 */
330 struct prde *prd = (struct prde *)&((struct command_desc *)
331 cmd_desc)->prdt;
332
333 struct prde *prd_ptr_to_indirect_ext = NULL;
334 unsigned indirect_ext_segment_sz = 0;
335 dma_addr_t indirect_ext_segment_paddr;
336 unsigned int si;
337
338 VPRINTK("SATA FSL : cd = 0x%x, prd = 0x%x\n", cmd_desc, prd);
339
340 indirect_ext_segment_paddr = cmd_desc_paddr +
341 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16;
342
343 for_each_sg(qc->sg, sg, qc->n_elem, si) {
344 dma_addr_t sg_addr = sg_dma_address(sg);
345 u32 sg_len = sg_dma_len(sg);
346
347 VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%x, sg_len = %d\n",
348 sg_addr, sg_len);
349
350 /* warn if each s/g element is not dword aligned */
351 if (sg_addr & 0x03)
352 ata_port_printk(qc->ap, KERN_ERR,
353 "s/g addr unaligned : 0x%x\n", sg_addr);
354 if (sg_len & 0x03)
355 ata_port_printk(qc->ap, KERN_ERR,
356 "s/g len unaligned : 0x%x\n", sg_len);
357
358 if ((num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1)) &&
359 (qc->n_iter + 1 != qc->n_elem)) {
360 VPRINTK("setting indirect prde\n");
361 prd_ptr_to_indirect_ext = prd;
362 prd->dba = cpu_to_le32(indirect_ext_segment_paddr);
363 indirect_ext_segment_sz = 0;
364 ++prd;
365 ++num_prde;
366 }
367
368 ttl_dwords += sg_len;
369 prd->dba = cpu_to_le32(sg_addr);
370 prd->ddc_and_ext =
371 cpu_to_le32(DATA_SNOOP_ENABLE | (sg_len & ~0x03));
372
373 VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n",
374 ttl_dwords, prd->dba, prd->ddc_and_ext);
375
376 ++num_prde;
377 ++prd;
378 if (prd_ptr_to_indirect_ext)
379 indirect_ext_segment_sz += sg_len;
380 }
381
382 if (prd_ptr_to_indirect_ext) {
383 /* set indirect extension flag along with indirect ext. size */
384 prd_ptr_to_indirect_ext->ddc_and_ext =
385 cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG |
386 DATA_SNOOP_ENABLE |
387 (indirect_ext_segment_sz & ~0x03)));
388 }
389
390 *ttl = ttl_dwords;
391 return num_prde;
392 }
393
394 static void sata_fsl_qc_prep(struct ata_queued_cmd *qc)
395 {
396 struct ata_port *ap = qc->ap;
397 struct sata_fsl_port_priv *pp = ap->private_data;
398 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
399 void __iomem *hcr_base = host_priv->hcr_base;
400 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
401 struct command_desc *cd;
402 u32 desc_info = CMD_DESC_SNOOP_ENABLE;
403 u32 num_prde = 0;
404 u32 ttl_dwords = 0;
405 dma_addr_t cd_paddr;
406
407 cd = (struct command_desc *)pp->cmdentry + tag;
408 cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE;
409
410 ata_tf_to_fis(&qc->tf, 0, 1, (u8 *) &cd->cfis);
411
412 VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n",
413 cd->cfis[0], cd->cfis[1], cd->cfis[2]);
414
415 if (qc->tf.protocol == ATA_PROT_NCQ) {
416 VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n",
417 cd->cfis[3], cd->cfis[11]);
418 }
419
420 /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */
421 if (ata_is_atapi(qc->tf.protocol)) {
422 desc_info |= ATAPI_CMD;
423 memset((void *)&cd->acmd, 0, 32);
424 memcpy((void *)&cd->acmd, qc->cdb, qc->dev->cdb_len);
425 }
426
427 if (qc->flags & ATA_QCFLAG_DMAMAP)
428 num_prde = sata_fsl_fill_sg(qc, (void *)cd,
429 &ttl_dwords, cd_paddr);
430
431 if (qc->tf.protocol == ATA_PROT_NCQ)
432 desc_info |= FPDMA_QUEUED_CMD;
433
434 sata_fsl_setup_cmd_hdr_entry(pp, tag, desc_info, ttl_dwords,
435 num_prde, 5);
436
437 VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n",
438 desc_info, ttl_dwords, num_prde);
439 }
440
441 static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc)
442 {
443 struct ata_port *ap = qc->ap;
444 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
445 void __iomem *hcr_base = host_priv->hcr_base;
446 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
447
448 VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n",
449 ioread32(CQ + hcr_base),
450 ioread32(CA + hcr_base),
451 ioread32(CE + hcr_base), ioread32(CC + hcr_base));
452
453 /* Simply queue command to the controller/device */
454 iowrite32(1 << tag, CQ + hcr_base);
455
456 VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n",
457 tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base));
458
459 VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n",
460 ioread32(CE + hcr_base),
461 ioread32(DE + hcr_base),
462 ioread32(CC + hcr_base), ioread32(COMMANDSTAT + csr_base));
463
464 return 0;
465 }
466
467 static int sata_fsl_scr_write(struct ata_port *ap, unsigned int sc_reg_in,
468 u32 val)
469 {
470 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
471 void __iomem *ssr_base = host_priv->ssr_base;
472 unsigned int sc_reg;
473
474 switch (sc_reg_in) {
475 case SCR_STATUS:
476 case SCR_ERROR:
477 case SCR_CONTROL:
478 case SCR_ACTIVE:
479 sc_reg = sc_reg_in;
480 break;
481 default:
482 return -EINVAL;
483 }
484
485 VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg);
486
487 iowrite32(val, ssr_base + (sc_reg * 4));
488 return 0;
489 }
490
491 static int sata_fsl_scr_read(struct ata_port *ap, unsigned int sc_reg_in,
492 u32 *val)
493 {
494 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
495 void __iomem *ssr_base = host_priv->ssr_base;
496 unsigned int sc_reg;
497
498 switch (sc_reg_in) {
499 case SCR_STATUS:
500 case SCR_ERROR:
501 case SCR_CONTROL:
502 case SCR_ACTIVE:
503 sc_reg = sc_reg_in;
504 break;
505 default:
506 return -EINVAL;
507 }
508
509 VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg);
510
511 *val = ioread32(ssr_base + (sc_reg * 4));
512 return 0;
513 }
514
515 static void sata_fsl_freeze(struct ata_port *ap)
516 {
517 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
518 void __iomem *hcr_base = host_priv->hcr_base;
519 u32 temp;
520
521 VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n",
522 ioread32(CQ + hcr_base),
523 ioread32(CA + hcr_base),
524 ioread32(CE + hcr_base), ioread32(DE + hcr_base));
525 VPRINTK("CmdStat = 0x%x\n", ioread32(csr_base + COMMANDSTAT));
526
527 /* disable interrupts on the controller/port */
528 temp = ioread32(hcr_base + HCONTROL);
529 iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
530
531 VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n",
532 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
533 }
534
535 static void sata_fsl_thaw(struct ata_port *ap)
536 {
537 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
538 void __iomem *hcr_base = host_priv->hcr_base;
539 u32 temp;
540
541 /* ack. any pending IRQs for this controller/port */
542 temp = ioread32(hcr_base + HSTATUS);
543
544 VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp & 0x3F));
545
546 if (temp & 0x3F)
547 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
548
549 /* enable interrupts on the controller/port */
550 temp = ioread32(hcr_base + HCONTROL);
551 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
552
553 VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n",
554 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
555 }
556
557 /*
558 * NOTE : 1st D2H FIS from device does not update sfis in command descriptor.
559 */
560 static inline void sata_fsl_cache_taskfile_from_d2h_fis(struct ata_queued_cmd
561 *qc,
562 struct ata_port *ap)
563 {
564 struct sata_fsl_port_priv *pp = ap->private_data;
565 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
566 void __iomem *hcr_base = host_priv->hcr_base;
567 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
568 struct command_desc *cd;
569
570 cd = pp->cmdentry + tag;
571
572 ata_tf_from_fis(cd->sfis, &pp->tf);
573 }
574
575 static u8 sata_fsl_check_status(struct ata_port *ap)
576 {
577 struct sata_fsl_port_priv *pp = ap->private_data;
578
579 return pp->tf.command;
580 }
581
582 static void sata_fsl_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
583 {
584 struct sata_fsl_port_priv *pp = ap->private_data;
585
586 *tf = pp->tf;
587 }
588
589 static int sata_fsl_port_start(struct ata_port *ap)
590 {
591 struct device *dev = ap->host->dev;
592 struct sata_fsl_port_priv *pp;
593 int retval;
594 void *mem;
595 dma_addr_t mem_dma;
596 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
597 void __iomem *hcr_base = host_priv->hcr_base;
598 u32 temp;
599
600 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
601 if (!pp)
602 return -ENOMEM;
603
604 /*
605 * allocate per command dma alignment pad buffer, which is used
606 * internally by libATA to ensure that all transfers ending on
607 * unaligned boundaries are padded, to align on Dword boundaries
608 */
609 retval = ata_pad_alloc(ap, dev);
610 if (retval) {
611 kfree(pp);
612 return retval;
613 }
614
615 mem = dma_alloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma,
616 GFP_KERNEL);
617 if (!mem) {
618 ata_pad_free(ap, dev);
619 kfree(pp);
620 return -ENOMEM;
621 }
622 memset(mem, 0, SATA_FSL_PORT_PRIV_DMA_SZ);
623
624 pp->cmdslot = mem;
625 pp->cmdslot_paddr = mem_dma;
626
627 mem += SATA_FSL_CMD_SLOT_SIZE;
628 mem_dma += SATA_FSL_CMD_SLOT_SIZE;
629
630 pp->cmdentry = mem;
631 pp->cmdentry_paddr = mem_dma;
632
633 ap->private_data = pp;
634
635 VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n",
636 pp->cmdslot_paddr, pp->cmdentry_paddr);
637
638 /* Now, update the CHBA register in host controller cmd register set */
639 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
640
641 /*
642 * Now, we can bring the controller on-line & also initiate
643 * the COMINIT sequence, we simply return here and the boot-probing
644 * & device discovery process is re-initiated by libATA using a
645 * Softreset EH (dummy) session. Hence, boot probing and device
646 * discovey will be part of sata_fsl_softreset() callback.
647 */
648
649 temp = ioread32(hcr_base + HCONTROL);
650 iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL);
651
652 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
653 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
654 VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base + CHBA));
655
656 #ifdef CONFIG_MPC8315_DS
657 /*
658 * Workaround for 8315DS board 3gbps link-up issue,
659 * currently limit SATA port to GEN1 speed
660 */
661 sata_fsl_scr_read(ap, SCR_CONTROL, &temp);
662 temp &= ~(0xF << 4);
663 temp |= (0x1 << 4);
664 sata_fsl_scr_write(ap, SCR_CONTROL, temp);
665
666 sata_fsl_scr_read(ap, SCR_CONTROL, &temp);
667 dev_printk(KERN_WARNING, dev, "scr_control, speed limited to %x\n",
668 temp);
669 #endif
670
671 return 0;
672 }
673
674 static void sata_fsl_port_stop(struct ata_port *ap)
675 {
676 struct device *dev = ap->host->dev;
677 struct sata_fsl_port_priv *pp = ap->private_data;
678 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
679 void __iomem *hcr_base = host_priv->hcr_base;
680 u32 temp;
681
682 /*
683 * Force host controller to go off-line, aborting current operations
684 */
685 temp = ioread32(hcr_base + HCONTROL);
686 temp &= ~HCONTROL_ONLINE_PHY_RST;
687 temp |= HCONTROL_FORCE_OFFLINE;
688 iowrite32(temp, hcr_base + HCONTROL);
689
690 /* Poll for controller to go offline - should happen immediately */
691 ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1);
692
693 ap->private_data = NULL;
694 dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ,
695 pp->cmdslot, pp->cmdslot_paddr);
696
697 ata_pad_free(ap, dev);
698 kfree(pp);
699 }
700
701 static unsigned int sata_fsl_dev_classify(struct ata_port *ap)
702 {
703 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
704 void __iomem *hcr_base = host_priv->hcr_base;
705 struct ata_taskfile tf;
706 u32 temp;
707
708 temp = ioread32(hcr_base + SIGNATURE);
709
710 VPRINTK("raw sig = 0x%x\n", temp);
711 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
712 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
713
714 tf.lbah = (temp >> 24) & 0xff;
715 tf.lbam = (temp >> 16) & 0xff;
716 tf.lbal = (temp >> 8) & 0xff;
717 tf.nsect = temp & 0xff;
718
719 return ata_dev_classify(&tf);
720 }
721
722 static int sata_fsl_softreset(struct ata_link *link, unsigned int *class,
723 unsigned long deadline)
724 {
725 struct ata_port *ap = link->ap;
726 struct sata_fsl_port_priv *pp = ap->private_data;
727 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
728 void __iomem *hcr_base = host_priv->hcr_base;
729 u32 temp;
730 struct ata_taskfile tf;
731 u8 *cfis;
732 u32 Serror;
733 int i = 0;
734 unsigned long start_jiffies;
735
736 DPRINTK("in xx_softreset\n");
737
738 try_offline_again:
739 /*
740 * Force host controller to go off-line, aborting current operations
741 */
742 temp = ioread32(hcr_base + HCONTROL);
743 temp &= ~HCONTROL_ONLINE_PHY_RST;
744 iowrite32(temp, hcr_base + HCONTROL);
745
746 /* Poll for controller to go offline */
747 temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 500);
748
749 if (temp & ONLINE) {
750 ata_port_printk(ap, KERN_ERR,
751 "Softreset failed, not off-lined %d\n", i);
752
753 /*
754 * Try to offline controller atleast twice
755 */
756 i++;
757 if (i == 2)
758 goto err;
759 else
760 goto try_offline_again;
761 }
762
763 DPRINTK("softreset, controller off-lined\n");
764 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
765 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
766
767 /*
768 * PHY reset should remain asserted for atleast 1ms
769 */
770 msleep(1);
771
772 /*
773 * Now, bring the host controller online again, this can take time
774 * as PHY reset and communication establishment, 1st D2H FIS and
775 * device signature update is done, on safe side assume 500ms
776 * NOTE : Host online status may be indicated immediately!!
777 */
778
779 temp = ioread32(hcr_base + HCONTROL);
780 temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE);
781 iowrite32(temp, hcr_base + HCONTROL);
782
783 temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, 0, 1, 500);
784
785 if (!(temp & ONLINE)) {
786 ata_port_printk(ap, KERN_ERR,
787 "Softreset failed, not on-lined\n");
788 goto err;
789 }
790
791 DPRINTK("softreset, controller off-lined & on-lined\n");
792 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
793 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
794
795 /*
796 * First, wait for the PHYRDY change to occur before waiting for
797 * the signature, and also verify if SStatus indicates device
798 * presence
799 */
800
801 temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0, 1, 500);
802 if ((!(temp & 0x10)) || ata_link_offline(link)) {
803 ata_port_printk(ap, KERN_WARNING,
804 "No Device OR PHYRDY change,Hstatus = 0x%x\n",
805 ioread32(hcr_base + HSTATUS));
806 goto err;
807 }
808
809 /*
810 * Wait for the first D2H from device,i.e,signature update notification
811 */
812 start_jiffies = jiffies;
813 temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0x10,
814 500, jiffies_to_msecs(deadline - start_jiffies));
815
816 if ((temp & 0xFF) != 0x18) {
817 ata_port_printk(ap, KERN_WARNING, "No Signature Update\n");
818 goto err;
819 } else {
820 ata_port_printk(ap, KERN_INFO,
821 "Signature Update detected @ %d msecs\n",
822 jiffies_to_msecs(jiffies - start_jiffies));
823 }
824
825 /*
826 * Send a device reset (SRST) explicitly on command slot #0
827 * Check : will the command queue (reg) be cleared during offlining ??
828 * Also we will be online only if Phy commn. has been established
829 * and device presence has been detected, therefore if we have
830 * reached here, we can send a command to the target device
831 */
832
833 DPRINTK("Sending SRST/device reset\n");
834
835 ata_tf_init(link->device, &tf);
836 cfis = (u8 *) &pp->cmdentry->cfis;
837
838 /* device reset/SRST is a control register update FIS, uses tag0 */
839 sata_fsl_setup_cmd_hdr_entry(pp, 0,
840 SRST_CMD | CMD_DESC_SNOOP_ENABLE, 0, 0, 5);
841
842 tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */
843 ata_tf_to_fis(&tf, 0, 0, cfis);
844
845 DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n",
846 cfis[0], cfis[1], cfis[2], cfis[3]);
847
848 /*
849 * Queue SRST command to the controller/device, ensure that no
850 * other commands are active on the controller/device
851 */
852
853 DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n",
854 ioread32(CQ + hcr_base),
855 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
856
857 iowrite32(0xFFFF, CC + hcr_base);
858 iowrite32(1, CQ + hcr_base);
859
860 temp = ata_wait_register(CQ + hcr_base, 0x1, 0x1, 1, 5000);
861 if (temp & 0x1) {
862 ata_port_printk(ap, KERN_WARNING, "ATA_SRST issue failed\n");
863
864 DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n",
865 ioread32(CQ + hcr_base),
866 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
867
868 sata_fsl_scr_read(ap, SCR_ERROR, &Serror);
869
870 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
871 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
872 DPRINTK("Serror = 0x%x\n", Serror);
873 goto err;
874 }
875
876 msleep(1);
877
878 /*
879 * SATA device enters reset state after receving a Control register
880 * FIS with SRST bit asserted and it awaits another H2D Control reg.
881 * FIS with SRST bit cleared, then the device does internal diags &
882 * initialization, followed by indicating it's initialization status
883 * using ATA signature D2H register FIS to the host controller.
884 */
885
886 sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_SNOOP_ENABLE, 0, 0, 5);
887
888 tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */
889 ata_tf_to_fis(&tf, 0, 0, cfis);
890
891 iowrite32(1, CQ + hcr_base);
892 msleep(150); /* ?? */
893
894 /*
895 * The above command would have signalled an interrupt on command
896 * complete, which needs special handling, by clearing the Nth
897 * command bit of the CCreg
898 */
899 iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */
900
901 DPRINTK("SATA FSL : Now checking device signature\n");
902
903 *class = ATA_DEV_NONE;
904
905 /* Verify if SStatus indicates device presence */
906 if (ata_link_online(link)) {
907 /*
908 * if we are here, device presence has been detected,
909 * 1st D2H FIS would have been received, but sfis in
910 * command desc. is not updated, but signature register
911 * would have been updated
912 */
913
914 *class = sata_fsl_dev_classify(ap);
915
916 DPRINTK("class = %d\n", *class);
917 VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC));
918 VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE));
919 }
920
921 return 0;
922
923 err:
924 return -EIO;
925 }
926
927 static void sata_fsl_error_handler(struct ata_port *ap)
928 {
929
930 DPRINTK("in xx_error_handler\n");
931
932 /* perform recovery */
933 ata_do_eh(ap, ata_std_prereset, sata_fsl_softreset, sata_std_hardreset,
934 ata_std_postreset);
935 }
936
937 static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc)
938 {
939 if (qc->flags & ATA_QCFLAG_FAILED)
940 qc->err_mask |= AC_ERR_OTHER;
941
942 if (qc->err_mask) {
943 /* make DMA engine forget about the failed command */
944
945 }
946 }
947
948 static void sata_fsl_irq_clear(struct ata_port *ap)
949 {
950 /* unused */
951 }
952
953 static void sata_fsl_error_intr(struct ata_port *ap)
954 {
955 struct ata_link *link = &ap->link;
956 struct ata_eh_info *ehi = &link->eh_info;
957 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
958 void __iomem *hcr_base = host_priv->hcr_base;
959 u32 hstatus, dereg, cereg = 0, SError = 0;
960 unsigned int err_mask = 0, action = 0;
961 struct ata_queued_cmd *qc;
962 int freeze = 0;
963
964 hstatus = ioread32(hcr_base + HSTATUS);
965 cereg = ioread32(hcr_base + CE);
966
967 ata_ehi_clear_desc(ehi);
968
969 /*
970 * Handle & Clear SError
971 */
972
973 sata_fsl_scr_read(ap, SCR_ERROR, &SError);
974 if (unlikely(SError & 0xFFFF0000)) {
975 sata_fsl_scr_write(ap, SCR_ERROR, SError);
976 err_mask |= AC_ERR_ATA_BUS;
977 }
978
979 DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n",
980 hstatus, cereg, ioread32(hcr_base + DE), SError);
981
982 /* handle single device errors */
983 if (cereg) {
984 /*
985 * clear the command error, also clears queue to the device
986 * in error, and we can (re)issue commands to this device.
987 * When a device is in error all commands queued into the
988 * host controller and at the device are considered aborted
989 * and the queue for that device is stopped. Now, after
990 * clearing the device error, we can issue commands to the
991 * device to interrogate it to find the source of the error.
992 */
993 dereg = ioread32(hcr_base + DE);
994 iowrite32(dereg, hcr_base + DE);
995 iowrite32(cereg, hcr_base + CE);
996
997 DPRINTK("single device error, CE=0x%x, DE=0x%x\n",
998 ioread32(hcr_base + CE), ioread32(hcr_base + DE));
999 /*
1000 * We should consider this as non fatal error, and TF must
1001 * be updated as done below.
1002 */
1003
1004 err_mask |= AC_ERR_DEV;
1005 }
1006
1007 /* handle fatal errors */
1008 if (hstatus & FATAL_ERROR_DECODE) {
1009 err_mask |= AC_ERR_ATA_BUS;
1010 action |= ATA_EH_SOFTRESET;
1011 /* how will fatal error interrupts be completed ?? */
1012 freeze = 1;
1013 }
1014
1015 /* Handle PHYRDY change notification */
1016 if (hstatus & INT_ON_PHYRDY_CHG) {
1017 DPRINTK("SATA FSL: PHYRDY change indication\n");
1018
1019 /* Setup a soft-reset EH action */
1020 ata_ehi_hotplugged(ehi);
1021 freeze = 1;
1022 }
1023
1024 /* record error info */
1025 qc = ata_qc_from_tag(ap, link->active_tag);
1026
1027 if (qc) {
1028 sata_fsl_cache_taskfile_from_d2h_fis(qc, qc->ap);
1029 qc->err_mask |= err_mask;
1030 } else
1031 ehi->err_mask |= err_mask;
1032
1033 ehi->action |= action;
1034 ehi->serror |= SError;
1035
1036 /* freeze or abort */
1037 if (freeze)
1038 ata_port_freeze(ap);
1039 else
1040 ata_port_abort(ap);
1041 }
1042
1043 static void sata_fsl_qc_complete(struct ata_queued_cmd *qc)
1044 {
1045 if (qc->flags & ATA_QCFLAG_RESULT_TF) {
1046 DPRINTK("xx_qc_complete called\n");
1047 sata_fsl_cache_taskfile_from_d2h_fis(qc, qc->ap);
1048 }
1049 }
1050
1051 static void sata_fsl_host_intr(struct ata_port *ap)
1052 {
1053 struct ata_link *link = &ap->link;
1054 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
1055 void __iomem *hcr_base = host_priv->hcr_base;
1056 u32 hstatus, qc_active = 0;
1057 struct ata_queued_cmd *qc;
1058 u32 SError;
1059
1060 hstatus = ioread32(hcr_base + HSTATUS);
1061
1062 sata_fsl_scr_read(ap, SCR_ERROR, &SError);
1063
1064 if (unlikely(SError & 0xFFFF0000)) {
1065 DPRINTK("serror @host_intr : 0x%x\n", SError);
1066 sata_fsl_error_intr(ap);
1067
1068 }
1069
1070 if (unlikely(hstatus & INT_ON_ERROR)) {
1071 DPRINTK("error interrupt!!\n");
1072 sata_fsl_error_intr(ap);
1073 return;
1074 }
1075
1076 if (link->sactive) { /* only true for NCQ commands */
1077 int i;
1078 /* Read command completed register */
1079 qc_active = ioread32(hcr_base + CC);
1080 /* clear CC bit, this will also complete the interrupt */
1081 iowrite32(qc_active, hcr_base + CC);
1082
1083 DPRINTK("Status of all queues :\n");
1084 DPRINTK("qc_active/CC = 0x%x, CA = 0x%x, CE=0x%x\n",
1085 qc_active, ioread32(hcr_base + CA),
1086 ioread32(hcr_base + CE));
1087
1088 for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) {
1089 if (qc_active & (1 << i)) {
1090 qc = ata_qc_from_tag(ap, i);
1091 if (qc) {
1092 sata_fsl_qc_complete(qc);
1093 ata_qc_complete(qc);
1094 }
1095 DPRINTK
1096 ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n",
1097 i, ioread32(hcr_base + CC),
1098 ioread32(hcr_base + CA));
1099 }
1100 }
1101 return;
1102
1103 } else if (ap->qc_active) {
1104 iowrite32(1, hcr_base + CC);
1105 qc = ata_qc_from_tag(ap, link->active_tag);
1106
1107 DPRINTK("completing non-ncq cmd, tag=%d,CC=0x%x\n",
1108 link->active_tag, ioread32(hcr_base + CC));
1109
1110 if (qc) {
1111 sata_fsl_qc_complete(qc);
1112 ata_qc_complete(qc);
1113 }
1114 } else {
1115 /* Spurious Interrupt!! */
1116 DPRINTK("spurious interrupt!!, CC = 0x%x\n",
1117 ioread32(hcr_base + CC));
1118 return;
1119 }
1120 }
1121
1122 static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance)
1123 {
1124 struct ata_host *host = dev_instance;
1125 struct sata_fsl_host_priv *host_priv = host->private_data;
1126 void __iomem *hcr_base = host_priv->hcr_base;
1127 u32 interrupt_enables;
1128 unsigned handled = 0;
1129 struct ata_port *ap;
1130
1131 /* ack. any pending IRQs for this controller/port */
1132 interrupt_enables = ioread32(hcr_base + HSTATUS);
1133 interrupt_enables &= 0x3F;
1134
1135 DPRINTK("interrupt status 0x%x\n", interrupt_enables);
1136
1137 if (!interrupt_enables)
1138 return IRQ_NONE;
1139
1140 spin_lock(&host->lock);
1141
1142 /* Assuming one port per host controller */
1143
1144 ap = host->ports[0];
1145 if (ap) {
1146 sata_fsl_host_intr(ap);
1147 } else {
1148 dev_printk(KERN_WARNING, host->dev,
1149 "interrupt on disabled port 0\n");
1150 }
1151
1152 iowrite32(interrupt_enables, hcr_base + HSTATUS);
1153 handled = 1;
1154
1155 spin_unlock(&host->lock);
1156
1157 return IRQ_RETVAL(handled);
1158 }
1159
1160 /*
1161 * Multiple ports are represented by multiple SATA controllers with
1162 * one port per controller
1163 */
1164 static int sata_fsl_init_controller(struct ata_host *host)
1165 {
1166 struct sata_fsl_host_priv *host_priv = host->private_data;
1167 void __iomem *hcr_base = host_priv->hcr_base;
1168 u32 temp;
1169
1170 /*
1171 * NOTE : We cannot bring the controller online before setting
1172 * the CHBA, hence main controller initialization is done as
1173 * part of the port_start() callback
1174 */
1175
1176 /* ack. any pending IRQs for this controller/port */
1177 temp = ioread32(hcr_base + HSTATUS);
1178 if (temp & 0x3F)
1179 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
1180
1181 /* Keep interrupts disabled on the controller */
1182 temp = ioread32(hcr_base + HCONTROL);
1183 iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
1184
1185 /* Disable interrupt coalescing control(icc), for the moment */
1186 DPRINTK("icc = 0x%x\n", ioread32(hcr_base + ICC));
1187 iowrite32(0x01000000, hcr_base + ICC);
1188
1189 /* clear error registers, SError is cleared by libATA */
1190 iowrite32(0x00000FFFF, hcr_base + CE);
1191 iowrite32(0x00000FFFF, hcr_base + DE);
1192
1193 /* initially assuming no Port multiplier, set CQPMP to 0 */
1194 iowrite32(0x0, hcr_base + CQPMP);
1195
1196 /*
1197 * host controller will be brought on-line, during xx_port_start()
1198 * callback, that should also initiate the OOB, COMINIT sequence
1199 */
1200
1201 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
1202 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
1203
1204 return 0;
1205 }
1206
1207 /*
1208 * scsi mid-layer and libata interface structures
1209 */
1210 static struct scsi_host_template sata_fsl_sht = {
1211 .module = THIS_MODULE,
1212 .name = "sata_fsl",
1213 .ioctl = ata_scsi_ioctl,
1214 .queuecommand = ata_scsi_queuecmd,
1215 .change_queue_depth = ata_scsi_change_queue_depth,
1216 .can_queue = SATA_FSL_QUEUE_DEPTH,
1217 .this_id = ATA_SHT_THIS_ID,
1218 .sg_tablesize = SATA_FSL_MAX_PRD_USABLE,
1219 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
1220 .emulated = ATA_SHT_EMULATED,
1221 .use_clustering = ATA_SHT_USE_CLUSTERING,
1222 .proc_name = "sata_fsl",
1223 .dma_boundary = ATA_DMA_BOUNDARY,
1224 .slave_configure = ata_scsi_slave_config,
1225 .slave_destroy = ata_scsi_slave_destroy,
1226 .bios_param = ata_std_bios_param,
1227 };
1228
1229 static const struct ata_port_operations sata_fsl_ops = {
1230 .check_status = sata_fsl_check_status,
1231 .check_altstatus = sata_fsl_check_status,
1232 .dev_select = ata_noop_dev_select,
1233
1234 .tf_read = sata_fsl_tf_read,
1235
1236 .qc_prep = sata_fsl_qc_prep,
1237 .qc_issue = sata_fsl_qc_issue,
1238 .irq_clear = sata_fsl_irq_clear,
1239
1240 .scr_read = sata_fsl_scr_read,
1241 .scr_write = sata_fsl_scr_write,
1242
1243 .freeze = sata_fsl_freeze,
1244 .thaw = sata_fsl_thaw,
1245 .error_handler = sata_fsl_error_handler,
1246 .post_internal_cmd = sata_fsl_post_internal_cmd,
1247
1248 .port_start = sata_fsl_port_start,
1249 .port_stop = sata_fsl_port_stop,
1250 };
1251
1252 static const struct ata_port_info sata_fsl_port_info[] = {
1253 {
1254 .flags = SATA_FSL_HOST_FLAGS,
1255 .link_flags = SATA_FSL_HOST_LFLAGS,
1256 .pio_mask = 0x1f, /* pio 0-4 */
1257 .udma_mask = 0x7f, /* udma 0-6 */
1258 .port_ops = &sata_fsl_ops,
1259 },
1260 };
1261
1262 static int sata_fsl_probe(struct of_device *ofdev,
1263 const struct of_device_id *match)
1264 {
1265 int retval = 0;
1266 void __iomem *hcr_base = NULL;
1267 void __iomem *ssr_base = NULL;
1268 void __iomem *csr_base = NULL;
1269 struct sata_fsl_host_priv *host_priv = NULL;
1270 struct resource *r;
1271 int irq;
1272 struct ata_host *host;
1273
1274 struct ata_port_info pi = sata_fsl_port_info[0];
1275 const struct ata_port_info *ppi[] = { &pi, NULL };
1276
1277 dev_printk(KERN_INFO, &ofdev->dev,
1278 "Sata FSL Platform/CSB Driver init\n");
1279
1280 r = kmalloc(sizeof(struct resource), GFP_KERNEL);
1281
1282 hcr_base = of_iomap(ofdev->node, 0);
1283 if (!hcr_base)
1284 goto error_exit_with_cleanup;
1285
1286 ssr_base = hcr_base + 0x100;
1287 csr_base = hcr_base + 0x140;
1288
1289 DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG));
1290 DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc));
1291 DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE);
1292
1293 host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL);
1294 if (!host_priv)
1295 goto error_exit_with_cleanup;
1296
1297 host_priv->hcr_base = hcr_base;
1298 host_priv->ssr_base = ssr_base;
1299 host_priv->csr_base = csr_base;
1300
1301 irq = irq_of_parse_and_map(ofdev->node, 0);
1302 if (irq < 0) {
1303 dev_printk(KERN_ERR, &ofdev->dev, "invalid irq from platform\n");
1304 goto error_exit_with_cleanup;
1305 }
1306 host_priv->irq = irq;
1307
1308 /* allocate host structure */
1309 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS);
1310
1311 /* host->iomap is not used currently */
1312 host->private_data = host_priv;
1313
1314 /* setup port(s) */
1315
1316 host->ports[0]->ioaddr.cmd_addr = host_priv->hcr_base;
1317 host->ports[0]->ioaddr.scr_addr = host_priv->ssr_base;
1318
1319 /* initialize host controller */
1320 sata_fsl_init_controller(host);
1321
1322 /*
1323 * Now, register with libATA core, this will also initiate the
1324 * device discovery process, invoking our port_start() handler &
1325 * error_handler() to execute a dummy Softreset EH session
1326 */
1327 ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG,
1328 &sata_fsl_sht);
1329
1330 dev_set_drvdata(&ofdev->dev, host);
1331
1332 return 0;
1333
1334 error_exit_with_cleanup:
1335
1336 if (hcr_base)
1337 iounmap(hcr_base);
1338 if (host_priv)
1339 kfree(host_priv);
1340
1341 return retval;
1342 }
1343
1344 static int sata_fsl_remove(struct of_device *ofdev)
1345 {
1346 struct ata_host *host = dev_get_drvdata(&ofdev->dev);
1347 struct sata_fsl_host_priv *host_priv = host->private_data;
1348
1349 ata_host_detach(host);
1350
1351 dev_set_drvdata(&ofdev->dev, NULL);
1352
1353 irq_dispose_mapping(host_priv->irq);
1354 iounmap(host_priv->hcr_base);
1355 kfree(host_priv);
1356
1357 return 0;
1358 }
1359
1360 static struct of_device_id fsl_sata_match[] = {
1361 {
1362 .compatible = "fsl,mpc8315-sata",
1363 },
1364 {
1365 .compatible = "fsl,mpc8379-sata",
1366 },
1367 {},
1368 };
1369
1370 MODULE_DEVICE_TABLE(of, fsl_sata_match);
1371
1372 static struct of_platform_driver fsl_sata_driver = {
1373 .name = "fsl-sata",
1374 .match_table = fsl_sata_match,
1375 .probe = sata_fsl_probe,
1376 .remove = sata_fsl_remove,
1377 };
1378
1379 static int __init sata_fsl_init(void)
1380 {
1381 of_register_platform_driver(&fsl_sata_driver);
1382 return 0;
1383 }
1384
1385 static void __exit sata_fsl_exit(void)
1386 {
1387 of_unregister_platform_driver(&fsl_sata_driver);
1388 }
1389
1390 MODULE_LICENSE("GPL");
1391 MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor");
1392 MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver");
1393 MODULE_VERSION("1.10");
1394
1395 module_init(sata_fsl_init);
1396 module_exit(sata_fsl_exit);
WRT350N Kernel Patches