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CRIS: Move common Kconfig variable ETRAX_RTC to arch independet Kconfig.
[wrt350n-kernel.git] / drivers / net / fs_enet / mac-fec.c
blob8a311d1e435b131a202588d903f557368fbe60f2
1 /*
2 * Freescale Ethernet controllers
3 *
4 * Copyright (c) 2005 Intracom S.A.
5 * by Pantelis Antoniou <panto@intracom.gr>
6 *
7 * 2005 (c) MontaVista Software, Inc.
8 * Vitaly Bordug <vbordug@ru.mvista.com>
9 *
10 * This file is licensed under the terms of the GNU General Public License
11 * version 2. This program is licensed "as is" without any warranty of any
12 * kind, whether express or implied.
13 */
14
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/string.h>
19 #include <linux/ptrace.h>
20 #include <linux/errno.h>
21 #include <linux/ioport.h>
22 #include <linux/slab.h>
23 #include <linux/interrupt.h>
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/netdevice.h>
27 #include <linux/etherdevice.h>
28 #include <linux/skbuff.h>
29 #include <linux/spinlock.h>
30 #include <linux/mii.h>
31 #include <linux/ethtool.h>
32 #include <linux/bitops.h>
33 #include <linux/fs.h>
34 #include <linux/platform_device.h>
35
36 #include <asm/irq.h>
37 #include <asm/uaccess.h>
38
39 #ifdef CONFIG_8xx
40 #include <asm/8xx_immap.h>
41 #include <asm/pgtable.h>
42 #include <asm/mpc8xx.h>
43 #include <asm/cpm1.h>
44 #endif
45
46 #ifdef CONFIG_PPC_CPM_NEW_BINDING
47 #include <asm/of_device.h>
48 #endif
49
50 #include "fs_enet.h"
51 #include "fec.h"
52
53 /*************************************************/
54
55 #if defined(CONFIG_CPM1)
56 /* for a CPM1 __raw_xxx's are sufficient */
57 #define __fs_out32(addr, x) __raw_writel(x, addr)
58 #define __fs_out16(addr, x) __raw_writew(x, addr)
59 #define __fs_in32(addr) __raw_readl(addr)
60 #define __fs_in16(addr) __raw_readw(addr)
61 #else
62 /* for others play it safe */
63 #define __fs_out32(addr, x) out_be32(addr, x)
64 #define __fs_out16(addr, x) out_be16(addr, x)
65 #define __fs_in32(addr) in_be32(addr)
66 #define __fs_in16(addr) in_be16(addr)
67 #endif
68
69 /* write */
70 #define FW(_fecp, _reg, _v) __fs_out32(&(_fecp)->fec_ ## _reg, (_v))
71
72 /* read */
73 #define FR(_fecp, _reg) __fs_in32(&(_fecp)->fec_ ## _reg)
74
75 /* set bits */
76 #define FS(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) | (_v))
77
78 /* clear bits */
79 #define FC(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) & ~(_v))
80
81 /*
82 * Delay to wait for FEC reset command to complete (in us)
83 */
84 #define FEC_RESET_DELAY 50
85
86 static int whack_reset(fec_t __iomem *fecp)
87 {
88 int i;
89
90 FW(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET);
91 for (i = 0; i < FEC_RESET_DELAY; i++) {
92 if ((FR(fecp, ecntrl) & FEC_ECNTRL_RESET) == 0)
93 return 0; /* OK */
94 udelay(1);
95 }
96
97 return -1;
98 }
99
100 static int do_pd_setup(struct fs_enet_private *fep)
101 {
102 #ifdef CONFIG_PPC_CPM_NEW_BINDING
103 struct of_device *ofdev = to_of_device(fep->dev);
104
105 fep->interrupt = of_irq_to_resource(ofdev->node, 0, NULL);
106 if (fep->interrupt == NO_IRQ)
107 return -EINVAL;
108
109 fep->fec.fecp = of_iomap(ofdev->node, 0);
110 if (!fep->fcc.fccp)
111 return -EINVAL;
112
113 return 0;
114 #else
115 struct platform_device *pdev = to_platform_device(fep->dev);
116 struct resource *r;
117
118 /* Fill out IRQ field */
119 fep->interrupt = platform_get_irq_byname(pdev,"interrupt");
120 if (fep->interrupt < 0)
121 return -EINVAL;
122
123 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
124 fep->fec.fecp = ioremap(r->start, r->end - r->start + 1);
125
126 if(fep->fec.fecp == NULL)
127 return -EINVAL;
128
129 return 0;
130 #endif
131 }
132
133 #define FEC_NAPI_RX_EVENT_MSK (FEC_ENET_RXF | FEC_ENET_RXB)
134 #define FEC_RX_EVENT (FEC_ENET_RXF)
135 #define FEC_TX_EVENT (FEC_ENET_TXF)
136 #define FEC_ERR_EVENT_MSK (FEC_ENET_HBERR | FEC_ENET_BABR | \
137 FEC_ENET_BABT | FEC_ENET_EBERR)
138
139 static int setup_data(struct net_device *dev)
140 {
141 struct fs_enet_private *fep = netdev_priv(dev);
142
143 if (do_pd_setup(fep) != 0)
144 return -EINVAL;
145
146 fep->fec.hthi = 0;
147 fep->fec.htlo = 0;
148
149 fep->ev_napi_rx = FEC_NAPI_RX_EVENT_MSK;
150 fep->ev_rx = FEC_RX_EVENT;
151 fep->ev_tx = FEC_TX_EVENT;
152 fep->ev_err = FEC_ERR_EVENT_MSK;
153
154 return 0;
155 }
156
157 static int allocate_bd(struct net_device *dev)
158 {
159 struct fs_enet_private *fep = netdev_priv(dev);
160 const struct fs_platform_info *fpi = fep->fpi;
161
162 fep->ring_base = (void __force __iomem *)dma_alloc_coherent(fep->dev,
163 (fpi->tx_ring + fpi->rx_ring) *
164 sizeof(cbd_t), &fep->ring_mem_addr,
165 GFP_KERNEL);
166 if (fep->ring_base == NULL)
167 return -ENOMEM;
168
169 return 0;
170 }
171
172 static void free_bd(struct net_device *dev)
173 {
174 struct fs_enet_private *fep = netdev_priv(dev);
175 const struct fs_platform_info *fpi = fep->fpi;
176
177 if(fep->ring_base)
178 dma_free_coherent(fep->dev, (fpi->tx_ring + fpi->rx_ring)
179 * sizeof(cbd_t),
180 (void __force *)fep->ring_base,
181 fep->ring_mem_addr);
182 }
183
184 static void cleanup_data(struct net_device *dev)
185 {
186 /* nothing */
187 }
188
189 static void set_promiscuous_mode(struct net_device *dev)
190 {
191 struct fs_enet_private *fep = netdev_priv(dev);
192 fec_t __iomem *fecp = fep->fec.fecp;
193
194 FS(fecp, r_cntrl, FEC_RCNTRL_PROM);
195 }
196
197 static void set_multicast_start(struct net_device *dev)
198 {
199 struct fs_enet_private *fep = netdev_priv(dev);
200
201 fep->fec.hthi = 0;
202 fep->fec.htlo = 0;
203 }
204
205 static void set_multicast_one(struct net_device *dev, const u8 *mac)
206 {
207 struct fs_enet_private *fep = netdev_priv(dev);
208 int temp, hash_index, i, j;
209 u32 crc, csrVal;
210 u8 byte, msb;
211
212 crc = 0xffffffff;
213 for (i = 0; i < 6; i++) {
214 byte = mac[i];
215 for (j = 0; j < 8; j++) {
216 msb = crc >> 31;
217 crc <<= 1;
218 if (msb ^ (byte & 0x1))
219 crc ^= FEC_CRC_POLY;
220 byte >>= 1;
221 }
222 }
223
224 temp = (crc & 0x3f) >> 1;
225 hash_index = ((temp & 0x01) << 4) |
226 ((temp & 0x02) << 2) |
227 ((temp & 0x04)) |
228 ((temp & 0x08) >> 2) |
229 ((temp & 0x10) >> 4);
230 csrVal = 1 << hash_index;
231 if (crc & 1)
232 fep->fec.hthi |= csrVal;
233 else
234 fep->fec.htlo |= csrVal;
235 }
236
237 static void set_multicast_finish(struct net_device *dev)
238 {
239 struct fs_enet_private *fep = netdev_priv(dev);
240 fec_t __iomem *fecp = fep->fec.fecp;
241
242 /* if all multi or too many multicasts; just enable all */
243 if ((dev->flags & IFF_ALLMULTI) != 0 ||
244 dev->mc_count > FEC_MAX_MULTICAST_ADDRS) {
245 fep->fec.hthi = 0xffffffffU;
246 fep->fec.htlo = 0xffffffffU;
247 }
248
249 FC(fecp, r_cntrl, FEC_RCNTRL_PROM);
250 FW(fecp, hash_table_high, fep->fec.hthi);
251 FW(fecp, hash_table_low, fep->fec.htlo);
252 }
253
254 static void set_multicast_list(struct net_device *dev)
255 {
256 struct dev_mc_list *pmc;
257
258 if ((dev->flags & IFF_PROMISC) == 0) {
259 set_multicast_start(dev);
260 for (pmc = dev->mc_list; pmc != NULL; pmc = pmc->next)
261 set_multicast_one(dev, pmc->dmi_addr);
262 set_multicast_finish(dev);
263 } else
264 set_promiscuous_mode(dev);
265 }
266
267 static void restart(struct net_device *dev)
268 {
269 #ifdef CONFIG_DUET
270 immap_t *immap = fs_enet_immap;
271 u32 cptr;
272 #endif
273 struct fs_enet_private *fep = netdev_priv(dev);
274 fec_t __iomem *fecp = fep->fec.fecp;
275 const struct fs_platform_info *fpi = fep->fpi;
276 dma_addr_t rx_bd_base_phys, tx_bd_base_phys;
277 int r;
278 u32 addrhi, addrlo;
279
280 struct mii_bus* mii = fep->phydev->bus;
281 struct fec_info* fec_inf = mii->priv;
282
283 r = whack_reset(fep->fec.fecp);
284 if (r != 0)
285 printk(KERN_ERR DRV_MODULE_NAME
286 ": %s FEC Reset FAILED!\n", dev->name);
287 /*
288 * Set station address.
289 */
290 addrhi = ((u32) dev->dev_addr[0] << 24) |
291 ((u32) dev->dev_addr[1] << 16) |
292 ((u32) dev->dev_addr[2] << 8) |
293 (u32) dev->dev_addr[3];
294 addrlo = ((u32) dev->dev_addr[4] << 24) |
295 ((u32) dev->dev_addr[5] << 16);
296 FW(fecp, addr_low, addrhi);
297 FW(fecp, addr_high, addrlo);
298
299 /*
300 * Reset all multicast.
301 */
302 FW(fecp, hash_table_high, fep->fec.hthi);
303 FW(fecp, hash_table_low, fep->fec.htlo);
304
305 /*
306 * Set maximum receive buffer size.
307 */
308 FW(fecp, r_buff_size, PKT_MAXBLR_SIZE);
309 FW(fecp, r_hash, PKT_MAXBUF_SIZE);
310
311 /* get physical address */
312 rx_bd_base_phys = fep->ring_mem_addr;
313 tx_bd_base_phys = rx_bd_base_phys + sizeof(cbd_t) * fpi->rx_ring;
314
315 /*
316 * Set receive and transmit descriptor base.
317 */
318 FW(fecp, r_des_start, rx_bd_base_phys);
319 FW(fecp, x_des_start, tx_bd_base_phys);
320
321 fs_init_bds(dev);
322
323 /*
324 * Enable big endian and don't care about SDMA FC.
325 */
326 FW(fecp, fun_code, 0x78000000);
327
328 /*
329 * Set MII speed.
330 */
331 FW(fecp, mii_speed, fec_inf->mii_speed);
332
333 /*
334 * Clear any outstanding interrupt.
335 */
336 FW(fecp, ievent, 0xffc0);
337 #ifndef CONFIG_PPC_MERGE
338 FW(fecp, ivec, (fep->interrupt / 2) << 29);
339 #else
340 FW(fecp, ivec, (virq_to_hw(fep->interrupt) / 2) << 29);
341 #endif
342
343 /*
344 * adjust to speed (only for DUET & RMII)
345 */
346 #ifdef CONFIG_DUET
347 if (fpi->use_rmii) {
348 cptr = in_be32(&immap->im_cpm.cp_cptr);
349 switch (fs_get_fec_index(fpi->fs_no)) {
350 case 0:
351 cptr |= 0x100;
352 if (fep->speed == 10)
353 cptr |= 0x0000010;
354 else if (fep->speed == 100)
355 cptr &= ~0x0000010;
356 break;
357 case 1:
358 cptr |= 0x80;
359 if (fep->speed == 10)
360 cptr |= 0x0000008;
361 else if (fep->speed == 100)
362 cptr &= ~0x0000008;
363 break;
364 default:
365 BUG(); /* should never happen */
366 break;
367 }
368 out_be32(&immap->im_cpm.cp_cptr, cptr);
369 }
370 #endif
371
372
373 FW(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */
374 /*
375 * adjust to duplex mode
376 */
377 if (fep->phydev->duplex) {
378 FC(fecp, r_cntrl, FEC_RCNTRL_DRT);
379 FS(fecp, x_cntrl, FEC_TCNTRL_FDEN); /* FD enable */
380 } else {
381 FS(fecp, r_cntrl, FEC_RCNTRL_DRT);
382 FC(fecp, x_cntrl, FEC_TCNTRL_FDEN); /* FD disable */
383 }
384
385 /*
386 * Enable interrupts we wish to service.
387 */
388 FW(fecp, imask, FEC_ENET_TXF | FEC_ENET_TXB |
389 FEC_ENET_RXF | FEC_ENET_RXB);
390
391 /*
392 * And last, enable the transmit and receive processing.
393 */
394 FW(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
395 FW(fecp, r_des_active, 0x01000000);
396 }
397
398 static void stop(struct net_device *dev)
399 {
400 struct fs_enet_private *fep = netdev_priv(dev);
401 const struct fs_platform_info *fpi = fep->fpi;
402 fec_t __iomem *fecp = fep->fec.fecp;
403
404 struct fec_info* feci= fep->phydev->bus->priv;
405
406 int i;
407
408 if ((FR(fecp, ecntrl) & FEC_ECNTRL_ETHER_EN) == 0)
409 return; /* already down */
410
411 FW(fecp, x_cntrl, 0x01); /* Graceful transmit stop */
412 for (i = 0; ((FR(fecp, ievent) & 0x10000000) == 0) &&
413 i < FEC_RESET_DELAY; i++)
414 udelay(1);
415
416 if (i == FEC_RESET_DELAY)
417 printk(KERN_WARNING DRV_MODULE_NAME
418 ": %s FEC timeout on graceful transmit stop\n",
419 dev->name);
420 /*
421 * Disable FEC. Let only MII interrupts.
422 */
423 FW(fecp, imask, 0);
424 FC(fecp, ecntrl, FEC_ECNTRL_ETHER_EN);
425
426 fs_cleanup_bds(dev);
427
428 /* shut down FEC1? that's where the mii bus is */
429 if (fpi->has_phy) {
430 FS(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */
431 FS(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
432 FW(fecp, ievent, FEC_ENET_MII);
433 FW(fecp, mii_speed, feci->mii_speed);
434 }
435 }
436
437 static void pre_request_irq(struct net_device *dev, int irq)
438 {
439 #ifndef CONFIG_PPC_MERGE
440 immap_t *immap = fs_enet_immap;
441 u32 siel;
442
443 /* SIU interrupt */
444 if (irq >= SIU_IRQ0 && irq < SIU_LEVEL7) {
445
446 siel = in_be32(&immap->im_siu_conf.sc_siel);
447 if ((irq & 1) == 0)
448 siel |= (0x80000000 >> irq);
449 else
450 siel &= ~(0x80000000 >> (irq & ~1));
451 out_be32(&immap->im_siu_conf.sc_siel, siel);
452 }
453 #endif
454 }
455
456 static void post_free_irq(struct net_device *dev, int irq)
457 {
458 /* nothing */
459 }
460
461 static void napi_clear_rx_event(struct net_device *dev)
462 {
463 struct fs_enet_private *fep = netdev_priv(dev);
464 fec_t __iomem *fecp = fep->fec.fecp;
465
466 FW(fecp, ievent, FEC_NAPI_RX_EVENT_MSK);
467 }
468
469 static void napi_enable_rx(struct net_device *dev)
470 {
471 struct fs_enet_private *fep = netdev_priv(dev);
472 fec_t __iomem *fecp = fep->fec.fecp;
473
474 FS(fecp, imask, FEC_NAPI_RX_EVENT_MSK);
475 }
476
477 static void napi_disable_rx(struct net_device *dev)
478 {
479 struct fs_enet_private *fep = netdev_priv(dev);
480 fec_t __iomem *fecp = fep->fec.fecp;
481
482 FC(fecp, imask, FEC_NAPI_RX_EVENT_MSK);
483 }
484
485 static void rx_bd_done(struct net_device *dev)
486 {
487 struct fs_enet_private *fep = netdev_priv(dev);
488 fec_t __iomem *fecp = fep->fec.fecp;
489
490 FW(fecp, r_des_active, 0x01000000);
491 }
492
493 static void tx_kickstart(struct net_device *dev)
494 {
495 struct fs_enet_private *fep = netdev_priv(dev);
496 fec_t __iomem *fecp = fep->fec.fecp;
497
498 FW(fecp, x_des_active, 0x01000000);
499 }
500
501 static u32 get_int_events(struct net_device *dev)
502 {
503 struct fs_enet_private *fep = netdev_priv(dev);
504 fec_t __iomem *fecp = fep->fec.fecp;
505
506 return FR(fecp, ievent) & FR(fecp, imask);
507 }
508
509 static void clear_int_events(struct net_device *dev, u32 int_events)
510 {
511 struct fs_enet_private *fep = netdev_priv(dev);
512 fec_t __iomem *fecp = fep->fec.fecp;
513
514 FW(fecp, ievent, int_events);
515 }
516
517 static void ev_error(struct net_device *dev, u32 int_events)
518 {
519 printk(KERN_WARNING DRV_MODULE_NAME
520 ": %s FEC ERROR(s) 0x%x\n", dev->name, int_events);
521 }
522
523 static int get_regs(struct net_device *dev, void *p, int *sizep)
524 {
525 struct fs_enet_private *fep = netdev_priv(dev);
526
527 if (*sizep < sizeof(fec_t))
528 return -EINVAL;
529
530 memcpy_fromio(p, fep->fec.fecp, sizeof(fec_t));
531
532 return 0;
533 }
534
535 static int get_regs_len(struct net_device *dev)
536 {
537 return sizeof(fec_t);
538 }
539
540 static void tx_restart(struct net_device *dev)
541 {
542 /* nothing */
543 }
544
545 /*************************************************************************/
546
547 const struct fs_ops fs_fec_ops = {
548 .setup_data = setup_data,
549 .cleanup_data = cleanup_data,
550 .set_multicast_list = set_multicast_list,
551 .restart = restart,
552 .stop = stop,
553 .pre_request_irq = pre_request_irq,
554 .post_free_irq = post_free_irq,
555 .napi_clear_rx_event = napi_clear_rx_event,
556 .napi_enable_rx = napi_enable_rx,
557 .napi_disable_rx = napi_disable_rx,
558 .rx_bd_done = rx_bd_done,
559 .tx_kickstart = tx_kickstart,
560 .get_int_events = get_int_events,
561 .clear_int_events = clear_int_events,
562 .ev_error = ev_error,
563 .get_regs = get_regs,
564 .get_regs_len = get_regs_len,
565 .tx_restart = tx_restart,
566 .allocate_bd = allocate_bd,
567 .free_bd = free_bd,
568 };
569
WRT350N Kernel Patches