include/asm-blackfin/mach-bf527/bfin_serial_5xx.h

   1 #include <linux/serial.h>
   2 #include <asm/dma.h>
   3 #include <asm/portmux.h>
   4
   5 #define NR_PORTS                2
   6
   7 #define OFFSET_THR              0x00    /* Transmit Holding register            */
   8 #define OFFSET_RBR              0x00    /* Receive Buffer register              */
   9 #define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
  10 #define OFFSET_IER              0x04    /* Interrupt Enable Register            */
  11 #define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
  12 #define OFFSET_IIR              0x08    /* Interrupt Identification Register    */
  13 #define OFFSET_LCR              0x0C    /* Line Control Register                */
  14 #define OFFSET_MCR              0x10    /* Modem Control Register               */
  15 #define OFFSET_LSR              0x14    /* Line Status Register                 */
  16 #define OFFSET_MSR              0x18    /* Modem Status Register                */
  17 #define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
  18 #define OFFSET_GCTL             0x24    /* Global Control Register              */
  19
  20 #define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
  21 #define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
  22 #define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER))
  23 #define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
  24 #define UART_GET_IIR(uart)      bfin_read16(((uart)->port.membase + OFFSET_IIR))
  25 #define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
  26 #define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
  27
  28 #define UART_PUT_CHAR(uart, v)   bfin_write16(((uart)->port.membase + OFFSET_THR), v)
  29 #define UART_PUT_DLL(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
  30 #define UART_PUT_IER(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_IER), v)
  31 #define UART_PUT_DLH(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_DLH), v)
  32 #define UART_PUT_LCR(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_LCR), v)
  33 #define UART_PUT_GCTL(uart, v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL), v)
  34
  35 #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
  36 # define CONFIG_SERIAL_BFIN_CTSRTS
  37
  38 # ifndef CONFIG_UART0_CTS_PIN
  39 #  define CONFIG_UART0_CTS_PIN -1
  40 # endif
  41
  42 # ifndef CONFIG_UART0_RTS_PIN
  43 #  define CONFIG_UART0_RTS_PIN -1
  44 # endif
  45
  46 # ifndef CONFIG_UART1_CTS_PIN
  47 #  define CONFIG_UART1_CTS_PIN -1
  48 # endif
  49
  50 # ifndef CONFIG_UART1_RTS_PIN
  51 #  define CONFIG_UART1_RTS_PIN -1
  52 # endif
  53 #endif
  54 /*
  55  * The pin configuration is different from schematic
  56  */
  57 struct bfin_serial_port {
  58         struct uart_port port;
  59         unsigned int old_status;
  60         unsigned int lsr;
  61 #ifdef CONFIG_SERIAL_BFIN_DMA
  62         int tx_done;
  63         int tx_count;
  64         struct circ_buf rx_dma_buf;
  65         struct timer_list rx_dma_timer;
  66         int rx_dma_nrows;
  67         unsigned int tx_dma_channel;
  68         unsigned int rx_dma_channel;
  69         struct work_struct tx_dma_workqueue;
  70 #endif
  71 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
  72         struct work_struct cts_workqueue;
  73         int cts_pin;
  74         int rts_pin;
  75 #endif
  76 };
  77
  78 /* The hardware clears the LSR bits upon read, so we need to cache
  79  * some of the more fun bits in software so they don't get lost
  80  * when checking the LSR in other code paths (TX).
  81  */
  82 static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
  83 {
  84         unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
  85         uart->lsr |= (lsr & (BI|FE|PE|OE));
  86         return lsr | uart->lsr;
  87 }
  88
  89 static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
  90 {
  91         uart->lsr = 0;
  92         bfin_write16(uart->port.membase + OFFSET_LSR, -1);
  93 }
  94
  95 struct bfin_serial_port bfin_serial_ports[NR_PORTS];
  96 struct bfin_serial_res {
  97         unsigned long uart_base_addr;
  98         int uart_irq;
  99 #ifdef CONFIG_SERIAL_BFIN_DMA
 100         unsigned int uart_tx_dma_channel;
 101         unsigned int uart_rx_dma_channel;
 102 #endif
 103 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
 104         int uart_cts_pin;
 105         int uart_rts_pin;
 106 #endif
 107 };
 108
 109 struct bfin_serial_res bfin_serial_resource[] = {
 110 #ifdef CONFIG_SERIAL_BFIN_UART0
 111         {
 112          0xFFC00400,
 113          IRQ_UART0_RX,
 114 #ifdef CONFIG_SERIAL_BFIN_DMA
 115          CH_UART0_TX,
 116          CH_UART0_RX,
 117 #endif
 118 #ifdef CONFIG_BFIN_UART0_CTSRTS
 119          CONFIG_UART0_CTS_PIN,
 120          CONFIG_UART0_RTS_PIN,
 121 #endif
 122          },
 123 #endif
 124 #ifdef CONFIG_SERIAL_BFIN_UART1
 125         {
 126          0xFFC02000,
 127          IRQ_UART1_RX,
 128 #ifdef CONFIG_SERIAL_BFIN_DMA
 129          CH_UART1_TX,
 130          CH_UART1_RX,
 131 #endif
 132 #ifdef CONFIG_BFIN_UART1_CTSRTS
 133          CONFIG_UART1_CTS_PIN,
 134          CONFIG_UART1_RTS_PIN,
 135 #endif
 136          },
 137 #endif
 138 };
 139
 140 int nr_ports = ARRAY_SIZE(bfin_serial_resource);
 141
 142 #define DRIVER_NAME "bfin-uart"
 143
 144 static void bfin_serial_hw_init(struct bfin_serial_port *uart)
 145 {
 146
 147 #ifdef CONFIG_SERIAL_BFIN_UART0
 148         peripheral_request(P_UART0_TX, DRIVER_NAME);
 149         peripheral_request(P_UART0_RX, DRIVER_NAME);
 150 #endif
 151
 152 #ifdef CONFIG_SERIAL_BFIN_UART1
 153         peripheral_request(P_UART1_TX, DRIVER_NAME);
 154         peripheral_request(P_UART1_RX, DRIVER_NAME);
 155 #endif
 156
 157 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
 158         if (uart->cts_pin >= 0) {
 159                 gpio_request(uart->cts_pin, DRIVER_NAME);
 160                 gpio_direction_input(uart->cts_pin);
 161         }
 162
 163         if (uart->rts_pin >= 0) {
 164                 gpio_request(uart->rts_pin, DRIVER_NAME);
 165                 gpio_direction_output(uart->rts_pin, 0);
 166         }
 167 #endif
 168 }