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Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc
[wrt350n-kernel.git] / drivers / crypto / padlock-aes.c
blob2f3ad3f7dfea2229893864b7b31e9a3dfb5f61c6
1 /*
2 * Cryptographic API.
3 *
4 * Support for VIA PadLock hardware crypto engine.
5 *
6 * Copyright (c) 2004 Michal Ludvig <michal@logix.cz>
7 *
8 * Key expansion routine taken from crypto/aes_generic.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * ---------------------------------------------------------------------------
16 * Copyright (c) 2002, Dr Brian Gladman <brg@gladman.me.uk>, Worcester, UK.
17 * All rights reserved.
18 *
19 * LICENSE TERMS
20 *
21 * The free distribution and use of this software in both source and binary
22 * form is allowed (with or without changes) provided that:
23 *
24 * 1. distributions of this source code include the above copyright
25 * notice, this list of conditions and the following disclaimer;
26 *
27 * 2. distributions in binary form include the above copyright
28 * notice, this list of conditions and the following disclaimer
29 * in the documentation and/or other associated materials;
30 *
31 * 3. the copyright holder's name is not used to endorse products
32 * built using this software without specific written permission.
33 *
34 * ALTERNATIVELY, provided that this notice is retained in full, this product
35 * may be distributed under the terms of the GNU General Public License (GPL),
36 * in which case the provisions of the GPL apply INSTEAD OF those given above.
37 *
38 * DISCLAIMER
39 *
40 * This software is provided 'as is' with no explicit or implied warranties
41 * in respect of its properties, including, but not limited to, correctness
42 * and/or fitness for purpose.
43 * ---------------------------------------------------------------------------
44 */
45
46 #include <crypto/algapi.h>
47 #include <crypto/aes.h>
48 #include <linux/module.h>
49 #include <linux/init.h>
50 #include <linux/types.h>
51 #include <linux/errno.h>
52 #include <linux/interrupt.h>
53 #include <linux/kernel.h>
54 #include <asm/byteorder.h>
55 #include "padlock.h"
56
57 #define AES_EXTENDED_KEY_SIZE 64 /* in uint32_t units */
58 #define AES_EXTENDED_KEY_SIZE_B (AES_EXTENDED_KEY_SIZE * sizeof(uint32_t))
59
60 /* Control word. */
61 struct cword {
62 unsigned int __attribute__ ((__packed__))
63 rounds:4,
64 algo:3,
65 keygen:1,
66 interm:1,
67 encdec:1,
68 ksize:2;
69 } __attribute__ ((__aligned__(PADLOCK_ALIGNMENT)));
70
71 /* Whenever making any changes to the following
72 * structure *make sure* you keep E, d_data
73 * and cword aligned on 16 Bytes boundaries!!! */
74 struct aes_ctx {
75 struct {
76 struct cword encrypt;
77 struct cword decrypt;
78 } cword;
79 u32 *D;
80 int key_length;
81 u32 E[AES_EXTENDED_KEY_SIZE]
82 __attribute__ ((__aligned__(PADLOCK_ALIGNMENT)));
83 u32 d_data[AES_EXTENDED_KEY_SIZE]
84 __attribute__ ((__aligned__(PADLOCK_ALIGNMENT)));
85 };
86
87 /* ====== Key management routines ====== */
88
89 static inline uint32_t
90 generic_rotr32 (const uint32_t x, const unsigned bits)
91 {
92 const unsigned n = bits % 32;
93 return (x >> n) | (x << (32 - n));
94 }
95
96 static inline uint32_t
97 generic_rotl32 (const uint32_t x, const unsigned bits)
98 {
99 const unsigned n = bits % 32;
100 return (x << n) | (x >> (32 - n));
101 }
102
103 #define rotl generic_rotl32
104 #define rotr generic_rotr32
105
106 /*
107 * #define byte(x, nr) ((unsigned char)((x) >> (nr*8)))
108 */
109 static inline uint8_t
110 byte(const uint32_t x, const unsigned n)
111 {
112 return x >> (n << 3);
113 }
114
115 #define E_KEY ctx->E
116 #define D_KEY ctx->D
117
118 static uint8_t pow_tab[256];
119 static uint8_t log_tab[256];
120 static uint8_t sbx_tab[256];
121 static uint8_t isb_tab[256];
122 static uint32_t rco_tab[10];
123 static uint32_t ft_tab[4][256];
124 static uint32_t it_tab[4][256];
125
126 static uint32_t fl_tab[4][256];
127 static uint32_t il_tab[4][256];
128
129 static inline uint8_t
130 f_mult (uint8_t a, uint8_t b)
131 {
132 uint8_t aa = log_tab[a], cc = aa + log_tab[b];
133
134 return pow_tab[cc + (cc < aa ? 1 : 0)];
135 }
136
137 #define ff_mult(a,b) (a && b ? f_mult(a, b) : 0)
138
139 #define f_rn(bo, bi, n, k) \
140 bo[n] = ft_tab[0][byte(bi[n],0)] ^ \
141 ft_tab[1][byte(bi[(n + 1) & 3],1)] ^ \
142 ft_tab[2][byte(bi[(n + 2) & 3],2)] ^ \
143 ft_tab[3][byte(bi[(n + 3) & 3],3)] ^ *(k + n)
144
145 #define i_rn(bo, bi, n, k) \
146 bo[n] = it_tab[0][byte(bi[n],0)] ^ \
147 it_tab[1][byte(bi[(n + 3) & 3],1)] ^ \
148 it_tab[2][byte(bi[(n + 2) & 3],2)] ^ \
149 it_tab[3][byte(bi[(n + 1) & 3],3)] ^ *(k + n)
150
151 #define ls_box(x) \
152 ( fl_tab[0][byte(x, 0)] ^ \
153 fl_tab[1][byte(x, 1)] ^ \
154 fl_tab[2][byte(x, 2)] ^ \
155 fl_tab[3][byte(x, 3)] )
156
157 #define f_rl(bo, bi, n, k) \
158 bo[n] = fl_tab[0][byte(bi[n],0)] ^ \
159 fl_tab[1][byte(bi[(n + 1) & 3],1)] ^ \
160 fl_tab[2][byte(bi[(n + 2) & 3],2)] ^ \
161 fl_tab[3][byte(bi[(n + 3) & 3],3)] ^ *(k + n)
162
163 #define i_rl(bo, bi, n, k) \
164 bo[n] = il_tab[0][byte(bi[n],0)] ^ \
165 il_tab[1][byte(bi[(n + 3) & 3],1)] ^ \
166 il_tab[2][byte(bi[(n + 2) & 3],2)] ^ \
167 il_tab[3][byte(bi[(n + 1) & 3],3)] ^ *(k + n)
168
169 static void
170 gen_tabs (void)
171 {
172 uint32_t i, t;
173 uint8_t p, q;
174
175 /* log and power tables for GF(2**8) finite field with
176 0x011b as modular polynomial - the simplest prmitive
177 root is 0x03, used here to generate the tables */
178
179 for (i = 0, p = 1; i < 256; ++i) {
180 pow_tab[i] = (uint8_t) p;
181 log_tab[p] = (uint8_t) i;
182
183 p ^= (p << 1) ^ (p & 0x80 ? 0x01b : 0);
184 }
185
186 log_tab[1] = 0;
187
188 for (i = 0, p = 1; i < 10; ++i) {
189 rco_tab[i] = p;
190
191 p = (p << 1) ^ (p & 0x80 ? 0x01b : 0);
192 }
193
194 for (i = 0; i < 256; ++i) {
195 p = (i ? pow_tab[255 - log_tab[i]] : 0);
196 q = ((p >> 7) | (p << 1)) ^ ((p >> 6) | (p << 2));
197 p ^= 0x63 ^ q ^ ((q >> 6) | (q << 2));
198 sbx_tab[i] = p;
199 isb_tab[p] = (uint8_t) i;
200 }
201
202 for (i = 0; i < 256; ++i) {
203 p = sbx_tab[i];
204
205 t = p;
206 fl_tab[0][i] = t;
207 fl_tab[1][i] = rotl (t, 8);
208 fl_tab[2][i] = rotl (t, 16);
209 fl_tab[3][i] = rotl (t, 24);
210
211 t = ((uint32_t) ff_mult (2, p)) |
212 ((uint32_t) p << 8) |
213 ((uint32_t) p << 16) | ((uint32_t) ff_mult (3, p) << 24);
214
215 ft_tab[0][i] = t;
216 ft_tab[1][i] = rotl (t, 8);
217 ft_tab[2][i] = rotl (t, 16);
218 ft_tab[3][i] = rotl (t, 24);
219
220 p = isb_tab[i];
221
222 t = p;
223 il_tab[0][i] = t;
224 il_tab[1][i] = rotl (t, 8);
225 il_tab[2][i] = rotl (t, 16);
226 il_tab[3][i] = rotl (t, 24);
227
228 t = ((uint32_t) ff_mult (14, p)) |
229 ((uint32_t) ff_mult (9, p) << 8) |
230 ((uint32_t) ff_mult (13, p) << 16) |
231 ((uint32_t) ff_mult (11, p) << 24);
232
233 it_tab[0][i] = t;
234 it_tab[1][i] = rotl (t, 8);
235 it_tab[2][i] = rotl (t, 16);
236 it_tab[3][i] = rotl (t, 24);
237 }
238 }
239
240 #define star_x(x) (((x) & 0x7f7f7f7f) << 1) ^ ((((x) & 0x80808080) >> 7) * 0x1b)
241
242 #define imix_col(y,x) \
243 u = star_x(x); \
244 v = star_x(u); \
245 w = star_x(v); \
246 t = w ^ (x); \
247 (y) = u ^ v ^ w; \
248 (y) ^= rotr(u ^ t, 8) ^ \
249 rotr(v ^ t, 16) ^ \
250 rotr(t,24)
251
252 /* initialise the key schedule from the user supplied key */
253
254 #define loop4(i) \
255 { t = rotr(t, 8); t = ls_box(t) ^ rco_tab[i]; \
256 t ^= E_KEY[4 * i]; E_KEY[4 * i + 4] = t; \
257 t ^= E_KEY[4 * i + 1]; E_KEY[4 * i + 5] = t; \
258 t ^= E_KEY[4 * i + 2]; E_KEY[4 * i + 6] = t; \
259 t ^= E_KEY[4 * i + 3]; E_KEY[4 * i + 7] = t; \
260 }
261
262 #define loop6(i) \
263 { t = rotr(t, 8); t = ls_box(t) ^ rco_tab[i]; \
264 t ^= E_KEY[6 * i]; E_KEY[6 * i + 6] = t; \
265 t ^= E_KEY[6 * i + 1]; E_KEY[6 * i + 7] = t; \
266 t ^= E_KEY[6 * i + 2]; E_KEY[6 * i + 8] = t; \
267 t ^= E_KEY[6 * i + 3]; E_KEY[6 * i + 9] = t; \
268 t ^= E_KEY[6 * i + 4]; E_KEY[6 * i + 10] = t; \
269 t ^= E_KEY[6 * i + 5]; E_KEY[6 * i + 11] = t; \
270 }
271
272 #define loop8(i) \
273 { t = rotr(t, 8); ; t = ls_box(t) ^ rco_tab[i]; \
274 t ^= E_KEY[8 * i]; E_KEY[8 * i + 8] = t; \
275 t ^= E_KEY[8 * i + 1]; E_KEY[8 * i + 9] = t; \
276 t ^= E_KEY[8 * i + 2]; E_KEY[8 * i + 10] = t; \
277 t ^= E_KEY[8 * i + 3]; E_KEY[8 * i + 11] = t; \
278 t = E_KEY[8 * i + 4] ^ ls_box(t); \
279 E_KEY[8 * i + 12] = t; \
280 t ^= E_KEY[8 * i + 5]; E_KEY[8 * i + 13] = t; \
281 t ^= E_KEY[8 * i + 6]; E_KEY[8 * i + 14] = t; \
282 t ^= E_KEY[8 * i + 7]; E_KEY[8 * i + 15] = t; \
283 }
284
285 /* Tells whether the ACE is capable to generate
286 the extended key for a given key_len. */
287 static inline int
288 aes_hw_extkey_available(uint8_t key_len)
289 {
290 /* TODO: We should check the actual CPU model/stepping
291 as it's possible that the capability will be
292 added in the next CPU revisions. */
293 if (key_len == 16)
294 return 1;
295 return 0;
296 }
297
298 static inline struct aes_ctx *aes_ctx_common(void *ctx)
299 {
300 unsigned long addr = (unsigned long)ctx;
301 unsigned long align = PADLOCK_ALIGNMENT;
302
303 if (align <= crypto_tfm_ctx_alignment())
304 align = 1;
305 return (struct aes_ctx *)ALIGN(addr, align);
306 }
307
308 static inline struct aes_ctx *aes_ctx(struct crypto_tfm *tfm)
309 {
310 return aes_ctx_common(crypto_tfm_ctx(tfm));
311 }
312
313 static inline struct aes_ctx *blk_aes_ctx(struct crypto_blkcipher *tfm)
314 {
315 return aes_ctx_common(crypto_blkcipher_ctx(tfm));
316 }
317
318 static int aes_set_key(struct crypto_tfm *tfm, const u8 *in_key,
319 unsigned int key_len)
320 {
321 struct aes_ctx *ctx = aes_ctx(tfm);
322 const __le32 *key = (const __le32 *)in_key;
323 u32 *flags = &tfm->crt_flags;
324 uint32_t i, t, u, v, w;
325 uint32_t P[AES_EXTENDED_KEY_SIZE];
326 uint32_t rounds;
327
328 if (key_len % 8) {
329 *flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
330 return -EINVAL;
331 }
332
333 ctx->key_length = key_len;
334
335 /*
336 * If the hardware is capable of generating the extended key
337 * itself we must supply the plain key for both encryption
338 * and decryption.
339 */
340 ctx->D = ctx->E;
341
342 E_KEY[0] = le32_to_cpu(key[0]);
343 E_KEY[1] = le32_to_cpu(key[1]);
344 E_KEY[2] = le32_to_cpu(key[2]);
345 E_KEY[3] = le32_to_cpu(key[3]);
346
347 /* Prepare control words. */
348 memset(&ctx->cword, 0, sizeof(ctx->cword));
349
350 ctx->cword.decrypt.encdec = 1;
351 ctx->cword.encrypt.rounds = 10 + (key_len - 16) / 4;
352 ctx->cword.decrypt.rounds = ctx->cword.encrypt.rounds;
353 ctx->cword.encrypt.ksize = (key_len - 16) / 8;
354 ctx->cword.decrypt.ksize = ctx->cword.encrypt.ksize;
355
356 /* Don't generate extended keys if the hardware can do it. */
357 if (aes_hw_extkey_available(key_len))
358 return 0;
359
360 ctx->D = ctx->d_data;
361 ctx->cword.encrypt.keygen = 1;
362 ctx->cword.decrypt.keygen = 1;
363
364 switch (key_len) {
365 case 16:
366 t = E_KEY[3];
367 for (i = 0; i < 10; ++i)
368 loop4 (i);
369 break;
370
371 case 24:
372 E_KEY[4] = le32_to_cpu(key[4]);
373 t = E_KEY[5] = le32_to_cpu(key[5]);
374 for (i = 0; i < 8; ++i)
375 loop6 (i);
376 break;
377
378 case 32:
379 E_KEY[4] = le32_to_cpu(key[4]);
380 E_KEY[5] = le32_to_cpu(key[5]);
381 E_KEY[6] = le32_to_cpu(key[6]);
382 t = E_KEY[7] = le32_to_cpu(key[7]);
383 for (i = 0; i < 7; ++i)
384 loop8 (i);
385 break;
386 }
387
388 D_KEY[0] = E_KEY[0];
389 D_KEY[1] = E_KEY[1];
390 D_KEY[2] = E_KEY[2];
391 D_KEY[3] = E_KEY[3];
392
393 for (i = 4; i < key_len + 24; ++i) {
394 imix_col (D_KEY[i], E_KEY[i]);
395 }
396
397 /* PadLock needs a different format of the decryption key. */
398 rounds = 10 + (key_len - 16) / 4;
399
400 for (i = 0; i < rounds; i++) {
401 P[((i + 1) * 4) + 0] = D_KEY[((rounds - i - 1) * 4) + 0];
402 P[((i + 1) * 4) + 1] = D_KEY[((rounds - i - 1) * 4) + 1];
403 P[((i + 1) * 4) + 2] = D_KEY[((rounds - i - 1) * 4) + 2];
404 P[((i + 1) * 4) + 3] = D_KEY[((rounds - i - 1) * 4) + 3];
405 }
406
407 P[0] = E_KEY[(rounds * 4) + 0];
408 P[1] = E_KEY[(rounds * 4) + 1];
409 P[2] = E_KEY[(rounds * 4) + 2];
410 P[3] = E_KEY[(rounds * 4) + 3];
411
412 memcpy(D_KEY, P, AES_EXTENDED_KEY_SIZE_B);
413
414 return 0;
415 }
416
417 /* ====== Encryption/decryption routines ====== */
418
419 /* These are the real call to PadLock. */
420 static inline void padlock_reset_key(void)
421 {
422 asm volatile ("pushfl; popfl");
423 }
424
425 static inline void padlock_xcrypt(const u8 *input, u8 *output, void *key,
426 void *control_word)
427 {
428 asm volatile (".byte 0xf3,0x0f,0xa7,0xc8" /* rep xcryptecb */
429 : "+S"(input), "+D"(output)
430 : "d"(control_word), "b"(key), "c"(1));
431 }
432
433 static void aes_crypt_copy(const u8 *in, u8 *out, u32 *key, struct cword *cword)
434 {
435 u8 buf[AES_BLOCK_SIZE * 2 + PADLOCK_ALIGNMENT - 1];
436 u8 *tmp = PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);
437
438 memcpy(tmp, in, AES_BLOCK_SIZE);
439 padlock_xcrypt(tmp, out, key, cword);
440 }
441
442 static inline void aes_crypt(const u8 *in, u8 *out, u32 *key,
443 struct cword *cword)
444 {
445 /* padlock_xcrypt requires at least two blocks of data. */
446 if (unlikely(!(((unsigned long)in ^ (PAGE_SIZE - AES_BLOCK_SIZE)) &
447 (PAGE_SIZE - 1)))) {
448 aes_crypt_copy(in, out, key, cword);
449 return;
450 }
451
452 padlock_xcrypt(in, out, key, cword);
453 }
454
455 static inline void padlock_xcrypt_ecb(const u8 *input, u8 *output, void *key,
456 void *control_word, u32 count)
457 {
458 if (count == 1) {
459 aes_crypt(input, output, key, control_word);
460 return;
461 }
462
463 asm volatile ("test $1, %%cl;"
464 "je 1f;"
465 "lea -1(%%ecx), %%eax;"
466 "mov $1, %%ecx;"
467 ".byte 0xf3,0x0f,0xa7,0xc8;" /* rep xcryptecb */
468 "mov %%eax, %%ecx;"
469 "1:"
470 ".byte 0xf3,0x0f,0xa7,0xc8" /* rep xcryptecb */
471 : "+S"(input), "+D"(output)
472 : "d"(control_word), "b"(key), "c"(count)
473 : "ax");
474 }
475
476 static inline u8 *padlock_xcrypt_cbc(const u8 *input, u8 *output, void *key,
477 u8 *iv, void *control_word, u32 count)
478 {
479 /* rep xcryptcbc */
480 asm volatile (".byte 0xf3,0x0f,0xa7,0xd0"
481 : "+S" (input), "+D" (output), "+a" (iv)
482 : "d" (control_word), "b" (key), "c" (count));
483 return iv;
484 }
485
486 static void aes_encrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in)
487 {
488 struct aes_ctx *ctx = aes_ctx(tfm);
489 padlock_reset_key();
490 aes_crypt(in, out, ctx->E, &ctx->cword.encrypt);
491 }
492
493 static void aes_decrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in)
494 {
495 struct aes_ctx *ctx = aes_ctx(tfm);
496 padlock_reset_key();
497 aes_crypt(in, out, ctx->D, &ctx->cword.decrypt);
498 }
499
500 static struct crypto_alg aes_alg = {
501 .cra_name = "aes",
502 .cra_driver_name = "aes-padlock",
503 .cra_priority = PADLOCK_CRA_PRIORITY,
504 .cra_flags = CRYPTO_ALG_TYPE_CIPHER,
505 .cra_blocksize = AES_BLOCK_SIZE,
506 .cra_ctxsize = sizeof(struct aes_ctx),
507 .cra_alignmask = PADLOCK_ALIGNMENT - 1,
508 .cra_module = THIS_MODULE,
509 .cra_list = LIST_HEAD_INIT(aes_alg.cra_list),
510 .cra_u = {
511 .cipher = {
512 .cia_min_keysize = AES_MIN_KEY_SIZE,
513 .cia_max_keysize = AES_MAX_KEY_SIZE,
514 .cia_setkey = aes_set_key,
515 .cia_encrypt = aes_encrypt,
516 .cia_decrypt = aes_decrypt,
517 }
518 }
519 };
520
521 static int ecb_aes_encrypt(struct blkcipher_desc *desc,
522 struct scatterlist *dst, struct scatterlist *src,
523 unsigned int nbytes)
524 {
525 struct aes_ctx *ctx = blk_aes_ctx(desc->tfm);
526 struct blkcipher_walk walk;
527 int err;
528
529 padlock_reset_key();
530
531 blkcipher_walk_init(&walk, dst, src, nbytes);
532 err = blkcipher_walk_virt(desc, &walk);
533
534 while ((nbytes = walk.nbytes)) {
535 padlock_xcrypt_ecb(walk.src.virt.addr, walk.dst.virt.addr,
536 ctx->E, &ctx->cword.encrypt,
537 nbytes / AES_BLOCK_SIZE);
538 nbytes &= AES_BLOCK_SIZE - 1;
539 err = blkcipher_walk_done(desc, &walk, nbytes);
540 }
541
542 return err;
543 }
544
545 static int ecb_aes_decrypt(struct blkcipher_desc *desc,
546 struct scatterlist *dst, struct scatterlist *src,
547 unsigned int nbytes)
548 {
549 struct aes_ctx *ctx = blk_aes_ctx(desc->tfm);
550 struct blkcipher_walk walk;
551 int err;
552
553 padlock_reset_key();
554
555 blkcipher_walk_init(&walk, dst, src, nbytes);
556 err = blkcipher_walk_virt(desc, &walk);
557
558 while ((nbytes = walk.nbytes)) {
559 padlock_xcrypt_ecb(walk.src.virt.addr, walk.dst.virt.addr,
560 ctx->D, &ctx->cword.decrypt,
561 nbytes / AES_BLOCK_SIZE);
562 nbytes &= AES_BLOCK_SIZE - 1;
563 err = blkcipher_walk_done(desc, &walk, nbytes);
564 }
565
566 return err;
567 }
568
569 static struct crypto_alg ecb_aes_alg = {
570 .cra_name = "ecb(aes)",
571 .cra_driver_name = "ecb-aes-padlock",
572 .cra_priority = PADLOCK_COMPOSITE_PRIORITY,
573 .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
574 .cra_blocksize = AES_BLOCK_SIZE,
575 .cra_ctxsize = sizeof(struct aes_ctx),
576 .cra_alignmask = PADLOCK_ALIGNMENT - 1,
577 .cra_type = &crypto_blkcipher_type,
578 .cra_module = THIS_MODULE,
579 .cra_list = LIST_HEAD_INIT(ecb_aes_alg.cra_list),
580 .cra_u = {
581 .blkcipher = {
582 .min_keysize = AES_MIN_KEY_SIZE,
583 .max_keysize = AES_MAX_KEY_SIZE,
584 .setkey = aes_set_key,
585 .encrypt = ecb_aes_encrypt,
586 .decrypt = ecb_aes_decrypt,
587 }
588 }
589 };
590
591 static int cbc_aes_encrypt(struct blkcipher_desc *desc,
592 struct scatterlist *dst, struct scatterlist *src,
593 unsigned int nbytes)
594 {
595 struct aes_ctx *ctx = blk_aes_ctx(desc->tfm);
596 struct blkcipher_walk walk;
597 int err;
598
599 padlock_reset_key();
600
601 blkcipher_walk_init(&walk, dst, src, nbytes);
602 err = blkcipher_walk_virt(desc, &walk);
603
604 while ((nbytes = walk.nbytes)) {
605 u8 *iv = padlock_xcrypt_cbc(walk.src.virt.addr,
606 walk.dst.virt.addr, ctx->E,
607 walk.iv, &ctx->cword.encrypt,
608 nbytes / AES_BLOCK_SIZE);
609 memcpy(walk.iv, iv, AES_BLOCK_SIZE);
610 nbytes &= AES_BLOCK_SIZE - 1;
611 err = blkcipher_walk_done(desc, &walk, nbytes);
612 }
613
614 return err;
615 }
616
617 static int cbc_aes_decrypt(struct blkcipher_desc *desc,
618 struct scatterlist *dst, struct scatterlist *src,
619 unsigned int nbytes)
620 {
621 struct aes_ctx *ctx = blk_aes_ctx(desc->tfm);
622 struct blkcipher_walk walk;
623 int err;
624
625 padlock_reset_key();
626
627 blkcipher_walk_init(&walk, dst, src, nbytes);
628 err = blkcipher_walk_virt(desc, &walk);
629
630 while ((nbytes = walk.nbytes)) {
631 padlock_xcrypt_cbc(walk.src.virt.addr, walk.dst.virt.addr,
632 ctx->D, walk.iv, &ctx->cword.decrypt,
633 nbytes / AES_BLOCK_SIZE);
634 nbytes &= AES_BLOCK_SIZE - 1;
635 err = blkcipher_walk_done(desc, &walk, nbytes);
636 }
637
638 return err;
639 }
640
641 static struct crypto_alg cbc_aes_alg = {
642 .cra_name = "cbc(aes)",
643 .cra_driver_name = "cbc-aes-padlock",
644 .cra_priority = PADLOCK_COMPOSITE_PRIORITY,
645 .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
646 .cra_blocksize = AES_BLOCK_SIZE,
647 .cra_ctxsize = sizeof(struct aes_ctx),
648 .cra_alignmask = PADLOCK_ALIGNMENT - 1,
649 .cra_type = &crypto_blkcipher_type,
650 .cra_module = THIS_MODULE,
651 .cra_list = LIST_HEAD_INIT(cbc_aes_alg.cra_list),
652 .cra_u = {
653 .blkcipher = {
654 .min_keysize = AES_MIN_KEY_SIZE,
655 .max_keysize = AES_MAX_KEY_SIZE,
656 .ivsize = AES_BLOCK_SIZE,
657 .setkey = aes_set_key,
658 .encrypt = cbc_aes_encrypt,
659 .decrypt = cbc_aes_decrypt,
660 }
661 }
662 };
663
664 static int __init padlock_init(void)
665 {
666 int ret;
667
668 if (!cpu_has_xcrypt) {
669 printk(KERN_ERR PFX "VIA PadLock not detected.\n");
670 return -ENODEV;
671 }
672
673 if (!cpu_has_xcrypt_enabled) {
674 printk(KERN_ERR PFX "VIA PadLock detected, but not enabled. Hmm, strange...\n");
675 return -ENODEV;
676 }
677
678 gen_tabs();
679 if ((ret = crypto_register_alg(&aes_alg)))
680 goto aes_err;
681
682 if ((ret = crypto_register_alg(&ecb_aes_alg)))
683 goto ecb_aes_err;
684
685 if ((ret = crypto_register_alg(&cbc_aes_alg)))
686 goto cbc_aes_err;
687
688 printk(KERN_NOTICE PFX "Using VIA PadLock ACE for AES algorithm.\n");
689
690 out:
691 return ret;
692
693 cbc_aes_err:
694 crypto_unregister_alg(&ecb_aes_alg);
695 ecb_aes_err:
696 crypto_unregister_alg(&aes_alg);
697 aes_err:
698 printk(KERN_ERR PFX "VIA PadLock AES initialization failed.\n");
699 goto out;
700 }
701
702 static void __exit padlock_fini(void)
703 {
704 crypto_unregister_alg(&cbc_aes_alg);
705 crypto_unregister_alg(&ecb_aes_alg);
706 crypto_unregister_alg(&aes_alg);
707 }
708
709 module_init(padlock_init);
710 module_exit(padlock_fini);
711
712 MODULE_DESCRIPTION("VIA PadLock AES algorithm support");
713 MODULE_LICENSE("GPL");
714 MODULE_AUTHOR("Michal Ludvig");
715
716 MODULE_ALIAS("aes");
WRT350N Kernel Patches