[IA64] make pfm_get_task work with virtual pids
[wrt350n-kernel.git] / include / asm-sparc64 / head.h
blob67960a751f4dae9cc79d851c68c56e4271fb08ee
1 /* $Id: head.h,v 1.30 1997/08/08 08:34:33 jj Exp $ */
2 #ifndef _SPARC64_HEAD_H
3 #define _SPARC64_HEAD_H
5 #include <asm/pstate.h>
7 /* wrpr %g0, val, %gl */
8 #define SET_GL(val) \
9 .word 0xa1902000 | val
11 /* rdpr %gl, %gN */
12 #define GET_GL_GLOBAL(N) \
13 .word 0x81540000 | (N << 25)
15 #define KERNBASE 0x400000
17 #define PTREGS_OFF (STACK_BIAS + STACKFRAME_SZ)
19 #define __CHEETAH_ID 0x003e0014
20 #define __JALAPENO_ID 0x003e0016
21 #define __SERRANO_ID 0x003e0022
23 #define CHEETAH_MANUF 0x003e
24 #define CHEETAH_IMPL 0x0014 /* Ultra-III */
25 #define CHEETAH_PLUS_IMPL 0x0015 /* Ultra-III+ */
26 #define JALAPENO_IMPL 0x0016 /* Ultra-IIIi */
27 #define JAGUAR_IMPL 0x0018 /* Ultra-IV */
28 #define PANTHER_IMPL 0x0019 /* Ultra-IV+ */
29 #define SERRANO_IMPL 0x0022 /* Ultra-IIIi+ */
31 #define BRANCH_IF_SUN4V(tmp1,label) \
32 sethi %hi(is_sun4v), %tmp1; \
33 lduw [%tmp1 + %lo(is_sun4v)], %tmp1; \
34 brnz,pn %tmp1, label; \
35 nop
37 #define BRANCH_IF_CHEETAH_BASE(tmp1,tmp2,label) \
38 rdpr %ver, %tmp1; \
39 sethi %hi(__CHEETAH_ID), %tmp2; \
40 srlx %tmp1, 32, %tmp1; \
41 or %tmp2, %lo(__CHEETAH_ID), %tmp2;\
42 cmp %tmp1, %tmp2; \
43 be,pn %icc, label; \
44 nop;
46 #define BRANCH_IF_JALAPENO(tmp1,tmp2,label) \
47 rdpr %ver, %tmp1; \
48 sethi %hi(__JALAPENO_ID), %tmp2; \
49 srlx %tmp1, 32, %tmp1; \
50 or %tmp2, %lo(__JALAPENO_ID), %tmp2;\
51 cmp %tmp1, %tmp2; \
52 be,pn %icc, label; \
53 nop;
55 #define BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(tmp1,tmp2,label) \
56 rdpr %ver, %tmp1; \
57 srlx %tmp1, (32 + 16), %tmp2; \
58 cmp %tmp2, CHEETAH_MANUF; \
59 bne,pt %xcc, 99f; \
60 sllx %tmp1, 16, %tmp1; \
61 srlx %tmp1, (32 + 16), %tmp2; \
62 cmp %tmp2, CHEETAH_PLUS_IMPL; \
63 bgeu,pt %xcc, label; \
64 99: nop;
66 #define BRANCH_IF_ANY_CHEETAH(tmp1,tmp2,label) \
67 rdpr %ver, %tmp1; \
68 srlx %tmp1, (32 + 16), %tmp2; \
69 cmp %tmp2, CHEETAH_MANUF; \
70 bne,pt %xcc, 99f; \
71 sllx %tmp1, 16, %tmp1; \
72 srlx %tmp1, (32 + 16), %tmp2; \
73 cmp %tmp2, CHEETAH_IMPL; \
74 bgeu,pt %xcc, label; \
75 99: nop;
77 #endif /* !(_SPARC64_HEAD_H) */