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x86: fix bogus KERN_ALERT on oops
[wrt350n-kernel.git] / arch / ia64 / ia32 / ia32priv.h
blob466bbcb138b2f57beed7181010beeda0d2513726
1 #ifndef _ASM_IA64_IA32_PRIV_H
2 #define _ASM_IA64_IA32_PRIV_H
3
4
5 #include <asm/ia32.h>
6
7 #ifdef CONFIG_IA32_SUPPORT
8
9 #include <linux/binfmts.h>
10 #include <linux/compat.h>
11 #include <linux/rbtree.h>
12
13 #include <asm/processor.h>
14
15 /*
16 * 32 bit structures for IA32 support.
17 */
18
19 #define IA32_PAGE_SIZE (1UL << IA32_PAGE_SHIFT)
20 #define IA32_PAGE_MASK (~(IA32_PAGE_SIZE - 1))
21 #define IA32_PAGE_ALIGN(addr) (((addr) + IA32_PAGE_SIZE - 1) & IA32_PAGE_MASK)
22 #define IA32_CLOCKS_PER_SEC 100 /* Cast in stone for IA32 Linux */
23
24 /*
25 * partially mapped pages provide precise accounting of which 4k sub pages
26 * are mapped and which ones are not, thereby improving IA-32 compatibility.
27 */
28 struct ia64_partial_page {
29 struct ia64_partial_page *next; /* linked list, sorted by address */
30 struct rb_node pp_rb;
31 /* 64K is the largest "normal" page supported by ia64 ABI. So 4K*64
32 * should suffice.*/
33 unsigned long bitmap;
34 unsigned int base;
35 };
36
37 struct ia64_partial_page_list {
38 struct ia64_partial_page *pp_head; /* list head, points to the lowest
39 * addressed partial page */
40 struct rb_root ppl_rb;
41 struct ia64_partial_page *pp_hint; /* pp_hint->next is the last
42 * accessed partial page */
43 atomic_t pp_count; /* reference count */
44 };
45
46 #if PAGE_SHIFT > IA32_PAGE_SHIFT
47 struct ia64_partial_page_list* ia32_init_pp_list (void);
48 #else
49 # define ia32_init_pp_list() 0
50 #endif
51
52 /* sigcontext.h */
53 /*
54 * As documented in the iBCS2 standard..
55 *
56 * The first part of "struct _fpstate" is just the
57 * normal i387 hardware setup, the extra "status"
58 * word is used to save the coprocessor status word
59 * before entering the handler.
60 */
61 struct _fpreg_ia32 {
62 unsigned short significand[4];
63 unsigned short exponent;
64 };
65
66 struct _fpxreg_ia32 {
67 unsigned short significand[4];
68 unsigned short exponent;
69 unsigned short padding[3];
70 };
71
72 struct _xmmreg_ia32 {
73 unsigned int element[4];
74 };
75
76
77 struct _fpstate_ia32 {
78 unsigned int cw,
79 sw,
80 tag,
81 ipoff,
82 cssel,
83 dataoff,
84 datasel;
85 struct _fpreg_ia32 _st[8];
86 unsigned short status;
87 unsigned short magic; /* 0xffff = regular FPU data only */
88
89 /* FXSR FPU environment */
90 unsigned int _fxsr_env[6]; /* FXSR FPU env is ignored */
91 unsigned int mxcsr;
92 unsigned int reserved;
93 struct _fpxreg_ia32 _fxsr_st[8]; /* FXSR FPU reg data is ignored */
94 struct _xmmreg_ia32 _xmm[8];
95 unsigned int padding[56];
96 };
97
98 struct sigcontext_ia32 {
99 unsigned short gs, __gsh;
100 unsigned short fs, __fsh;
101 unsigned short es, __esh;
102 unsigned short ds, __dsh;
103 unsigned int edi;
104 unsigned int esi;
105 unsigned int ebp;
106 unsigned int esp;
107 unsigned int ebx;
108 unsigned int edx;
109 unsigned int ecx;
110 unsigned int eax;
111 unsigned int trapno;
112 unsigned int err;
113 unsigned int eip;
114 unsigned short cs, __csh;
115 unsigned int eflags;
116 unsigned int esp_at_signal;
117 unsigned short ss, __ssh;
118 unsigned int fpstate; /* really (struct _fpstate_ia32 *) */
119 unsigned int oldmask;
120 unsigned int cr2;
121 };
122
123 /* user.h */
124 /*
125 * IA32 (Pentium III/4) FXSR, SSE support
126 *
127 * Provide support for the GDB 5.0+ PTRACE_{GET|SET}FPXREGS requests for
128 * interacting with the FXSR-format floating point environment. Floating
129 * point data can be accessed in the regular format in the usual manner,
130 * and both the standard and SIMD floating point data can be accessed via
131 * the new ptrace requests. In either case, changes to the FPU environment
132 * will be reflected in the task's state as expected.
133 */
134 struct ia32_user_i387_struct {
135 int cwd;
136 int swd;
137 int twd;
138 int fip;
139 int fcs;
140 int foo;
141 int fos;
142 /* 8*10 bytes for each FP-reg = 80 bytes */
143 struct _fpreg_ia32 st_space[8];
144 };
145
146 struct ia32_user_fxsr_struct {
147 unsigned short cwd;
148 unsigned short swd;
149 unsigned short twd;
150 unsigned short fop;
151 int fip;
152 int fcs;
153 int foo;
154 int fos;
155 int mxcsr;
156 int reserved;
157 int st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
158 int xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
159 int padding[56];
160 };
161
162 /* signal.h */
163 #define IA32_SET_SA_HANDLER(ka,handler,restorer) \
164 ((ka)->sa.sa_handler = (__sighandler_t) \
165 (((unsigned long)(restorer) << 32) \
166 | ((handler) & 0xffffffff)))
167 #define IA32_SA_HANDLER(ka) ((unsigned long) (ka)->sa.sa_handler & 0xffffffff)
168 #define IA32_SA_RESTORER(ka) ((unsigned long) (ka)->sa.sa_handler >> 32)
169
170 #define __IA32_NR_sigreturn 119
171 #define __IA32_NR_rt_sigreturn 173
172
173 struct sigaction32 {
174 unsigned int sa_handler; /* Really a pointer, but need to deal with 32 bits */
175 unsigned int sa_flags;
176 unsigned int sa_restorer; /* Another 32 bit pointer */
177 compat_sigset_t sa_mask; /* A 32 bit mask */
178 };
179
180 struct old_sigaction32 {
181 unsigned int sa_handler; /* Really a pointer, but need to deal
182 with 32 bits */
183 compat_old_sigset_t sa_mask; /* A 32 bit mask */
184 unsigned int sa_flags;
185 unsigned int sa_restorer; /* Another 32 bit pointer */
186 };
187
188 typedef struct sigaltstack_ia32 {
189 unsigned int ss_sp;
190 int ss_flags;
191 unsigned int ss_size;
192 } stack_ia32_t;
193
194 struct ucontext_ia32 {
195 unsigned int uc_flags;
196 unsigned int uc_link;
197 stack_ia32_t uc_stack;
198 struct sigcontext_ia32 uc_mcontext;
199 sigset_t uc_sigmask; /* mask last for extensibility */
200 };
201
202 struct stat64 {
203 unsigned long long st_dev;
204 unsigned char __pad0[4];
205 unsigned int __st_ino;
206 unsigned int st_mode;
207 unsigned int st_nlink;
208 unsigned int st_uid;
209 unsigned int st_gid;
210 unsigned long long st_rdev;
211 unsigned char __pad3[4];
212 unsigned int st_size_lo;
213 unsigned int st_size_hi;
214 unsigned int st_blksize;
215 unsigned int st_blocks; /* Number 512-byte blocks allocated. */
216 unsigned int __pad4; /* future possible st_blocks high bits */
217 unsigned int st_atime;
218 unsigned int st_atime_nsec;
219 unsigned int st_mtime;
220 unsigned int st_mtime_nsec;
221 unsigned int st_ctime;
222 unsigned int st_ctime_nsec;
223 unsigned int st_ino_lo;
224 unsigned int st_ino_hi;
225 };
226
227 typedef struct compat_siginfo {
228 int si_signo;
229 int si_errno;
230 int si_code;
231
232 union {
233 int _pad[((128/sizeof(int)) - 3)];
234
235 /* kill() */
236 struct {
237 unsigned int _pid; /* sender's pid */
238 unsigned int _uid; /* sender's uid */
239 } _kill;
240
241 /* POSIX.1b timers */
242 struct {
243 compat_timer_t _tid; /* timer id */
244 int _overrun; /* overrun count */
245 char _pad[sizeof(unsigned int) - sizeof(int)];
246 compat_sigval_t _sigval; /* same as below */
247 int _sys_private; /* not to be passed to user */
248 } _timer;
249
250 /* POSIX.1b signals */
251 struct {
252 unsigned int _pid; /* sender's pid */
253 unsigned int _uid; /* sender's uid */
254 compat_sigval_t _sigval;
255 } _rt;
256
257 /* SIGCHLD */
258 struct {
259 unsigned int _pid; /* which child */
260 unsigned int _uid; /* sender's uid */
261 int _status; /* exit code */
262 compat_clock_t _utime;
263 compat_clock_t _stime;
264 } _sigchld;
265
266 /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
267 struct {
268 unsigned int _addr; /* faulting insn/memory ref. */
269 } _sigfault;
270
271 /* SIGPOLL */
272 struct {
273 int _band; /* POLL_IN, POLL_OUT, POLL_MSG */
274 int _fd;
275 } _sigpoll;
276 } _sifields;
277 } compat_siginfo_t;
278
279 struct old_linux32_dirent {
280 u32 d_ino;
281 u32 d_offset;
282 u16 d_namlen;
283 char d_name[1];
284 };
285
286 /*
287 * IA-32 ELF specific definitions for IA-64.
288 */
289
290 #define _ASM_IA64_ELF_H /* Don't include elf.h */
291
292 #include <linux/sched.h>
293 #include <asm/processor.h>
294
295 /*
296 * This is used to ensure we don't load something for the wrong architecture.
297 */
298 #define elf_check_arch(x) ((x)->e_machine == EM_386)
299
300 /*
301 * These are used to set parameters in the core dumps.
302 */
303 #define ELF_CLASS ELFCLASS32
304 #define ELF_DATA ELFDATA2LSB
305 #define ELF_ARCH EM_386
306
307 #define IA32_STACK_TOP IA32_PAGE_OFFSET
308 #define IA32_GATE_OFFSET IA32_PAGE_OFFSET
309 #define IA32_GATE_END IA32_PAGE_OFFSET + PAGE_SIZE
310
311 /*
312 * The system segments (GDT, TSS, LDT) have to be mapped below 4GB so the IA-32 engine can
313 * access them.
314 */
315 #define IA32_GDT_OFFSET (IA32_PAGE_OFFSET + PAGE_SIZE)
316 #define IA32_TSS_OFFSET (IA32_PAGE_OFFSET + 2*PAGE_SIZE)
317 #define IA32_LDT_OFFSET (IA32_PAGE_OFFSET + 3*PAGE_SIZE)
318
319 #define ELF_EXEC_PAGESIZE IA32_PAGE_SIZE
320
321 /*
322 * This is the location that an ET_DYN program is loaded if exec'ed.
323 * Typical use of this is to invoke "./ld.so someprog" to test out a
324 * new version of the loader. We need to make sure that it is out of
325 * the way of the program that it will "exec", and that there is
326 * sufficient room for the brk.
327 */
328 #define ELF_ET_DYN_BASE (IA32_PAGE_OFFSET/3 + 0x1000000)
329
330 void ia64_elf32_init(struct pt_regs *regs);
331 #define ELF_PLAT_INIT(_r, load_addr) ia64_elf32_init(_r)
332
333 /* This macro yields a bitmask that programs can use to figure out
334 what instruction set this CPU supports. */
335 #define ELF_HWCAP 0
336
337 /* This macro yields a string that ld.so will use to load
338 implementation specific libraries for optimization. Not terribly
339 relevant until we have real hardware to play with... */
340 #define ELF_PLATFORM NULL
341
342 #ifdef __KERNEL__
343 # define SET_PERSONALITY(EX,IBCS2) \
344 (current->personality = (IBCS2) ? PER_SVR4 : PER_LINUX)
345 #endif
346
347 #define IA32_EFLAG 0x200
348
349 /*
350 * IA-32 ELF specific definitions for IA-64.
351 */
352
353 #define __USER_CS 0x23
354 #define __USER_DS 0x2B
355
356 /*
357 * The per-cpu GDT has 32 entries: see <asm-i386/segment.h>
358 */
359 #define GDT_ENTRIES 32
360
361 #define GDT_SIZE (GDT_ENTRIES * 8)
362
363 #define TSS_ENTRY 14
364 #define LDT_ENTRY (TSS_ENTRY + 1)
365
366 #define IA32_SEGSEL_RPL (0x3 << 0)
367 #define IA32_SEGSEL_TI (0x1 << 2)
368 #define IA32_SEGSEL_INDEX_SHIFT 3
369
370 #define _TSS ((unsigned long) TSS_ENTRY << IA32_SEGSEL_INDEX_SHIFT)
371 #define _LDT ((unsigned long) LDT_ENTRY << IA32_SEGSEL_INDEX_SHIFT)
372
373 #define IA32_SEG_BASE 16
374 #define IA32_SEG_TYPE 40
375 #define IA32_SEG_SYS 44
376 #define IA32_SEG_DPL 45
377 #define IA32_SEG_P 47
378 #define IA32_SEG_HIGH_LIMIT 48
379 #define IA32_SEG_AVL 52
380 #define IA32_SEG_DB 54
381 #define IA32_SEG_G 55
382 #define IA32_SEG_HIGH_BASE 56
383
384 #define IA32_SEG_DESCRIPTOR(base, limit, segtype, nonsysseg, dpl, segpresent, avl, segdb, gran) \
385 (((limit) & 0xffff) \
386 | (((unsigned long) (base) & 0xffffff) << IA32_SEG_BASE) \
387 | ((unsigned long) (segtype) << IA32_SEG_TYPE) \
388 | ((unsigned long) (nonsysseg) << IA32_SEG_SYS) \
389 | ((unsigned long) (dpl) << IA32_SEG_DPL) \
390 | ((unsigned long) (segpresent) << IA32_SEG_P) \
391 | ((((unsigned long) (limit) >> 16) & 0xf) << IA32_SEG_HIGH_LIMIT) \
392 | ((unsigned long) (avl) << IA32_SEG_AVL) \
393 | ((unsigned long) (segdb) << IA32_SEG_DB) \
394 | ((unsigned long) (gran) << IA32_SEG_G) \
395 | ((((unsigned long) (base) >> 24) & 0xff) << IA32_SEG_HIGH_BASE))
396
397 #define SEG_LIM 32
398 #define SEG_TYPE 52
399 #define SEG_SYS 56
400 #define SEG_DPL 57
401 #define SEG_P 59
402 #define SEG_AVL 60
403 #define SEG_DB 62
404 #define SEG_G 63
405
406 /* Unscramble an IA-32 segment descriptor into the IA-64 format. */
407 #define IA32_SEG_UNSCRAMBLE(sd) \
408 ( (((sd) >> IA32_SEG_BASE) & 0xffffff) | ((((sd) >> IA32_SEG_HIGH_BASE) & 0xff) << 24) \
409 | ((((sd) & 0xffff) | ((((sd) >> IA32_SEG_HIGH_LIMIT) & 0xf) << 16)) << SEG_LIM) \
410 | ((((sd) >> IA32_SEG_TYPE) & 0xf) << SEG_TYPE) \
411 | ((((sd) >> IA32_SEG_SYS) & 0x1) << SEG_SYS) \
412 | ((((sd) >> IA32_SEG_DPL) & 0x3) << SEG_DPL) \
413 | ((((sd) >> IA32_SEG_P) & 0x1) << SEG_P) \
414 | ((((sd) >> IA32_SEG_AVL) & 0x1) << SEG_AVL) \
415 | ((((sd) >> IA32_SEG_DB) & 0x1) << SEG_DB) \
416 | ((((sd) >> IA32_SEG_G) & 0x1) << SEG_G))
417
418 #define IA32_IOBASE 0x2000000000000000UL /* Virtual address for I/O space */
419
420 #define IA32_CR0 0x80000001 /* Enable PG and PE bits */
421 #define IA32_CR4 0x600 /* MMXEX and FXSR on */
422
423 /*
424 * IA32 floating point control registers starting values
425 */
426
427 #define IA32_FSR_DEFAULT 0x55550000 /* set all tag bits */
428 #define IA32_FCR_DEFAULT 0x17800000037fUL /* extended precision, all masks */
429
430 #define IA32_PTRACE_GETREGS 12
431 #define IA32_PTRACE_SETREGS 13
432 #define IA32_PTRACE_GETFPREGS 14
433 #define IA32_PTRACE_SETFPREGS 15
434 #define IA32_PTRACE_GETFPXREGS 18
435 #define IA32_PTRACE_SETFPXREGS 19
436
437 #define ia32_start_thread(regs,new_ip,new_sp) do { \
438 set_fs(USER_DS); \
439 ia64_psr(regs)->cpl = 3; /* set user mode */ \
440 ia64_psr(regs)->ri = 0; /* clear return slot number */ \
441 ia64_psr(regs)->is = 1; /* IA-32 instruction set */ \
442 regs->cr_iip = new_ip; \
443 regs->ar_rsc = 0xc; /* enforced lazy mode, priv. level 3 */ \
444 regs->ar_rnat = 0; \
445 regs->loadrs = 0; \
446 regs->r12 = new_sp; \
447 } while (0)
448
449 /*
450 * Local Descriptor Table (LDT) related declarations.
451 */
452
453 #define IA32_LDT_ENTRIES 8192 /* Maximum number of LDT entries supported. */
454 #define IA32_LDT_ENTRY_SIZE 8 /* The size of each LDT entry. */
455
456 #define LDT_entry_a(info) \
457 ((((info)->base_addr & 0x0000ffff) << 16) | ((info)->limit & 0x0ffff))
458
459 #define LDT_entry_b(info) \
460 (((info)->base_addr & 0xff000000) | \
461 (((info)->base_addr & 0x00ff0000) >> 16) | \
462 ((info)->limit & 0xf0000) | \
463 (((info)->read_exec_only ^ 1) << 9) | \
464 ((info)->contents << 10) | \
465 (((info)->seg_not_present ^ 1) << 15) | \
466 ((info)->seg_32bit << 22) | \
467 ((info)->limit_in_pages << 23) | \
468 ((info)->useable << 20) | \
469 0x7100)
470
471 #define LDT_empty(info) ( \
472 (info)->base_addr == 0 && \
473 (info)->limit == 0 && \
474 (info)->contents == 0 && \
475 (info)->read_exec_only == 1 && \
476 (info)->seg_32bit == 0 && \
477 (info)->limit_in_pages == 0 && \
478 (info)->seg_not_present == 1 && \
479 (info)->useable == 0 )
480
481 static inline void
482 load_TLS (struct thread_struct *t, unsigned int cpu)
483 {
484 extern unsigned long *cpu_gdt_table[NR_CPUS];
485
486 memcpy(cpu_gdt_table[cpu] + GDT_ENTRY_TLS_MIN + 0, &t->tls_array[0], sizeof(long));
487 memcpy(cpu_gdt_table[cpu] + GDT_ENTRY_TLS_MIN + 1, &t->tls_array[1], sizeof(long));
488 memcpy(cpu_gdt_table[cpu] + GDT_ENTRY_TLS_MIN + 2, &t->tls_array[2], sizeof(long));
489 }
490
491 struct ia32_user_desc {
492 unsigned int entry_number;
493 unsigned int base_addr;
494 unsigned int limit;
495 unsigned int seg_32bit:1;
496 unsigned int contents:2;
497 unsigned int read_exec_only:1;
498 unsigned int limit_in_pages:1;
499 unsigned int seg_not_present:1;
500 unsigned int useable:1;
501 };
502
503 struct linux_binprm;
504
505 extern void ia32_init_addr_space (struct pt_regs *regs);
506 extern int ia32_setup_arg_pages (struct linux_binprm *bprm, int exec_stack);
507 extern unsigned long ia32_do_mmap (struct file *, unsigned long, unsigned long, int, int, loff_t);
508 extern void ia32_load_segment_descriptors (struct task_struct *task);
509
510 #define ia32f2ia64f(dst,src) \
511 do { \
512 ia64_ldfe(6,src); \
513 ia64_stop(); \
514 ia64_stf_spill(dst, 6); \
515 } while(0)
516
517 #define ia64f2ia32f(dst,src) \
518 do { \
519 ia64_ldf_fill(6, src); \
520 ia64_stop(); \
521 ia64_stfe(dst, 6); \
522 } while(0)
523
524 struct user_regs_struct32 {
525 __u32 ebx, ecx, edx, esi, edi, ebp, eax;
526 unsigned short ds, __ds, es, __es;
527 unsigned short fs, __fs, gs, __gs;
528 __u32 orig_eax, eip;
529 unsigned short cs, __cs;
530 __u32 eflags, esp;
531 unsigned short ss, __ss;
532 };
533
534 /* Prototypes for use in elfcore32.h */
535 extern int save_ia32_fpstate (struct task_struct *, struct ia32_user_i387_struct __user *);
536 extern int save_ia32_fpxstate (struct task_struct *, struct ia32_user_fxsr_struct __user *);
537
538 #endif /* !CONFIG_IA32_SUPPORT */
539
540 #endif /* _ASM_IA64_IA32_PRIV_H */
WRT350N Kernel Patches