include/asm-parisc/assembly.h

   1 /*
   2  * Copyright (C) 1999 Hewlett-Packard (Frank Rowand)
   3  * Copyright (C) 1999 Philipp Rumpf <prumpf@tux.org>
   4  * Copyright (C) 1999 SuSE GmbH
   5  *
   6  *    This program is free software; you can redistribute it and/or modify
   7  *    it under the terms of the GNU General Public License as published by
   8  *    the Free Software Foundation; either version 2, or (at your option)
   9  *    any later version.
  10  *
  11  *    This program is distributed in the hope that it will be useful,
  12  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *    GNU General Public License for more details.
  15  *
  16  *    You should have received a copy of the GNU General Public License
  17  *    along with this program; if not, write to the Free Software
  18  *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20
  21 #ifndef _PARISC_ASSEMBLY_H
  22 #define _PARISC_ASSEMBLY_H
  23
  24 #define CALLEE_FLOAT_FRAME_SIZE 80
  25
  26 #ifdef CONFIG_64BIT
  27 #define LDREG   ldd
  28 #define STREG   std
  29 #define LDREGX  ldd,s
  30 #define LDREGM  ldd,mb
  31 #define STREGM  std,ma
  32 #define SHRREG  shrd
  33 #define SHLREG  shld
  34 #define ADDIB   addib,*
  35 #define CMPB    cmpb,*
  36 #define ANDCM   andcm,*
  37 #define RP_OFFSET       16
  38 #define FRAME_SIZE      128
  39 #define CALLEE_REG_FRAME_SIZE   144
  40 #define ASM_ULONG_INSN  .dword
  41 #else   /* CONFIG_64BIT */
  42 #define LDREG   ldw
  43 #define STREG   stw
  44 #define LDREGX  ldwx,s
  45 #define LDREGM  ldwm
  46 #define STREGM  stwm
  47 #define SHRREG  shr
  48 #define SHLREG  shlw
  49 #define ADDIB   addib,
  50 #define CMPB    cmpb,
  51 #define ANDCM   andcm
  52 #define RP_OFFSET       20
  53 #define FRAME_SIZE      64
  54 #define CALLEE_REG_FRAME_SIZE   128
  55 #define ASM_ULONG_INSN  .word
  56 #endif
  57
  58 #define CALLEE_SAVE_FRAME_SIZE (CALLEE_REG_FRAME_SIZE + CALLEE_FLOAT_FRAME_SIZE)
  59
  60 #ifdef CONFIG_PA20
  61 #define LDCW            ldcw,co
  62 #define BL              b,l
  63 # ifdef CONFIG_64BIT
  64 #  define LEVEL         2.0w
  65 # else
  66 #  define LEVEL         2.0
  67 # endif
  68 #else
  69 #define LDCW            ldcw
  70 #define BL              bl
  71 #define LEVEL           1.1
  72 #endif
  73
  74 #ifdef __ASSEMBLY__
  75
  76 #ifdef CONFIG_64BIT
  77 /* the 64-bit pa gnu assembler unfortunately defaults to .level 1.1 or 2.0 so
  78  * work around that for now... */
  79         .level 2.0w
  80 #endif
  81
  82 #include <asm/asm-offsets.h>
  83 #include <asm/page.h>
  84
  85 #include <asm/asmregs.h>
  86
  87         sp      =       30
  88         gp      =       27
  89         ipsw    =       22
  90
  91         /*
  92          * We provide two versions of each macro to convert from physical
  93          * to virtual and vice versa. The "_r1" versions take one argument
  94          * register, but trashes r1 to do the conversion. The other
  95          * version takes two arguments: a src and destination register.
  96          * However, the source and destination registers can not be
  97          * the same register.
  98          */
  99
 100         .macro  tophys  grvirt, grphys
 101         ldil    L%(__PAGE_OFFSET), \grphys
 102         sub     \grvirt, \grphys, \grphys
 103         .endm
 104
 105         .macro  tovirt  grphys, grvirt
 106         ldil    L%(__PAGE_OFFSET), \grvirt
 107         add     \grphys, \grvirt, \grvirt
 108         .endm
 109
 110         .macro  tophys_r1  gr
 111         ldil    L%(__PAGE_OFFSET), %r1
 112         sub     \gr, %r1, \gr
 113         .endm
 114
 115         .macro  tovirt_r1  gr
 116         ldil    L%(__PAGE_OFFSET), %r1
 117         add     \gr, %r1, \gr
 118         .endm
 119
 120         .macro delay value
 121         ldil    L%\value, 1
 122         ldo     R%\value(1), 1
 123         addib,UV,n -1,1,.
 124         addib,NUV,n -1,1,.+8
 125         nop
 126         .endm
 127
 128         .macro  debug value
 129         .endm
 130
 131
 132         /* Shift Left - note the r and t can NOT be the same! */
 133         .macro shl r, sa, t
 134         dep,z   \r, 31-\sa, 32-\sa, \t
 135         .endm
 136
 137         /* The PA 2.0 shift left */
 138         .macro shlw r, sa, t
 139         depw,z  \r, 31-\sa, 32-\sa, \t
 140         .endm
 141
 142         /* And the PA 2.0W shift left */
 143         .macro shld r, sa, t
 144         depd,z  \r, 63-\sa, 64-\sa, \t
 145         .endm
 146
 147         /* Shift Right - note the r and t can NOT be the same! */
 148         .macro shr r, sa, t
 149         extru \r, 31-\sa, 32-\sa, \t
 150         .endm
 151
 152         /* pa20w version of shift right */
 153         .macro shrd r, sa, t
 154         extrd,u \r, 63-\sa, 64-\sa, \t
 155         .endm
 156
 157         /* load 32-bit 'value' into 'reg' compensating for the ldil
 158          * sign-extension when running in wide mode.
 159          * WARNING!! neither 'value' nor 'reg' can be expressions
 160          * containing '.'!!!! */
 161         .macro  load32 value, reg
 162         ldil    L%\value, \reg
 163         ldo     R%\value(\reg), \reg
 164         .endm
 165
 166         .macro loadgp
 167 #ifdef CONFIG_64BIT
 168         ldil            L%__gp, %r27
 169         ldo             R%__gp(%r27), %r27
 170 #else
 171         ldil            L%$global$, %r27
 172         ldo             R%$global$(%r27), %r27
 173 #endif
 174         .endm
 175
 176 #define SAVE_SP(r, where) mfsp r, %r1 ! STREG %r1, where
 177 #define REST_SP(r, where) LDREG where, %r1 ! mtsp %r1, r
 178 #define SAVE_CR(r, where) mfctl r, %r1 ! STREG %r1, where
 179 #define REST_CR(r, where) LDREG where, %r1 ! mtctl %r1, r
 180
 181         .macro  save_general    regs
 182         STREG %r1, PT_GR1 (\regs)
 183         STREG %r2, PT_GR2 (\regs)
 184         STREG %r3, PT_GR3 (\regs)
 185         STREG %r4, PT_GR4 (\regs)
 186         STREG %r5, PT_GR5 (\regs)
 187         STREG %r6, PT_GR6 (\regs)
 188         STREG %r7, PT_GR7 (\regs)
 189         STREG %r8, PT_GR8 (\regs)
 190         STREG %r9, PT_GR9 (\regs)
 191         STREG %r10, PT_GR10(\regs)
 192         STREG %r11, PT_GR11(\regs)
 193         STREG %r12, PT_GR12(\regs)
 194         STREG %r13, PT_GR13(\regs)
 195         STREG %r14, PT_GR14(\regs)
 196         STREG %r15, PT_GR15(\regs)
 197         STREG %r16, PT_GR16(\regs)
 198         STREG %r17, PT_GR17(\regs)
 199         STREG %r18, PT_GR18(\regs)
 200         STREG %r19, PT_GR19(\regs)
 201         STREG %r20, PT_GR20(\regs)
 202         STREG %r21, PT_GR21(\regs)
 203         STREG %r22, PT_GR22(\regs)
 204         STREG %r23, PT_GR23(\regs)
 205         STREG %r24, PT_GR24(\regs)
 206         STREG %r25, PT_GR25(\regs)
 207         /* r26 is saved in get_stack and used to preserve a value across virt_map */
 208         STREG %r27, PT_GR27(\regs)
 209         STREG %r28, PT_GR28(\regs)
 210         /* r29 is saved in get_stack and used to point to saved registers */
 211         /* r30 stack pointer saved in get_stack */
 212         STREG %r31, PT_GR31(\regs)
 213         .endm
 214
 215         .macro  rest_general    regs
 216         /* r1 used as a temp in rest_stack and is restored there */
 217         LDREG PT_GR2 (\regs), %r2
 218         LDREG PT_GR3 (\regs), %r3
 219         LDREG PT_GR4 (\regs), %r4
 220         LDREG PT_GR5 (\regs), %r5
 221         LDREG PT_GR6 (\regs), %r6
 222         LDREG PT_GR7 (\regs), %r7
 223         LDREG PT_GR8 (\regs), %r8
 224         LDREG PT_GR9 (\regs), %r9
 225         LDREG PT_GR10(\regs), %r10
 226         LDREG PT_GR11(\regs), %r11
 227         LDREG PT_GR12(\regs), %r12
 228         LDREG PT_GR13(\regs), %r13
 229         LDREG PT_GR14(\regs), %r14
 230         LDREG PT_GR15(\regs), %r15
 231         LDREG PT_GR16(\regs), %r16
 232         LDREG PT_GR17(\regs), %r17
 233         LDREG PT_GR18(\regs), %r18
 234         LDREG PT_GR19(\regs), %r19
 235         LDREG PT_GR20(\regs), %r20
 236         LDREG PT_GR21(\regs), %r21
 237         LDREG PT_GR22(\regs), %r22
 238         LDREG PT_GR23(\regs), %r23
 239         LDREG PT_GR24(\regs), %r24
 240         LDREG PT_GR25(\regs), %r25
 241         LDREG PT_GR26(\regs), %r26
 242         LDREG PT_GR27(\regs), %r27
 243         LDREG PT_GR28(\regs), %r28
 244         /* r29 points to register save area, and is restored in rest_stack */
 245         /* r30 stack pointer restored in rest_stack */
 246         LDREG PT_GR31(\regs), %r31
 247         .endm
 248
 249         .macro  save_fp         regs
 250         fstd,ma  %fr0, 8(\regs)
 251         fstd,ma  %fr1, 8(\regs)
 252         fstd,ma  %fr2, 8(\regs)
 253         fstd,ma  %fr3, 8(\regs)
 254         fstd,ma  %fr4, 8(\regs)
 255         fstd,ma  %fr5, 8(\regs)
 256         fstd,ma  %fr6, 8(\regs)
 257         fstd,ma  %fr7, 8(\regs)
 258         fstd,ma  %fr8, 8(\regs)
 259         fstd,ma  %fr9, 8(\regs)
 260         fstd,ma %fr10, 8(\regs)
 261         fstd,ma %fr11, 8(\regs)
 262         fstd,ma %fr12, 8(\regs)
 263         fstd,ma %fr13, 8(\regs)
 264         fstd,ma %fr14, 8(\regs)
 265         fstd,ma %fr15, 8(\regs)
 266         fstd,ma %fr16, 8(\regs)
 267         fstd,ma %fr17, 8(\regs)
 268         fstd,ma %fr18, 8(\regs)
 269         fstd,ma %fr19, 8(\regs)
 270         fstd,ma %fr20, 8(\regs)
 271         fstd,ma %fr21, 8(\regs)
 272         fstd,ma %fr22, 8(\regs)
 273         fstd,ma %fr23, 8(\regs)
 274         fstd,ma %fr24, 8(\regs)
 275         fstd,ma %fr25, 8(\regs)
 276         fstd,ma %fr26, 8(\regs)
 277         fstd,ma %fr27, 8(\regs)
 278         fstd,ma %fr28, 8(\regs)
 279         fstd,ma %fr29, 8(\regs)
 280         fstd,ma %fr30, 8(\regs)
 281         fstd    %fr31, 0(\regs)
 282         .endm
 283
 284         .macro  rest_fp         regs
 285         fldd    0(\regs),        %fr31
 286         fldd,mb -8(\regs),       %fr30
 287         fldd,mb -8(\regs),       %fr29
 288         fldd,mb -8(\regs),       %fr28
 289         fldd,mb -8(\regs),       %fr27
 290         fldd,mb -8(\regs),       %fr26
 291         fldd,mb -8(\regs),       %fr25
 292         fldd,mb -8(\regs),       %fr24
 293         fldd,mb -8(\regs),       %fr23
 294         fldd,mb -8(\regs),       %fr22
 295         fldd,mb -8(\regs),       %fr21
 296         fldd,mb -8(\regs),       %fr20
 297         fldd,mb -8(\regs),       %fr19
 298         fldd,mb -8(\regs),       %fr18
 299         fldd,mb -8(\regs),       %fr17
 300         fldd,mb -8(\regs),       %fr16
 301         fldd,mb -8(\regs),       %fr15
 302         fldd,mb -8(\regs),       %fr14
 303         fldd,mb -8(\regs),       %fr13
 304         fldd,mb -8(\regs),       %fr12
 305         fldd,mb -8(\regs),       %fr11
 306         fldd,mb -8(\regs),       %fr10
 307         fldd,mb -8(\regs),       %fr9
 308         fldd,mb -8(\regs),       %fr8
 309         fldd,mb -8(\regs),       %fr7
 310         fldd,mb -8(\regs),       %fr6
 311         fldd,mb -8(\regs),       %fr5
 312         fldd,mb -8(\regs),       %fr4
 313         fldd,mb -8(\regs),       %fr3
 314         fldd,mb -8(\regs),       %fr2
 315         fldd,mb -8(\regs),       %fr1
 316         fldd,mb -8(\regs),       %fr0
 317         .endm
 318
 319         .macro  callee_save_float
 320         fstd,ma  %fr12, 8(%r30)
 321         fstd,ma  %fr13, 8(%r30)
 322         fstd,ma  %fr14, 8(%r30)
 323         fstd,ma  %fr15, 8(%r30)
 324         fstd,ma  %fr16, 8(%r30)
 325         fstd,ma  %fr17, 8(%r30)
 326         fstd,ma  %fr18, 8(%r30)
 327         fstd,ma  %fr19, 8(%r30)
 328         fstd,ma  %fr20, 8(%r30)
 329         fstd,ma  %fr21, 8(%r30)
 330         .endm
 331
 332         .macro  callee_rest_float
 333         fldd,mb -8(%r30),   %fr21
 334         fldd,mb -8(%r30),   %fr20
 335         fldd,mb -8(%r30),   %fr19
 336         fldd,mb -8(%r30),   %fr18
 337         fldd,mb -8(%r30),   %fr17
 338         fldd,mb -8(%r30),   %fr16
 339         fldd,mb -8(%r30),   %fr15
 340         fldd,mb -8(%r30),   %fr14
 341         fldd,mb -8(%r30),   %fr13
 342         fldd,mb -8(%r30),   %fr12
 343         .endm
 344
 345 #ifdef CONFIG_64BIT
 346         .macro  callee_save
 347         std,ma    %r3,   CALLEE_REG_FRAME_SIZE(%r30)
 348         mfctl     %cr27, %r3
 349         std       %r4,  -136(%r30)
 350         std       %r5,  -128(%r30)
 351         std       %r6,  -120(%r30)
 352         std       %r7,  -112(%r30)
 353         std       %r8,  -104(%r30)
 354         std       %r9,   -96(%r30)
 355         std      %r10,   -88(%r30)
 356         std      %r11,   -80(%r30)
 357         std      %r12,   -72(%r30)
 358         std      %r13,   -64(%r30)
 359         std      %r14,   -56(%r30)
 360         std      %r15,   -48(%r30)
 361         std      %r16,   -40(%r30)
 362         std      %r17,   -32(%r30)
 363         std      %r18,   -24(%r30)
 364         std       %r3,   -16(%r30)
 365         .endm
 366
 367         .macro  callee_rest
 368         ldd      -16(%r30),    %r3
 369         ldd      -24(%r30),   %r18
 370         ldd      -32(%r30),   %r17
 371         ldd      -40(%r30),   %r16
 372         ldd      -48(%r30),   %r15
 373         ldd      -56(%r30),   %r14
 374         ldd      -64(%r30),   %r13
 375         ldd      -72(%r30),   %r12
 376         ldd      -80(%r30),   %r11
 377         ldd      -88(%r30),   %r10
 378         ldd      -96(%r30),    %r9
 379         ldd     -104(%r30),    %r8
 380         ldd     -112(%r30),    %r7
 381         ldd     -120(%r30),    %r6
 382         ldd     -128(%r30),    %r5
 383         ldd     -136(%r30),    %r4
 384         mtctl   %r3, %cr27
 385         ldd,mb  -CALLEE_REG_FRAME_SIZE(%r30),    %r3
 386         .endm
 387
 388 #else /* ! CONFIG_64BIT */
 389
 390         .macro  callee_save
 391         stw,ma   %r3,   CALLEE_REG_FRAME_SIZE(%r30)
 392         mfctl    %cr27, %r3
 393         stw      %r4,   -124(%r30)
 394         stw      %r5,   -120(%r30)
 395         stw      %r6,   -116(%r30)
 396         stw      %r7,   -112(%r30)
 397         stw      %r8,   -108(%r30)
 398         stw      %r9,   -104(%r30)
 399         stw      %r10,  -100(%r30)
 400         stw      %r11,   -96(%r30)
 401         stw      %r12,   -92(%r30)
 402         stw      %r13,   -88(%r30)
 403         stw      %r14,   -84(%r30)
 404         stw      %r15,   -80(%r30)
 405         stw      %r16,   -76(%r30)
 406         stw      %r17,   -72(%r30)
 407         stw      %r18,   -68(%r30)
 408         stw       %r3,   -64(%r30)
 409         .endm
 410
 411         .macro  callee_rest
 412         ldw      -64(%r30),    %r3
 413         ldw      -68(%r30),   %r18
 414         ldw      -72(%r30),   %r17
 415         ldw      -76(%r30),   %r16
 416         ldw      -80(%r30),   %r15
 417         ldw      -84(%r30),   %r14
 418         ldw      -88(%r30),   %r13
 419         ldw      -92(%r30),   %r12
 420         ldw      -96(%r30),   %r11
 421         ldw     -100(%r30),   %r10
 422         ldw     -104(%r30),   %r9
 423         ldw     -108(%r30),   %r8
 424         ldw     -112(%r30),   %r7
 425         ldw     -116(%r30),   %r6
 426         ldw     -120(%r30),   %r5
 427         ldw     -124(%r30),   %r4
 428         mtctl   %r3, %cr27
 429         ldw,mb  -CALLEE_REG_FRAME_SIZE(%r30),   %r3
 430         .endm
 431 #endif /* ! CONFIG_64BIT */
 432
 433         .macro  save_specials   regs
 434
 435         SAVE_SP  (%sr0, PT_SR0 (\regs))
 436         SAVE_SP  (%sr1, PT_SR1 (\regs))
 437         SAVE_SP  (%sr2, PT_SR2 (\regs))
 438         SAVE_SP  (%sr3, PT_SR3 (\regs))
 439         SAVE_SP  (%sr4, PT_SR4 (\regs))
 440         SAVE_SP  (%sr5, PT_SR5 (\regs))
 441         SAVE_SP  (%sr6, PT_SR6 (\regs))
 442         SAVE_SP  (%sr7, PT_SR7 (\regs))
 443
 444         SAVE_CR  (%cr17, PT_IASQ0(\regs))
 445         mtctl    %r0,   %cr17
 446         SAVE_CR  (%cr17, PT_IASQ1(\regs))
 447
 448         SAVE_CR  (%cr18, PT_IAOQ0(\regs))
 449         mtctl    %r0,   %cr18
 450         SAVE_CR  (%cr18, PT_IAOQ1(\regs))
 451
 452 #ifdef CONFIG_64BIT
 453         /* cr11 (sar) is a funny one.  5 bits on PA1.1 and 6 bit on PA2.0
 454          * For PA2.0 mtsar or mtctl always write 6 bits, but mfctl only
 455          * reads 5 bits.  Use mfctl,w to read all six bits.  Otherwise
 456          * we lose the 6th bit on a save/restore over interrupt.
 457          */
 458         mfctl,w  %cr11, %r1
 459         STREG    %r1, PT_SAR (\regs)
 460 #else
 461         SAVE_CR  (%cr11, PT_SAR  (\regs))
 462 #endif
 463         SAVE_CR  (%cr19, PT_IIR  (\regs))
 464
 465         /*
 466          * Code immediately following this macro (in intr_save) relies
 467          * on r8 containing ipsw.
 468          */
 469         mfctl    %cr22, %r8
 470         STREG    %r8,   PT_PSW(\regs)
 471         .endm
 472
 473         .macro  rest_specials   regs
 474
 475         REST_SP  (%sr0, PT_SR0 (\regs))
 476         REST_SP  (%sr1, PT_SR1 (\regs))
 477         REST_SP  (%sr2, PT_SR2 (\regs))
 478         REST_SP  (%sr3, PT_SR3 (\regs))
 479         REST_SP  (%sr4, PT_SR4 (\regs))
 480         REST_SP  (%sr5, PT_SR5 (\regs))
 481         REST_SP  (%sr6, PT_SR6 (\regs))
 482         REST_SP  (%sr7, PT_SR7 (\regs))
 483
 484         REST_CR (%cr17, PT_IASQ0(\regs))
 485         REST_CR (%cr17, PT_IASQ1(\regs))
 486
 487         REST_CR (%cr18, PT_IAOQ0(\regs))
 488         REST_CR (%cr18, PT_IAOQ1(\regs))
 489
 490         REST_CR (%cr11, PT_SAR  (\regs))
 491
 492         REST_CR (%cr22, PT_PSW  (\regs))
 493         .endm
 494
 495
 496         /* First step to create a "relied upon translation"
 497          * See PA 2.0 Arch. page F-4 and F-5.
 498          *
 499          * The ssm was originally necessary due to a "PCxT bug".
 500          * But someone decided it needed to be added to the architecture
 501          * and this "feature" went into rev3 of PA-RISC 1.1 Arch Manual.
 502          * It's been carried forward into PA 2.0 Arch as well. :^(
 503          *
 504          * "ssm 0,%r0" is a NOP with side effects (prefetch barrier).
 505          * rsm/ssm prevents the ifetch unit from speculatively fetching
 506          * instructions past this line in the code stream.
 507          * PA 2.0 processor will single step all insn in the same QUAD (4 insn).
 508          */
 509         .macro  pcxt_ssm_bug
 510         rsm     PSW_SM_I,%r0
 511         nop     /* 1 */
 512         nop     /* 2 */
 513         nop     /* 3 */
 514         nop     /* 4 */
 515         nop     /* 5 */
 516         nop     /* 6 */
 517         nop     /* 7 */
 518         .endm
 519
 520 #endif /* __ASSEMBLY__ */
 521 #endif