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OMAP3: X-Loader: Make MMC register macros volatile
[x-load.git] / board / omap3evm / omap3evm.c
blob20b4a883994ce7c58fcf9b575c69585ae469e1f5
1 /*
2 * (C) Copyright 2006
3 * Texas Instruments, <www.ti.com>
4 * Jian Zhang <jzhang@ti.com>
5 * Richard Woodruff <r-woodruff2@ti.com>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25 #include <common.h>
26 #include <command.h>
27 #include <part.h>
28 #include <fat.h>
29 #include <asm/arch/cpu.h>
30 #include <asm/arch/bits.h>
31 #include <asm/arch/mux.h>
32 #include <asm/arch/sys_proto.h>
33 #include <asm/arch/sys_info.h>
34 #include <asm/arch/clocks.h>
35 #include <asm/arch/mem.h>
36
37 /* Used to index into DPLL parameter tables */
38 struct dpll_param {
39 unsigned int m;
40 unsigned int n;
41 unsigned int fsel;
42 unsigned int m2;
43 };
44
45 typedef struct dpll_param dpll_param;
46
47 /* Following functions are exported from lowlevel_init.S */
48 extern dpll_param * get_mpu_dpll_param();
49 extern dpll_param * get_iva_dpll_param();
50 extern dpll_param * get_core_dpll_param();
51 extern dpll_param * get_per_dpll_param();
52
53 #define __raw_readl(a) (*(volatile unsigned int *)(a))
54 #define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v))
55 #define __raw_readw(a) (*(volatile unsigned short *)(a))
56 #define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v))
57
58 /*******************************************************
59 * Routine: delay
60 * Description: spinning delay to use before udelay works
61 ******************************************************/
62 static inline void delay(unsigned long loops)
63 {
64 __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
65 "bne 1b":"=r" (loops):"0"(loops));
66 }
67
68 void udelay (unsigned long usecs) {
69 delay(usecs);
70 }
71
72 /*****************************************
73 * Routine: board_init
74 * Description: Early hardware init.
75 *****************************************/
76 int board_init (void)
77 {
78 return 0;
79 }
80
81 /*************************************************************
82 * get_device_type(): tell if GP/HS/EMU/TST
83 *************************************************************/
84 u32 get_device_type(void)
85 {
86 int mode;
87 mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK);
88 return(mode >>= 8);
89 }
90
91 /************************************************
92 * get_sysboot_value(void) - return SYS_BOOT[4:0]
93 ************************************************/
94 u32 get_sysboot_value(void)
95 {
96 int mode;
97 mode = __raw_readl(CONTROL_STATUS) & (SYSBOOT_MASK);
98 return mode;
99 }
100 /*************************************************************
101 * Routine: get_mem_type(void) - returns the kind of memory connected
102 * to GPMC that we are trying to boot form. Uses SYS BOOT settings.
103 *************************************************************/
104 u32 get_mem_type(void)
105 {
106 u32 mem_type = get_sysboot_value();
107 switch (mem_type){
108 case 0:
109 case 2:
110 case 4:
111 case 16:
112 case 22: return GPMC_ONENAND;
113
114 case 1:
115 case 12:
116 case 15:
117 case 21:
118 case 27: return GPMC_NAND;
119
120 case 3:
121 case 6: return MMC_ONENAND;
122
123 case 8:
124 case 11:
125 case 14:
126 case 20:
127 case 26: return GPMC_MDOC;
128
129 case 17:
130 case 18:
131 case 24: return MMC_NAND;
132
133 case 7:
134 case 10:
135 case 13:
136 case 19:
137 case 25:
138 default: return GPMC_NOR;
139 }
140 }
141
142 /******************************************
143 * get_cpu_rev(void) - extract version info
144 ******************************************/
145 u32 get_cpu_rev(void)
146 {
147 u32 cpuid=0;
148 /* On ES1.0 the IDCODE register is not exposed on L4
149 * so using CPU ID to differentiate
150 * between ES2.0 and ES1.0.
151 */
152 __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r" (cpuid));
153 if((cpuid & 0xf) == 0x0)
154 return CPU_3430_ES1;
155 else
156 return CPU_3430_ES2;
157
158 }
159
160 /******************************************
161 * cpu_is_3410(void) - returns true for 3410
162 ******************************************/
163 u32 cpu_is_3410(void)
164 {
165 int status;
166 if(get_cpu_rev() < CPU_3430_ES2) {
167 return 0;
168 } else {
169 /* read scalability status and return 1 for 3410*/
170 status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS);
171 /* Check whether MPU frequency is set to 266 MHz which
172 * is nominal for 3410. If yes return true else false
173 */
174 if (((status >> 8) & 0x3) == 0x2)
175 return 1;
176 else
177 return 0;
178 }
179 }
180
181 /*****************************************************************
182 * sr32 - clear & set a value in a bit range for a 32 bit address
183 *****************************************************************/
184 void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value)
185 {
186 u32 tmp, msk = 0;
187 msk = 1 << num_bits;
188 --msk;
189 tmp = __raw_readl(addr) & ~(msk << start_bit);
190 tmp |= value << start_bit;
191 __raw_writel(tmp, addr);
192 }
193
194 /*********************************************************************
195 * wait_on_value() - common routine to allow waiting for changes in
196 * volatile regs.
197 *********************************************************************/
198 u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
199 {
200 u32 i = 0, val;
201 do {
202 ++i;
203 val = __raw_readl(read_addr) & read_bit_mask;
204 if (val == match_value)
205 return (1);
206 if (i == bound)
207 return (0);
208 } while (1);
209 }
210
211 #ifdef CFG_3430SDRAM_DDR
212 /*********************************************************************
213 * config_3430sdram_ddr() - Init DDR on 3430SDP dev board.
214 *********************************************************************/
215 void config_3430sdram_ddr(void)
216 {
217 /* reset sdrc controller */
218 __raw_writel(SOFTRESET, SDRC_SYSCONFIG);
219 wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);
220 __raw_writel(0, SDRC_SYSCONFIG);
221
222 /* setup sdrc to ball mux */
223 __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING);
224
225 /* set mdcfg */
226 __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
227
228 /* set timing */
229 if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)){
230 __raw_writel(INFINEON_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
231 __raw_writel(INFINEON_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
232 }
233 if ((get_mem_type() == GPMC_NAND) ||(get_mem_type() == MMC_NAND)){
234 __raw_writel(MICRON_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
235 __raw_writel(MICRON_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
236 }
237
238 __raw_writel(SDP_SDRC_RFR_CTRL, SDRC_RFR_CTRL);
239 __raw_writel(SDP_SDRC_POWER_POP, SDRC_POWER);
240
241 /* init sequence for mDDR/mSDR using manual commands (DDR is different) */
242 __raw_writel(CMD_NOP, SDRC_MANUAL_0);
243 delay(5000);
244 __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
245 __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
246 __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
247
248 /* set mr0 */
249 __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0);
250
251 /* set up dll */
252 __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL);
253 delay(0x2000); /* give time to lock */
254
255 }
256 #endif // CFG_3430SDRAM_DDR
257
258 /*************************************************************
259 * get_sys_clk_speed - determine reference oscillator speed
260 * based on known 32kHz clock and gptimer.
261 *************************************************************/
262 u32 get_osc_clk_speed(void)
263 {
264 u32 start, cstart, cend, cdiff, val;
265
266 val = __raw_readl(PRM_CLKSRC_CTRL);
267 /* If SYS_CLK is being divided by 2, remove for now */
268 val = (val & (~BIT7)) | BIT6;
269 __raw_writel(val, PRM_CLKSRC_CTRL);
270
271 /* enable timer2 */
272 val = __raw_readl(CM_CLKSEL_WKUP) | BIT0;
273 __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */
274
275 /* Enable I and F Clocks for GPT1 */
276 val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2;
277 __raw_writel(val, CM_ICLKEN_WKUP);
278 val = __raw_readl(CM_FCLKEN_WKUP) | BIT0;
279 __raw_writel(val, CM_FCLKEN_WKUP);
280
281 __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */
282 __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */
283 /* enable 32kHz source *//* enabled out of reset */
284 /* determine sys_clk via gauging */
285
286 start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */
287 while (__raw_readl(S32K_CR) < start); /* dead loop till start time */
288 cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */
289 while (__raw_readl(S32K_CR) < (start + 20)); /* wait for 40 cycles */
290 cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */
291 cdiff = cend - cstart; /* get elapsed ticks */
292
293 /* based on number of ticks assign speed */
294 if (cdiff > 19000)
295 return (S38_4M);
296 else if (cdiff > 15200)
297 return (S26M);
298 else if (cdiff > 13000)
299 return (S24M);
300 else if (cdiff > 9000)
301 return (S19_2M);
302 else if (cdiff > 7600)
303 return (S13M);
304 else
305 return (S12M);
306 }
307
308 /******************************************************************************
309 * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on
310 * -- input oscillator clock frequency.
311 *
312 *****************************************************************************/
313 void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
314 {
315 if(osc_clk == S38_4M)
316 *sys_clkin_sel= 4;
317 else if(osc_clk == S26M)
318 *sys_clkin_sel = 3;
319 else if(osc_clk == S19_2M)
320 *sys_clkin_sel = 2;
321 else if(osc_clk == S13M)
322 *sys_clkin_sel = 1;
323 else if(osc_clk == S12M)
324 *sys_clkin_sel = 0;
325 }
326
327 /******************************************************************************
328 * prcm_init() - inits clocks for PRCM as defined in clocks.h
329 * -- called from SRAM, or Flash (using temp SRAM stack).
330 *****************************************************************************/
331 void prcm_init(void)
332 {
333 u32 osc_clk=0, sys_clkin_sel;
334 dpll_param *dpll_param_p;
335 u32 clk_index, sil_index;
336
337 /* Gauge the input clock speed and find out the sys_clkin_sel
338 * value corresponding to the input clock.
339 */
340 osc_clk = get_osc_clk_speed();
341 get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
342
343 sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */
344
345 /* If the input clock is greater than 19.2M always divide/2 */
346 if(sys_clkin_sel > 2) {
347 sr32(PRM_CLKSRC_CTRL, 6, 2, 2);/* input clock divider */
348 clk_index = sys_clkin_sel/2;
349 } else {
350 sr32(PRM_CLKSRC_CTRL, 6, 2, 1);/* input clock divider */
351 clk_index = sys_clkin_sel;
352 }
353
354 /* The DPLL tables are defined according to sysclk value and
355 * silicon revision. The clk_index value will be used to get
356 * the values for that input sysclk from the DPLL param table
357 * and sil_index will get the values for that SysClk for the
358 * appropriate silicon rev.
359 */
360 sil_index = get_cpu_rev() - 1;
361
362 /* Unlock MPU DPLL (slows things down, and needed later) */
363 sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS);
364 wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY);
365
366 /* Getting the base address of Core DPLL param table*/
367 dpll_param_p = (dpll_param *)get_core_dpll_param();
368 /* Moving it to the right sysclk and ES rev base */
369 dpll_param_p = dpll_param_p + 2*clk_index + sil_index;
370 /* CORE DPLL */
371 /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */
372 sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
373 wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);
374 sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */
375 sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */
376 sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */
377 sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */
378 sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */
379 sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */
380 sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */
381 sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */
382 sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */
383 sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */
384 sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */
385 sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */
386 sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */
387 wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY);
388
389 /* Getting the base address to PER DPLL param table*/
390 dpll_param_p = (dpll_param *)get_per_dpll_param();
391 /* Moving it to the right sysclk base */
392 dpll_param_p = dpll_param_p + clk_index;
393 /* PER DPLL */
394 sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP);
395 wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY);
396 sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */
397 sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */
398 sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */
399 sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */
400 sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */
401 sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */
402 sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */
403 sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel);/* FREQSEL */
404 sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */
405 wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY);
406
407 /* Getting the base address to MPU DPLL param table*/
408 dpll_param_p = (dpll_param *)get_mpu_dpll_param();
409 /* Moving it to the right sysclk and ES rev base */
410 dpll_param_p = dpll_param_p + 2*clk_index + sil_index;
411 /* MPU DPLL (unlocked already) */
412 sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */
413 sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */
414 sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */
415 sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */
416 sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */
417 wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY);
418
419 /* Getting the base address to IVA DPLL param table*/
420 dpll_param_p = (dpll_param *)get_iva_dpll_param();
421 /* Moving it to the right sysclk and ES rev base */
422 dpll_param_p = dpll_param_p + 2*clk_index + sil_index;
423 /* IVA DPLL (set to 12*20=240MHz) */
424 sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP);
425 wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY);
426 sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */
427 sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */
428 sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */
429 sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */
430 sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */
431 wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY);
432
433 /* Set up GPTimers to sys_clk source only */
434 sr32(CM_CLKSEL_PER, 0, 8, 0xff);
435 sr32(CM_CLKSEL_WKUP, 0, 1, 1);
436
437 delay(5000);
438 }
439
440 /*****************************************
441 * Routine: secure_unlock
442 * Description: Setup security registers for access
443 * (GP Device only)
444 *****************************************/
445 void secure_unlock(void)
446 {
447 /* Permission values for registers -Full fledged permissions to all */
448 #define UNLOCK_1 0xFFFFFFFF
449 #define UNLOCK_2 0x00000000
450 #define UNLOCK_3 0x0000FFFF
451 /* Protection Module Register Target APE (PM_RT)*/
452 __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1);
453 __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0);
454 __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0);
455 __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1);
456
457 __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0);
458 __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0);
459 __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0);
460
461 __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0);
462 __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0);
463 __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0);
464 __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2);
465
466 /* IVA Changes */
467 __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0);
468 __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0);
469 __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0);
470
471 __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */
472 }
473
474 /**********************************************************
475 * Routine: try_unlock_sram()
476 * Description: If chip is GP type, unlock the SRAM for
477 * general use.
478 ***********************************************************/
479 void try_unlock_memory(void)
480 {
481 int mode;
482
483 /* if GP device unlock device SRAM for general use */
484 /* secure code breaks for Secure/Emulation device - HS/E/T*/
485 mode = get_device_type();
486 if (mode == GP_DEVICE) {
487 secure_unlock();
488 }
489 return;
490 }
491
492 /**********************************************************
493 * Routine: s_init
494 * Description: Does early system init of muxing and clocks.
495 * - Called at time when only stack is available.
496 **********************************************************/
497
498 void s_init(void)
499 {
500 watchdog_init();
501 #ifdef CONFIG_3430_AS_3410
502 /* setup the scalability control register for
503 * 3430 to work in 3410 mode
504 */
505 __raw_writel(0x5ABF,CONTROL_SCALABLE_OMAP_OCP);
506 #endif
507 try_unlock_memory();
508 set_muxconf_regs();
509 delay(100);
510 prcm_init();
511 per_clocks_enable();
512 config_3430sdram_ddr();
513 }
514
515 /*******************************************************
516 * Routine: misc_init_r
517 * Description: Init ethernet (done here so udelay works)
518 ********************************************************/
519 int misc_init_r (void)
520 {
521 return(0);
522 }
523
524 /******************************************************
525 * Routine: wait_for_command_complete
526 * Description: Wait for posting to finish on watchdog
527 ******************************************************/
528 void wait_for_command_complete(unsigned int wd_base)
529 {
530 int pending = 1;
531 do {
532 pending = __raw_readl(wd_base + WWPS);
533 } while (pending);
534 }
535
536 /****************************************
537 * Routine: watchdog_init
538 * Description: Shut down watch dogs
539 *****************************************/
540 void watchdog_init(void)
541 {
542 /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
543 * either taken care of by ROM (HS/EMU) or not accessible (GP).
544 * We need to take care of WD2-MPU or take a PRCM reset. WD3
545 * should not be running and does not generate a PRCM reset.
546 */
547 sr32(CM_FCLKEN_WKUP, 5, 1, 1);
548 sr32(CM_ICLKEN_WKUP, 5, 1, 1);
549 wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */
550
551 __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);
552 wait_for_command_complete(WD2_BASE);
553 __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
554 }
555
556 /**********************************************
557 * Routine: dram_init
558 * Description: sets uboots idea of sdram size
559 **********************************************/
560 int dram_init (void)
561 {
562 return 0;
563 }
564
565 /*****************************************************************
566 * Routine: peripheral_enable
567 * Description: Enable the clks & power for perifs (GPT2, UART1,...)
568 ******************************************************************/
569 void per_clocks_enable(void)
570 {
571 /* Enable GP2 timer. */
572 sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */
573 sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */
574 sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */
575
576 #ifdef CFG_NS16550
577 /* Enable UART1 clocks */
578 sr32(CM_FCLKEN1_CORE, 13, 1, 0x1);
579 sr32(CM_ICLKEN1_CORE, 13, 1, 0x1);
580 #endif
581 delay(1000);
582 }
583
584 /* Set MUX for UART, GPMC, SDRC, GPIO */
585
586 #define MUX_VAL(OFFSET,VALUE)\
587 __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
588
589 #define CP(x) (CONTROL_PADCONF_##x)
590 /*
591 * IEN - Input Enable
592 * IDIS - Input Disable
593 * PTD - Pull type Down
594 * PTU - Pull type Up
595 * DIS - Pull type selection is inactive
596 * EN - Pull type selection is active
597 * M0 - Mode 0
598 * The commented string gives the final mux configuration for that pin
599 */
600 #define MUX_DEFAULT()\
601 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
602 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
603 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
604 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
605 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
606 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
607 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
608 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
609 MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
610 MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
611 MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
612 MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
613 MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
614 MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
615 MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
616 MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
617 MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
618 MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
619 MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
620 MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
621 MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
622 MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
623 MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
624 MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
625 MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
626 MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
627 MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
628 MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
629 MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
630 MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
631 MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
632 MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
633 MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
634 MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
635 MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
636 MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
637 MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
638 MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
639 MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
640 MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
641 MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
642 MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
643 MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
644 MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
645 MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
646 MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
647 MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
648 MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
649 MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
650 MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
651 MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
652 MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
653 MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
654 MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
655 MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
656 MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
657 MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
658 MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
659 MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
660 MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
661 MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
662 MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
663 MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
664 MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
665 MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
666 MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
667 MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
668 MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
669 MUX_VAL(CP(GPMC_nCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\
670 MUX_VAL(CP(GPMC_nCS6), (IDIS | PTU | EN | M0)) /*GPMC_nCS6*/\
671 MUX_VAL(CP(GPMC_nCS7), (IDIS | PTU | EN | M0)) /*GPMC_nCS7*/\
672 MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
673 MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
674 MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
675 MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
676 MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
677 MUX_VAL(CP(GPMC_nBE1), (IDIS | PTD | DIS | M4)) /*GPIO_61*/\
678 MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
679 MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
680 MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
681 MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
682 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) /*GPIO_65*/\
683 MUX_VAL(CP(DSS_DATA18), (IEN | PTD | DIS | M4)) /*GPIO_88*/\
684 MUX_VAL(CP(DSS_DATA19), (IEN | PTD | DIS | M4)) /*GPIO_89*/\
685 MUX_VAL(CP(DSS_DATA20), (IEN | PTD | DIS | M4)) /*GPIO_90*/\
686 MUX_VAL(CP(DSS_DATA21), (IEN | PTD | DIS | M4)) /*GPIO_91*/\
687 MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
688 MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
689 MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\
690 MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\
691 MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
692 MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\
693 MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
694 MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 */\
695 MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
696 MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 */\
697 MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 */\
698 MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 */\
699 MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 */\
700 MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8 */\
701 MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
702 MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\
703 MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\
704 MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\
705 MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\
706 MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\
707 MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\
708 MUX_VAL(CP(ETK_CLK), (IEN | PTD | DIS | M4)) /*GPIO_12*/\
709 MUX_VAL(CP(ETK_CTL), (IEN | PTD | DIS | M4)) /*GPIO_13*/\
710 MUX_VAL(CP(ETK_D0 ), (IEN | PTD | DIS | M4)) /*GPIO_14*/\
711 MUX_VAL(CP(ETK_D1 ), (IEN | PTD | DIS | M4)) /*GPIO_15*/\
712 MUX_VAL(CP(ETK_D2 ), (IEN | PTD | DIS | M4)) /*GPIO_16*/\
713 MUX_VAL(CP(ETK_D10), (IEN | PTD | DIS | M4)) /*GPIO_24*/\
714 MUX_VAL(CP(ETK_D11), (IEN | PTD | DIS | M4)) /*GPIO_25*/\
715 MUX_VAL(CP(ETK_D12), (IEN | PTD | DIS | M4)) /*GPIO_26*/\
716 MUX_VAL(CP(ETK_D13), (IEN | PTD | DIS | M4)) /*GPIO_27*/\
717 MUX_VAL(CP(ETK_D14), (IEN | PTD | DIS | M4)) /*GPIO_28*/\
718 MUX_VAL(CP(ETK_D15), (IEN | PTD | DIS | M4)) /*GPIO_29*/
719
720 /**********************************************************
721 * Routine: set_muxconf_regs
722 * Description: Setting up the configuration Mux registers
723 * specific to the hardware. Many pins need
724 * to be moved from protect to primary mode.
725 *********************************************************/
726 void set_muxconf_regs(void)
727 {
728 MUX_DEFAULT();
729 }
730
731 /**********************************************************
732 * Routine: nand+_init
733 * Description: Set up nand for nand and jffs2 commands
734 *********************************************************/
735
736 int nand_init(void)
737 {
738 /* global settings */
739 __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */
740 __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */
741 __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */
742
743 /* Set the GPMC Vals . For NAND boot on 3430SDP, NAND is mapped at CS0
744 * , NOR at CS1 and MPDB at CS3. And oneNAND boot, we map oneNAND at CS0.
745 * We configure only GPMC CS0 with required values. Configiring other devices
746 * at other CS in done in u-boot anyway. So we don't have to bother doing it here.
747 */
748 __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0);
749 delay(1000);
750
751 if ((get_mem_type() == GPMC_NAND) || (get_mem_type() == MMC_NAND)){
752 __raw_writel( M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
753 __raw_writel( M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
754 __raw_writel( M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
755 __raw_writel( M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
756 __raw_writel( M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
757 __raw_writel( M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
758
759 /* Enable the GPMC Mapping */
760 __raw_writel(( ((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
761 ((NAND_BASE_ADR>>24) & 0x3F) |
762 (1<<6) ), (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
763 delay(2000);
764
765 if (nand_chip()){
766 #ifdef CFG_PRINTF
767 printf("Unsupported Chip!\n");
768 #endif
769 return 1;
770 }
771
772 }
773
774 if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)){
775 __raw_writel( ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
776 __raw_writel( ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
777 __raw_writel( ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
778 __raw_writel( ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
779 __raw_writel( ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
780 __raw_writel( ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
781
782 /* Enable the GPMC Mapping */
783 __raw_writel(( ((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
784 ((ONENAND_BASE>>24) & 0x3F) |
785 (1<<6) ), (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
786 delay(2000);
787
788 if (onenand_chip()){
789 #ifdef CFG_PRINTF
790 printf("OneNAND Unsupported !\n");
791 #endif
792 return 1;
793 }
794 }
795 return 0;
796 }
797
798 /* optionally do something like blinking LED */
799 void board_hang (void)
800 { while (0) {};}
801
802 /******************************************************************************
803 * Dummy function to handle errors for EABI incompatibility
804 *****************************************************************************/
805 void raise(void)
806 {
807 }
808
809 /******************************************************************************
810 * Dummy function to handle errors for EABI incompatibility
811 *****************************************************************************/
812 void abort(void)
813 {
814 }
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