From c0bc8cc7005abad65be07b0c64901bcfaff71971 Mon Sep 17 00:00:00 2001
From: Steve Sakoman <steve@sakoman.com>
Date: Wed, 30 Jul 2008 23:22:24 -0700
Subject: [PATCH] Add support for beagle and overo

Signed-off-by: Steve Sakoman <steve@sakoman.com>
---
 Makefile                                           |   8 +-
 {drivers => board/omap3530beagle}/Makefile         |  53 +--
 board/omap3530beagle/config.mk                     |  20 +
 .../omap3evm.c => omap3530beagle/omap3530beagle.c} | 470 ++++++++++++---------
 board/omap3530beagle/platform.S                    | 360 ++++++++++++++++
 board/omap3530beagle/platform.S_old                | 435 +++++++++++++++++++
 board/omap3530beagle/x-load.lds                    |  54 +++
 board/omap3evm/omap3evm.c                          |   2 -
 {drivers => board/overo}/Makefile                  |  53 +--
 board/overo/config.mk                              |  20 +
 board/{omap3evm/omap3evm.c => overo/overo.c}       | 344 ++++++++-------
 board/overo/platform.S                             | 435 +++++++++++++++++++
 board/overo/x-load.lds                             |  54 +++
 drivers/Makefile                                   |   8 +
 include/asm/arch-omap3/omap3430.h                  |   8 +
 include/configs/omap3530beagle.h                   | 200 +++++++++
 include/configs/overo.h                            | 200 +++++++++
 17 files changed, 2272 insertions(+), 452 deletions(-)
 copy {drivers => board/omap3530beagle}/Makefile (57%)
 create mode 100644 board/omap3530beagle/config.mk
 copy board/{omap3evm/omap3evm.c => omap3530beagle/omap3530beagle.c} (73%)
 mode change 100755 => 100644
 create mode 100644 board/omap3530beagle/platform.S
 create mode 100644 board/omap3530beagle/platform.S_old
 create mode 100644 board/omap3530beagle/x-load.lds
 copy {drivers => board/overo}/Makefile (57%)
 mode change 100644 => 100755
 create mode 100755 board/overo/config.mk
 copy board/{omap3evm/omap3evm.c => overo/overo.c} (82%)
 create mode 100755 board/overo/platform.S
 create mode 100755 board/overo/x-load.lds
 create mode 100644 include/configs/omap3530beagle.h
 create mode 100755 include/configs/overo.h

diff --git a/Makefile b/Makefile
index 56c6dd7..ea93acb 100644
--- a/Makefile
+++ b/Makefile
@@ -147,9 +147,15 @@ omap3430labrador_config :    unconfig
 	@./mkconfig $(@:_config=) arm omap3 omap3430labrador
 
 omap3evm_config :	unconfig
-
 	@./mkconfig $(@:_config=) arm omap3 omap3evm
 
+overo_config :	unconfig
+	@./mkconfig $(@:_config=) arm omap3 overo
+
+omap3530beagle_config :    unconfig
+
+	@./mkconfig $(@:_config=) arm omap3 omap3530beagle
+
 #########################################################################
 
 clean:
diff --git a/drivers/Makefile b/board/omap3530beagle/Makefile
similarity index 57%
copy from drivers/Makefile
copy to board/omap3530beagle/Makefile
index 2352f42..2dab831 100644
--- a/drivers/Makefile
+++ b/board/omap3530beagle/Makefile
@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2000
+# (C) Copyright 2000, 2001, 2002
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -23,52 +23,25 @@
 
 include $(TOPDIR)/config.mk
 
-# CFLAGS += -DET_DEBUG -DDEBUG
+LIB	= lib$(BOARD).a
 
-LIB	= libdrivers.a
-OBJS	= serial.o ns16550.o onenand.o
+OBJS	:= omap3530beagle.o 
+SOBJS	:= platform.o
 
-ifeq ($(BOARD), omap3430sdp)
-OBJS 	+= k9f1g08r0a.o
-endif
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
 
-ifeq ($(BOARD), omap3430labrador)
-OBJS 	+= k9f1g08r0a.o
-endif
+clean:
+	rm -f $(SOBJS) $(OBJS)
 
-ifeq ($(BOARD), omap3evm)
-OBJS 	+= k9f1g08r0a.o
-endif
-
-ifeq ($(BOARD), omap2420h4) 
-OBJS 	+= k9k1216.o
-endif
-
-ifeq ($(BOARD), omap2430sdp)
-OBJS    += k9k1216.o
-endif
-
-ifeq ($(BOARD), omap1710h3)
-OBJS    += k9f5616.o
-endif
-
-
-## Disabled for now:
-##	  cs8900.o ct69000.o dataflash.o dc2114x.o ds1722.o \
-##	  lan91c96.o mw_eeprom.o natsemi.o \
-##	  smc91111.o smiLynxEM.o spi_eeprom.o sym53c8xx.o \
-##
-
-all:	$(LIB)
-
-$(LIB):	$(OBJS)
-	$(AR) crv $@ $(OBJS)
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
 
 #########################################################################
 
-.depend:	Makefile $(OBJS:.o=.c)
-		$(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
 
-sinclude .depend
+-include .depend
 
 #########################################################################
diff --git a/board/omap3530beagle/config.mk b/board/omap3530beagle/config.mk
new file mode 100644
index 0000000..f271b14
--- /dev/null
+++ b/board/omap3530beagle/config.mk
@@ -0,0 +1,20 @@
+#
+# (C) Copyright 2006
+# Texas Instruments, <www.ti.com>
+#
+# Beagle board uses TI OMAP3530 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# Beagle has 1 bank of 128MB mPOP-SDRAM on CS0
+# Physical Address:
+# 8000'0000 (bank0)
+
+# For use if you want X-Loader to relocate from SRAM to DDR
+#TEXT_BASE = 0x80e80000
+
+# For XIP in 64K of SRAM or debug (GP device has it all availabe)
+# SRAM 40200000-4020FFFF base
+# initial stack at 0x4020fffc used in s_init (below xloader).
+# The run time stack is (above xloader, 2k below)
+# If any globals exist there needs to be room for them also
+TEXT_BASE = 0x40200800
diff --git a/board/omap3evm/omap3evm.c b/board/omap3530beagle/omap3530beagle.c
old mode 100755
new mode 100644
similarity index 73%
copy from board/omap3evm/omap3evm.c
copy to board/omap3530beagle/omap3530beagle.c
index f94518e..a3a8d80
--- a/board/omap3evm/omap3evm.c
+++ b/board/omap3530beagle/omap3530beagle.c
@@ -22,6 +22,7 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
+
 #include <common.h>
 #include <command.h>
 #include <part.h>
@@ -36,26 +37,24 @@
 
 /* Used to index into DPLL parameter tables */
 struct dpll_param {
-        unsigned int m;
-        unsigned int n;
-        unsigned int fsel;
-        unsigned int m2;
+	unsigned int m;
+	unsigned int n;
+	unsigned int fsel;
+	unsigned int m2;
 };
 
 typedef struct dpll_param dpll_param;
 
-#define MAX_SIL_INDEX	3
-
 /* Following functions are exported from lowlevel_init.S */
-extern dpll_param * get_mpu_dpll_param();
-extern dpll_param * get_iva_dpll_param();
-extern dpll_param * get_core_dpll_param();
-extern dpll_param * get_per_dpll_param();
+extern dpll_param *get_mpu_dpll_param();
+extern dpll_param *get_iva_dpll_param();
+extern dpll_param *get_core_dpll_param();
+extern dpll_param *get_per_dpll_param();
 
-#define __raw_readl(a)    (*(volatile unsigned int *)(a))
-#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v))
-#define __raw_readw(a)    (*(volatile unsigned short *)(a))
-#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v))
+#define __raw_readl(a)		(*(volatile unsigned int *)(a))
+#define __raw_writel(v, a)	(*(volatile unsigned int *)(a) = (v))
+#define __raw_readw(a)		(*(volatile unsigned short *)(a))
+#define __raw_writew(v, a)	(*(volatile unsigned short *)(a) = (v))
 
 /*******************************************************
  * Routine: delay
@@ -71,7 +70,7 @@ static inline void delay(unsigned long loops)
  * Routine: board_init
  * Description: Early hardware init.
  *****************************************/
-int board_init (void)
+int board_init(void)
 {
 	return 0;
 }
@@ -81,9 +80,9 @@ int board_init (void)
  *************************************************************/
 u32 get_device_type(void)
 {
-        int mode;
-        mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK);
-        return(mode >>= 8);
+	int mode;
+	mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK);
+	return mode >>= 8;
 }
 
 /************************************************
@@ -91,50 +90,57 @@ u32 get_device_type(void)
  ************************************************/
 u32 get_sysboot_value(void)
 {
-        int mode;
-        mode = __raw_readl(CONTROL_STATUS) & (SYSBOOT_MASK);
-        return mode;
+	int mode;
+	mode = __raw_readl(CONTROL_STATUS) & (SYSBOOT_MASK);
+	return mode;
 }
+
 /*************************************************************
  * Routine: get_mem_type(void) - returns the kind of memory connected
  * to GPMC that we are trying to boot form. Uses SYS BOOT settings.
  *************************************************************/
 u32 get_mem_type(void)
 {
-        u32   mem_type = get_sysboot_value();
-        switch (mem_type){
-            case 0:
-            case 2:
-            case 4:
-            case 16:
-            case 22:    return GPMC_ONENAND;
-
-            case 1:
-            case 12:
-            case 15:
-            case 21:
-            case 27:    return GPMC_NAND;
-
-            case 3:
-            case 6:     return MMC_ONENAND;
-
-            case 8:
-            case 11:
-            case 14:
-            case 20:
-            case 26:    return GPMC_MDOC;
-
-            case 17:
-            case 18:
-            case 24:	return MMC_NAND;
-
-            case 7:
-            case 10:
-            case 13:
-            case 19:
-            case 25:
-            default:    return GPMC_NOR;
-        }
+	u32   mem_type = get_sysboot_value();
+	switch (mem_type) {
+	case 0:
+	case 2:
+	case 4:
+	case 16:
+	case 22:
+		return GPMC_ONENAND;
+
+	case 1:
+	case 12:
+	case 15:
+	case 21:
+	case 27:
+		return GPMC_NAND;
+
+	case 3:
+	case 6:
+		return MMC_ONENAND;
+
+	case 8:
+	case 11:
+	case 14:
+	case 20:
+	case 26:
+		return GPMC_MDOC;
+
+	case 17:
+	case 18:
+	case 24:
+		return MMC_NAND;
+
+	case 7:
+	case 10:
+	case 13:
+	case 19:
+	case 25:
+	default:
+		return GPMC_NOR;
+	}
 }
 
 /******************************************
@@ -142,13 +148,13 @@ u32 get_mem_type(void)
  ******************************************/
 u32 get_cpu_rev(void)
 {
-	u32 cpuid=0;
+	u32 cpuid = 0;
 	/* On ES1.0 the IDCODE register is not exposed on L4
 	 * so using CPU ID to differentiate
 	 * between ES2.0 and ES1.0.
 	 */
 	__asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r" (cpuid));
-	if((cpuid  & 0xf) == 0x0)
+	if ((cpuid  & 0xf) == 0x0)
 		return CPU_3430_ES1;
 	else
 		return CPU_3430_ES2;
@@ -161,7 +167,7 @@ u32 get_cpu_rev(void)
 u32 cpu_is_3410(void)
 {
 	int status;
-	if(get_cpu_rev() < CPU_3430_ES2) {
+	if (get_cpu_rev() < CPU_3430_ES2) {
 		return 0;
 	} else {
 		/* read scalability status and return 1 for 3410*/
@@ -185,7 +191,7 @@ void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value)
 	msk = 1 << num_bits;
 	--msk;
 	tmp = __raw_readl(addr) & ~(msk << start_bit);
-	tmp |=  value << start_bit;
+	tmp |= value << start_bit;
 	__raw_writel(tmp, addr);
 }
 
@@ -200,10 +206,10 @@ u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
 		++i;
 		val = __raw_readl(read_addr) & read_bit_mask;
 		if (val == match_value)
-			return (1);
+			return 1;
 		if (i == bound)
-			return (0);
-	} while (1);
+			return 0;
+	} while 1;
 }
 
 #ifdef CFG_3430SDRAM_DDR
@@ -224,13 +230,13 @@ void config_3430sdram_ddr(void)
 	__raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
 
 	/* set timing */
-	if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)){
-        	__raw_writel(INFINEON_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
-        	__raw_writel(INFINEON_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
+	if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)) {
+		__raw_writel(INFINEON_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
+		__raw_writel(INFINEON_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
 	}
-	if ((get_mem_type() == GPMC_NAND) ||(get_mem_type() == MMC_NAND)){
-        	__raw_writel(MICRON_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
-        	__raw_writel(MICRON_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
+	if ((get_mem_type() == GPMC_NAND) || (get_mem_type() == MMC_NAND)) {
+		__raw_writel(MICRON_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
+		__raw_writel(MICRON_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
 	}
 
 	__raw_writel(SDP_SDRC_RFR_CTRL, SDRC_RFR_CTRL);
@@ -251,7 +257,7 @@ void config_3430sdram_ddr(void)
 	delay(0x2000);	/* give time to lock */
 
 }
-#endif // CFG_3430SDRAM_DDR
+#endif /* CFG_3430SDRAM_DDR */
 
 /*************************************************************
  * get_sys_clk_speed - determine reference oscillator speed
@@ -276,31 +282,32 @@ u32 get_osc_clk_speed(void)
 	val = __raw_readl(CM_FCLKEN_WKUP) | BIT0;
 	__raw_writel(val, CM_FCLKEN_WKUP);
 
-	__raw_writel(0, OMAP34XX_GPT1 + TLDR);	/* start counting at 0 */
-	__raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR);     /* enable clock */
-	/* enable 32kHz source *//* enabled out of reset */
+	__raw_writel(0, OMAP34XX_GPT1 + TLDR);		/* start counting at 0 */
+	__raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR);	/* enable clock */
+	/* enable 32kHz source */
+	/* enabled out of reset */
 	/* determine sys_clk via gauging */
 
 	start = 20 + __raw_readl(S32K_CR);	/* start time in 20 cycles */
-	while (__raw_readl(S32K_CR) < start);	/* dead loop till start time */
+	while (__raw_readl(S32K_CR) < start) ;	/* dead loop till start time */
 	cstart = __raw_readl(OMAP34XX_GPT1 + TCRR);	/* get start sys_clk count */
-	while (__raw_readl(S32K_CR) < (start + 20));	/* wait for 40 cycles */
+	while (__raw_readl(S32K_CR) < (start + 20)) ;	/* wait for 40 cycles */
 	cend = __raw_readl(OMAP34XX_GPT1 + TCRR);	/* get end sys_clk count */
-	cdiff = cend - cstart;				/* get elapsed ticks */
+	cdiff = cend - cstart;	/* get elapsed ticks */
 
 	/* based on number of ticks assign speed */
 	if (cdiff > 19000)
-		return (S38_4M);
+		return S38_4M;
 	else if (cdiff > 15200)
-		return (S26M);
+		return S26M;
 	else if (cdiff > 13000)
-		return (S24M);
+		return S24M;
 	else if (cdiff > 9000)
-		return (S19_2M);
+		return S19_2M;
 	else if (cdiff > 7600)
-		return (S13M);
+		return S13M;
 	else
-		return (S12M);
+		return S12M;
 }
 
 /******************************************************************************
@@ -310,15 +317,15 @@ u32 get_osc_clk_speed(void)
  *****************************************************************************/
 void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
 {
-	if(osc_clk == S38_4M)
-		*sys_clkin_sel=  4;
-	else if(osc_clk == S26M)
+	if (osc_clk == S38_4M)
+		*sys_clkin_sel = 4;
+	else if (osc_clk == S26M)
 		*sys_clkin_sel = 3;
-	else if(osc_clk == S19_2M)
+	else if (osc_clk == S19_2M)
 		*sys_clkin_sel = 2;
-	else if(osc_clk == S13M)
+	else if (osc_clk == S13M)
 		*sys_clkin_sel = 1;
-	else if(osc_clk == S12M)
+	else if (osc_clk == S12M)
 		*sys_clkin_sel = 0;
 }
 
@@ -328,7 +335,7 @@ void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
  *****************************************************************************/
 void prcm_init(void)
 {
-	u32 osc_clk=0, sys_clkin_sel;
+	u32 osc_clk = 0, sys_clkin_sel;
 	dpll_param *dpll_param_p;
 	u32 clk_index, sil_index;
 
@@ -338,17 +345,19 @@ void prcm_init(void)
 	osc_clk = get_osc_clk_speed();
 	get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
 
-	sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */
+	sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel);	/* set input crystal speed */
 
 	/* If the input clock is greater than 19.2M always divide/2 */
-	if(sys_clkin_sel > 2) {
-		sr32(PRM_CLKSRC_CTRL, 6, 2, 2);/* input clock divider */
-		clk_index = sys_clkin_sel/2;
+	if (sys_clkin_sel > 2) {
+		sr32(PRM_CLKSRC_CTRL, 6, 2, 2);	/* input clock divider */
+		clk_index = sys_clkin_sel / 2;
 	} else {
-		sr32(PRM_CLKSRC_CTRL, 6, 2, 1);/* input clock divider */
+		sr32(PRM_CLKSRC_CTRL, 6, 2, 1);	/* input clock divider */
 		clk_index = sys_clkin_sel;
 	}
 
+	sr32(PRM_CLKSRC_CTRL, 0, 2, 0);/* Bypass mode: T2 inputs a square clock */
+
 	/* The DPLL tables are defined according to sysclk value and
 	 * silicon revision. The clk_index value will be used to get
 	 * the values for that input sysclk from the DPLL param table
@@ -361,31 +370,35 @@ void prcm_init(void)
 	sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS);
 	wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY);
 
-	/* Getting the base address of Core DPLL param table*/
-	dpll_param_p = (dpll_param *)get_core_dpll_param();
+	/* Getting the base address of Core DPLL param table */
+	dpll_param_p = (dpll_param *) get_core_dpll_param();
 	/* Moving it to the right sysclk and ES rev base */
-	dpll_param_p = dpll_param_p + 2*clk_index + sil_index;
+	dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
 	/* CORE DPLL */
 	/* sr32(CM_CLKSEL2_EMU) set override to work when asleep */
 	sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
 	wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);
+
+	 /* For 3430 ES1.0 Errata 1.50, default value directly doesnt
+	work. write another value and then default value. */
+	sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1);     /* m3x2 */
 	sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2);	/* m3x2 */
 	sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2);	/* Set M2 */
 	sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m);	/* Set M */
 	sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n);	/* Set N */
-	sr32(CM_CLKSEL1_PLL, 6, 1, 0);			/* 96M Src */
+	sr32(CM_CLKSEL1_PLL, 6, 1, 0);	/* 96M Src */
 	sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV);	/* ssi */
 	sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV);	/* fsusb */
 	sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV);	/* l4 */
 	sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV);	/* l3 */
-	sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV);		/* gfx */
-	sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM);		/* reset mgr */
+	sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV);	/* gfx */
+	sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM);	/* reset mgr */
 	sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel);	/* FREQSEL */
-	sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK);		/* lock mode */
+	sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK);	/* lock mode */
 	wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY);
 
-	/* Getting the base address to PER  DPLL param table*/
-	dpll_param_p = (dpll_param *)get_per_dpll_param();
+	/* Getting the base address to PER  DPLL param table */
+	dpll_param_p = (dpll_param *) get_per_dpll_param();
 	/* Moving it to the right sysclk base */
 	dpll_param_p = dpll_param_p + clk_index;
 	/* PER DPLL */
@@ -398,38 +411,40 @@ void prcm_init(void)
 	sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2);	/* set M2 */
 	sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m);	/* set m */
 	sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n);	/* set n */
-	sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel);/* FREQSEL */
+	sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel);	/* FREQSEL */
 	sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK);	/* lock mode */
 	wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY);
 
-	/* Getting the base address to MPU DPLL param table*/
-	dpll_param_p = (dpll_param *)get_mpu_dpll_param();
+	/* Getting the base address to MPU DPLL param table */
+	dpll_param_p = (dpll_param *) get_mpu_dpll_param();
+
 	/* Moving it to the right sysclk and ES rev base */
-	dpll_param_p = dpll_param_p + 2*clk_index + sil_index;
+	dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
+
 	/* MPU DPLL (unlocked already) */
 	sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2);	/* Set M2 */
 	sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m);	/* Set M */
 	sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n);	/* Set N */
 	sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel);	/* FREQSEL */
-	sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */
+	sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK);	/* lock mode */
 	wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY);
 
-	/* Getting the base address to IVA DPLL param table*/
-	dpll_param_p = (dpll_param *)get_iva_dpll_param();
+	/* Getting the base address to IVA DPLL param table */
+	dpll_param_p = (dpll_param *) get_iva_dpll_param();
 	/* Moving it to the right sysclk and ES rev base */
-	dpll_param_p = dpll_param_p + 2*clk_index + sil_index;
+	dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
 	/* IVA DPLL (set to 12*20=240MHz) */
 	sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP);
 	wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY);
 	sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2);	/* set M2 */
 	sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m);	/* set M */
-  	sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n);	/* set N */
+	sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n);	/* set N */
 	sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel);	/* FREQSEL */
 	sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK);	/* lock mode */
 	wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY);
 
 	/* Set up GPTimers to sys_clk source only */
- 	sr32(CM_CLKSEL_PER, 0, 8, 0xff);
+	sr32(CM_CLKSEL_PER, 0, 8, 0xff);
 	sr32(CM_CLKSEL_WKUP, 0, 1, 1);
 
 	delay(5000);
@@ -443,10 +458,10 @@ void prcm_init(void)
 void secure_unlock(void)
 {
 	/* Permission values for registers -Full fledged permissions to all */
-	#define UNLOCK_1 0xFFFFFFFF
-	#define UNLOCK_2 0x00000000
-	#define UNLOCK_3 0x0000FFFF
-	/* Protection Module Register Target APE (PM_RT)*/
+#define UNLOCK_1 0xFFFFFFFF
+#define UNLOCK_2 0x00000000
+#define UNLOCK_3 0x0000FFFF
+	/* Protection Module Register Target APE (PM_RT) */
 	__raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1);
 	__raw_writel(UNLOCK_1, RT_READ_PERMISSION_0);
 	__raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0);
@@ -466,7 +481,7 @@ void secure_unlock(void)
 	__raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0);
 	__raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0);
 
-	__raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */
+	__raw_writel(UNLOCK_1, SMS_RG_ATT0);	/* SDRC region 0 public */
 }
 
 /**********************************************************
@@ -479,11 +494,10 @@ void try_unlock_memory(void)
 	int mode;
 
 	/* if GP device unlock device SRAM for general use */
-	/* secure code breaks for Secure/Emulation device - HS/E/T*/
+	/* secure code breaks for Secure/Emulation device - HS/E/T */
 	mode = get_device_type();
-	if (mode == GP_DEVICE) {
+	if (mode == GP_DEVICE)
 		secure_unlock();
-	}
 	return;
 }
 
@@ -500,7 +514,7 @@ void s_init(void)
 	/* setup the scalability control register for
 	 * 3430 to work in 3410 mode
 	 */
-	__raw_writel(0x5ABF,CONTROL_SCALABLE_OMAP_OCP);
+	__raw_writel(0x5ABF, CONTROL_SCALABLE_OMAP_OCP);
 #endif
 	try_unlock_memory();
 	set_muxconf_regs();
@@ -514,9 +528,9 @@ void s_init(void)
  * Routine: misc_init_r
  * Description: Init ethernet (done here so udelay works)
  ********************************************************/
-int misc_init_r (void)
+int misc_init_r(void)
 {
-	return(0);
+	return 0;
 }
 
 /******************************************************
@@ -544,7 +558,7 @@ void watchdog_init(void)
 	 */
 	sr32(CM_FCLKEN_WKUP, 5, 1, 1);
 	sr32(CM_ICLKEN_WKUP, 5, 1, 1);
-	wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */
+	wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5);	/* some issue here */
 
 	__raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);
 	wait_for_command_complete(WD2_BASE);
@@ -555,7 +569,7 @@ void watchdog_init(void)
  * Routine: dram_init
  * Description: sets uboots idea of sdram size
  **********************************************/
-int dram_init (void)
+int dram_init(void)
 {
 	return 0;
 }
@@ -567,15 +581,25 @@ int dram_init (void)
 void per_clocks_enable(void)
 {
 	/* Enable GP2 timer. */
-	sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */
-	sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */
-	sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */
+	sr32(CM_CLKSEL_PER, 0, 1, 0x1);	/* GPT2 = sys clk */
+	sr32(CM_ICLKEN_PER, 3, 1, 0x1);	/* ICKen GPT2 */
+	sr32(CM_FCLKEN_PER, 3, 1, 0x1);	/* FCKen GPT2 */
 
 #ifdef CFG_NS16550
-	/* Enable UART1 clocks */
+	/* UART1 clocks */
 	sr32(CM_FCLKEN1_CORE, 13, 1, 0x1);
 	sr32(CM_ICLKEN1_CORE, 13, 1, 0x1);
+
+	/* UART 3 Clocks */
+	sr32(CM_FCLKEN_PER, 11, 1, 0x1);
+	sr32(CM_ICLKEN_PER, 11, 1, 0x1);
+
 #endif
+
+	/* Enable GPIO5 clocks for blinky LEDs */
+	sr32(CM_FCLKEN_PER, 16, 1, 0x1);	/* FCKen GPIO5 */
+	sr32(CM_ICLKEN_PER, 16, 1, 0x1);	/* ICKen GPIO5 */
+
 	delay(1000);
 }
 
@@ -664,29 +688,33 @@ void per_clocks_enable(void)
 	MUX_VAL(CP(GPMC_nCS2),      (IDIS | PTU | EN  | M0)) /*GPMC_nCS2*/\
 	MUX_VAL(CP(GPMC_nCS3),      (IDIS | PTU | EN  | M0)) /*GPMC_nCS3*/\
 	MUX_VAL(CP(GPMC_nCS4),      (IDIS | PTU | EN  | M0)) /*GPMC_nCS4*/\
-	MUX_VAL(CP(GPMC_nCS5),      (IDIS | PTU | EN  | M0)) /*GPMC_nCS5*/\
-	MUX_VAL(CP(GPMC_nCS6),      (IDIS | PTU | EN  | M0)) /*GPMC_nCS6*/\
-	MUX_VAL(CP(GPMC_nCS7),      (IDIS | PTU | EN  | M0)) /*GPMC_nCS7*/\
+	MUX_VAL(CP(GPMC_nCS5),      (IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\
+	MUX_VAL(CP(GPMC_nCS6),      (IEN  | PTD | DIS | M1)) /*GPMC_nCS6*/\
+	MUX_VAL(CP(GPMC_nCS7),      (IEN  | PTU | EN  | M1)) /*GPMC_nCS7*/\
 	MUX_VAL(CP(GPMC_CLK),       (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
 	MUX_VAL(CP(GPMC_nADV_ALE),  (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
 	MUX_VAL(CP(GPMC_nOE),       (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
 	MUX_VAL(CP(GPMC_nWE),       (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
 	MUX_VAL(CP(GPMC_nBE0_CLE),  (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
-	MUX_VAL(CP(GPMC_nBE1),      (IDIS | PTD | DIS | M4)) /*GPIO_61*/\
+	MUX_VAL(CP(GPMC_nBE1),      (IEN  | PTD | DIS | M0)) /*GPIO_61*/\
 	MUX_VAL(CP(GPMC_nWP),       (IEN  | PTD | DIS | M0)) /*GPMC_nWP*/\
 	MUX_VAL(CP(GPMC_WAIT0),     (IEN  | PTU | EN  | M0)) /*GPMC_WAIT0*/\
 	MUX_VAL(CP(GPMC_WAIT1),     (IEN  | PTU | EN  | M0)) /*GPMC_WAIT1*/\
-	MUX_VAL(CP(GPMC_WAIT2),     (IEN  | PTU | EN  | M4)) /*GPIO_64*/\
-	MUX_VAL(CP(GPMC_WAIT3),     (IEN  | PTU | EN  | M4)) /*GPIO_65*/\
+	MUX_VAL(CP(GPMC_WAIT2),     (IEN  | PTU | EN  | M0)) /*GPIO_64*/\
+	MUX_VAL(CP(GPMC_WAIT3),     (IEN  | PTU | EN  | M0)) /*GPIO_65*/\
 	MUX_VAL(CP(DSS_DATA18),     (IEN  | PTD | DIS | M4)) /*GPIO_88*/\
 	MUX_VAL(CP(DSS_DATA19),     (IEN  | PTD | DIS | M4)) /*GPIO_89*/\
 	MUX_VAL(CP(DSS_DATA20),     (IEN  | PTD | DIS | M4)) /*GPIO_90*/\
 	MUX_VAL(CP(DSS_DATA21),     (IEN  | PTD | DIS | M4)) /*GPIO_91*/\
 	MUX_VAL(CP(CAM_WEN),        (IEN  | PTD | DIS | M4)) /*GPIO_167*/\
 	MUX_VAL(CP(UART1_TX),       (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
-	MUX_VAL(CP(UART1_RTS),      (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\
-	MUX_VAL(CP(UART1_CTS),      (IEN | PTU | DIS | M0)) /*UART1_CTS*/\
-	MUX_VAL(CP(UART1_RX),       (IEN | PTD | DIS | M0)) /*UART1_RX*/\
+	MUX_VAL(CP(UART1_RTS),      (IDIS | PTD | DIS | M4)) /*GPIO_149*/\
+	MUX_VAL(CP(UART1_CTS),      (IDIS | PTD | DIS | M4)) /*GPIO_150*/\
+	MUX_VAL(CP(UART1_RX),       (IEN  | PTD | DIS | M0)) /*UART1_RX*/\
+	MUX_VAL(CP(UART3_CTS_RCTX), (IEN  | PTD | EN  | M0)) /*UART3_CTS_RCTX */\
+	MUX_VAL(CP(UART3_RTS_SD),   (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
+	MUX_VAL(CP(UART3_RX_IRRX),  (IEN  | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
+	MUX_VAL(CP(UART3_TX_IRTX),  (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
 	MUX_VAL(CP(McBSP1_DX),      (IEN  | PTD | DIS | M4)) /*GPIO_158*/\
 	MUX_VAL(CP(SYS_32K),        (IEN  | PTD | DIS | M0)) /*SYS_32K*/\
 	MUX_VAL(CP(SYS_BOOT0),      (IEN  | PTD | DIS | M4)) /*GPIO_2 */\
@@ -705,15 +733,16 @@ void per_clocks_enable(void)
 	MUX_VAL(CP(JTAG_EMU1),      (IEN  | PTD | DIS | M0)) /*JTAG_EMU1*/\
 	MUX_VAL(CP(ETK_CLK),        (IEN  | PTD | DIS | M4)) /*GPIO_12*/\
 	MUX_VAL(CP(ETK_CTL),        (IEN  | PTD | DIS | M4)) /*GPIO_13*/\
-	MUX_VAL(CP(ETK_D0 ),        (IEN  | PTD | DIS | M4)) /*GPIO_14*/\
-	MUX_VAL(CP(ETK_D1 ),        (IEN  | PTD | DIS | M4)) /*GPIO_15*/\
-	MUX_VAL(CP(ETK_D2 ),        (IEN  | PTD | DIS | M4)) /*GPIO_16*/\
-	MUX_VAL(CP(ETK_D10),        (IEN  | PTD | DIS | M4)) /*GPIO_24*/\
+	MUX_VAL(CP(ETK_D0),         (IEN  | PTD | DIS | M4)) /*GPIO_14*/\
+	MUX_VAL(CP(ETK_D1),         (IEN  | PTD | DIS | M4)) /*GPIO_15*/\
+	MUX_VAL(CP(ETK_D2),         (IEN  | PTD | DIS | M4)) /*GPIO_16*/\
 	MUX_VAL(CP(ETK_D11),        (IEN  | PTD | DIS | M4)) /*GPIO_25*/\
 	MUX_VAL(CP(ETK_D12),        (IEN  | PTD | DIS | M4)) /*GPIO_26*/\
 	MUX_VAL(CP(ETK_D13),        (IEN  | PTD | DIS | M4)) /*GPIO_27*/\
 	MUX_VAL(CP(ETK_D14),        (IEN  | PTD | DIS | M4)) /*GPIO_28*/\
-	MUX_VAL(CP(ETK_D15),        (IEN  | PTD | DIS | M4)) /*GPIO_29*/
+	MUX_VAL(CP(ETK_D15),        (IEN  | PTD | DIS | M4)) /*GPIO_29 */\
+	MUX_VAL(CP(sdrc_cke0),      (IDIS | PTU | EN  | M0)) /*sdrc_cke0 */\
+	MUX_VAL(CP(sdrc_cke1),      (IDIS | PTD | DIS | M7)) /*sdrc_cke1 not used*/
 
 /**********************************************************
  * Routine: set_muxconf_regs
@@ -738,92 +767,119 @@ int nand_init(void)
 	__raw_writel(0x0, GPMC_IRQENABLE);	/* isr's sources masked */
 	__raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */
 
-	/* Set the GPMC Vals . For NAND boot on 3430SDP, NAND is mapped at CS0
-         *  , NOR at CS1 and MPDB at CS3. And oneNAND boot, we map oneNAND at CS0.
+	/* Set the GPMC Vals, NAND is mapped at CS0, oneNAND at CS0.
 	 *  We configure only GPMC CS0 with required values. Configiring other devices
-	 *  at other CS in done in u-boot anyway. So we don't have to bother doing it here.
-         */
+	 *  at other CS is done in u-boot. So we don't have to bother doing it here.
+	 */
 	__raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0);
 	delay(1000);
 
-	if ((get_mem_type() == GPMC_NAND) || (get_mem_type() == MMC_NAND)){
-        	__raw_writel( M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
-        	__raw_writel( M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
-        	__raw_writel( M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
-        	__raw_writel( M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
-        	__raw_writel( M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
-        	__raw_writel( M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
-
-        	/* Enable the GPMC Mapping */
-        	__raw_writel(( ((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
-        		     ((NAND_BASE_ADR>>24) & 0x3F) |
-        		     (1<<6) ),  (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
-        	delay(2000);
-
-         	if (nand_chip()){
+	if ((get_mem_type() == GPMC_NAND) || (get_mem_type() == MMC_NAND)) {
+		__raw_writel(M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
+		__raw_writel(M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
+		__raw_writel(M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
+		__raw_writel(M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
+		__raw_writel(M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
+		__raw_writel(M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
+
+		/* Enable the GPMC Mapping */
+		__raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
+			     ((NAND_BASE_ADR>>24) & 0x3F) |
+			     (1<<6)),  (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
+		delay(2000);
+
+		if (nand_chip()) {
 #ifdef CFG_PRINTF
-        		printf("Unsupported Chip!\n");
+			printf("Unsupported Chip!\n");
 #endif
-        		return 1;
-        	}
+			return 1;
+		}
 
 	}
 
-	if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)){
-        	__raw_writel( ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
-        	__raw_writel( ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
-        	__raw_writel( ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
-        	__raw_writel( ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
-        	__raw_writel( ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
-        	__raw_writel( ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
-
-        	/* Enable the GPMC Mapping */
-        	__raw_writel(( ((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
-        		     ((ONENAND_BASE>>24) & 0x3F) |
-        		     (1<<6) ),  (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
-        	delay(2000);
-
-        	if (onenand_chip()){
+	if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)) {
+		__raw_writel(ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
+		__raw_writel(ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
+		__raw_writel(ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
+		__raw_writel(ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
+		__raw_writel(ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
+		__raw_writel(ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
+
+		/* Enable the GPMC Mapping */
+		__raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
+			     ((ONENAND_BASE>>24) & 0x3F) |
+			     (1<<6)),  (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
+		delay(2000);
+
+		if (onenand_chip()) {
 #ifdef CFG_PRINTF
-        		printf("OneNAND Unsupported !\n");
+			printf("OneNAND Unsupported !\n");
 #endif
-        		return 1;
-        	}
+			return 1;
+		}
 	}
 	return 0;
 }
 
+#define DEBUG_LED1			149	/* gpio */
+#define DEBUG_LED2			150	/* gpio */
+
+void blinkLEDs()
+{
+	void *p;
+
+	/* Alternately turn the LEDs on and off */
+	p = (unsigned long *)OMAP34XX_GPIO5_BASE;
+	while (1) {
+		/* turn LED1 on and LED2 off */
+		*(unsigned long *)(p + 0x94) = 1 << (DEBUG_LED1 % 32);
+		*(unsigned long *)(p + 0x90) = 1 << (DEBUG_LED2 % 32);
+
+		/* delay for a while */
+		delay(1000);
+
+		/* turn LED1 off and LED2 on */
+		*(unsigned long *)(p + 0x90) = 1 << (DEBUG_LED1 % 32);
+		*(unsigned long *)(p + 0x94) = 1 << (DEBUG_LED2 % 32);
+
+		/* delay for a while */
+		delay(1000);
+	}
+}
 
 typedef int (mmc_boot_addr) (void);
 int mmc_boot(unsigned char *buf)
 {
 
-       long size = 0;
+	long size = 0;
 #ifdef CFG_CMD_FAT
-       block_dev_desc_t *dev_desc = NULL;
-       unsigned char ret = 0;
-
-       printf("Starting X-loader on MMC \n");
-
-       ret = mmc_init(1);
-       if(ret == 0){
-               printf("\n MMC init failed \n");
-               return 0;
-       }
-
-       dev_desc = mmc_get_dev(0);
-       fat_register_device(dev_desc, 1);
-       size = file_fat_read("u-boot.bin", buf, 0);
-       if (size == -1) {
-               return 0;
-       }
-       printf("\n%ld Bytes Read from MMC \n", size);
-
-       printf("Starting OS Bootloader from MMC...\n");
+	block_dev_desc_t *dev_desc = NULL;
+	unsigned char ret = 0;
+
+	printf("Starting X-loader on MMC \n");
+
+	ret = mmc_init(1);
+	if (ret == 0) {
+		printf("\n MMC init failed \n");
+		return 0;
+	}
+
+	dev_desc = mmc_get_dev(0);
+	fat_register_device(dev_desc, 1);
+	size = file_fat_read("u-boot.bin", buf, 0);
+	if (size == -1)
+		return 0;
+
+	printf("\n%ld Bytes Read from MMC \n", size);
+
+	printf("Starting OS Bootloader from MMC...\n");
 #endif
-       return size;
+	return size;
 }
 
 /* optionally do something like blinking LED */
-void board_hang (void)
-{ while (0) {};}
+void board_hang(void)
+{
+	while (1)
+		blinkLEDs();
+}
diff --git a/board/omap3530beagle/platform.S b/board/omap3530beagle/platform.S
new file mode 100644
index 0000000..5869270
--- /dev/null
+++ b/board/omap3530beagle/platform.S
@@ -0,0 +1,360 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2004-2006
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/clocks.h>
+
+_TEXT_BASE:
+	.word	TEXT_BASE	/* sdram load addr from config.mk */
+
+#if !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT)
+/**************************************************************************
+ * cpy_clk_code: relocates clock code into SRAM where its safer to execute
+ * R1 = SRAM destination address.
+ *************************************************************************/
+.global cpy_clk_code
+ cpy_clk_code:
+        /* Copy DPLL code into SRAM */ 
+        adr     r0, go_to_speed         /* get addr of clock setting code */
+        mov     r2, #384                /* r2 size to copy (div by 32 bytes) */
+        mov     r1, r1                  /* r1 <- dest address (passed in) */
+        add     r2, r2, r0              /* r2 <- source end address */
+next2:
+        ldmia   r0!, {r3-r10}           /* copy from source address [r0]    */
+        stmia   r1!, {r3-r10}           /* copy to   target address [r1]    */
+        cmp     r0, r2                  /* until source end address [r2]    */
+        bne     next2
+	mov	pc, lr                  /* back to caller */
+
+/* **************************************************************************** 
+ * NOTE: 3430 X-loader currently does not use this code.  
+*   It could be removed its is kept for compatabily with u-boot.
+ *
+ *  go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
+ *               -executed from SRAM.
+ *  R0 = CM_CLKEN_PLL-bypass value
+ *  R1 = CM_CLKSEL1_PLL-m, n, and divider values
+ *  R2 = CM_CLKSEL_CORE-divider values
+ *  R3 = CM_IDLEST_CKGEN - addr dpll lock wait
+ *
+ *  Note: If core unlocks/relocks and SDRAM is running fast already it gets
+ *        confused.  A reset of the controller gets it back.  Taking away its
+ *        L3 when its not in self refresh seems bad for it.  Normally, this code
+ *        runs from flash before SDR is init so that should be ok.
+ ******************************************************************************/    
+.global go_to_speed
+ go_to_speed:
+        stmfd sp!, {r4-r6}
+
+        /* move into fast relock bypass */
+        ldr     r4, pll_ctl_add
+        str     r0, [r4]
+wait1:
+        ldr     r5, [r3]       /* get status */
+        and     r5, r5, #0x1   /* isolate core status */
+        cmp     r5, #0x1       /* still locked? */
+        beq     wait1          /* if lock, loop */
+
+	/* set new dpll dividers _after_ in bypass */
+	ldr     r5, pll_div_add1
+        str     r1, [r5]          /* set m, n, m2 */
+        ldr     r5, pll_div_add2
+        str     r2, [r5]          /* set l3/l4/.. dividers*/
+        ldr     r5, pll_div_add3  /* wkup */
+        ldr     r2, pll_div_val3  /* rsm val */
+        str     r2, [r5]          
+        ldr     r5, pll_div_add4  /* gfx */
+        ldr     r2, pll_div_val4 
+        str     r2, [r5]         
+        ldr     r5, pll_div_add5  /* emu */
+        ldr     r2, pll_div_val5 
+        str     r2, [r5]     
+
+        /* now prepare GPMC (flash) for new dpll speed */
+	/* flash needs to be stable when we jump back to it */
+        ldr     r5, flash_cfg3_addr
+        ldr     r2, flash_cfg3_val
+        str     r2, [r5]
+        ldr     r5, flash_cfg4_addr
+        ldr     r2, flash_cfg4_val
+        str     r2, [r5]
+        ldr     r5, flash_cfg5_addr
+        ldr     r2, flash_cfg5_val
+        str     r2, [r5]
+        ldr     r5, flash_cfg1_addr
+        ldr     r2, [r5]
+        orr     r2, r2, #0x3     /* up gpmc divider */
+        str     r2, [r5]
+
+        /* lock DPLL3 and wait a bit */
+        orr     r0, r0, #0x7   /* set up for lock mode */     
+        str     r0, [r4]       /* lock */
+        nop                    /* ARM slow at this point working at sys_clk */
+        nop
+        nop
+        nop
+wait2:
+        ldr     r5, [r3]       /* get status */
+        and     r5, r5, #0x1   /* isolate core status */
+        cmp     r5, #0x1       /* still locked? */
+        bne     wait2          /* if lock, loop */
+        nop
+        nop
+        nop
+        nop
+        ldmfd sp!, {r4-r6}
+        mov     pc, lr           /* back to caller, locked */        
+
+_go_to_speed: .word go_to_speed
+
+/* these constants need to be close for PIC code */
+/* The Nor has to be in the Flash Base CS0 for this condition to happen */
+flash_cfg1_addr:
+    .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1)
+flash_cfg3_addr:
+    .word  (GPMC_CONFIG_CS0 + GPMC_CONFIG3)
+flash_cfg3_val: 
+    .word  STNOR_GPMC_CONFIG3
+flash_cfg4_addr:
+    .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4)
+flash_cfg4_val:
+    .word  STNOR_GPMC_CONFIG4
+flash_cfg5_val:
+    .word  STNOR_GPMC_CONFIG5
+flash_cfg5_addr:
+    .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5)
+pll_ctl_add:
+    .word CM_CLKEN_PLL
+pll_div_add1:
+    .word CM_CLKSEL1_PLL 
+pll_div_add2:
+    .word CM_CLKSEL_CORE
+pll_div_add3:
+    .word CM_CLKSEL_WKUP
+pll_div_val3:
+    .word (WKUP_RSM << 1) 
+pll_div_add4:
+    .word CM_CLKSEL_GFX
+pll_div_val4:
+    .word (GFX_DIV << 0) 
+pll_div_add5:
+    .word CM_CLKSEL1_EMU
+pll_div_val5:
+    .word CLSEL1_EMU_VAL
+
+#endif
+
+.globl lowlevel_init
+lowlevel_init:
+	ldr	sp,	SRAM_STACK
+        str     ip,	[sp]    /* stash old link register */
+	mov	ip,	lr	/* save link reg across call */
+	bl      s_init          /* go setup pll,mux,memory */
+        ldr     ip,	[sp]    /* restore save ip */
+	mov	lr,	ip	/* restore link reg */
+
+	/* back to arch calling code */
+	mov	pc,	lr
+
+	/* the literal pools origin */
+	.ltorg
+
+REG_CONTROL_STATUS:
+	.word CONTROL_STATUS
+SRAM_STACK:
+	.word LOW_LEVEL_SRAM_STACK
+
+/* DPLL(1-4) PARAM TABLES */
+/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal
+ * OPP (1.2V). The fields are defined according to dpll_param struct(clock.c). 
+ * The values are defined for all possible sysclk and for ES1 and ES2.
+ */
+
+mpu_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word 0x0FE,0x07,0x05,0x01
+/* ES2 */
+.word 0x0FA,0x05,0x07,0x01
+/* 3410 */
+.word 0x085,0x05,0x07,0x01
+
+/* 13MHz */
+/* ES1 */
+.word 0x17D,0x0C,0x03,0x01
+/* ES2 */
+.word 0x1F4,0x0C,0x03,0x01
+/* 3410 */
+.word 0x10A,0x0C,0x03,0x01
+ 
+/* 19.2MHz */
+/* ES1 */
+.word 0x179,0x12,0x04,0x01
+/* ES2 */
+.word 0x271,0x17,0x03,0x01
+/* 3410 */
+.word 0x14C,0x17,0x03,0x01
+
+/* 26MHz */
+/* ES1 */
+.word 0x17D,0x19,0x03,0x01
+/* ES2 */
+.word 0x0FA,0x0C,0x07,0x01
+/* 3410 */
+.word 0x085,0x0C,0x07,0x01
+
+/* 38.4MHz */
+/* ES1 */
+.word 0x1FA,0x32,0x03,0x01
+/* ES2 */
+.word 0x271,0x2F,0x03,0x01
+/* 3410 */
+.word 0x14C,0x2F,0x03,0x01
+
+
+.globl get_mpu_dpll_param
+get_mpu_dpll_param:
+	adr r0, mpu_dpll_param
+	mov pc, lr
+
+iva_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word 0x07D,0x05,0x07,0x01
+/* ES2 */
+.word 0x0B4,0x05,0x07,0x01
+/* 3410 */
+.word 0x085,0x05,0x07,0x01
+
+/* 13MHz */
+/* ES1 */
+.word 0x0FA,0x0C,0x03,0x01
+/* ES2 */
+.word 0x168,0x0C,0x03,0x01
+/* 3410 */
+.word 0x10A,0x0C,0x03,0x01
+
+/* 19.2MHz */
+/* ES1 */
+.word 0x082,0x09,0x07,0x01
+/* ES2 */
+.word 0x0E1,0x0B,0x06,0x01
+/* 3410 */
+.word 0x14C,0x17,0x03,0x01
+
+/* 26MHz */
+/* ES1 */
+.word 0x07D,0x0C,0x07,0x01
+/* ES2 */
+.word 0x0B4,0x0C,0x07,0x01
+/* 3410 */
+.word 0x085,0x0C,0x07,0x01
+
+/* 38.4MHz */
+/* ES1 */
+.word 0x13F,0x30,0x03,0x01
+/* ES2 */
+.word 0x0E1,0x17,0x06,0x01
+/* 3410 */
+.word 0x14C,0x2F,0x03,0x01
+
+
+.globl get_iva_dpll_param
+get_iva_dpll_param:
+	adr r0, iva_dpll_param
+	mov pc, lr
+
+/* Core DPLL targets for L3 at 166 & L133 */
+core_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word M_12_ES1,M_12_ES1,FSL_12_ES1,M2_12_ES1
+/* ES2 */
+.word M_12,N_12,FSEL_12,M2_12
+/* 3410 */
+.word M_12,N_12,FSEL_12,M2_12
+
+/* 13MHz */
+/* ES1 */
+.word M_13_ES1,N_13_ES1,FSL_13_ES1,M2_13_ES1
+/* ES2 */
+.word M_13,N_13,FSEL_13,M2_13
+/* 3410 */
+.word M_13,N_13,FSEL_13,M2_13
+
+/* 19.2MHz */
+/* ES1 */
+.word M_19p2_ES1,N_19p2_ES1,FSL_19p2_ES1,M2_19p2_ES1
+/* ES2 */
+.word M_19p2,N_19p2,FSEL_19p2,M2_19p2
+/* 3410 */
+.word M_19p2,N_19p2,FSEL_19p2,M2_19p2
+
+/* 26MHz */
+/* ES1 */
+.word M_26_ES1,N_26_ES1,FSL_26_ES1,M2_26_ES1
+/* ES2 */
+.word M_26,N_26,FSEL_26,M2_26
+/* 3410 */
+.word M_26,N_26,FSEL_26,M2_26
+
+/* 38.4MHz */
+/* ES1 */
+.word M_38p4_ES1,N_38p4_ES1,FSL_38p4_ES1,M2_38p4_ES1
+/* ES2 */
+.word M_38p4,N_38p4,FSEL_38p4,M2_38p4
+/* 3410 */
+.word M_38p4,N_38p4,FSEL_38p4,M2_38p4
+
+.globl get_core_dpll_param
+get_core_dpll_param:
+	adr r0, core_dpll_param
+	mov pc, lr
+
+/* PER DPLL values are same for both ES1 and ES2 */
+per_dpll_param:
+/* 12MHz */
+.word 0xD8,0x05,0x07,0x09
+
+/* 13MHz */
+.word 0x1B0,0x0C,0x03,0x09
+
+/* 19.2MHz */
+.word 0xE1,0x09,0x07,0x09
+
+/* 26MHz */
+.word 0xD8,0x0C,0x07,0x09
+
+/* 38.4MHz */
+.word 0xE1,0x13,0x07,0x09
+
+.globl get_per_dpll_param
+get_per_dpll_param:
+	adr r0, per_dpll_param
+	mov pc, lr
+
diff --git a/board/omap3530beagle/platform.S_old b/board/omap3530beagle/platform.S_old
new file mode 100644
index 0000000..8368487
--- /dev/null
+++ b/board/omap3530beagle/platform.S_old
@@ -0,0 +1,435 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2004-2006
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/clocks.h>
+
+_TEXT_BASE:
+	.word	TEXT_BASE	/* sdram load addr from config.mk */
+
+#if !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT)
+/**************************************************************************
+ * cpy_clk_code: relocates clock code into SRAM where its safer to execute
+ * R1 = SRAM destination address.
+ *************************************************************************/
+.global cpy_clk_code
+ cpy_clk_code:
+        /* Copy DPLL code into SRAM */ 
+        adr     r0, go_to_speed         /* get addr of clock setting code */
+        mov     r2, #384                /* r2 size to copy (div by 32 bytes) */
+        mov     r1, r1                  /* r1 <- dest address (passed in) */
+        add     r2, r2, r0              /* r2 <- source end address */
+next2:
+        ldmia   r0!, {r3-r10}           /* copy from source address [r0]    */
+        stmia   r1!, {r3-r10}           /* copy to   target address [r1]    */
+        cmp     r0, r2                  /* until source end address [r2]    */
+        bne     next2
+	mov	pc, lr                  /* back to caller */
+
+/* **************************************************************************** 
+ * NOTE: 3430 X-loader currently does not use this code.  
+*   It could be removed its is kept for compatabily with u-boot.
+ *
+ *  go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
+ *               -executed from SRAM.
+ *  R0 = CM_CLKEN_PLL-bypass value
+ *  R1 = CM_CLKSEL1_PLL-m, n, and divider values
+ *  R2 = CM_CLKSEL_CORE-divider values
+ *  R3 = CM_IDLEST_CKGEN - addr dpll lock wait
+ *
+ *  Note: If core unlocks/relocks and SDRAM is running fast already it gets
+ *        confused.  A reset of the controller gets it back.  Taking away its
+ *        L3 when its not in self refresh seems bad for it.  Normally, this code
+ *        runs from flash before SDR is init so that should be ok.
+ ******************************************************************************/    
+.global go_to_speed
+ go_to_speed:
+        stmfd sp!, {r4-r6}
+
+        /* move into fast relock bypass */
+        ldr     r4, pll_ctl_add
+        str     r0, [r4]
+wait1:
+        ldr     r5, [r3]       /* get status */
+        and     r5, r5, #0x1   /* isolate core status */
+        cmp     r5, #0x1       /* still locked? */
+        beq     wait1          /* if lock, loop */
+
+	/* set new dpll dividers _after_ in bypass */
+	ldr     r5, pll_div_add1
+        str     r1, [r5]          /* set m, n, m2 */
+        ldr     r5, pll_div_add2
+        str     r2, [r5]          /* set l3/l4/.. dividers*/
+        ldr     r5, pll_div_add3  /* wkup */
+        ldr     r2, pll_div_val3  /* rsm val */
+        str     r2, [r5]          
+        ldr     r5, pll_div_add4  /* gfx */
+        ldr     r2, pll_div_val4 
+        str     r2, [r5]         
+        ldr     r5, pll_div_add5  /* emu */
+        ldr     r2, pll_div_val5 
+        str     r2, [r5]     
+
+        /* now prepare GPMC (flash) for new dpll speed */
+	/* flash needs to be stable when we jump back to it */
+        ldr     r5, flash_cfg3_addr
+        ldr     r2, flash_cfg3_val
+        str     r2, [r5]
+        ldr     r5, flash_cfg4_addr
+        ldr     r2, flash_cfg4_val
+        str     r2, [r5]
+        ldr     r5, flash_cfg5_addr
+        ldr     r2, flash_cfg5_val
+        str     r2, [r5]
+        ldr     r5, flash_cfg1_addr
+        ldr     r2, [r5]
+        orr     r2, r2, #0x3     /* up gpmc divider */
+        str     r2, [r5]
+
+        /* lock DPLL3 and wait a bit */
+        orr     r0, r0, #0x7   /* set up for lock mode */     
+        str     r0, [r4]       /* lock */
+        nop                    /* ARM slow at this point working at sys_clk */
+        nop
+        nop
+        nop
+wait2:
+        ldr     r5, [r3]       /* get status */
+        and     r5, r5, #0x1   /* isolate core status */
+        cmp     r5, #0x1       /* still locked? */
+        bne     wait2          /* if lock, loop */
+        nop
+        nop
+        nop
+        nop
+        ldmfd sp!, {r4-r6}
+        mov     pc, lr           /* back to caller, locked */        
+
+_go_to_speed: .word go_to_speed
+
+/* these constants need to be close for PIC code */
+/* The Nor has to be in the Flash Base CS0 for this condition to happen */
+flash_cfg1_addr:
+    .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1)
+flash_cfg3_addr:
+    .word  (GPMC_CONFIG_CS0 + GPMC_CONFIG3)
+flash_cfg3_val: 
+    .word  STNOR_GPMC_CONFIG3
+flash_cfg4_addr:
+    .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4)
+flash_cfg4_val:
+    .word  STNOR_GPMC_CONFIG4
+flash_cfg5_val:
+    .word  STNOR_GPMC_CONFIG5
+flash_cfg5_addr:
+    .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5)
+pll_ctl_add:
+    .word CM_CLKEN_PLL
+pll_div_add1:
+    .word CM_CLKSEL1_PLL 
+pll_div_add2:
+    .word CM_CLKSEL_CORE
+pll_div_add3:
+    .word CM_CLKSEL_WKUP
+pll_div_val3:
+    .word (WKUP_RSM << 1) 
+pll_div_add4:
+    .word CM_CLKSEL_GFX
+pll_div_val4:
+    .word (GFX_DIV << 0) 
+pll_div_add5:
+    .word CM_CLKSEL1_EMU
+pll_div_val5:
+    .word CLSEL1_EMU_VAL
+
+#endif
+
+.globl lowlevel_init
+lowlevel_init:
+	ldr	sp,	SRAM_STACK
+        str     ip,	[sp]    /* stash old link register */
+	mov	ip,	lr	/* save link reg across call */
+        bl      s_init          /* go setup pll,mux,memory */
+        ldr     ip,	[sp]    /* restore save ip */
+	mov	lr,	ip	/* restore link reg */
+
+	/* back to arch calling code */
+	mov	pc,	lr
+
+	/* the literal pools origin */
+	.ltorg
+
+REG_CONTROL_STATUS:
+	.word CONTROL_STATUS
+SRAM_STACK:
+	.word LOW_LEVEL_SRAM_STACK
+
+
+/* DPLL(1-4) PARAM TABLES */
+/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal
+ * OPP (1.2V). The fields are defined according to dpll_param struct(clock.c). 
+ * The values are defined for all possible sysclk and for ES1 and ES2.
+ */
+
+mpu_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word 0x0FE
+.word 0x07
+.word 0x05
+.word 0x01
+/* ES2 */
+.word 0x0FA
+.word 0x05
+.word 0x07
+.word 0x01
+
+/* 13MHz */
+/* ES1 */
+.word 0x17D
+.word 0x0C
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x1F4
+.word 0x0C
+.word 0x03
+.word 0x01
+ 
+/* 19.2MHz */
+/* ES1 */
+.word 0x179
+.word 0x12
+.word 0x04
+.word 0x01
+/* ES2 */
+.word 0x271
+.word 0x17
+.word 0x03
+.word 0x01
+
+/* 26MHz */
+/* ES1 */
+.word 0x17D
+.word 0x19
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x0FA
+.word 0x0C
+.word 0x07
+.word 0x01
+
+/* 38.4MHz */
+/* ES1 */
+.word 0x1FA
+.word 0x32
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x271
+.word 0x2F
+.word 0x03
+.word 0x01
+
+
+.globl get_mpu_dpll_param
+get_mpu_dpll_param:
+	adr r0, mpu_dpll_param
+	mov pc, lr
+
+iva_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word 0x07D
+.word 0x05
+.word 0x07
+.word 0x01
+/* ES2 */
+.word 0x0B4
+.word 0x05
+.word 0x07
+.word 0x01
+
+/* 13MHz */
+/* ES1 */
+.word 0x0FA
+.word 0x0C
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x168
+.word 0x0C
+.word 0x03
+.word 0x01
+
+/* 19.2MHz */
+/* ES1 */
+.word 0x082
+.word 0x09
+.word 0x07
+.word 0x01
+/* ES2 */
+.word 0x0E1
+.word 0x0B
+.word 0x06
+.word 0x01
+
+/* 26MHz */
+/* ES1 */
+.word 0x07D
+.word 0x0C
+.word 0x07
+.word 0x01
+/* ES2 */
+.word 0x0B4
+.word 0x0C
+.word 0x07
+.word 0x01
+
+/* 38.4MHz */
+/* ES1 */
+.word 0x13F
+.word 0x30
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x0E1
+.word 0x17
+.word 0x06
+.word 0x01
+
+
+.globl get_iva_dpll_param
+get_iva_dpll_param:
+	adr r0, iva_dpll_param
+	mov pc, lr
+
+core_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word 0x19F
+.word 0x0E
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x0A6
+.word 0x05
+.word 0x07
+.word 0x01
+
+/* 13MHz */
+/* ES1 */
+.word 0x1B2
+.word 0x10
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x14C
+.word 0x0C
+.word 0x03
+.word 0x01
+
+/* 19.2MHz */
+/* ES1 */
+.word 0x19F
+.word 0x17
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x19F
+.word 0x17
+.word 0x03
+.word 0x01
+
+/* 26MHz */
+/* ES1 */
+.word 0x1B2
+.word 0x21
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x0A6
+.word 0x0C
+.word 0x07
+.word 0x01
+
+/* 38.4MHz */
+/* ES1 */
+.word 0x19F
+.word 0x2F
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x19F
+.word 0x2F
+.word 0x03
+.word 0x01
+
+.globl get_core_dpll_param
+get_core_dpll_param:
+	adr r0, core_dpll_param
+	mov pc, lr
+
+/* PER DPLL values are same for both ES1 and ES2 */
+per_dpll_param:
+/* 12MHz */
+.word 0xD8
+.word 0x05
+.word 0x07
+.word 0x09
+
+/* 13MHz */
+.word 0x1B0
+.word 0x0C
+.word 0x03
+.word 0x09
+
+/* 19.2MHz */
+.word 0xE1
+.word 0x09
+.word 0x07
+.word 0x09
+
+/* 26MHz */
+.word 0xD8
+.word 0x0C
+.word 0x07
+.word 0x09
+
+/* 38.4MHz */
+.word 0xE1
+.word 0x13
+.word 0x07
+.word 0x09
+
+.globl get_per_dpll_param
+get_per_dpll_param:
+	adr r0, per_dpll_param
+	mov pc, lr
+
diff --git a/board/omap3530beagle/x-load.lds b/board/omap3530beagle/x-load.lds
new file mode 100644
index 0000000..9402f74
--- /dev/null
+++ b/board/omap3530beagle/x-load.lds
@@ -0,0 +1,54 @@
+/*
+ * November 2006 - Changed to support 3430sdp device 
+ * Copyright (c) 2004-2006 Texas Instruments 
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/omap3/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/board/omap3evm/omap3evm.c b/board/omap3evm/omap3evm.c
index f94518e..e1ebc20 100755
--- a/board/omap3evm/omap3evm.c
+++ b/board/omap3evm/omap3evm.c
@@ -44,8 +44,6 @@ struct dpll_param {
 
 typedef struct dpll_param dpll_param;
 
-#define MAX_SIL_INDEX	3
-
 /* Following functions are exported from lowlevel_init.S */
 extern dpll_param * get_mpu_dpll_param();
 extern dpll_param * get_iva_dpll_param();
diff --git a/drivers/Makefile b/board/overo/Makefile
old mode 100644
new mode 100755
similarity index 57%
copy from drivers/Makefile
copy to board/overo/Makefile
index 2352f42..2e6c25d
--- a/drivers/Makefile
+++ b/board/overo/Makefile
@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2000
+# (C) Copyright 2000, 2001, 2002
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -23,52 +23,25 @@
 
 include $(TOPDIR)/config.mk
 
-# CFLAGS += -DET_DEBUG -DDEBUG
+LIB	= lib$(BOARD).a
 
-LIB	= libdrivers.a
-OBJS	= serial.o ns16550.o onenand.o
+OBJS	:= overo.o 
+SOBJS	:= platform.o
 
-ifeq ($(BOARD), omap3430sdp)
-OBJS 	+= k9f1g08r0a.o
-endif
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
 
-ifeq ($(BOARD), omap3430labrador)
-OBJS 	+= k9f1g08r0a.o
-endif
+clean:
+	rm -f $(SOBJS) $(OBJS)
 
-ifeq ($(BOARD), omap3evm)
-OBJS 	+= k9f1g08r0a.o
-endif
-
-ifeq ($(BOARD), omap2420h4) 
-OBJS 	+= k9k1216.o
-endif
-
-ifeq ($(BOARD), omap2430sdp)
-OBJS    += k9k1216.o
-endif
-
-ifeq ($(BOARD), omap1710h3)
-OBJS    += k9f5616.o
-endif
-
-
-## Disabled for now:
-##	  cs8900.o ct69000.o dataflash.o dc2114x.o ds1722.o \
-##	  lan91c96.o mw_eeprom.o natsemi.o \
-##	  smc91111.o smiLynxEM.o spi_eeprom.o sym53c8xx.o \
-##
-
-all:	$(LIB)
-
-$(LIB):	$(OBJS)
-	$(AR) crv $@ $(OBJS)
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
 
 #########################################################################
 
-.depend:	Makefile $(OBJS:.o=.c)
-		$(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
 
-sinclude .depend
+-include .depend
 
 #########################################################################
diff --git a/board/overo/config.mk b/board/overo/config.mk
new file mode 100755
index 0000000..7ee3014
--- /dev/null
+++ b/board/overo/config.mk
@@ -0,0 +1,20 @@
+#
+# (C) Copyright 2006
+# Texas Instruments, <www.ti.com>
+#
+# Overo board uses TI OMAP35xx (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# Overo has 1 bank of 128MB mPOP-SDRAM on CS0
+# Physical Address:
+# 8000'0000 (bank0)
+
+# For use if you want X-Loader to relocate from SRAM to DDR
+#TEXT_BASE = 0x80e80000
+
+# For XIP in 64K of SRAM or debug (GP device has it all availabe)
+# SRAM 40200000-4020FFFF base
+# initial stack at 0x4020fffc used in s_init (below xloader).
+# The run time stack is (above xloader, 2k below)
+# If any globals exist there needs to be room for them also
+TEXT_BASE = 0x40200800
diff --git a/board/omap3evm/omap3evm.c b/board/overo/overo.c
similarity index 82%
copy from board/omap3evm/omap3evm.c
copy to board/overo/overo.c
index f94518e..0d4aba5 100755
--- a/board/omap3evm/omap3evm.c
+++ b/board/overo/overo.c
@@ -3,6 +3,9 @@
  * Texas Instruments, <www.ti.com>
  * Jian Zhang <jzhang@ti.com>
  * Richard Woodruff <r-woodruff2@ti.com>
+ * 
+ * Modified for overo
+ * Steve Sakoman <steve@sakoman.com>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -22,6 +25,7 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
+
 #include <common.h>
 #include <command.h>
 #include <part.h>
@@ -36,26 +40,24 @@
 
 /* Used to index into DPLL parameter tables */
 struct dpll_param {
-        unsigned int m;
-        unsigned int n;
-        unsigned int fsel;
-        unsigned int m2;
+	unsigned int m;
+	unsigned int n;
+	unsigned int fsel;
+	unsigned int m2;
 };
 
 typedef struct dpll_param dpll_param;
 
-#define MAX_SIL_INDEX	3
-
 /* Following functions are exported from lowlevel_init.S */
-extern dpll_param * get_mpu_dpll_param();
-extern dpll_param * get_iva_dpll_param();
-extern dpll_param * get_core_dpll_param();
-extern dpll_param * get_per_dpll_param();
+extern dpll_param *get_mpu_dpll_param();
+extern dpll_param *get_iva_dpll_param();
+extern dpll_param *get_core_dpll_param();
+extern dpll_param *get_per_dpll_param();
 
-#define __raw_readl(a)    (*(volatile unsigned int *)(a))
-#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v))
-#define __raw_readw(a)    (*(volatile unsigned short *)(a))
-#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v))
+#define __raw_readl(a)		(*(volatile unsigned int *)(a))
+#define __raw_writel(v, a)	(*(volatile unsigned int *)(a) = (v))
+#define __raw_readw(a)		(*(volatile unsigned short *)(a))
+#define __raw_writew(v, a)	(*(volatile unsigned short *)(a) = (v))
 
 /*******************************************************
  * Routine: delay
@@ -71,7 +73,7 @@ static inline void delay(unsigned long loops)
  * Routine: board_init
  * Description: Early hardware init.
  *****************************************/
-int board_init (void)
+int board_init(void)
 {
 	return 0;
 }
@@ -81,9 +83,9 @@ int board_init (void)
  *************************************************************/
 u32 get_device_type(void)
 {
-        int mode;
-        mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK);
-        return(mode >>= 8);
+	int mode;
+	mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK);
+	return mode >>= 8;
 }
 
 /************************************************
@@ -91,50 +93,57 @@ u32 get_device_type(void)
  ************************************************/
 u32 get_sysboot_value(void)
 {
-        int mode;
-        mode = __raw_readl(CONTROL_STATUS) & (SYSBOOT_MASK);
-        return mode;
+	int mode;
+	mode = __raw_readl(CONTROL_STATUS) & (SYSBOOT_MASK);
+	return mode;
 }
+
 /*************************************************************
  * Routine: get_mem_type(void) - returns the kind of memory connected
  * to GPMC that we are trying to boot form. Uses SYS BOOT settings.
  *************************************************************/
 u32 get_mem_type(void)
 {
-        u32   mem_type = get_sysboot_value();
-        switch (mem_type){
-            case 0:
-            case 2:
-            case 4:
-            case 16:
-            case 22:    return GPMC_ONENAND;
-
-            case 1:
-            case 12:
-            case 15:
-            case 21:
-            case 27:    return GPMC_NAND;
-
-            case 3:
-            case 6:     return MMC_ONENAND;
-
-            case 8:
-            case 11:
-            case 14:
-            case 20:
-            case 26:    return GPMC_MDOC;
-
-            case 17:
-            case 18:
-            case 24:	return MMC_NAND;
-
-            case 7:
-            case 10:
-            case 13:
-            case 19:
-            case 25:
-            default:    return GPMC_NOR;
-        }
+	u32   mem_type = get_sysboot_value();
+	switch (mem_type) {
+	case 0:
+	case 2:
+	case 4:
+	case 16:
+	case 22:
+		return GPMC_ONENAND;
+
+	case 1:
+	case 12:
+	case 15:
+	case 21:
+	case 27:
+		return GPMC_NAND;
+
+	case 3:
+	case 6:
+		return MMC_ONENAND;
+
+	case 8:
+	case 11:
+	case 14:
+	case 20:
+	case 26:
+		return GPMC_MDOC;
+
+	case 17:
+	case 18:
+	case 24:
+		return MMC_NAND;
+
+	case 7:
+	case 10:
+	case 13:
+	case 19:
+	case 25:
+	default:
+		return GPMC_NOR;
+	}
 }
 
 /******************************************
@@ -142,13 +151,13 @@ u32 get_mem_type(void)
  ******************************************/
 u32 get_cpu_rev(void)
 {
-	u32 cpuid=0;
+	u32 cpuid = 0;
 	/* On ES1.0 the IDCODE register is not exposed on L4
 	 * so using CPU ID to differentiate
 	 * between ES2.0 and ES1.0.
 	 */
 	__asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r" (cpuid));
-	if((cpuid  & 0xf) == 0x0)
+	if ((cpuid  & 0xf) == 0x0)
 		return CPU_3430_ES1;
 	else
 		return CPU_3430_ES2;
@@ -161,7 +170,7 @@ u32 get_cpu_rev(void)
 u32 cpu_is_3410(void)
 {
 	int status;
-	if(get_cpu_rev() < CPU_3430_ES2) {
+	if (get_cpu_rev() < CPU_3430_ES2) {
 		return 0;
 	} else {
 		/* read scalability status and return 1 for 3410*/
@@ -200,9 +209,9 @@ u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
 		++i;
 		val = __raw_readl(read_addr) & read_bit_mask;
 		if (val == match_value)
-			return (1);
+			return 1;
 		if (i == bound)
-			return (0);
+			return 0;
 	} while (1);
 }
 
@@ -224,13 +233,13 @@ void config_3430sdram_ddr(void)
 	__raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
 
 	/* set timing */
-	if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)){
-        	__raw_writel(INFINEON_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
-        	__raw_writel(INFINEON_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
+	if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)) {
+		__raw_writel(INFINEON_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
+		__raw_writel(INFINEON_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
 	}
-	if ((get_mem_type() == GPMC_NAND) ||(get_mem_type() == MMC_NAND)){
-        	__raw_writel(MICRON_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
-        	__raw_writel(MICRON_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
+	if ((get_mem_type() == GPMC_NAND) || (get_mem_type() == MMC_NAND)) {
+		__raw_writel(MICRON_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
+		__raw_writel(MICRON_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
 	}
 
 	__raw_writel(SDP_SDRC_RFR_CTRL, SDRC_RFR_CTRL);
@@ -251,7 +260,7 @@ void config_3430sdram_ddr(void)
 	delay(0x2000);	/* give time to lock */
 
 }
-#endif // CFG_3430SDRAM_DDR
+#endif /* CFG_3430SDRAM_DDR */
 
 /*************************************************************
  * get_sys_clk_speed - determine reference oscillator speed
@@ -276,9 +285,10 @@ u32 get_osc_clk_speed(void)
 	val = __raw_readl(CM_FCLKEN_WKUP) | BIT0;
 	__raw_writel(val, CM_FCLKEN_WKUP);
 
-	__raw_writel(0, OMAP34XX_GPT1 + TLDR);	/* start counting at 0 */
-	__raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR);     /* enable clock */
-	/* enable 32kHz source *//* enabled out of reset */
+	__raw_writel(0, OMAP34XX_GPT1 + TLDR);		/* start counting at 0 */
+	__raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR);	/* enable clock */
+	/* enable 32kHz source */
+	/* enabled out of reset */
 	/* determine sys_clk via gauging */
 
 	start = 20 + __raw_readl(S32K_CR);	/* start time in 20 cycles */
@@ -290,17 +300,17 @@ u32 get_osc_clk_speed(void)
 
 	/* based on number of ticks assign speed */
 	if (cdiff > 19000)
-		return (S38_4M);
+		return S38_4M;
 	else if (cdiff > 15200)
-		return (S26M);
+		return S26M;
 	else if (cdiff > 13000)
-		return (S24M);
+		return S24M;
 	else if (cdiff > 9000)
-		return (S19_2M);
+		return S19_2M;
 	else if (cdiff > 7600)
-		return (S13M);
+		return S13M;
 	else
-		return (S12M);
+		return S12M;
 }
 
 /******************************************************************************
@@ -310,15 +320,15 @@ u32 get_osc_clk_speed(void)
  *****************************************************************************/
 void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
 {
-	if(osc_clk == S38_4M)
-		*sys_clkin_sel=  4;
-	else if(osc_clk == S26M)
+	if (osc_clk == S38_4M)
+		*sys_clkin_sel =  4;
+	else if (osc_clk == S26M)
 		*sys_clkin_sel = 3;
-	else if(osc_clk == S19_2M)
+	else if (osc_clk == S19_2M)
 		*sys_clkin_sel = 2;
-	else if(osc_clk == S13M)
+	else if (osc_clk == S13M)
 		*sys_clkin_sel = 1;
-	else if(osc_clk == S12M)
+	else if (osc_clk == S12M)
 		*sys_clkin_sel = 0;
 }
 
@@ -328,7 +338,7 @@ void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
  *****************************************************************************/
 void prcm_init(void)
 {
-	u32 osc_clk=0, sys_clkin_sel;
+	u32 osc_clk = 0, sys_clkin_sel;
 	dpll_param *dpll_param_p;
 	u32 clk_index, sil_index;
 
@@ -341,7 +351,7 @@ void prcm_init(void)
 	sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */
 
 	/* If the input clock is greater than 19.2M always divide/2 */
-	if(sys_clkin_sel > 2) {
+	if (sys_clkin_sel > 2) {
 		sr32(PRM_CLKSRC_CTRL, 6, 2, 2);/* input clock divider */
 		clk_index = sys_clkin_sel/2;
 	} else {
@@ -423,13 +433,13 @@ void prcm_init(void)
 	wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY);
 	sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2);	/* set M2 */
 	sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m);	/* set M */
-  	sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n);	/* set N */
+	sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n);	/* set N */
 	sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel);	/* FREQSEL */
 	sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK);	/* lock mode */
 	wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY);
 
 	/* Set up GPTimers to sys_clk source only */
- 	sr32(CM_CLKSEL_PER, 0, 8, 0xff);
+	sr32(CM_CLKSEL_PER, 0, 8, 0xff);
 	sr32(CM_CLKSEL_WKUP, 0, 1, 1);
 
 	delay(5000);
@@ -481,9 +491,8 @@ void try_unlock_memory(void)
 	/* if GP device unlock device SRAM for general use */
 	/* secure code breaks for Secure/Emulation device - HS/E/T*/
 	mode = get_device_type();
-	if (mode == GP_DEVICE) {
+	if (mode == GP_DEVICE)
 		secure_unlock();
-	}
 	return;
 }
 
@@ -500,7 +509,7 @@ void s_init(void)
 	/* setup the scalability control register for
 	 * 3430 to work in 3410 mode
 	 */
-	__raw_writel(0x5ABF,CONTROL_SCALABLE_OMAP_OCP);
+	__raw_writel(0x5ABF, CONTROL_SCALABLE_OMAP_OCP);
 #endif
 	try_unlock_memory();
 	set_muxconf_regs();
@@ -514,9 +523,9 @@ void s_init(void)
  * Routine: misc_init_r
  * Description: Init ethernet (done here so udelay works)
  ********************************************************/
-int misc_init_r (void)
+int misc_init_r(void)
 {
-	return(0);
+	return 0;
 }
 
 /******************************************************
@@ -555,7 +564,7 @@ void watchdog_init(void)
  * Routine: dram_init
  * Description: sets uboots idea of sdram size
  **********************************************/
-int dram_init (void)
+int dram_init(void)
 {
 	return 0;
 }
@@ -572,9 +581,14 @@ void per_clocks_enable(void)
 	sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */
 
 #ifdef CFG_NS16550
-	/* Enable UART1 clocks */
+	/* UART1 clocks */
 	sr32(CM_FCLKEN1_CORE, 13, 1, 0x1);
 	sr32(CM_ICLKEN1_CORE, 13, 1, 0x1);
+
+	/* UART 3 Clocks */
+	sr32(CM_FCLKEN_PER, 11, 1, 0x1);
+	sr32(CM_ICLKEN_PER, 11, 1, 0x1);
+
 #endif
 	delay(1000);
 }
@@ -685,8 +699,12 @@ void per_clocks_enable(void)
 	MUX_VAL(CP(CAM_WEN),        (IEN  | PTD | DIS | M4)) /*GPIO_167*/\
 	MUX_VAL(CP(UART1_TX),       (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
 	MUX_VAL(CP(UART1_RTS),      (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\
-	MUX_VAL(CP(UART1_CTS),      (IEN | PTU | DIS | M0)) /*UART1_CTS*/\
-	MUX_VAL(CP(UART1_RX),       (IEN | PTD | DIS | M0)) /*UART1_RX*/\
+	MUX_VAL(CP(UART1_CTS),      (IEN  | PTU | DIS | M0)) /*UART1_CTS*/\
+	MUX_VAL(CP(UART1_RX),       (IEN  | PTD | DIS | M0)) /*UART1_RX*/\
+	MUX_VAL(CP(UART3_CTS_RCTX), (IEN  | PTD | EN  | M0)) /*UART3_CTS_RCTX */\
+	MUX_VAL(CP(UART3_RTS_SD),   (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
+	MUX_VAL(CP(UART3_RX_IRRX),  (IEN  | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
+	MUX_VAL(CP(UART3_TX_IRTX),  (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
 	MUX_VAL(CP(McBSP1_DX),      (IEN  | PTD | DIS | M4)) /*GPIO_158*/\
 	MUX_VAL(CP(SYS_32K),        (IEN  | PTD | DIS | M0)) /*SYS_32K*/\
 	MUX_VAL(CP(SYS_BOOT0),      (IEN  | PTD | DIS | M4)) /*GPIO_2 */\
@@ -705,9 +723,9 @@ void per_clocks_enable(void)
 	MUX_VAL(CP(JTAG_EMU1),      (IEN  | PTD | DIS | M0)) /*JTAG_EMU1*/\
 	MUX_VAL(CP(ETK_CLK),        (IEN  | PTD | DIS | M4)) /*GPIO_12*/\
 	MUX_VAL(CP(ETK_CTL),        (IEN  | PTD | DIS | M4)) /*GPIO_13*/\
-	MUX_VAL(CP(ETK_D0 ),        (IEN  | PTD | DIS | M4)) /*GPIO_14*/\
-	MUX_VAL(CP(ETK_D1 ),        (IEN  | PTD | DIS | M4)) /*GPIO_15*/\
-	MUX_VAL(CP(ETK_D2 ),        (IEN  | PTD | DIS | M4)) /*GPIO_16*/\
+	MUX_VAL(CP(ETK_D0),         (IEN  | PTD | DIS | M4)) /*GPIO_14*/\
+	MUX_VAL(CP(ETK_D1),         (IEN  | PTD | DIS | M4)) /*GPIO_15*/\
+	MUX_VAL(CP(ETK_D2),         (IEN  | PTD | DIS | M4)) /*GPIO_16*/\
 	MUX_VAL(CP(ETK_D10),        (IEN  | PTD | DIS | M4)) /*GPIO_24*/\
 	MUX_VAL(CP(ETK_D11),        (IEN  | PTD | DIS | M4)) /*GPIO_25*/\
 	MUX_VAL(CP(ETK_D12),        (IEN  | PTD | DIS | M4)) /*GPIO_26*/\
@@ -738,57 +756,56 @@ int nand_init(void)
 	__raw_writel(0x0, GPMC_IRQENABLE);	/* isr's sources masked */
 	__raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */
 
-	/* Set the GPMC Vals . For NAND boot on 3430SDP, NAND is mapped at CS0
-         *  , NOR at CS1 and MPDB at CS3. And oneNAND boot, we map oneNAND at CS0.
+	/* Set the GPMC Vals, NAND is mapped at CS0, oneNAND at CS0.
 	 *  We configure only GPMC CS0 with required values. Configiring other devices
-	 *  at other CS in done in u-boot anyway. So we don't have to bother doing it here.
-         */
+	 *  at other CS is done in u-boot. So we don't have to bother doing it here.
+	 */
 	__raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0);
 	delay(1000);
 
-	if ((get_mem_type() == GPMC_NAND) || (get_mem_type() == MMC_NAND)){
-        	__raw_writel( M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
-        	__raw_writel( M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
-        	__raw_writel( M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
-        	__raw_writel( M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
-        	__raw_writel( M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
-        	__raw_writel( M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
-
-        	/* Enable the GPMC Mapping */
-        	__raw_writel(( ((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
-        		     ((NAND_BASE_ADR>>24) & 0x3F) |
-        		     (1<<6) ),  (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
-        	delay(2000);
-
-         	if (nand_chip()){
+	if ((get_mem_type() == GPMC_NAND) || (get_mem_type() == MMC_NAND)) {
+		__raw_writel(M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
+		__raw_writel(M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
+		__raw_writel(M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
+		__raw_writel(M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
+		__raw_writel(M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
+		__raw_writel(M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
+
+		/* Enable the GPMC Mapping */
+		__raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
+			     ((NAND_BASE_ADR>>24) & 0x3F) |
+			     (1<<6)),  (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
+		delay(2000);
+
+		if (nand_chip()) {
 #ifdef CFG_PRINTF
-        		printf("Unsupported Chip!\n");
+			printf("Unsupported Chip!\n");
 #endif
-        		return 1;
-        	}
+			return 1;
+		}
 
 	}
 
-	if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)){
-        	__raw_writel( ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
-        	__raw_writel( ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
-        	__raw_writel( ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
-        	__raw_writel( ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
-        	__raw_writel( ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
-        	__raw_writel( ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
-
-        	/* Enable the GPMC Mapping */
-        	__raw_writel(( ((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
-        		     ((ONENAND_BASE>>24) & 0x3F) |
-        		     (1<<6) ),  (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
-        	delay(2000);
-
-        	if (onenand_chip()){
+	if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)) {
+		__raw_writel(ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
+		__raw_writel(ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
+		__raw_writel(ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
+		__raw_writel(ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
+		__raw_writel(ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
+		__raw_writel(ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
+
+		/* Enable the GPMC Mapping */
+		__raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
+			     ((ONENAND_BASE>>24) & 0x3F) |
+			     (1<<6)),  (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
+		delay(2000);
+
+		if (onenand_chip()) {
 #ifdef CFG_PRINTF
-        		printf("OneNAND Unsupported !\n");
+			printf("OneNAND Unsupported !\n");
 #endif
-        		return 1;
-        	}
+			return 1;
+		}
 	}
 	return 0;
 }
@@ -798,32 +815,35 @@ typedef int (mmc_boot_addr) (void);
 int mmc_boot(unsigned char *buf)
 {
 
-       long size = 0;
+	long size = 0;
 #ifdef CFG_CMD_FAT
-       block_dev_desc_t *dev_desc = NULL;
-       unsigned char ret = 0;
-
-       printf("Starting X-loader on MMC \n");
-
-       ret = mmc_init(1);
-       if(ret == 0){
-               printf("\n MMC init failed \n");
-               return 0;
-       }
-
-       dev_desc = mmc_get_dev(0);
-       fat_register_device(dev_desc, 1);
-       size = file_fat_read("u-boot.bin", buf, 0);
-       if (size == -1) {
-               return 0;
-       }
-       printf("\n%ld Bytes Read from MMC \n", size);
-
-       printf("Starting OS Bootloader from MMC...\n");
+	block_dev_desc_t *dev_desc = NULL;
+	unsigned char ret = 0;
+
+	printf("Starting X-loader on MMC \n");
+
+	ret = mmc_init(1);
+	if (ret == 0) {
+		printf("\n MMC init failed \n");
+		return 0;
+	}
+
+	dev_desc = mmc_get_dev(0);
+	fat_register_device(dev_desc, 1);
+	size = file_fat_read("u-boot.bin", buf, 0);
+	if (size == -1)
+		return 0;
+
+	printf("\n%ld Bytes Read from MMC \n", size);
+
+	printf("Starting OS Bootloader from MMC...\n");
 #endif
-       return size;
+	return size;
 }
 
 /* optionally do something like blinking LED */
-void board_hang (void)
-{ while (0) {};}
+void board_hang(void)
+{
+	while (0)
+		;
+}
diff --git a/board/overo/platform.S b/board/overo/platform.S
new file mode 100755
index 0000000..8368487
--- /dev/null
+++ b/board/overo/platform.S
@@ -0,0 +1,435 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2004-2006
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/clocks.h>
+
+_TEXT_BASE:
+	.word	TEXT_BASE	/* sdram load addr from config.mk */
+
+#if !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT)
+/**************************************************************************
+ * cpy_clk_code: relocates clock code into SRAM where its safer to execute
+ * R1 = SRAM destination address.
+ *************************************************************************/
+.global cpy_clk_code
+ cpy_clk_code:
+        /* Copy DPLL code into SRAM */ 
+        adr     r0, go_to_speed         /* get addr of clock setting code */
+        mov     r2, #384                /* r2 size to copy (div by 32 bytes) */
+        mov     r1, r1                  /* r1 <- dest address (passed in) */
+        add     r2, r2, r0              /* r2 <- source end address */
+next2:
+        ldmia   r0!, {r3-r10}           /* copy from source address [r0]    */
+        stmia   r1!, {r3-r10}           /* copy to   target address [r1]    */
+        cmp     r0, r2                  /* until source end address [r2]    */
+        bne     next2
+	mov	pc, lr                  /* back to caller */
+
+/* **************************************************************************** 
+ * NOTE: 3430 X-loader currently does not use this code.  
+*   It could be removed its is kept for compatabily with u-boot.
+ *
+ *  go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
+ *               -executed from SRAM.
+ *  R0 = CM_CLKEN_PLL-bypass value
+ *  R1 = CM_CLKSEL1_PLL-m, n, and divider values
+ *  R2 = CM_CLKSEL_CORE-divider values
+ *  R3 = CM_IDLEST_CKGEN - addr dpll lock wait
+ *
+ *  Note: If core unlocks/relocks and SDRAM is running fast already it gets
+ *        confused.  A reset of the controller gets it back.  Taking away its
+ *        L3 when its not in self refresh seems bad for it.  Normally, this code
+ *        runs from flash before SDR is init so that should be ok.
+ ******************************************************************************/    
+.global go_to_speed
+ go_to_speed:
+        stmfd sp!, {r4-r6}
+
+        /* move into fast relock bypass */
+        ldr     r4, pll_ctl_add
+        str     r0, [r4]
+wait1:
+        ldr     r5, [r3]       /* get status */
+        and     r5, r5, #0x1   /* isolate core status */
+        cmp     r5, #0x1       /* still locked? */
+        beq     wait1          /* if lock, loop */
+
+	/* set new dpll dividers _after_ in bypass */
+	ldr     r5, pll_div_add1
+        str     r1, [r5]          /* set m, n, m2 */
+        ldr     r5, pll_div_add2
+        str     r2, [r5]          /* set l3/l4/.. dividers*/
+        ldr     r5, pll_div_add3  /* wkup */
+        ldr     r2, pll_div_val3  /* rsm val */
+        str     r2, [r5]          
+        ldr     r5, pll_div_add4  /* gfx */
+        ldr     r2, pll_div_val4 
+        str     r2, [r5]         
+        ldr     r5, pll_div_add5  /* emu */
+        ldr     r2, pll_div_val5 
+        str     r2, [r5]     
+
+        /* now prepare GPMC (flash) for new dpll speed */
+	/* flash needs to be stable when we jump back to it */
+        ldr     r5, flash_cfg3_addr
+        ldr     r2, flash_cfg3_val
+        str     r2, [r5]
+        ldr     r5, flash_cfg4_addr
+        ldr     r2, flash_cfg4_val
+        str     r2, [r5]
+        ldr     r5, flash_cfg5_addr
+        ldr     r2, flash_cfg5_val
+        str     r2, [r5]
+        ldr     r5, flash_cfg1_addr
+        ldr     r2, [r5]
+        orr     r2, r2, #0x3     /* up gpmc divider */
+        str     r2, [r5]
+
+        /* lock DPLL3 and wait a bit */
+        orr     r0, r0, #0x7   /* set up for lock mode */     
+        str     r0, [r4]       /* lock */
+        nop                    /* ARM slow at this point working at sys_clk */
+        nop
+        nop
+        nop
+wait2:
+        ldr     r5, [r3]       /* get status */
+        and     r5, r5, #0x1   /* isolate core status */
+        cmp     r5, #0x1       /* still locked? */
+        bne     wait2          /* if lock, loop */
+        nop
+        nop
+        nop
+        nop
+        ldmfd sp!, {r4-r6}
+        mov     pc, lr           /* back to caller, locked */        
+
+_go_to_speed: .word go_to_speed
+
+/* these constants need to be close for PIC code */
+/* The Nor has to be in the Flash Base CS0 for this condition to happen */
+flash_cfg1_addr:
+    .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1)
+flash_cfg3_addr:
+    .word  (GPMC_CONFIG_CS0 + GPMC_CONFIG3)
+flash_cfg3_val: 
+    .word  STNOR_GPMC_CONFIG3
+flash_cfg4_addr:
+    .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4)
+flash_cfg4_val:
+    .word  STNOR_GPMC_CONFIG4
+flash_cfg5_val:
+    .word  STNOR_GPMC_CONFIG5
+flash_cfg5_addr:
+    .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5)
+pll_ctl_add:
+    .word CM_CLKEN_PLL
+pll_div_add1:
+    .word CM_CLKSEL1_PLL 
+pll_div_add2:
+    .word CM_CLKSEL_CORE
+pll_div_add3:
+    .word CM_CLKSEL_WKUP
+pll_div_val3:
+    .word (WKUP_RSM << 1) 
+pll_div_add4:
+    .word CM_CLKSEL_GFX
+pll_div_val4:
+    .word (GFX_DIV << 0) 
+pll_div_add5:
+    .word CM_CLKSEL1_EMU
+pll_div_val5:
+    .word CLSEL1_EMU_VAL
+
+#endif
+
+.globl lowlevel_init
+lowlevel_init:
+	ldr	sp,	SRAM_STACK
+        str     ip,	[sp]    /* stash old link register */
+	mov	ip,	lr	/* save link reg across call */
+        bl      s_init          /* go setup pll,mux,memory */
+        ldr     ip,	[sp]    /* restore save ip */
+	mov	lr,	ip	/* restore link reg */
+
+	/* back to arch calling code */
+	mov	pc,	lr
+
+	/* the literal pools origin */
+	.ltorg
+
+REG_CONTROL_STATUS:
+	.word CONTROL_STATUS
+SRAM_STACK:
+	.word LOW_LEVEL_SRAM_STACK
+
+
+/* DPLL(1-4) PARAM TABLES */
+/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal
+ * OPP (1.2V). The fields are defined according to dpll_param struct(clock.c). 
+ * The values are defined for all possible sysclk and for ES1 and ES2.
+ */
+
+mpu_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word 0x0FE
+.word 0x07
+.word 0x05
+.word 0x01
+/* ES2 */
+.word 0x0FA
+.word 0x05
+.word 0x07
+.word 0x01
+
+/* 13MHz */
+/* ES1 */
+.word 0x17D
+.word 0x0C
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x1F4
+.word 0x0C
+.word 0x03
+.word 0x01
+ 
+/* 19.2MHz */
+/* ES1 */
+.word 0x179
+.word 0x12
+.word 0x04
+.word 0x01
+/* ES2 */
+.word 0x271
+.word 0x17
+.word 0x03
+.word 0x01
+
+/* 26MHz */
+/* ES1 */
+.word 0x17D
+.word 0x19
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x0FA
+.word 0x0C
+.word 0x07
+.word 0x01
+
+/* 38.4MHz */
+/* ES1 */
+.word 0x1FA
+.word 0x32
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x271
+.word 0x2F
+.word 0x03
+.word 0x01
+
+
+.globl get_mpu_dpll_param
+get_mpu_dpll_param:
+	adr r0, mpu_dpll_param
+	mov pc, lr
+
+iva_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word 0x07D
+.word 0x05
+.word 0x07
+.word 0x01
+/* ES2 */
+.word 0x0B4
+.word 0x05
+.word 0x07
+.word 0x01
+
+/* 13MHz */
+/* ES1 */
+.word 0x0FA
+.word 0x0C
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x168
+.word 0x0C
+.word 0x03
+.word 0x01
+
+/* 19.2MHz */
+/* ES1 */
+.word 0x082
+.word 0x09
+.word 0x07
+.word 0x01
+/* ES2 */
+.word 0x0E1
+.word 0x0B
+.word 0x06
+.word 0x01
+
+/* 26MHz */
+/* ES1 */
+.word 0x07D
+.word 0x0C
+.word 0x07
+.word 0x01
+/* ES2 */
+.word 0x0B4
+.word 0x0C
+.word 0x07
+.word 0x01
+
+/* 38.4MHz */
+/* ES1 */
+.word 0x13F
+.word 0x30
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x0E1
+.word 0x17
+.word 0x06
+.word 0x01
+
+
+.globl get_iva_dpll_param
+get_iva_dpll_param:
+	adr r0, iva_dpll_param
+	mov pc, lr
+
+core_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word 0x19F
+.word 0x0E
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x0A6
+.word 0x05
+.word 0x07
+.word 0x01
+
+/* 13MHz */
+/* ES1 */
+.word 0x1B2
+.word 0x10
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x14C
+.word 0x0C
+.word 0x03
+.word 0x01
+
+/* 19.2MHz */
+/* ES1 */
+.word 0x19F
+.word 0x17
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x19F
+.word 0x17
+.word 0x03
+.word 0x01
+
+/* 26MHz */
+/* ES1 */
+.word 0x1B2
+.word 0x21
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x0A6
+.word 0x0C
+.word 0x07
+.word 0x01
+
+/* 38.4MHz */
+/* ES1 */
+.word 0x19F
+.word 0x2F
+.word 0x03
+.word 0x01
+/* ES2 */
+.word 0x19F
+.word 0x2F
+.word 0x03
+.word 0x01
+
+.globl get_core_dpll_param
+get_core_dpll_param:
+	adr r0, core_dpll_param
+	mov pc, lr
+
+/* PER DPLL values are same for both ES1 and ES2 */
+per_dpll_param:
+/* 12MHz */
+.word 0xD8
+.word 0x05
+.word 0x07
+.word 0x09
+
+/* 13MHz */
+.word 0x1B0
+.word 0x0C
+.word 0x03
+.word 0x09
+
+/* 19.2MHz */
+.word 0xE1
+.word 0x09
+.word 0x07
+.word 0x09
+
+/* 26MHz */
+.word 0xD8
+.word 0x0C
+.word 0x07
+.word 0x09
+
+/* 38.4MHz */
+.word 0xE1
+.word 0x13
+.word 0x07
+.word 0x09
+
+.globl get_per_dpll_param
+get_per_dpll_param:
+	adr r0, per_dpll_param
+	mov pc, lr
+
diff --git a/board/overo/x-load.lds b/board/overo/x-load.lds
new file mode 100755
index 0000000..5f352d3
--- /dev/null
+++ b/board/overo/x-load.lds
@@ -0,0 +1,54 @@
+/*
+ * November 2006 - Changed to support 3430sdp device
+ * Copyright (c) 2004-2006 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/omap3/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/drivers/Makefile b/drivers/Makefile
index 2352f42..36b6fb2 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -36,10 +36,18 @@ ifeq ($(BOARD), omap3430labrador)
 OBJS 	+= k9f1g08r0a.o
 endif
 
+ifeq ($(BOARD), omap3530beagle)
+OBJS 	+= k9f1g08r0a.o
+endif
+
 ifeq ($(BOARD), omap3evm)
 OBJS 	+= k9f1g08r0a.o
 endif
 
+ifeq ($(BOARD), overo)
+OBJS 	+= k9f1g08r0a.o
+endif
+
 ifeq ($(BOARD), omap2420h4) 
 OBJS 	+= k9k1216.o
 endif
diff --git a/include/asm/arch-omap3/omap3430.h b/include/asm/arch-omap3/omap3430.h
index 89406de..3c583ae 100644
--- a/include/asm/arch-omap3/omap3430.h
+++ b/include/asm/arch-omap3/omap3430.h
@@ -94,6 +94,14 @@
 #define SYNC_32KTIMER_BASE		(0x48320000)
 #define S32K_CR				(SYNC_32KTIMER_BASE+0x10)
 
+/* omap3 GPIO registers */
+#define OMAP34XX_GPIO1_BASE		0x48310000
+#define OMAP34XX_GPIO2_BASE		0x49050000
+#define OMAP34XX_GPIO3_BASE		0x49052000
+#define OMAP34XX_GPIO4_BASE		0x49054000
+#define OMAP34XX_GPIO5_BASE		0x49056000
+#define OMAP34XX_GPIO6_BASE		0x49058000
+
 /*
  * SDP3430 specific Section
  */
diff --git a/include/configs/omap3530beagle.h b/include/configs/omap3530beagle.h
new file mode 100644
index 0000000..8728378
--- /dev/null
+++ b/include/configs/omap3530beagle.h
@@ -0,0 +1,200 @@
+/*
+ * (C) Copyright 2006 
+ * Texas Instruments <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * X-Loader Configuation settings for the TI OMAP SDP3430 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* serial printf facility takes about 3.5K */
+#define CFG_PRINTF 
+//#undef CFG_PRINTF 
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMCORTEXA8	1	/* This is an ARM V7 CPU core */
+#define CONFIG_OMAP		1	/* in a TI OMAP core */
+#define CONFIG_OMAP34XX		1	/* which is a 34XX */
+#define CONFIG_OMAP3430		1	/* which is in a 3430 */
+#define CONFIG_OMAP3_BEAGLE	1	/* working with BEAGLE */
+
+#define CONFIG_BEAGLE_REV2	 1
+
+/* Enable the below macro if MMC boot support is required */
+#define CONFIG_MMC	1
+#if defined(CONFIG_MMC)
+	#define CFG_CMD_MMC	1
+	#define CFG_CMD_FAT	1
+#endif
+
+#include <asm/arch/cpu.h>        /* get chip and board defs */
+
+/* uncomment it if you need timer based udelay(). it takes about 250 bytes */
+//#define CFG_UDELAY
+ 
+/* Clock Defines */
+#define V_OSCK	26000000  /* Clock output from T2 */
+
+#if (V_OSCK > 19200000)
+#define V_SCLK	(V_OSCK >> 1)
+#else
+#define V_SCLK	V_OSCK
+#endif
+
+//#define PRCM_CLK_CFG2_266MHZ	1	/* VDD2=1.15v - 133MHz DDR */
+#define PRCM_CLK_CFG2_332MHZ	1	/* VDD2=1.15v - 166MHz DDR */
+#define PRCM_PCLK_OPP2		1	/* ARM=381MHz - VDD1=1.20v */
+
+/* Memory type */
+#define CFG_3430SDRAM_DDR	1
+
+/* The actual register values are defined in u-boot- mem.h */
+/* SDRAM Bank Allocation method */
+//#define SDRC_B_R_C		1
+//#define SDRC_B1_R_B0_C	1
+#define SDRC_R_B_C		1
+
+#define NAND_BASE_ADR	NAND_BASE
+#define ONENAND_BASE	ONENAND_MAP
+#define ONENAND_ADDR	ONENAND_BASE
+
+#define OMAP34XX_GPMC_CS0_SIZE GPMC_SIZE_128M
+
+#ifdef CFG_PRINTF
+
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	-4
+#define CFG_NS16550_CLK		48000000
+#define CFG_NS16550_COM3	OMAP34XX_UART3
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1		3	/* use UART3 */
+#define CONFIG_CONS_INDEX	3
+
+#define CONFIG_BAUDRATE		115200
+#define CFG_PBSIZE		256
+
+#endif /* CFG_PRINTF */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LOADADDR		0x80008000
+  
+#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+ 
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Board NAND Info.
+ */
+
+
+#define CFG_NAND_K9F1G08R0A
+#define NAND_16BIT
+
+/* NAND is partitioned:
+ * 0x00000000 - 0x0007FFFF  Booting Image
+ * 0x00080000 - 0x000BFFFF  U-Boot Image
+ * 0x000C0000 - 0x000FFFFF  U-Boot Env Data (X-loader doesn't care)
+ * 0x00100000 - 0x002FFFFF  Kernel Image
+ * 0x00300000 - 0x08000000  depends on application
+ */
+#define NAND_UBOOT_START	0x0080000 /* Leaving first 4 blocks for x-load */
+#define NAND_UBOOT_END		0x0160000 /* Giving a space of 2 blocks = 256KB */
+#define NAND_BLOCK_SIZE		0x20000
+  
+#define GPMC_CONFIG 		(OMAP34XX_GPMC_BASE+0x50)
+#define GPMC_NAND_COMMAND_0	(OMAP34XX_GPMC_BASE+0x7C)
+#define GPMC_NAND_ADDRESS_0	(OMAP34XX_GPMC_BASE+0x80)
+#define GPMC_NAND_DATA_0	(OMAP34XX_GPMC_BASE+0x84)
+
+#ifdef NAND_16BIT
+#define WRITE_NAND_COMMAND(d, adr) \
+	do {*(volatile u16 *)GPMC_NAND_COMMAND_0 = d; } while (0)
+#define WRITE_NAND_ADDRESS(d, adr) \
+	do {*(volatile u16 *)GPMC_NAND_ADDRESS_0 = d; } while (0)
+#define WRITE_NAND(d, adr) \
+	do {*(volatile u16 *)GPMC_NAND_DATA_0 = d; } while (0)
+#define READ_NAND(adr) \
+	(*(volatile u16 *)GPMC_NAND_DATA_0)
+#define NAND_WAIT_READY()
+#define NAND_WP_OFF()  \
+	do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010; } while (0)
+#define NAND_WP_ON()  \
+	 do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010; } while (0)
+
+#else /* to support 8-bit NAND devices */
+#define WRITE_NAND_COMMAND(d, adr) \
+	do {*(volatile u8 *)GPMC_NAND_COMMAND_0 = d; } while (0)
+#define WRITE_NAND_ADDRESS(d, adr) \
+	 do {*(volatile u8 *)GPMC_NAND_ADDRESS_0 = d; } while (0)
+#define WRITE_NAND(d, adr) \
+	do {*(volatile u8 *)GPMC_NAND_DATA_0 = d; } while (0)
+#define READ_NAND(adr) \
+	(*(volatile u8 *)GPMC_NAND_DATA_0);
+#define NAND_WAIT_READY()
+#define NAND_WP_OFF()  \
+	do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010; } while (0)
+#define NAND_WP_ON()  \
+	do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010; } while (0)
+
+#endif
+
+#define NAND_CTL_CLRALE(adr) 
+#define NAND_CTL_SETALE(adr) 
+#define NAND_CTL_CLRCLE(adr) 
+#define NAND_CTL_SETCLE(adr) 
+#define NAND_DISABLE_CE() 
+#define NAND_ENABLE_CE() 
+
+/*-----------------------------------------------------------------------
+ * Board oneNAND Info.
+ */
+#define CFG_SYNC_BURST_READ	1
+
+/* OneNAND is partitioned:
+ *   0x0000000 - 0x0080000  X-Loader 
+ *   0x0080000 - 0x00c0000   U-boot Image
+ *   0x00c0000 - 0x00e0000   U-Boot Env Data (X-loader doesn't care)
+ *   0x00e0000 - 0x0120000   Kernel Image
+ *   0x0120000 - 0x4000000   depends on application
+ */
+
+#define ONENAND_START_BLOCK 	4
+#define ONENAND_END_BLOCK	6
+#define ONENAND_PAGE_SIZE	2048     /* 2KB */
+#define ONENAND_BLOCK_SIZE	0x20000  /* 128KB */
+
+#endif /* __CONFIG_H */
+
diff --git a/include/configs/overo.h b/include/configs/overo.h
new file mode 100755
index 0000000..44d80c0
--- /dev/null
+++ b/include/configs/overo.h
@@ -0,0 +1,200 @@
+/*
+ * (C) Copyright 2006 
+ * Texas Instruments <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * X-Loader Configuation settings for the overo board.
+ *
+ * Derived from /include/configs/omap3evm.h
+ * Steve Sakoman <steve@sakoman.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* serial printf facility takes about 3.5K */
+#define CFG_PRINTF
+//#undef CFG_PRINTF
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMCORTEXA8	1	/* This is an ARM V7 CPU core */
+#define CONFIG_OMAP		1	/* in a TI OMAP core */
+#define CONFIG_OMAP34XX		1	/* which is a 34XX */
+#define CONFIG_OMAP3430		1	/* which is in a 3430 */
+#define CONFIG_OVERO		1	/* working with overo */
+
+/* Enable the below macro if MMC boot support is required */
+#define CONFIG_MMC	1
+#if defined(CONFIG_MMC)
+	#define CFG_CMD_MMC	1
+	#define CFG_CMD_FAT	1
+#endif
+
+#include <asm/arch/cpu.h>        /* get chip and board defs */
+
+/* uncomment it if you need timer based udelay(). it takes about 250 bytes */
+//#define CFG_UDELAY
+
+/* Clock Defines */
+#define V_OSCK	26000000  /* Clock output from T2 */
+
+#if (V_OSCK > 19200000)
+#define V_SCLK	(V_OSCK >> 1)
+#else
+#define V_SCLK	V_OSCK
+#endif
+
+//#define PRCM_CLK_CFG2_266MHZ	1	/* VDD2=1.15v - 133MHz DDR */
+#define PRCM_CLK_CFG2_332MHZ	1	/* VDD2=1.15v - 166MHz DDR */
+#define PRCM_PCLK_OPP2		1	/* ARM=381MHz - VDD1=1.20v */
+
+/* Memory type */
+#define CFG_3430SDRAM_DDR	1
+
+/* The actual register values are defined in u-boot- mem.h */
+/* SDRAM Bank Allocation method */
+//#define SDRC_B_R_C		1
+//#define SDRC_B1_R_B0_C	1
+#define SDRC_R_B_C		1
+
+#define NAND_BASE_ADR	NAND_BASE
+#define ONENAND_BASE	ONENAND_MAP
+#define ONENAND_ADDR	ONENAND_BASE
+
+#define OMAP34XX_GPMC_CS0_SIZE GPMC_SIZE_128M
+
+#ifdef CFG_PRINTF
+
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	-4
+#define CFG_NS16550_CLK		48000000
+#define CFG_NS16550_COM3	OMAP34XX_UART3
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1		3	/* use UART3 */
+#define CONFIG_CONS_INDEX	3
+
+#define CONFIG_BAUDRATE		115200
+#define CFG_PBSIZE		256
+
+#endif /* CFG_PRINTF */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LOADADDR		0x80008000
+
+#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Board NAND Info.
+ */
+
+#define CFG_NAND_K9F1G08R0A
+#define NAND_16BIT
+
+/* NAND is partitioned:
+ * 0x00000000 - 0x0007FFFF  Booting Image
+ * 0x00080000 - 0x0023FFFF  U-Boot Image
+ * 0x00240000 - 0x0027FFFF  U-Boot Env Data (X-loader doesn't care)
+ * 0x00280000 - 0x0077FFFF  Kernel Image
+ * 0x00780000 - 0x08000000  depends on application
+ */
+#define NAND_UBOOT_START	0x0080000 /* Leaving first 4 blocks for x-load */
+#define NAND_UBOOT_END		0x0240000 /* Giving a space of 2 blocks = 256KB */
+#define NAND_BLOCK_SIZE		0x20000
+
+#define GPMC_CONFIG		(OMAP34XX_GPMC_BASE+0x50)
+#define GPMC_NAND_COMMAND_0	(OMAP34XX_GPMC_BASE+0x7C)
+#define GPMC_NAND_ADDRESS_0	(OMAP34XX_GPMC_BASE+0x80)
+#define GPMC_NAND_DATA_0	(OMAP34XX_GPMC_BASE+0x84)
+
+#ifdef NAND_16BIT
+#define WRITE_NAND_COMMAND(d, adr) \
+	do {*(volatile u16 *)GPMC_NAND_COMMAND_0 = d; } while (0)
+#define WRITE_NAND_ADDRESS(d, adr) \
+	do {*(volatile u16 *)GPMC_NAND_ADDRESS_0 = d; } while (0)
+#define WRITE_NAND(d, adr) \
+	do {*(volatile u16 *)GPMC_NAND_DATA_0 = d; } while (0)
+#define READ_NAND(adr) \
+	(*(volatile u16 *)GPMC_NAND_DATA_0)
+#define NAND_WAIT_READY()
+#define NAND_WP_OFF()  \
+	do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010; } while (0)
+#define NAND_WP_ON()  \
+	 do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010; } while (0)
+
+#else /* to support 8-bit NAND devices */
+#define WRITE_NAND_COMMAND(d, adr) \
+	do {*(volatile u8 *)GPMC_NAND_COMMAND_0 = d; } while (0)
+#define WRITE_NAND_ADDRESS(d, adr) \
+	 do {*(volatile u8 *)GPMC_NAND_ADDRESS_0 = d; } while (0)
+#define WRITE_NAND(d, adr) \
+	do {*(volatile u8 *)GPMC_NAND_DATA_0 = d; } while (0)
+#define READ_NAND(adr) \
+	(*(volatile u8 *)GPMC_NAND_DATA_0);
+#define NAND_WAIT_READY()
+#define NAND_WP_OFF()  \
+	do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010; } while (0)
+#define NAND_WP_ON()  \
+	do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010; } while (0)
+
+#endif
+
+#define NAND_CTL_CLRALE(adr)
+#define NAND_CTL_SETALE(adr)
+#define NAND_CTL_CLRCLE(adr)
+#define NAND_CTL_SETCLE(adr)
+#define NAND_DISABLE_CE()
+#define NAND_ENABLE_CE()
+
+/*-----------------------------------------------------------------------
+ * Board oneNAND Info.
+ */
+#define CFG_SYNC_BURST_READ	1
+
+/* OneNAND is partitioned:
+ *   0x0000000 - 0x0080000  X-Loader
+ *   0x0080000 - 0x0240000   U-boot Image
+ *   0x0240000 - 0x0280000   U-Boot Env Data (X-loader doesn't care)
+ *   0x0280000 - 0x0780000   Kernel Image
+ *   0x0780000 - 0x8000000   depends on application
+ */
+
+#define ONENAND_START_BLOCK	4
+#define ONENAND_END_BLOCK	18
+#define ONENAND_PAGE_SIZE	2048     /* 2KB */
+#define ONENAND_BLOCK_SIZE	0x20000  /* 128KB */
+
+#endif /* __CONFIG_H */
+
-- 
2.11.4.GIT